[linux-2.6-block.git] / sound / oss / ad1889.h

#ifndef _AD1889_H_
#define _AD1889_H_

#define AD_DS_WSMC	0x00	/* DMA input wave/syn mixer control */
#define AD_DS_RAMC	0x02	/* DMA output resamp/ADC mixer control */
#define AD_DS_WADA	0x04	/* DMA input wave attenuation */
#define AD_DS_SYDA	0x06	/* DMA input syn attentuation */
#define AD_DS_WAS	0x08	/* wave input sample rate */
#define AD_DS_RES	0x0a	/* resampler output sample rate */
#define AD_DS_CCS	0x0c	/* chip control/status */

#define AD_DMA_RESBA	0x40	/* RES base addr */
#define AD_DMA_RESCA	0x44	/* RES current addr */
#define AD_DMA_RESBC	0x48	/* RES base cnt */
#define AD_DMA_RESCC	0x4c	/* RES current count */
#define AD_DMA_ADCBA	0x50	/* ADC */
#define AD_DMA_ADCCA	0x54
#define AD_DMA_ADCBC	0x58
#define AD_DMA_ADCCC	0x5c
#define AD_DMA_SYNBA	0x60	/* SYN */
#define AD_DMA_SYNCA	0x64
#define AD_DMA_SYNBC	0x68
#define AD_DMA_SYNCC	0x6c
#define AD_DMA_WAVBA	0x70	/* WAV */
#define AD_DMA_WAVCA	0x74
#define AD_DMA_WAVBC	0x78
#define AD_DMA_WAVCC	0x7c
#define AD_DMA_RESICC	0x80	/* RES interrupt current count */
#define AD_DMA_RESIBC	0x84	/* RES interrupt base count */
#define AD_DMA_ADCICC	0x88	/* ADC interrupt current count */
#define AD_DMA_ADCIBC	0x8c	/* ADC interrupt base count */
#define AD_DMA_SYNICC	0x90	/* SYN interrupt current count */
#define AD_DMA_SYNIBC	0x94	/* SYN interrupt base count */
#define AD_DMA_WAVICC	0x98	/* WAV interrupt current count */
#define AD_DMA_WAVIBC	0x9c	/* WAV interrupt base count */
#define AD_DMA_RESCTRL	0xa0	/* RES PCI control/status */
#define AD_DMA_ADCCTRL	0xa8	/* ADC PCI control/status */
#define AD_DMA_SYNCTRL	0xb0	/* SYN PCI control/status */
#define AD_DMA_WAVCTRL	0xb8	/* WAV PCI control/status */
#define AD_DMA_DISR	0xc0	/* PCI DMA intr status */
#define AD_DMA_CHSS	0xc4	/* PCI DMA channel stop status */

#define AD_GPIO_IPC	0xc8	/* IO port ctrl */
#define AD_GPIO_OP	0xca	/* IO output status */
#define AD_GPIO_IP	0xcc	/* IO input status */

/* AC97 registers, 0x100 - 0x17f; see ac97.h */
#define AD_AC97_BASE    0x100   /* ac97 base register */
#define AD_AC97_ACIC	0x180	/* AC Link interface ctrl */

/* OPL3; BAR1 */
#define AD_OPL_M0AS	0x00	/* Music0 address/status */
#define AD_OPL_M0DATA	0x01	/* Music0 data */
#define AD_OPL_M1A	0x02	/* Music1 address */
#define AD_OPL_M1DATA	0x03	/* Music1 data */
/* 0x04-0x0f reserved */

/* MIDI; BAR2 */
#define AD_MIDA		0x00	/* MIDI data */
#define AD_MISC		0x01	/* MIDI status/cmd */
/* 0x02-0xff reserved */

#define AD_DS_IOMEMSIZE	512
#define AD_OPL_MEMSIZE	16
#define AD_MIDI_MEMSIZE	16

#define AD_WAV_STATE	0
#define AD_ADC_STATE	1
#define AD_MAX_STATES	2

#define DMA_SIZE	(128*1024)

#define DMA_FLAG_MAPPED	1

struct ad1889_dev;

typedef struct ad1889_state {
	struct ad1889_dev *card;

	mode_t open_mode;
	struct dmabuf {
		unsigned int rate;
		unsigned char fmt, enable;

		/* buf management */
		size_t rawbuf_size;
		void *rawbuf;
		dma_addr_t dma_handle;	/* mapped address */
		unsigned long dma_len;	/* number of bytes mapped */

		/* indexes into rawbuf for setting up DMA engine */
		volatile unsigned long rd_ptr, wr_ptr;

		wait_queue_head_t wait; /* to wait for buf servicing */

		/* OSS bits */
		unsigned int mapped:1;
		unsigned int ready:1;
		unsigned int ossfragshift;
		int ossmaxfrags;
		unsigned int subdivision;
	} dmabuf;

	struct mutex mutex;
} ad1889_state_t;

typedef struct ad1889_dev {
	void __iomem *regbase;
	struct pci_dev *pci;
	
	spinlock_t lock;

	int dev_audio;

	/* states; one per channel; right now only WAV and ADC */
	struct ad1889_state state[AD_MAX_STATES];

	/* AC97 codec */
	struct ac97_codec *ac97_codec;
	u16 ac97_features;

	/* debugging stuff */
	struct stats {
		unsigned int wav_intrs, adc_intrs;
		unsigned int blocks, underrun, error;
	} stats;
} ad1889_dev_t;

typedef struct ad1889_reg {
	const char *name;
	int offset;
	int width;
} ad1889_reg_t;

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef _AD1889_H_
	2	#define _AD1889_H_
	3
e74eb808 SB	4	#define AD_DS_WSMC 0x00 /* DMA input wave/syn mixer control */
	5	#define AD_DS_RAMC 0x02 /* DMA output resamp/ADC mixer control */
	6	#define AD_DS_WADA 0x04 /* DMA input wave attenuation */
	7	#define AD_DS_SYDA 0x06 /* DMA input syn attentuation */
	8	#define AD_DS_WAS 0x08 /* wave input sample rate */
	9	#define AD_DS_RES 0x0a /* resampler output sample rate */
	10	#define AD_DS_CCS 0x0c /* chip control/status */
1da177e4	11
e74eb808 SB	12	#define AD_DMA_RESBA 0x40 /* RES base addr */
	13	#define AD_DMA_RESCA 0x44 /* RES current addr */
	14	#define AD_DMA_RESBC 0x48 /* RES base cnt */
	15	#define AD_DMA_RESCC 0x4c /* RES current count */
	16	#define AD_DMA_ADCBA 0x50 /* ADC */
	17	#define AD_DMA_ADCCA 0x54
	18	#define AD_DMA_ADCBC 0x58
	19	#define AD_DMA_ADCCC 0x5c
	20	#define AD_DMA_SYNBA 0x60 /* SYN */
	21	#define AD_DMA_SYNCA 0x64
	22	#define AD_DMA_SYNBC 0x68
	23	#define AD_DMA_SYNCC 0x6c
	24	#define AD_DMA_WAVBA 0x70 /* WAV */
	25	#define AD_DMA_WAVCA 0x74
	26	#define AD_DMA_WAVBC 0x78
	27	#define AD_DMA_WAVCC 0x7c
	28	#define AD_DMA_RESICC 0x80 /* RES interrupt current count */
	29	#define AD_DMA_RESIBC 0x84 /* RES interrupt base count */
	30	#define AD_DMA_ADCICC 0x88 /* ADC interrupt current count */
	31	#define AD_DMA_ADCIBC 0x8c /* ADC interrupt base count */
	32	#define AD_DMA_SYNICC 0x90 /* SYN interrupt current count */
	33	#define AD_DMA_SYNIBC 0x94 /* SYN interrupt base count */
	34	#define AD_DMA_WAVICC 0x98 /* WAV interrupt current count */
	35	#define AD_DMA_WAVIBC 0x9c /* WAV interrupt base count */
	36	#define AD_DMA_RESCTRL 0xa0 /* RES PCI control/status */
	37	#define AD_DMA_ADCCTRL 0xa8 /* ADC PCI control/status */
	38	#define AD_DMA_SYNCTRL 0xb0 /* SYN PCI control/status */
	39	#define AD_DMA_WAVCTRL 0xb8 /* WAV PCI control/status */
	40	#define AD_DMA_DISR 0xc0 /* PCI DMA intr status */
	41	#define AD_DMA_CHSS 0xc4 /* PCI DMA channel stop status */
1da177e4	42
e74eb808 SB	43	#define AD_GPIO_IPC 0xc8 /* IO port ctrl */
	44	#define AD_GPIO_OP 0xca /* IO output status */
	45	#define AD_GPIO_IP 0xcc /* IO input status */
1da177e4 LT	46
1da177e4 LT	47	/* AC97 registers, 0x100 - 0x17f; see ac97.h */
e74eb808 SB	48	#define AD_AC97_BASE 0x100 /* ac97 base register */
e74eb808 SB	49	#define AD_AC97_ACIC 0x180 /* AC Link interface ctrl */
1da177e4 LT	50
1da177e4 LT	51	/* OPL3; BAR1 */
e74eb808 SB	52	#define AD_OPL_M0AS 0x00 /* Music0 address/status */
	53	#define AD_OPL_M0DATA 0x01 /* Music0 data */
	54	#define AD_OPL_M1A 0x02 /* Music1 address */
	55	#define AD_OPL_M1DATA 0x03 /* Music1 data */
1da177e4 LT	56	/* 0x04-0x0f reserved */
	57
	58	/* MIDI; BAR2 */
	59	#define AD_MIDA 0x00 /* MIDI data */
	60	#define AD_MISC 0x01 /* MIDI status/cmd */
	61	/* 0x02-0xff reserved */
	62
e74eb808 SB	63	#define AD_DS_IOMEMSIZE 512
	64	#define AD_OPL_MEMSIZE 16
	65	#define AD_MIDI_MEMSIZE 16
1da177e4 LT	66
	67	#define AD_WAV_STATE 0
	68	#define AD_ADC_STATE 1
	69	#define AD_MAX_STATES 2
	70
	71	#define DMA_SIZE (128*1024)
	72
	73	#define DMA_FLAG_MAPPED 1
	74
	75	struct ad1889_dev;
	76
	77	typedef struct ad1889_state {
	78	struct ad1889_dev *card;
	79
	80	mode_t open_mode;
	81	struct dmabuf {
	82	unsigned int rate;
	83	unsigned char fmt, enable;
	84
	85	/* buf management */
	86	size_t rawbuf_size;
	87	void *rawbuf;
	88	dma_addr_t dma_handle; /* mapped address */
	89	unsigned long dma_len; /* number of bytes mapped */
	90
	91	/* indexes into rawbuf for setting up DMA engine */
	92	volatile unsigned long rd_ptr, wr_ptr;
	93
	94	wait_queue_head_t wait; /* to wait for buf servicing */
	95
	96	/* OSS bits */
	97	unsigned int mapped:1;
	98	unsigned int ready:1;
	99	unsigned int ossfragshift;
	100	int ossmaxfrags;
	101	unsigned int subdivision;
	102	} dmabuf;
	103
910f5d20	104	struct mutex mutex;
1da177e4 LT	105	} ad1889_state_t;
	106
	107	typedef struct ad1889_dev {
	108	void __iomem *regbase;
	109	struct pci_dev *pci;
	110
	111	spinlock_t lock;
	112
	113	int dev_audio;
	114
	115	/* states; one per channel; right now only WAV and ADC */
	116	struct ad1889_state state[AD_MAX_STATES];
	117
	118	/* AC97 codec */
	119	struct ac97_codec *ac97_codec;
	120	u16 ac97_features;
	121
	122	/* debugging stuff */
	123	struct stats {
	124	unsigned int wav_intrs, adc_intrs;
	125	unsigned int blocks, underrun, error;
	126	} stats;
	127	} ad1889_dev_t;
	128
	129	typedef struct ad1889_reg {
	130	const char *name;
	131	int offset;
	132	int width;
	133	} ad1889_reg_t;
	134
	135	#endif