[linux-block.git] / sound / mips / hal2.h

/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __HAL2_H
#define __HAL2_H

/*
 *  Driver for HAL2 sound processors
 *  Copyright (c) 1999 Ulf Carlsson <ulfc@bun.falkenberg.se>
 *  Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
 */

#include <linux/types.h>

/* Indirect status register */

#define H2_ISR_TSTATUS		0x01	/* RO: transaction status 1=busy */
#define H2_ISR_USTATUS		0x02	/* RO: utime status bit 1=armed */
#define H2_ISR_QUAD_MODE	0x04	/* codec mode 0=indigo 1=quad */
#define H2_ISR_GLOBAL_RESET_N	0x08	/* chip global reset 0=reset */
#define H2_ISR_CODEC_RESET_N	0x10	/* codec/synth reset 0=reset  */

/* Revision register */

#define H2_REV_AUDIO_PRESENT	0x8000	/* RO: audio present 0=present */
#define H2_REV_BOARD_M		0x7000	/* RO: bits 14:12, board revision */
#define H2_REV_MAJOR_CHIP_M	0x00F0	/* RO: bits 7:4, major chip revision */
#define H2_REV_MINOR_CHIP_M	0x000F	/* RO: bits 3:0, minor chip revision */

/* Indirect address register */

/*
 * Address of indirect internal register to be accessed. A write to this
 * register initiates read or write access to the indirect registers in the
 * HAL2. Note that there af four indirect data registers for write access to
 * registers larger than 16 byte.
 */

#define H2_IAR_TYPE_M		0xF000	/* bits 15:12, type of functional */
					/* block the register resides in */
					/* 1=DMA Port */
					/* 9=Global DMA Control */
					/* 2=Bresenham */
					/* 3=Unix Timer */
#define H2_IAR_NUM_M		0x0F00	/* bits 11:8 instance of the */
					/* blockin which the indirect */
					/* register resides */
					/* If IAR_TYPE_M=DMA Port: */
					/* 1=Synth In */
					/* 2=AES In */
					/* 3=AES Out */
					/* 4=DAC Out */
					/* 5=ADC Out */
					/* 6=Synth Control */
					/* If IAR_TYPE_M=Global DMA Control: */
					/* 1=Control */
					/* If IAR_TYPE_M=Bresenham: */
					/* 1=Bresenham Clock Gen 1 */
					/* 2=Bresenham Clock Gen 2 */
					/* 3=Bresenham Clock Gen 3 */
					/* If IAR_TYPE_M=Unix Timer: */
					/* 1=Unix Timer */
#define H2_IAR_ACCESS_SELECT	0x0080	/* 1=read 0=write */
#define H2_IAR_PARAM		0x000C	/* Parameter Select */
#define H2_IAR_RB_INDEX_M	0x0003	/* Read Back Index */
					/* 00:word0 */
					/* 01:word1 */
					/* 10:word2 */
					/* 11:word3 */
/*
 * HAL2 internal addressing
 *
 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
 * Indirect Data registers. Write the address to the Indirect Address register
 * to transfer the data.
 *
 * We define the H2IR_* to the read address and H2IW_* to the write address and
 * H2I_* to be fields in whatever register is referred to.
 *
 * When we write to indirect registers which are larger than one word (16 bit)
 * we have to fill more than one indirect register before writing. When we read
 * back however we have to read several times, each time with different Read
 * Back Indexes (there are defs for doing this easily).
 */

/*
 * Relay Control
 */
#define H2I_RELAY_C		0x9100
#define H2I_RELAY_C_STATE	0x01		/* state of RELAY pin signal */

/* DMA port enable */

#define H2I_DMA_PORT_EN		0x9104
#define H2I_DMA_PORT_EN_SY_IN	0x01		/* Synth_in DMA port */
#define H2I_DMA_PORT_EN_AESRX	0x02		/* AES receiver DMA port */
#define H2I_DMA_PORT_EN_AESTX	0x04		/* AES transmitter DMA port */
#define H2I_DMA_PORT_EN_CODECTX	0x08		/* CODEC transmit DMA port */
#define H2I_DMA_PORT_EN_CODECR	0x10		/* CODEC receive DMA port */

#define H2I_DMA_END		0x9108 		/* global dma endian select */
#define H2I_DMA_END_SY_IN	0x01		/* Synth_in DMA port */
#define H2I_DMA_END_AESRX	0x02		/* AES receiver DMA port */
#define H2I_DMA_END_AESTX	0x04		/* AES transmitter DMA port */
#define H2I_DMA_END_CODECTX	0x08		/* CODEC transmit DMA port */
#define H2I_DMA_END_CODECR	0x10		/* CODEC receive DMA port */
						/* 0=b_end 1=l_end */

#define H2I_DMA_DRV		0x910C  	/* global PBUS DMA enable */

#define H2I_SYNTH_C		0x1104		/* Synth DMA control */

#define H2I_AESRX_C		0x1204	 	/* AES RX dma control */

#define H2I_C_TS_EN		0x20		/* Timestamp enable */
#define H2I_C_TS_FRMT		0x40		/* Timestamp format */
#define H2I_C_NAUDIO		0x80		/* Sign extend */

/* AESRX CTL, 16 bit */

#define H2I_AESTX_C		0x1304		/* AES TX DMA control */
#define H2I_AESTX_C_CLKID_SHIFT	3		/* Bresenham Clock Gen 1-3 */
#define H2I_AESTX_C_CLKID_M	0x18
#define H2I_AESTX_C_DATAT_SHIFT	8		/* 1=mono 2=stereo (3=quad) */
#define H2I_AESTX_C_DATAT_M	0x300

/* CODEC registers */

#define H2I_DAC_C1		0x1404 		/* DAC DMA control, 16 bit */
#define H2I_DAC_C2		0x1408		/* DAC DMA control, 32 bit */
#define H2I_ADC_C1		0x1504 		/* ADC DMA control, 16 bit */
#define H2I_ADC_C2		0x1508		/* ADC DMA control, 32 bit */

/* Bits in CTL1 register */

#define H2I_C1_DMA_SHIFT	0		/* DMA channel */
#define H2I_C1_DMA_M		0x7
#define H2I_C1_CLKID_SHIFT	3		/* Bresenham Clock Gen 1-3 */
#define H2I_C1_CLKID_M		0x18
#define H2I_C1_DATAT_SHIFT	8		/* 1=mono 2=stereo (3=quad) */
#define H2I_C1_DATAT_M		0x300

/* Bits in CTL2 register */

#define H2I_C2_R_GAIN_SHIFT	0		/* right a/d input gain */
#define H2I_C2_R_GAIN_M		0xf
#define H2I_C2_L_GAIN_SHIFT	4		/* left a/d input gain */
#define H2I_C2_L_GAIN_M		0xf0
#define H2I_C2_R_SEL		0x100		/* right input select */
#define H2I_C2_L_SEL		0x200		/* left input select */
#define H2I_C2_MUTE		0x400		/* mute */
#define H2I_C2_DO1		0x00010000	/* digital output port bit 0 */
#define H2I_C2_DO2		0x00020000	/* digital output port bit 1 */
#define H2I_C2_R_ATT_SHIFT	18		/* right d/a output - */
#define H2I_C2_R_ATT_M		0x007c0000	/* attenuation */
#define H2I_C2_L_ATT_SHIFT	23		/* left d/a output - */
#define H2I_C2_L_ATT_M		0x0f800000	/* attenuation */

#define H2I_SYNTH_MAP_C		0x1104		/* synth dma handshake ctrl */

/* Clock generator CTL 1, 16 bit */

#define H2I_BRES1_C1		0x2104
#define H2I_BRES2_C1		0x2204
#define H2I_BRES3_C1		0x2304

#define H2I_BRES_C1_SHIFT	0		/* 0=48.0 1=44.1 2=aes_rx */
#define H2I_BRES_C1_M		0x03

/* Clock generator CTL 2, 32 bit */

#define H2I_BRES1_C2		0x2108
#define H2I_BRES2_C2		0x2208
#define H2I_BRES3_C2		0x2308

#define H2I_BRES_C2_INC_SHIFT	0		/* increment value */
#define H2I_BRES_C2_INC_M	0xffff
#define H2I_BRES_C2_MOD_SHIFT	16		/* modcontrol value */
#define H2I_BRES_C2_MOD_M	0xffff0000	/* modctrl=0xffff&(modinc-1) */

/* Unix timer, 64 bit */

#define H2I_UTIME		0x3104
#define H2I_UTIME_0_LD		0xffff		/* microseconds, LSB's */
#define H2I_UTIME_1_LD0		0x0f		/* microseconds, MSB's */
#define H2I_UTIME_1_LD1		0xf0		/* tenths of microseconds */
#define H2I_UTIME_2_LD		0xffff		/* seconds, LSB's */
#define H2I_UTIME_3_LD		0xffff		/* seconds, MSB's */

struct hal2_ctl_regs {
	u32 _unused0[4];
	u32 isr;		/* 0x10 Status Register */
	u32 _unused1[3];
	u32 rev;		/* 0x20 Revision Register */
	u32 _unused2[3];
	u32 iar;		/* 0x30 Indirect Address Register */
	u32 _unused3[3];
	u32 idr0;		/* 0x40 Indirect Data Register 0 */
	u32 _unused4[3];
	u32 idr1;		/* 0x50 Indirect Data Register 1 */
	u32 _unused5[3];
	u32 idr2;		/* 0x60 Indirect Data Register 2 */
	u32 _unused6[3];
	u32 idr3;		/* 0x70 Indirect Data Register 3 */
};

struct hal2_aes_regs {
	u32 rx_stat[2];	/* Status registers */
	u32 rx_cr[2];		/* Control registers */
	u32 rx_ud[4];		/* User data window */
	u32 rx_st[24];		/* Channel status data */

	u32 tx_stat[1];	/* Status register */
	u32 tx_cr[3];		/* Control registers */
	u32 tx_ud[4];		/* User data window */
	u32 tx_st[24];		/* Channel status data */
};

struct hal2_vol_regs {
	u32 right;		/* Right volume */
	u32 left;		/* Left volume */
};

struct hal2_syn_regs {
	u32 _unused0[2];
	u32 page;		/* DOC Page register */
	u32 regsel;		/* DOC Register selection */
	u32 dlow;		/* DOC Data low */
	u32 dhigh;		/* DOC Data high */
	u32 irq;		/* IRQ Status */
	u32 dram;		/* DRAM Access */
};

#endif	/* __HAL2_H */
Commit	Line	Data
82c29810	1	/* SPDX-License-Identifier: GPL-2.0-only */
787dba37 TB	2	#ifndef __HAL2_H
	3	#define __HAL2_H
	4
	5	/*
	6	* Driver for HAL2 sound processors
	7	* Copyright (c) 1999 Ulf Carlsson <ulfc@bun.falkenberg.se>
	8	* Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
787dba37 TB	9	*/
	10
	11	#include <linux/types.h>
	12
	13	/* Indirect status register */
	14
	15	#define H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */
	16	#define H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */
	17	#define H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */
	18	#define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */
	19	#define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */
	20
	21	/* Revision register */
	22
	23	#define H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */
	24	#define H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */
	25	#define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */
	26	#define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */
	27
	28	/* Indirect address register */
	29
	30	/*
	31	* Address of indirect internal register to be accessed. A write to this
	32	* register initiates read or write access to the indirect registers in the
	33	* HAL2. Note that there af four indirect data registers for write access to
	34	* registers larger than 16 byte.
	35	*/
	36
	37	#define H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */
	38	/* block the register resides in */
	39	/* 1=DMA Port */
	40	/* 9=Global DMA Control */
	41	/* 2=Bresenham */
	42	/* 3=Unix Timer */
	43	#define H2_IAR_NUM_M 0x0F00 /* bits 11:8 instance of the */
	44	/* blockin which the indirect */
	45	/* register resides */
	46	/* If IAR_TYPE_M=DMA Port: */
	47	/* 1=Synth In */
	48	/* 2=AES In */
	49	/* 3=AES Out */
	50	/* 4=DAC Out */
	51	/* 5=ADC Out */
	52	/* 6=Synth Control */
	53	/* If IAR_TYPE_M=Global DMA Control: */
	54	/* 1=Control */
	55	/* If IAR_TYPE_M=Bresenham: */
	56	/* 1=Bresenham Clock Gen 1 */
	57	/* 2=Bresenham Clock Gen 2 */
	58	/* 3=Bresenham Clock Gen 3 */
	59	/* If IAR_TYPE_M=Unix Timer: */
	60	/* 1=Unix Timer */
	61	#define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */
	62	#define H2_IAR_PARAM 0x000C /* Parameter Select */
	63	#define H2_IAR_RB_INDEX_M 0x0003 /* Read Back Index */
	64	/* 00:word0 */
	65	/* 01:word1 */
	66	/* 10:word2 */
	67	/* 11:word3 */
	68	/*
	69	* HAL2 internal addressing
	70	*
	71	* The HAL2 has "indirect registers" (idr) which are accessed by writing to the
	72	* Indirect Data registers. Write the address to the Indirect Address register
73	* to transfer the data.
74	*
75	* We define the H2IR_* to the read address and H2IW_* to the write address and
76	* H2I_* to be fields in whatever register is referred to.
77	*
78	* When we write to indirect registers which are larger than one word (16 bit)
79	* we have to fill more than one indirect register before writing. When we read
80	* back however we have to read several times, each time with different Read
81	* Back Indexes (there are defs for doing this easily).
82	*/
83
84	/*
85	* Relay Control
86	*/
87	#define H2I_RELAY_C 0x9100
88	#define H2I_RELAY_C_STATE 0x01 /* state of RELAY pin signal */
89
90	/* DMA port enable */
91
92	#define H2I_DMA_PORT_EN 0x9104
93	#define H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */
94	#define H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */
95	#define H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */
96	#define H2I_DMA_PORT_EN_CODECTX 0x08 /* CODEC transmit DMA port */
97	#define H2I_DMA_PORT_EN_CODECR 0x10 /* CODEC receive DMA port */
98
99	#define H2I_DMA_END 0x9108 /* global dma endian select */
100	#define H2I_DMA_END_SY_IN 0x01 /* Synth_in DMA port */
101	#define H2I_DMA_END_AESRX 0x02 /* AES receiver DMA port */
102	#define H2I_DMA_END_AESTX 0x04 /* AES transmitter DMA port */
103	#define H2I_DMA_END_CODECTX 0x08 /* CODEC transmit DMA port */
104	#define H2I_DMA_END_CODECR 0x10 /* CODEC receive DMA port */
105	/* 0=b_end 1=l_end */
106
107	#define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */
108
109	#define H2I_SYNTH_C 0x1104 /* Synth DMA control */
110
111	#define H2I_AESRX_C 0x1204 /* AES RX dma control */
112
113	#define H2I_C_TS_EN 0x20 /* Timestamp enable */
114	#define H2I_C_TS_FRMT 0x40 /* Timestamp format */
115	#define H2I_C_NAUDIO 0x80 /* Sign extend */
116
117	/* AESRX CTL, 16 bit */
118
119	#define H2I_AESTX_C 0x1304 /* AES TX DMA control */
120	#define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
121	#define H2I_AESTX_C_CLKID_M 0x18
122	#define H2I_AESTX_C_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
123	#define H2I_AESTX_C_DATAT_M 0x300
124
125	/* CODEC registers */
126
127	#define H2I_DAC_C1 0x1404 /* DAC DMA control, 16 bit */
128	#define H2I_DAC_C2 0x1408 /* DAC DMA control, 32 bit */
129	#define H2I_ADC_C1 0x1504 /* ADC DMA control, 16 bit */
130	#define H2I_ADC_C2 0x1508 /* ADC DMA control, 32 bit */
131
132	/* Bits in CTL1 register */
133
134	#define H2I_C1_DMA_SHIFT 0 /* DMA channel */
135	#define H2I_C1_DMA_M 0x7
136	#define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
137	#define H2I_C1_CLKID_M 0x18
138	#define H2I_C1_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
139	#define H2I_C1_DATAT_M 0x300
140
141	/* Bits in CTL2 register */
142
143	#define H2I_C2_R_GAIN_SHIFT 0 /* right a/d input gain */
144	#define H2I_C2_R_GAIN_M 0xf
145	#define H2I_C2_L_GAIN_SHIFT 4 /* left a/d input gain */
146	#define H2I_C2_L_GAIN_M 0xf0
147	#define H2I_C2_R_SEL 0x100 /* right input select */
148	#define H2I_C2_L_SEL 0x200 /* left input select */
149	#define H2I_C2_MUTE 0x400 /* mute */
150	#define H2I_C2_DO1 0x00010000 /* digital output port bit 0 */
151	#define H2I_C2_DO2 0x00020000 /* digital output port bit 1 */
152	#define H2I_C2_R_ATT_SHIFT 18 /* right d/a output - */
153	#define H2I_C2_R_ATT_M 0x007c0000 /* attenuation */
154	#define H2I_C2_L_ATT_SHIFT 23 /* left d/a output - */
155	#define H2I_C2_L_ATT_M 0x0f800000 /* attenuation */
156
157	#define H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */
158
159	/* Clock generator CTL 1, 16 bit */
160
161	#define H2I_BRES1_C1 0x2104
162	#define H2I_BRES2_C1 0x2204
163	#define H2I_BRES3_C1 0x2304
164
165	#define H2I_BRES_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
166	#define H2I_BRES_C1_M 0x03
167
168	/* Clock generator CTL 2, 32 bit */
169
170	#define H2I_BRES1_C2 0x2108
171	#define H2I_BRES2_C2 0x2208
172	#define H2I_BRES3_C2 0x2308
173
174	#define H2I_BRES_C2_INC_SHIFT 0 /* increment value */
175	#define H2I_BRES_C2_INC_M 0xffff
176	#define H2I_BRES_C2_MOD_SHIFT 16 /* modcontrol value */
177	#define H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
178
179	/* Unix timer, 64 bit */
180
181	#define H2I_UTIME 0x3104
182	#define H2I_UTIME_0_LD 0xffff /* microseconds, LSB's */
183	#define H2I_UTIME_1_LD0 0x0f /* microseconds, MSB's */
184	#define H2I_UTIME_1_LD1 0xf0 /* tenths of microseconds */
185	#define H2I_UTIME_2_LD 0xffff /* seconds, LSB's */
186	#define H2I_UTIME_3_LD 0xffff /* seconds, MSB's */
187
188	struct hal2_ctl_regs {
189	u32 _unused0[4];
190	u32 isr; /* 0x10 Status Register */
191	u32 _unused1[3];
192	u32 rev; /* 0x20 Revision Register */
193	u32 _unused2[3];
194	u32 iar; /* 0x30 Indirect Address Register */
195	u32 _unused3[3];
196	u32 idr0; /* 0x40 Indirect Data Register 0 */
197	u32 _unused4[3];
198	u32 idr1; /* 0x50 Indirect Data Register 1 */
199	u32 _unused5[3];
200	u32 idr2; /* 0x60 Indirect Data Register 2 */
201	u32 _unused6[3];
202	u32 idr3; /* 0x70 Indirect Data Register 3 */
203	};
204
205	struct hal2_aes_regs {
206	u32 rx_stat[2]; /* Status registers */
207	u32 rx_cr[2]; /* Control registers */
208	u32 rx_ud[4]; /* User data window */
209	u32 rx_st[24]; /* Channel status data */
210
211	u32 tx_stat[1]; /* Status register */
212	u32 tx_cr[3]; /* Control registers */
213	u32 tx_ud[4]; /* User data window */
214	u32 tx_st[24]; /* Channel status data */
215	};
216
217	struct hal2_vol_regs {
218	u32 right; /* Right volume */
219	u32 left; /* Left volume */
220	};
221
222	struct hal2_syn_regs {
223	u32 _unused0[2];
224	u32 page; /* DOC Page register */
225	u32 regsel; /* DOC Register selection */
226	u32 dlow; /* DOC Data low */
227	u32 dhigh; /* DOC Data high */
228	u32 irq; /* IRQ Status */
229	u32 dram; /* DRAM Access */
230	};
231
232	#endif /* __HAL2_H */