[linux-block.git] / sound / i2c / cs8427.c

/*
 *  Routines for control of the CS8427 via i2c bus
 *  IEC958 (S/PDIF) receiver & transmitter by Cirrus Logic
 *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>
 *
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 */

#include <sound/driver.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/pcm.h>
#include <sound/cs8427.h>
#include <sound/asoundef.h>

static void snd_cs8427_reset(struct snd_i2c_device *cs8427);

MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
MODULE_DESCRIPTION("IEC958 (S/PDIF) receiver & transmitter by Cirrus Logic");
MODULE_LICENSE("GPL");

#define CS8427_ADDR			(0x20>>1) /* fixed address */

struct cs8427_stream {
	struct snd_pcm_substream *substream;
	char hw_status[24];		/* hardware status */
	char def_status[24];		/* default status */
	char pcm_status[24];		/* PCM private status */
	char hw_udata[32];
	struct snd_kcontrol *pcm_ctl;
};

struct cs8427 {
	unsigned char regmap[0x14];	/* map of first 1 + 13 registers */
	unsigned int rate;
	unsigned int reset_timeout;
	struct cs8427_stream playback;
	struct cs8427_stream capture;
};

static unsigned char swapbits(unsigned char val)
{
	int bit;
	unsigned char res = 0;
	for (bit = 0; bit < 8; bit++) {
		res <<= 1;
		res |= val & 1;
		val >>= 1;
	}
	return res;
}

int snd_cs8427_reg_write(struct snd_i2c_device *device, unsigned char reg,
			 unsigned char val)
{
	int err;
	unsigned char buf[2];

	buf[0] = reg & 0x7f;
	buf[1] = val;
	if ((err = snd_i2c_sendbytes(device, buf, 2)) != 2) {
		snd_printk(KERN_ERR "unable to send bytes 0x%02x:0x%02x to CS8427 (%i)\n", buf[0], buf[1], err);
		return err < 0 ? err : -EIO;
	}
	return 0;
}

static int snd_cs8427_reg_read(struct snd_i2c_device *device, unsigned char reg)
{
	int err;
	unsigned char buf;

	if ((err = snd_i2c_sendbytes(device, &reg, 1)) != 1) {
		snd_printk(KERN_ERR "unable to send register 0x%x byte to CS8427\n", reg);
		return err < 0 ? err : -EIO;
	}
	if ((err = snd_i2c_readbytes(device, &buf, 1)) != 1) {
		snd_printk(KERN_ERR "unable to read register 0x%x byte from CS8427\n", reg);
		return err < 0 ? err : -EIO;
	}
	return buf;
}

static int snd_cs8427_select_corudata(struct snd_i2c_device *device, int udata)
{
	struct cs8427 *chip = device->private_data;
	int err;

	udata = udata ? CS8427_BSEL : 0;
	if (udata != (chip->regmap[CS8427_REG_CSDATABUF] & udata)) {
		chip->regmap[CS8427_REG_CSDATABUF] &= ~CS8427_BSEL;
		chip->regmap[CS8427_REG_CSDATABUF] |= udata;
		err = snd_cs8427_reg_write(device, CS8427_REG_CSDATABUF,
					   chip->regmap[CS8427_REG_CSDATABUF]);
		if (err < 0)
			return err;
	}
	return 0;
}

static int snd_cs8427_send_corudata(struct snd_i2c_device *device,
				    int udata,
				    unsigned char *ndata,
				    int count)
{
	struct cs8427 *chip = device->private_data;
	char *hw_data = udata ? chip->playback.hw_udata : chip->playback.hw_status;
	char data[32];
	int err, idx;

	if (!memcmp(hw_data, ndata, count))
		return 0;
	if ((err = snd_cs8427_select_corudata(device, udata)) < 0)
		return err;
	memcpy(hw_data, ndata, count);
	if (udata) {
		memset(data, 0, sizeof(data));
		if (memcmp(hw_data, data, count) == 0) {
			chip->regmap[CS8427_REG_UDATABUF] &= ~CS8427_UBMMASK;
			chip->regmap[CS8427_REG_UDATABUF] |= CS8427_UBMZEROS | CS8427_EFTUI;
			if ((err = snd_cs8427_reg_write(device, CS8427_REG_UDATABUF,
							chip->regmap[CS8427_REG_UDATABUF])) < 0)
				return err;
			return 0;
		}
	}
	data[0] = CS8427_REG_AUTOINC | CS8427_REG_CORU_DATABUF;
	for (idx = 0; idx < count; idx++)
		data[idx + 1] = swapbits(ndata[idx]);
	if (snd_i2c_sendbytes(device, data, count + 1) != count + 1)
		return -EIO;
	return 1;
}

static void snd_cs8427_free(struct snd_i2c_device *device)
{
	kfree(device->private_data);
}

int snd_cs8427_create(struct snd_i2c_bus *bus,
		      unsigned char addr,
		      unsigned int reset_timeout,
		      struct snd_i2c_device **r_cs8427)
{
	static unsigned char initvals1[] = {
	  CS8427_REG_CONTROL1 | CS8427_REG_AUTOINC,
	  /* CS8427_REG_CONTROL1: RMCK to OMCK, valid PCM audio, disable mutes, TCBL=output */
	  CS8427_SWCLK | CS8427_TCBLDIR,
	  /* CS8427_REG_CONTROL2: hold last valid audio sample, RMCK=256*Fs, normal stereo operation */
	  0x00,
	  /* CS8427_REG_DATAFLOW: output drivers normal operation, Tx<=serial, Rx=>serial */
	  CS8427_TXDSERIAL | CS8427_SPDAES3RECEIVER,
	  /* CS8427_REG_CLOCKSOURCE: Run off, CMCK=256*Fs, output time base = OMCK, input time base =
	     recovered input clock, recovered input clock source is ILRCK changed to AES3INPUT (workaround, see snd_cs8427_reset) */
	  CS8427_RXDILRCK,
	  /* CS8427_REG_SERIALINPUT: Serial audio input port data format = I2S, 24-bit, 64*Fsi */
	  CS8427_SIDEL | CS8427_SILRPOL,
	  /* CS8427_REG_SERIALOUTPUT: Serial audio output port data format = I2S, 24-bit, 64*Fsi */
	  CS8427_SODEL | CS8427_SOLRPOL,
	};
	static unsigned char initvals2[] = {
	  CS8427_REG_RECVERRMASK | CS8427_REG_AUTOINC,
	  /* CS8427_REG_RECVERRMASK: unmask the input PLL clock, V, confidence, biphase, parity status bits */
	  /* CS8427_UNLOCK | CS8427_V | CS8427_CONF | CS8427_BIP | CS8427_PAR, */
	  0xff, /* set everything */
	  /* CS8427_REG_CSDATABUF:
	     Registers 32-55 window to CS buffer
	     Inhibit D->E transfers from overwriting first 5 bytes of CS data.
	     Inhibit D->E transfers (all) of CS data.
	     Allow E->F transfer of CS data.
	     One byte mode; both A/B channels get same written CB data.
	     A channel info is output to chip's EMPH* pin. */
	  CS8427_CBMR | CS8427_DETCI,
	  /* CS8427_REG_UDATABUF:
	     Use internal buffer to transmit User (U) data.
	     Chip's U pin is an output.
	     Transmit all O's for user data.
	     Inhibit D->E transfers.
	     Inhibit E->F transfers. */
	  CS8427_UD | CS8427_EFTUI | CS8427_DETUI,
	};
	int err;
	struct cs8427 *chip;
	struct snd_i2c_device *device;
	unsigned char buf[24];

	if ((err = snd_i2c_device_create(bus, "CS8427", CS8427_ADDR | (addr & 7),
					 &device)) < 0)
		return err;
	chip = device->private_data = kzalloc(sizeof(*chip), GFP_KERNEL);
	if (chip == NULL) {
	      	snd_i2c_device_free(device);
		return -ENOMEM;
	}
	device->private_free = snd_cs8427_free;
	
	snd_i2c_lock(bus);
	if ((err = snd_cs8427_reg_read(device, CS8427_REG_ID_AND_VER)) !=
	    CS8427_VER8427A) {
		snd_i2c_unlock(bus);
		snd_printk(KERN_ERR "unable to find CS8427 signature "
			   "(expected 0x%x, read 0x%x),\n",
			   CS8427_VER8427A, err);
		snd_printk(KERN_ERR "   initialization is not completed\n");
		return -EFAULT;
	}
	/* turn off run bit while making changes to configuration */
	if ((err = snd_cs8427_reg_write(device, CS8427_REG_CLOCKSOURCE, 0x00)) < 0)
		goto __fail;
	/* send initial values */
	memcpy(chip->regmap + (initvals1[0] & 0x7f), initvals1 + 1, 6);
	if ((err = snd_i2c_sendbytes(device, initvals1, 7)) != 7) {
		err = err < 0 ? err : -EIO;
		goto __fail;
	}
	/* Turn off CS8427 interrupt stuff that is not used in hardware */
	memset(buf, 0, 7);
	/* from address 9 to 15 */
	buf[0] = 9;	/* register */
	if ((err = snd_i2c_sendbytes(device, buf, 7)) != 7)
		goto __fail;
	/* send transfer initialization sequence */
	memcpy(chip->regmap + (initvals2[0] & 0x7f), initvals2 + 1, 3);
	if ((err = snd_i2c_sendbytes(device, initvals2, 4)) != 4) {
		err = err < 0 ? err : -EIO;
		goto __fail;
	}
	/* write default channel status bytes */
	buf[0] = ((unsigned char)(SNDRV_PCM_DEFAULT_CON_SPDIF >> 0));
	buf[1] = ((unsigned char)(SNDRV_PCM_DEFAULT_CON_SPDIF >> 8));
	buf[2] = ((unsigned char)(SNDRV_PCM_DEFAULT_CON_SPDIF >> 16));
	buf[3] = ((unsigned char)(SNDRV_PCM_DEFAULT_CON_SPDIF >> 24));
	memset(buf + 4, 0, 24 - 4);
	if (snd_cs8427_send_corudata(device, 0, buf, 24) < 0)
		goto __fail;
	memcpy(chip->playback.def_status, buf, 24);
	memcpy(chip->playback.pcm_status, buf, 24);
	snd_i2c_unlock(bus);

	/* turn on run bit and rock'n'roll */
	if (reset_timeout < 1)
		reset_timeout = 1;
	chip->reset_timeout = reset_timeout;
	snd_cs8427_reset(device);

#if 0	// it's nice for read tests
	{
	char buf[128];
	int xx;
	buf[0] = 0x81;
	snd_i2c_sendbytes(device, buf, 1);
	snd_i2c_readbytes(device, buf, 127);
	for (xx = 0; xx < 127; xx++)
		printk(KERN_DEBUG "reg[0x%x] = 0x%x\n", xx+1, buf[xx]);
	}
#endif
	
	if (r_cs8427)
		*r_cs8427 = device;
	return 0;

      __fail:
      	snd_i2c_unlock(bus);
      	snd_i2c_device_free(device);
      	return err < 0 ? err : -EIO;
}

/*
 * Reset the chip using run bit, also lock PLL using ILRCK and
 * put back AES3INPUT. This workaround is described in latest
 * CS8427 datasheet, otherwise TXDSERIAL will not work.
 */
static void snd_cs8427_reset(struct snd_i2c_device *cs8427)
{
	struct cs8427 *chip;
	unsigned long end_time;
	int data, aes3input = 0;

	snd_assert(cs8427, return);
	chip = cs8427->private_data;
	snd_i2c_lock(cs8427->bus);
	if ((chip->regmap[CS8427_REG_CLOCKSOURCE] & CS8427_RXDAES3INPUT) == CS8427_RXDAES3INPUT)  /* AES3 bit is set */
		aes3input = 1;
	chip->regmap[CS8427_REG_CLOCKSOURCE] &= ~(CS8427_RUN | CS8427_RXDMASK);
	snd_cs8427_reg_write(cs8427, CS8427_REG_CLOCKSOURCE,
			     chip->regmap[CS8427_REG_CLOCKSOURCE]);
	udelay(200);
	chip->regmap[CS8427_REG_CLOCKSOURCE] |= CS8427_RUN | CS8427_RXDILRCK;
	snd_cs8427_reg_write(cs8427, CS8427_REG_CLOCKSOURCE,
			     chip->regmap[CS8427_REG_CLOCKSOURCE]);
	udelay(200);
	snd_i2c_unlock(cs8427->bus);
	end_time = jiffies + chip->reset_timeout;
	while (time_after_eq(end_time, jiffies)) {
		snd_i2c_lock(cs8427->bus);
		data = snd_cs8427_reg_read(cs8427, CS8427_REG_RECVERRORS);
		snd_i2c_unlock(cs8427->bus);
		if (!(data & CS8427_UNLOCK))
			break;
		schedule_timeout_uninterruptible(1);
	}
	snd_i2c_lock(cs8427->bus);
	chip->regmap[CS8427_REG_CLOCKSOURCE] &= ~CS8427_RXDMASK;
	if (aes3input)
		chip->regmap[CS8427_REG_CLOCKSOURCE] |= CS8427_RXDAES3INPUT;
	snd_cs8427_reg_write(cs8427, CS8427_REG_CLOCKSOURCE,
			     chip->regmap[CS8427_REG_CLOCKSOURCE]);
	snd_i2c_unlock(cs8427->bus);
}

static int snd_cs8427_in_status_info(struct snd_kcontrol *kcontrol,
				     struct snd_ctl_elem_info *uinfo)
{
	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	uinfo->count = 1;
	uinfo->value.integer.min = 0;
	uinfo->value.integer.max = 255;
	return 0;
}

static int snd_cs8427_in_status_get(struct snd_kcontrol *kcontrol,
				    struct snd_ctl_elem_value *ucontrol)
{
	struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
	int data;

	snd_i2c_lock(device->bus);
	data = snd_cs8427_reg_read(device, kcontrol->private_value);
	snd_i2c_unlock(device->bus);
	if (data < 0)
		return data;
	ucontrol->value.integer.value[0] = data;
	return 0;
}

static int snd_cs8427_qsubcode_info(struct snd_kcontrol *kcontrol,
				    struct snd_ctl_elem_info *uinfo)
{
	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
	uinfo->count = 10;
	return 0;
}

static int snd_cs8427_qsubcode_get(struct snd_kcontrol *kcontrol,
				   struct snd_ctl_elem_value *ucontrol)
{
	struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
	unsigned char reg = CS8427_REG_QSUBCODE;
	int err;

	snd_i2c_lock(device->bus);
	if ((err = snd_i2c_sendbytes(device, &reg, 1)) != 1) {
		snd_printk(KERN_ERR "unable to send register 0x%x byte to CS8427\n", reg);
		snd_i2c_unlock(device->bus);
		return err < 0 ? err : -EIO;
	}
	if ((err = snd_i2c_readbytes(device, ucontrol->value.bytes.data, 10)) != 10) {
		snd_printk(KERN_ERR "unable to read Q-subcode bytes from CS8427\n");
		snd_i2c_unlock(device->bus);
		return err < 0 ? err : -EIO;
	}
	snd_i2c_unlock(device->bus);
	return 0;
}

static int snd_cs8427_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
	uinfo->count = 1;
	return 0;
}

static int snd_cs8427_spdif_get(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
	struct cs8427 *chip = device->private_data;
	
	snd_i2c_lock(device->bus);
	memcpy(ucontrol->value.iec958.status, chip->playback.def_status, 24);
	snd_i2c_unlock(device->bus);
	return 0;
}

static int snd_cs8427_spdif_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
	struct cs8427 *chip = device->private_data;
	unsigned char *status = kcontrol->private_value ?
		chip->playback.pcm_status : chip->playback.def_status;
	struct snd_pcm_runtime *runtime = chip->playback.substream ?
		chip->playback.substream->runtime : NULL;
	int err, change;

	snd_i2c_lock(device->bus);
	change = memcmp(ucontrol->value.iec958.status, status, 24) != 0;
	memcpy(status, ucontrol->value.iec958.status, 24);
	if (change && (kcontrol->private_value ? runtime != NULL : runtime == NULL)) {
		err = snd_cs8427_send_corudata(device, 0, status, 24);
		if (err < 0)
			change = err;
	}
	snd_i2c_unlock(device->bus);
	return change;
}

static int snd_cs8427_spdif_mask_info(struct snd_kcontrol *kcontrol,
				      struct snd_ctl_elem_info *uinfo)
{
	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
	uinfo->count = 1;
	return 0;
}

static int snd_cs8427_spdif_mask_get(struct snd_kcontrol *kcontrol,
				      struct snd_ctl_elem_value *ucontrol)
{
	memset(ucontrol->value.iec958.status, 0xff, 24);
	return 0;
}

static struct snd_kcontrol_new snd_cs8427_iec958_controls[] = {
{
	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
	.info =		snd_cs8427_in_status_info,
	.name =		"IEC958 CS8427 Input Status",
	.access =	SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
	.get =		snd_cs8427_in_status_get,
	.private_value = 15,
},
{
	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
	.info =		snd_cs8427_in_status_info,
	.name =		"IEC958 CS8427 Error Status",
	.access =	SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
	.get =		snd_cs8427_in_status_get,
	.private_value = 16,
},
{
	.access =	SNDRV_CTL_ELEM_ACCESS_READ,
	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
	.info =		snd_cs8427_spdif_mask_info,
	.get =		snd_cs8427_spdif_mask_get,
},
{
	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
	.info =		snd_cs8427_spdif_info,
	.get =		snd_cs8427_spdif_get,
	.put =		snd_cs8427_spdif_put,
	.private_value = 0
},
{
	.access =	SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
	.info =		snd_cs8427_spdif_info,
	.get =		snd_cs8427_spdif_get,
	.put =		snd_cs8427_spdif_put,
	.private_value = 1
},
{
	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
	.info =		snd_cs8427_qsubcode_info,
	.name =		"IEC958 Q-subcode Capture Default",
	.access =	SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
	.get =		snd_cs8427_qsubcode_get
}};

int snd_cs8427_iec958_build(struct snd_i2c_device *cs8427,
			    struct snd_pcm_substream *play_substream,
			    struct snd_pcm_substream *cap_substream)
{
	struct cs8427 *chip = cs8427->private_data;
	struct snd_kcontrol *kctl;
	unsigned int idx;
	int err;

	snd_assert(play_substream && cap_substream, return -EINVAL);
	for (idx = 0; idx < ARRAY_SIZE(snd_cs8427_iec958_controls); idx++) {
		kctl = snd_ctl_new1(&snd_cs8427_iec958_controls[idx], cs8427);
		if (kctl == NULL)
			return -ENOMEM;
		kctl->id.device = play_substream->pcm->device;
		kctl->id.subdevice = play_substream->number;
		err = snd_ctl_add(cs8427->bus->card, kctl);
		if (err < 0)
			return err;
		if (!strcmp(kctl->id.name, SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM)))
			chip->playback.pcm_ctl = kctl;
	}

	chip->playback.substream = play_substream;
	chip->capture.substream = cap_substream;
	snd_assert(chip->playback.pcm_ctl, return -EIO);
	return 0;
}

int snd_cs8427_iec958_active(struct snd_i2c_device *cs8427, int active)
{
	struct cs8427 *chip;

	snd_assert(cs8427, return -ENXIO);
	chip = cs8427->private_data;
	if (active)
		memcpy(chip->playback.pcm_status, chip->playback.def_status, 24);
	chip->playback.pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
	snd_ctl_notify(cs8427->bus->card, SNDRV_CTL_EVENT_MASK_VALUE |
					  SNDRV_CTL_EVENT_MASK_INFO, &chip->playback.pcm_ctl->id);
	return 0;
}

int snd_cs8427_iec958_pcm(struct snd_i2c_device *cs8427, unsigned int rate)
{
	struct cs8427 *chip;
	char *status;
	int err, reset;

	snd_assert(cs8427, return -ENXIO);
	chip = cs8427->private_data;
	status = chip->playback.pcm_status;
	snd_i2c_lock(cs8427->bus);
	if (status[0] & IEC958_AES0_PROFESSIONAL) {
		status[0] &= ~IEC958_AES0_PRO_FS;
		switch (rate) {
		case 32000: status[0] |= IEC958_AES0_PRO_FS_32000; break;
		case 44100: status[0] |= IEC958_AES0_PRO_FS_44100; break;
		case 48000: status[0] |= IEC958_AES0_PRO_FS_48000; break;
		default: status[0] |= IEC958_AES0_PRO_FS_NOTID; break;
		}
	} else {
		status[3] &= ~IEC958_AES3_CON_FS;
		switch (rate) {
		case 32000: status[3] |= IEC958_AES3_CON_FS_32000; break;
		case 44100: status[3] |= IEC958_AES3_CON_FS_44100; break;
		case 48000: status[3] |= IEC958_AES3_CON_FS_48000; break;
		}
	}
	err = snd_cs8427_send_corudata(cs8427, 0, status, 24);
	if (err > 0)
		snd_ctl_notify(cs8427->bus->card,
			       SNDRV_CTL_EVENT_MASK_VALUE,
			       &chip->playback.pcm_ctl->id);
	reset = chip->rate != rate;
	chip->rate = rate;
	snd_i2c_unlock(cs8427->bus);
	if (reset)
		snd_cs8427_reset(cs8427);
	return err < 0 ? err : 0;
}

static int __init alsa_cs8427_module_init(void)
{
	return 0;
}

static void __exit alsa_cs8427_module_exit(void)
{
}

module_init(alsa_cs8427_module_init)
module_exit(alsa_cs8427_module_exit)

EXPORT_SYMBOL(snd_cs8427_create);
EXPORT_SYMBOL(snd_cs8427_reg_write);
EXPORT_SYMBOL(snd_cs8427_iec958_build);
EXPORT_SYMBOL(snd_cs8427_iec958_active);
EXPORT_SYMBOL(snd_cs8427_iec958_pcm);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Routines for control of the CS8427 via i2c bus
	3	* IEC958 (S/PDIF) receiver & transmitter by Cirrus Logic
	4	* Copyright (c) by Jaroslav Kysela <perex@suse.cz>
	5	*
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*
	21	*/
	22
	23	#include <sound/driver.h>
	24	#include <linux/slab.h>
	25	#include <linux/delay.h>
	26	#include <linux/init.h>
	27	#include <sound/core.h>
	28	#include <sound/control.h>
	29	#include <sound/pcm.h>
	30	#include <sound/cs8427.h>
	31	#include <sound/asoundef.h>
	32
97f02e05	33	static void snd_cs8427_reset(struct snd_i2c_device *cs8427);
1da177e4 LT	34
	35	MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
	36	MODULE_DESCRIPTION("IEC958 (S/PDIF) receiver & transmitter by Cirrus Logic");
	37	MODULE_LICENSE("GPL");
	38
	39	#define CS8427_ADDR (0x20>>1) /* fixed address */
	40
97f02e05 TI	41	struct cs8427_stream {
97f02e05 TI	42	struct snd_pcm_substream *substream;
1da177e4 LT	43	char hw_status[24]; /* hardware status */
	44	char def_status[24]; /* default status */
	45	char pcm_status[24]; /* PCM private status */
	46	char hw_udata[32];
97f02e05 TI	47	struct snd_kcontrol *pcm_ctl;
97f02e05 TI	48	};
1da177e4	49
97f02e05	50	struct cs8427 {
1da177e4 LT	51	unsigned char regmap[0x14]; /* map of first 1 + 13 registers */
	52	unsigned int rate;
	53	unsigned int reset_timeout;
97f02e05 TI	54	struct cs8427_stream playback;
	55	struct cs8427_stream capture;
	56	};
1da177e4 LT	57
	58	static unsigned char swapbits(unsigned char val)
	59	{
	60	int bit;
	61	unsigned char res = 0;
	62	for (bit = 0; bit < 8; bit++) {
	63	res <<= 1;
	64	res \|= val & 1;
	65	val >>= 1;
	66	}
	67	return res;
	68	}
	69
97f02e05 TI	70	int snd_cs8427_reg_write(struct snd_i2c_device *device, unsigned char reg,
97f02e05 TI	71	unsigned char val)
1da177e4 LT	72	{
	73	int err;
	74	unsigned char buf[2];
	75
	76	buf[0] = reg & 0x7f;
	77	buf[1] = val;
	78	if ((err = snd_i2c_sendbytes(device, buf, 2)) != 2) {
99b359ba	79	snd_printk(KERN_ERR "unable to send bytes 0x%02x:0x%02x to CS8427 (%i)\n", buf[0], buf[1], err);
1da177e4 LT	80	return err < 0 ? err : -EIO;
	81	}
	82	return 0;
	83	}
	84
97f02e05	85	static int snd_cs8427_reg_read(struct snd_i2c_device *device, unsigned char reg)
1da177e4 LT	86	{
	87	int err;
	88	unsigned char buf;
	89
	90	if ((err = snd_i2c_sendbytes(device, &reg, 1)) != 1) {
99b359ba	91	snd_printk(KERN_ERR "unable to send register 0x%x byte to CS8427\n", reg);
1da177e4 LT	92	return err < 0 ? err : -EIO;
	93	}
	94	if ((err = snd_i2c_readbytes(device, &buf, 1)) != 1) {
99b359ba	95	snd_printk(KERN_ERR "unable to read register 0x%x byte from CS8427\n", reg);
1da177e4 LT	96	return err < 0 ? err : -EIO;
	97	}
	98	return buf;
	99	}
	100
97f02e05	101	static int snd_cs8427_select_corudata(struct snd_i2c_device *device, int udata)
1da177e4	102	{
97f02e05	103	struct cs8427 *chip = device->private_data;
1da177e4 LT	104	int err;
	105
	106	udata = udata ? CS8427_BSEL : 0;
	107	if (udata != (chip->regmap[CS8427_REG_CSDATABUF] & udata)) {
	108	chip->regmap[CS8427_REG_CSDATABUF] &= ~CS8427_BSEL;
	109	chip->regmap[CS8427_REG_CSDATABUF] \|= udata;
97f02e05 TI	110	err = snd_cs8427_reg_write(device, CS8427_REG_CSDATABUF,
97f02e05 TI	111	chip->regmap[CS8427_REG_CSDATABUF]);
1da177e4 LT	112	if (err < 0)
	113	return err;
	114	}
	115	return 0;
	116	}
	117
97f02e05	118	static int snd_cs8427_send_corudata(struct snd_i2c_device *device,
1da177e4 LT	119	int udata,
	120	unsigned char *ndata,
	121	int count)
	122	{
97f02e05	123	struct cs8427 *chip = device->private_data;
1da177e4 LT	124	char *hw_data = udata ? chip->playback.hw_udata : chip->playback.hw_status;
	125	char data[32];
	126	int err, idx;
	127
	128	if (!memcmp(hw_data, ndata, count))
	129	return 0;
	130	if ((err = snd_cs8427_select_corudata(device, udata)) < 0)
	131	return err;
	132	memcpy(hw_data, ndata, count);
	133	if (udata) {
	134	memset(data, 0, sizeof(data));
	135	if (memcmp(hw_data, data, count) == 0) {
	136	chip->regmap[CS8427_REG_UDATABUF] &= ~CS8427_UBMMASK;
	137	chip->regmap[CS8427_REG_UDATABUF] \|= CS8427_UBMZEROS \| CS8427_EFTUI;
97f02e05 TI	138	if ((err = snd_cs8427_reg_write(device, CS8427_REG_UDATABUF,
97f02e05 TI	139	chip->regmap[CS8427_REG_UDATABUF])) < 0)
1da177e4 LT	140	return err;
	141	return 0;
	142	}
	143	}
	144	data[0] = CS8427_REG_AUTOINC \| CS8427_REG_CORU_DATABUF;
	145	for (idx = 0; idx < count; idx++)
	146	data[idx + 1] = swapbits(ndata[idx]);
	147	if (snd_i2c_sendbytes(device, data, count + 1) != count + 1)
	148	return -EIO;
	149	return 1;
	150	}
	151
97f02e05	152	static void snd_cs8427_free(struct snd_i2c_device *device)
1da177e4 LT	153	{
	154	kfree(device->private_data);
	155	}
	156
97f02e05	157	int snd_cs8427_create(struct snd_i2c_bus *bus,
1da177e4 LT	158	unsigned char addr,
1da177e4 LT	159	unsigned int reset_timeout,
97f02e05	160	struct snd_i2c_device **r_cs8427)
1da177e4 LT	161	{
	162	static unsigned char initvals1[] = {
	163	CS8427_REG_CONTROL1 \| CS8427_REG_AUTOINC,
	164	/* CS8427_REG_CONTROL1: RMCK to OMCK, valid PCM audio, disable mutes, TCBL=output */
	165	CS8427_SWCLK \| CS8427_TCBLDIR,
	166	/* CS8427_REG_CONTROL2: hold last valid audio sample, RMCK=256Fs, normal stereo operation /
	167	0x00,
	168	/* CS8427_REG_DATAFLOW: output drivers normal operation, Tx<=serial, Rx=>serial */
	169	CS8427_TXDSERIAL \| CS8427_SPDAES3RECEIVER,
	170	/* CS8427_REG_CLOCKSOURCE: Run off, CMCK=256*Fs, output time base = OMCK, input time base =
	171	recovered input clock, recovered input clock source is ILRCK changed to AES3INPUT (workaround, see snd_cs8427_reset) */
	172	CS8427_RXDILRCK,
	173	/* CS8427_REG_SERIALINPUT: Serial audio input port data format = I2S, 24-bit, 64Fsi /
	174	CS8427_SIDEL \| CS8427_SILRPOL,
	175	/* CS8427_REG_SERIALOUTPUT: Serial audio output port data format = I2S, 24-bit, 64Fsi /
	176	CS8427_SODEL \| CS8427_SOLRPOL,
	177	};
	178	static unsigned char initvals2[] = {
	179	CS8427_REG_RECVERRMASK \| CS8427_REG_AUTOINC,
	180	/* CS8427_REG_RECVERRMASK: unmask the input PLL clock, V, confidence, biphase, parity status bits */
	181	/* CS8427_UNLOCK \| CS8427_V \| CS8427_CONF \| CS8427_BIP \| CS8427_PAR, */
	182	0xff, /* set everything */
	183	/* CS8427_REG_CSDATABUF:
	184	Registers 32-55 window to CS buffer
	185	Inhibit D->E transfers from overwriting first 5 bytes of CS data.
	186	Inhibit D->E transfers (all) of CS data.
	187	Allow E->F transfer of CS data.
	188	One byte mode; both A/B channels get same written CB data.
	189	A channel info is output to chip's EMPH* pin. */
	190	CS8427_CBMR \| CS8427_DETCI,
	191	/* CS8427_REG_UDATABUF:
	192	Use internal buffer to transmit User (U) data.
	193	Chip's U pin is an output.
	194	Transmit all O's for user data.
	195	Inhibit D->E transfers.
	196	Inhibit E->F transfers. */
	197	CS8427_UD \| CS8427_EFTUI \| CS8427_DETUI,
	198	};
	199	int err;
97f02e05 TI	200	struct cs8427 *chip;
97f02e05 TI	201	struct snd_i2c_device *device;
1da177e4 LT	202	unsigned char buf[24];
1da177e4 LT	203
97f02e05 TI	204	if ((err = snd_i2c_device_create(bus, "CS8427", CS8427_ADDR \| (addr & 7),
97f02e05 TI	205	&device)) < 0)
1da177e4	206	return err;
561b220a	207	chip = device->private_data = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4 LT	208	if (chip == NULL) {
	209	snd_i2c_device_free(device);
	210	return -ENOMEM;
	211	}
	212	device->private_free = snd_cs8427_free;
	213
	214	snd_i2c_lock(bus);
97f02e05 TI	215	if ((err = snd_cs8427_reg_read(device, CS8427_REG_ID_AND_VER)) !=
97f02e05 TI	216	CS8427_VER8427A) {
1da177e4	217	snd_i2c_unlock(bus);
97f02e05 TI	218	snd_printk(KERN_ERR "unable to find CS8427 signature "
	219	"(expected 0x%x, read 0x%x),\n",
	220	CS8427_VER8427A, err);
	221	snd_printk(KERN_ERR " initialization is not completed\n");
1da177e4 LT	222	return -EFAULT;
	223	}
	224	/* turn off run bit while making changes to configuration */
	225	if ((err = snd_cs8427_reg_write(device, CS8427_REG_CLOCKSOURCE, 0x00)) < 0)
	226	goto __fail;
	227	/* send initial values */
	228	memcpy(chip->regmap + (initvals1[0] & 0x7f), initvals1 + 1, 6);
	229	if ((err = snd_i2c_sendbytes(device, initvals1, 7)) != 7) {
	230	err = err < 0 ? err : -EIO;
	231	goto __fail;
	232	}
	233	/* Turn off CS8427 interrupt stuff that is not used in hardware */
	234	memset(buf, 0, 7);
	235	/* from address 9 to 15 */
	236	buf[0] = 9; /* register */
	237	if ((err = snd_i2c_sendbytes(device, buf, 7)) != 7)
	238	goto __fail;
	239	/* send transfer initialization sequence */
	240	memcpy(chip->regmap + (initvals2[0] & 0x7f), initvals2 + 1, 3);
	241	if ((err = snd_i2c_sendbytes(device, initvals2, 4)) != 4) {
	242	err = err < 0 ? err : -EIO;
	243	goto __fail;
	244	}
	245	/* write default channel status bytes */
	246	buf[0] = ((unsigned char)(SNDRV_PCM_DEFAULT_CON_SPDIF >> 0));
	247	buf[1] = ((unsigned char)(SNDRV_PCM_DEFAULT_CON_SPDIF >> 8));
	248	buf[2] = ((unsigned char)(SNDRV_PCM_DEFAULT_CON_SPDIF >> 16));
	249	buf[3] = ((unsigned char)(SNDRV_PCM_DEFAULT_CON_SPDIF >> 24));
	250	memset(buf + 4, 0, 24 - 4);
	251	if (snd_cs8427_send_corudata(device, 0, buf, 24) < 0)
	252	goto __fail;
	253	memcpy(chip->playback.def_status, buf, 24);
	254	memcpy(chip->playback.pcm_status, buf, 24);
	255	snd_i2c_unlock(bus);
	256
	257	/* turn on run bit and rock'n'roll */
	258	if (reset_timeout < 1)
	259	reset_timeout = 1;
	260	chip->reset_timeout = reset_timeout;
	261	snd_cs8427_reset(device);
	262
	263	#if 0 // it's nice for read tests
	264	{
	265	char buf[128];
	266	int xx;
	267	buf[0] = 0x81;
	268	snd_i2c_sendbytes(device, buf, 1);
	269	snd_i2c_readbytes(device, buf, 127);
	270	for (xx = 0; xx < 127; xx++)
99b359ba	271	printk(KERN_DEBUG "reg[0x%x] = 0x%x\n", xx+1, buf[xx]);
1da177e4 LT	272	}
	273	#endif
	274
	275	if (r_cs8427)
	276	*r_cs8427 = device;
	277	return 0;
	278
	279	__fail:
	280	snd_i2c_unlock(bus);
	281	snd_i2c_device_free(device);
	282	return err < 0 ? err : -EIO;
	283	}
	284
	285	/*
	286	* Reset the chip using run bit, also lock PLL using ILRCK and
	287	* put back AES3INPUT. This workaround is described in latest
	288	* CS8427 datasheet, otherwise TXDSERIAL will not work.
	289	*/
97f02e05	290	static void snd_cs8427_reset(struct snd_i2c_device *cs8427)
1da177e4	291	{
97f02e05	292	struct cs8427 *chip;
1da177e4	293	unsigned long end_time;
e957ebf1	294	int data, aes3input = 0;
1da177e4 LT	295
	296	snd_assert(cs8427, return);
	297	chip = cs8427->private_data;
	298	snd_i2c_lock(cs8427->bus);
e957ebf1 JK	299	if ((chip->regmap[CS8427_REG_CLOCKSOURCE] & CS8427_RXDAES3INPUT) == CS8427_RXDAES3INPUT) /* AES3 bit is set */
e957ebf1 JK	300	aes3input = 1;
1da177e4	301	chip->regmap[CS8427_REG_CLOCKSOURCE] &= ~(CS8427_RUN \| CS8427_RXDMASK);
97f02e05 TI	302	snd_cs8427_reg_write(cs8427, CS8427_REG_CLOCKSOURCE,
97f02e05 TI	303	chip->regmap[CS8427_REG_CLOCKSOURCE]);
1da177e4 LT	304	udelay(200);
1da177e4 LT	305	chip->regmap[CS8427_REG_CLOCKSOURCE] \|= CS8427_RUN \| CS8427_RXDILRCK;
97f02e05 TI	306	snd_cs8427_reg_write(cs8427, CS8427_REG_CLOCKSOURCE,
97f02e05 TI	307	chip->regmap[CS8427_REG_CLOCKSOURCE]);
1da177e4 LT	308	udelay(200);
	309	snd_i2c_unlock(cs8427->bus);
	310	end_time = jiffies + chip->reset_timeout;
	311	while (time_after_eq(end_time, jiffies)) {
	312	snd_i2c_lock(cs8427->bus);
	313	data = snd_cs8427_reg_read(cs8427, CS8427_REG_RECVERRORS);
	314	snd_i2c_unlock(cs8427->bus);
	315	if (!(data & CS8427_UNLOCK))
	316	break;
8433a509	317	schedule_timeout_uninterruptible(1);
1da177e4 LT	318	}
	319	snd_i2c_lock(cs8427->bus);
	320	chip->regmap[CS8427_REG_CLOCKSOURCE] &= ~CS8427_RXDMASK;
e957ebf1 JK	321	if (aes3input)
e957ebf1 JK	322	chip->regmap[CS8427_REG_CLOCKSOURCE] \|= CS8427_RXDAES3INPUT;
97f02e05 TI	323	snd_cs8427_reg_write(cs8427, CS8427_REG_CLOCKSOURCE,
97f02e05 TI	324	chip->regmap[CS8427_REG_CLOCKSOURCE]);
1da177e4 LT	325	snd_i2c_unlock(cs8427->bus);
	326	}
	327
97f02e05 TI	328	static int snd_cs8427_in_status_info(struct snd_kcontrol *kcontrol,
97f02e05 TI	329	struct snd_ctl_elem_info *uinfo)
1da177e4 LT	330	{
	331	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	332	uinfo->count = 1;
	333	uinfo->value.integer.min = 0;
	334	uinfo->value.integer.max = 255;
	335	return 0;
	336	}
	337
97f02e05 TI	338	static int snd_cs8427_in_status_get(struct snd_kcontrol *kcontrol,
97f02e05 TI	339	struct snd_ctl_elem_value *ucontrol)
1da177e4	340	{
97f02e05	341	struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
1da177e4 LT	342	int data;
	343
	344	snd_i2c_lock(device->bus);
	345	data = snd_cs8427_reg_read(device, kcontrol->private_value);
	346	snd_i2c_unlock(device->bus);
	347	if (data < 0)
	348	return data;
	349	ucontrol->value.integer.value[0] = data;
	350	return 0;
	351	}
	352
97f02e05 TI	353	static int snd_cs8427_qsubcode_info(struct snd_kcontrol *kcontrol,
97f02e05 TI	354	struct snd_ctl_elem_info *uinfo)
1da177e4 LT	355	{
	356	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
	357	uinfo->count = 10;
	358	return 0;
	359	}
	360
97f02e05 TI	361	static int snd_cs8427_qsubcode_get(struct snd_kcontrol *kcontrol,
97f02e05 TI	362	struct snd_ctl_elem_value *ucontrol)
1da177e4	363	{
97f02e05	364	struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
1da177e4 LT	365	unsigned char reg = CS8427_REG_QSUBCODE;
	366	int err;
	367
	368	snd_i2c_lock(device->bus);
	369	if ((err = snd_i2c_sendbytes(device, &reg, 1)) != 1) {
99b359ba	370	snd_printk(KERN_ERR "unable to send register 0x%x byte to CS8427\n", reg);
1da177e4 LT	371	snd_i2c_unlock(device->bus);
	372	return err < 0 ? err : -EIO;
	373	}
	374	if ((err = snd_i2c_readbytes(device, ucontrol->value.bytes.data, 10)) != 10) {
99b359ba	375	snd_printk(KERN_ERR "unable to read Q-subcode bytes from CS8427\n");
1da177e4 LT	376	snd_i2c_unlock(device->bus);
	377	return err < 0 ? err : -EIO;
	378	}
	379	snd_i2c_unlock(device->bus);
	380	return 0;
	381	}
	382
97f02e05	383	static int snd_cs8427_spdif_info(struct snd_kcontrol kcontrol, struct snd_ctl_elem_info uinfo)
1da177e4 LT	384	{
	385	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
	386	uinfo->count = 1;
	387	return 0;
	388	}
	389
97f02e05 TI	390	static int snd_cs8427_spdif_get(struct snd_kcontrol *kcontrol,
97f02e05 TI	391	struct snd_ctl_elem_value *ucontrol)
1da177e4	392	{
97f02e05 TI	393	struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
97f02e05 TI	394	struct cs8427 *chip = device->private_data;
1da177e4 LT	395
	396	snd_i2c_lock(device->bus);
	397	memcpy(ucontrol->value.iec958.status, chip->playback.def_status, 24);
	398	snd_i2c_unlock(device->bus);
	399	return 0;
	400	}
	401
97f02e05 TI	402	static int snd_cs8427_spdif_put(struct snd_kcontrol *kcontrol,
97f02e05 TI	403	struct snd_ctl_elem_value *ucontrol)
1da177e4	404	{
97f02e05 TI	405	struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
	406	struct cs8427 *chip = device->private_data;
	407	unsigned char *status = kcontrol->private_value ?
	408	chip->playback.pcm_status : chip->playback.def_status;
	409	struct snd_pcm_runtime *runtime = chip->playback.substream ?
	410	chip->playback.substream->runtime : NULL;
1da177e4 LT	411	int err, change;
	412
	413	snd_i2c_lock(device->bus);
	414	change = memcmp(ucontrol->value.iec958.status, status, 24) != 0;
	415	memcpy(status, ucontrol->value.iec958.status, 24);
	416	if (change && (kcontrol->private_value ? runtime != NULL : runtime == NULL)) {
	417	err = snd_cs8427_send_corudata(device, 0, status, 24);
	418	if (err < 0)
	419	change = err;
	420	}
	421	snd_i2c_unlock(device->bus);
	422	return change;
	423	}
	424
97f02e05 TI	425	static int snd_cs8427_spdif_mask_info(struct snd_kcontrol *kcontrol,
97f02e05 TI	426	struct snd_ctl_elem_info *uinfo)
1da177e4 LT	427	{
	428	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
	429	uinfo->count = 1;
	430	return 0;
	431	}
	432
97f02e05 TI	433	static int snd_cs8427_spdif_mask_get(struct snd_kcontrol *kcontrol,
97f02e05 TI	434	struct snd_ctl_elem_value *ucontrol)
1da177e4 LT	435	{
	436	memset(ucontrol->value.iec958.status, 0xff, 24);
	437	return 0;
	438	}
	439
97f02e05	440	static struct snd_kcontrol_new snd_cs8427_iec958_controls[] = {
1da177e4 LT	441	{
	442	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
	443	.info = snd_cs8427_in_status_info,
	444	.name = "IEC958 CS8427 Input Status",
	445	.access = SNDRV_CTL_ELEM_ACCESS_READ \| SNDRV_CTL_ELEM_ACCESS_VOLATILE,
	446	.get = snd_cs8427_in_status_get,
	447	.private_value = 15,
	448	},
	449	{
	450	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
	451	.info = snd_cs8427_in_status_info,
	452	.name = "IEC958 CS8427 Error Status",
	453	.access = SNDRV_CTL_ELEM_ACCESS_READ \| SNDRV_CTL_ELEM_ACCESS_VOLATILE,
	454	.get = snd_cs8427_in_status_get,
	455	.private_value = 16,
	456	},
	457	{
	458	.access = SNDRV_CTL_ELEM_ACCESS_READ,
	459	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
	460	.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
	461	.info = snd_cs8427_spdif_mask_info,
	462	.get = snd_cs8427_spdif_mask_get,
	463	},
	464	{
	465	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
	466	.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
	467	.info = snd_cs8427_spdif_info,
	468	.get = snd_cs8427_spdif_get,
	469	.put = snd_cs8427_spdif_put,
	470	.private_value = 0
	471	},
	472	{
	473	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE \| SNDRV_CTL_ELEM_ACCESS_INACTIVE,
	474	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
	475	.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
	476	.info = snd_cs8427_spdif_info,
	477	.get = snd_cs8427_spdif_get,
	478	.put = snd_cs8427_spdif_put,
	479	.private_value = 1
	480	},
	481	{
	482	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
	483	.info = snd_cs8427_qsubcode_info,
	484	.name = "IEC958 Q-subcode Capture Default",
	485	.access = SNDRV_CTL_ELEM_ACCESS_READ \| SNDRV_CTL_ELEM_ACCESS_VOLATILE,
	486	.get = snd_cs8427_qsubcode_get
	487	}};
	488
97f02e05 TI	489	int snd_cs8427_iec958_build(struct snd_i2c_device *cs8427,
	490	struct snd_pcm_substream *play_substream,
	491	struct snd_pcm_substream *cap_substream)
1da177e4	492	{
97f02e05 TI	493	struct cs8427 *chip = cs8427->private_data;
97f02e05 TI	494	struct snd_kcontrol *kctl;
1da177e4 LT	495	unsigned int idx;
	496	int err;
	497
	498	snd_assert(play_substream && cap_substream, return -EINVAL);
	499	for (idx = 0; idx < ARRAY_SIZE(snd_cs8427_iec958_controls); idx++) {
	500	kctl = snd_ctl_new1(&snd_cs8427_iec958_controls[idx], cs8427);
	501	if (kctl == NULL)
	502	return -ENOMEM;
	503	kctl->id.device = play_substream->pcm->device;
	504	kctl->id.subdevice = play_substream->number;
	505	err = snd_ctl_add(cs8427->bus->card, kctl);
	506	if (err < 0)
	507	return err;
	508	if (!strcmp(kctl->id.name, SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM)))
	509	chip->playback.pcm_ctl = kctl;
	510	}
	511
	512	chip->playback.substream = play_substream;
	513	chip->capture.substream = cap_substream;
	514	snd_assert(chip->playback.pcm_ctl, return -EIO);
	515	return 0;
	516	}
	517
97f02e05	518	int snd_cs8427_iec958_active(struct snd_i2c_device *cs8427, int active)
1da177e4	519	{
97f02e05	520	struct cs8427 *chip;
1da177e4 LT	521
	522	snd_assert(cs8427, return -ENXIO);
	523	chip = cs8427->private_data;
	524	if (active)
	525	memcpy(chip->playback.pcm_status, chip->playback.def_status, 24);
	526	chip->playback.pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
	527	snd_ctl_notify(cs8427->bus->card, SNDRV_CTL_EVENT_MASK_VALUE \|
	528	SNDRV_CTL_EVENT_MASK_INFO, &chip->playback.pcm_ctl->id);
	529	return 0;
	530	}
	531
97f02e05	532	int snd_cs8427_iec958_pcm(struct snd_i2c_device *cs8427, unsigned int rate)
1da177e4	533	{
97f02e05	534	struct cs8427 *chip;
1da177e4 LT	535	char *status;
	536	int err, reset;
	537
	538	snd_assert(cs8427, return -ENXIO);
	539	chip = cs8427->private_data;
	540	status = chip->playback.pcm_status;
	541	snd_i2c_lock(cs8427->bus);
	542	if (status[0] & IEC958_AES0_PROFESSIONAL) {
	543	status[0] &= ~IEC958_AES0_PRO_FS;
	544	switch (rate) {
	545	case 32000: status[0] \|= IEC958_AES0_PRO_FS_32000; break;
	546	case 44100: status[0] \|= IEC958_AES0_PRO_FS_44100; break;
	547	case 48000: status[0] \|= IEC958_AES0_PRO_FS_48000; break;
	548	default: status[0] \|= IEC958_AES0_PRO_FS_NOTID; break;
	549	}
	550	} else {
	551	status[3] &= ~IEC958_AES3_CON_FS;
	552	switch (rate) {
	553	case 32000: status[3] \|= IEC958_AES3_CON_FS_32000; break;
	554	case 44100: status[3] \|= IEC958_AES3_CON_FS_44100; break;
	555	case 48000: status[3] \|= IEC958_AES3_CON_FS_48000; break;
	556	}
	557	}
	558	err = snd_cs8427_send_corudata(cs8427, 0, status, 24);
	559	if (err > 0)
	560	snd_ctl_notify(cs8427->bus->card,
	561	SNDRV_CTL_EVENT_MASK_VALUE,
	562	&chip->playback.pcm_ctl->id);
	563	reset = chip->rate != rate;
	564	chip->rate = rate;
	565	snd_i2c_unlock(cs8427->bus);
	566	if (reset)
	567	snd_cs8427_reset(cs8427);
	568	return err < 0 ? err : 0;
	569	}
	570
	571	static int __init alsa_cs8427_module_init(void)
	572	{
	573	return 0;
	574	}
	575
	576	static void __exit alsa_cs8427_module_exit(void)
	577	{
	578	}
	579
	580	module_init(alsa_cs8427_module_init)
	581	module_exit(alsa_cs8427_module_exit)
	582
	583	EXPORT_SYMBOL(snd_cs8427_create);
1da177e4 LT	584	EXPORT_SYMBOL(snd_cs8427_reg_write);
	585	EXPORT_SYMBOL(snd_cs8427_iec958_build);
	586	EXPORT_SYMBOL(snd_cs8427_iec958_active);
	587	EXPORT_SYMBOL(snd_cs8427_iec958_pcm);