Commit | Line | Data |
---|---|---|
457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
14752412 TI |
2 | /* |
3 | * HD-audio stream operations | |
4 | */ | |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/delay.h> | |
8 | #include <linux/export.h> | |
5f26face | 9 | #include <linux/clocksource.h> |
14752412 TI |
10 | #include <sound/core.h> |
11 | #include <sound/pcm.h> | |
12 | #include <sound/hdaudio.h> | |
13 | #include <sound/hda_register.h> | |
598dfb56 | 14 | #include "trace.h" |
14752412 | 15 | |
ea2ddd25 PLB |
16 | /* |
17 | * the hdac_stream library is intended to be used with the following | |
18 | * transitions. The states are not formally defined in the code but loosely | |
19 | * inspired by boolean variables. Note that the 'prepared' field is not used | |
20 | * in this library but by the callers during the hw_params/prepare transitions | |
21 | * | |
22 | * | | |
23 | * stream_init() | | |
24 | * v | |
25 | * +--+-------+ | |
26 | * | unused | | |
27 | * +--+----+--+ | |
28 | * | ^ | |
29 | * stream_assign() | | stream_release() | |
30 | * v | | |
31 | * +--+----+--+ | |
32 | * | opened | | |
33 | * +--+----+--+ | |
34 | * | ^ | |
35 | * stream_reset() | | | |
36 | * stream_setup() | | stream_cleanup() | |
37 | * v | | |
38 | * +--+----+--+ | |
39 | * | prepared | | |
40 | * +--+----+--+ | |
41 | * | ^ | |
42 | * stream_start() | | stream_stop() | |
43 | * v | | |
44 | * +--+----+--+ | |
45 | * | running | | |
46 | * +----------+ | |
47 | */ | |
48 | ||
5dd3d271 SP |
49 | /** |
50 | * snd_hdac_get_stream_stripe_ctl - get stripe control value | |
51 | * @bus: HD-audio core bus | |
52 | * @substream: PCM substream | |
53 | */ | |
54 | int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, | |
55 | struct snd_pcm_substream *substream) | |
56 | { | |
57 | struct snd_pcm_runtime *runtime = substream->runtime; | |
58 | unsigned int channels = runtime->channels, | |
59 | rate = runtime->rate, | |
60 | bits_per_sample = runtime->sample_bits, | |
61 | max_sdo_lines, value, sdo_line; | |
62 | ||
63 | /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */ | |
64 | max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO; | |
65 | ||
66 | /* following is from HD audio spec */ | |
67 | for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) { | |
68 | if (rate > 48000) | |
69 | value = (channels * bits_per_sample * | |
70 | (rate / 48000)) / sdo_line; | |
71 | else | |
72 | value = (channels * bits_per_sample) / sdo_line; | |
73 | ||
67ae482a | 74 | if (value >= bus->sdo_limit) |
5dd3d271 SP |
75 | break; |
76 | } | |
77 | ||
78 | /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */ | |
79 | return sdo_line >> 1; | |
80 | } | |
81 | EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl); | |
82 | ||
14752412 TI |
83 | /** |
84 | * snd_hdac_stream_init - initialize each stream (aka device) | |
85 | * @bus: HD-audio core bus | |
86 | * @azx_dev: HD-audio core stream object to initialize | |
87 | * @idx: stream index number | |
88 | * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE) | |
89 | * @tag: the tag id to assign | |
90 | * | |
91 | * Assign the starting bdl address to each stream (device) and initialize. | |
92 | */ | |
93 | void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, | |
94 | int idx, int direction, int tag) | |
95 | { | |
96 | azx_dev->bus = bus; | |
14752412 TI |
97 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
98 | azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80); | |
99 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
100 | azx_dev->sd_int_sta_mask = 1 << idx; | |
101 | azx_dev->index = idx; | |
102 | azx_dev->direction = direction; | |
103 | azx_dev->stream_tag = tag; | |
8f3f600b | 104 | snd_hdac_dsp_lock_init(azx_dev); |
14752412 | 105 | list_add_tail(&azx_dev->list, &bus->stream_list); |
62582341 PLB |
106 | |
107 | if (bus->spbcap) { | |
108 | azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE + | |
109 | AZX_SPB_INTERVAL * idx + | |
110 | AZX_SPB_SPIB; | |
111 | ||
112 | azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE + | |
113 | AZX_SPB_INTERVAL * idx + | |
114 | AZX_SPB_MAXFIFO; | |
115 | } | |
116 | ||
117 | if (bus->drsmcap) | |
118 | azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE + | |
119 | AZX_DRSM_INTERVAL * idx; | |
14752412 TI |
120 | } |
121 | EXPORT_SYMBOL_GPL(snd_hdac_stream_init); | |
122 | ||
123 | /** | |
124 | * snd_hdac_stream_start - start a stream | |
125 | * @azx_dev: HD-audio core stream to start | |
126 | * @fresh_start: false = wallclock timestamp relative to period wallclock | |
127 | * | |
128 | * Start a stream, set start_wallclk and set the running flag. | |
129 | */ | |
130 | void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start) | |
131 | { | |
132 | struct hdac_bus *bus = azx_dev->bus; | |
9b6f7e7a | 133 | int stripe_ctl; |
14752412 | 134 | |
598dfb56 LY |
135 | trace_snd_hdac_stream_start(bus, azx_dev); |
136 | ||
14752412 TI |
137 | azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK); |
138 | if (!fresh_start) | |
139 | azx_dev->start_wallclk -= azx_dev->period_wallclk; | |
140 | ||
141 | /* enable SIE */ | |
fc2a6cf0 KJ |
142 | snd_hdac_chip_updatel(bus, INTCTL, |
143 | 1 << azx_dev->index, | |
144 | 1 << azx_dev->index); | |
9b6f7e7a | 145 | /* set stripe control */ |
e38e486d TI |
146 | if (azx_dev->stripe) { |
147 | if (azx_dev->substream) | |
148 | stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream); | |
149 | else | |
150 | stripe_ctl = 0; | |
151 | snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, | |
152 | stripe_ctl); | |
153 | } | |
14752412 TI |
154 | /* set DMA start and interrupt mask */ |
155 | snd_hdac_stream_updateb(azx_dev, SD_CTL, | |
156 | 0, SD_CTL_DMA_START | SD_INT_MASK); | |
157 | azx_dev->running = true; | |
158 | } | |
159 | EXPORT_SYMBOL_GPL(snd_hdac_stream_start); | |
160 | ||
161 | /** | |
2ea13c83 | 162 | * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers |
14752412 TI |
163 | * @azx_dev: HD-audio core stream to stop |
164 | */ | |
2ea13c83 | 165 | static void snd_hdac_stream_clear(struct hdac_stream *azx_dev) |
14752412 TI |
166 | { |
167 | snd_hdac_stream_updateb(azx_dev, SD_CTL, | |
168 | SD_CTL_DMA_START | SD_INT_MASK, 0); | |
169 | snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
6fd739c0 | 170 | if (azx_dev->stripe) |
e38e486d | 171 | snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0); |
14752412 TI |
172 | azx_dev->running = false; |
173 | } | |
14752412 TI |
174 | |
175 | /** | |
176 | * snd_hdac_stream_stop - stop a stream | |
177 | * @azx_dev: HD-audio core stream to stop | |
178 | * | |
179 | * Stop a stream DMA and disable stream interrupt | |
180 | */ | |
181 | void snd_hdac_stream_stop(struct hdac_stream *azx_dev) | |
182 | { | |
598dfb56 LY |
183 | trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev); |
184 | ||
14752412 TI |
185 | snd_hdac_stream_clear(azx_dev); |
186 | /* disable SIE */ | |
187 | snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0); | |
188 | } | |
189 | EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); | |
190 | ||
24ad3835 PLB |
191 | /** |
192 | * snd_hdac_stop_streams - stop all streams | |
193 | * @bus: HD-audio core bus | |
194 | */ | |
195 | void snd_hdac_stop_streams(struct hdac_bus *bus) | |
196 | { | |
197 | struct hdac_stream *stream; | |
198 | ||
199 | list_for_each_entry(stream, &bus->stream_list, list) | |
200 | snd_hdac_stream_stop(stream); | |
201 | } | |
202 | EXPORT_SYMBOL_GPL(snd_hdac_stop_streams); | |
203 | ||
12054f0c PLB |
204 | /** |
205 | * snd_hdac_stop_streams_and_chip - stop all streams and chip if running | |
206 | * @bus: HD-audio core bus | |
207 | */ | |
208 | void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus) | |
209 | { | |
12054f0c PLB |
210 | |
211 | if (bus->chip_init) { | |
24ad3835 | 212 | snd_hdac_stop_streams(bus); |
12054f0c PLB |
213 | snd_hdac_bus_stop_chip(bus); |
214 | } | |
215 | } | |
216 | EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip); | |
217 | ||
14752412 TI |
218 | /** |
219 | * snd_hdac_stream_reset - reset a stream | |
220 | * @azx_dev: HD-audio core stream to reset | |
221 | */ | |
222 | void snd_hdac_stream_reset(struct hdac_stream *azx_dev) | |
223 | { | |
224 | unsigned char val; | |
4106820b | 225 | int dma_run_state; |
14752412 TI |
226 | |
227 | snd_hdac_stream_clear(azx_dev); | |
228 | ||
4106820b MK |
229 | dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START; |
230 | ||
14752412 | 231 | snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); |
d9185705 AS |
232 | |
233 | /* wait for hardware to report that the stream entered reset */ | |
234 | snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300); | |
4106820b MK |
235 | |
236 | if (azx_dev->bus->dma_stop_delay && dma_run_state) | |
237 | udelay(azx_dev->bus->dma_stop_delay); | |
238 | ||
d9185705 | 239 | snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0); |
14752412 | 240 | |
d9185705 AS |
241 | /* wait for hardware to report that the stream is out of reset */ |
242 | snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300); | |
14752412 TI |
243 | |
244 | /* reset first position - may not be synced with hw at this time */ | |
245 | if (azx_dev->posbuf) | |
246 | *azx_dev->posbuf = 0; | |
247 | } | |
248 | EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); | |
249 | ||
250 | /** | |
251 | * snd_hdac_stream_setup - set up the SD for streaming | |
252 | * @azx_dev: HD-audio core stream to set up | |
253 | */ | |
254 | int snd_hdac_stream_setup(struct hdac_stream *azx_dev) | |
255 | { | |
256 | struct hdac_bus *bus = azx_dev->bus; | |
4214c534 | 257 | struct snd_pcm_runtime *runtime; |
14752412 TI |
258 | unsigned int val; |
259 | ||
4214c534 TI |
260 | if (azx_dev->substream) |
261 | runtime = azx_dev->substream->runtime; | |
262 | else | |
263 | runtime = NULL; | |
14752412 TI |
264 | /* make sure the run bit is zero for SD */ |
265 | snd_hdac_stream_clear(azx_dev); | |
266 | /* program the stream_tag */ | |
267 | val = snd_hdac_stream_readl(azx_dev, SD_CTL); | |
268 | val = (val & ~SD_CTL_STREAM_TAG_MASK) | | |
269 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); | |
270 | if (!bus->snoop) | |
271 | val |= SD_CTL_TRAFFIC_PRIO; | |
272 | snd_hdac_stream_writel(azx_dev, SD_CTL, val); | |
273 | ||
274 | /* program the length of samples in cyclic buffer */ | |
275 | snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
276 | ||
277 | /* program the stream format */ | |
278 | /* this value needs to be the same as the one programmed */ | |
279 | snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
280 | ||
281 | /* program the stream LVI (last valid index) of the BDL */ | |
282 | snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
283 | ||
284 | /* program the BDL address */ | |
285 | /* lower BDL address */ | |
286 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); | |
287 | /* upper BDL address */ | |
288 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, | |
289 | upper_32_bits(azx_dev->bdl.addr)); | |
290 | ||
291 | /* enable the position buffer */ | |
292 | if (bus->use_posbuf && bus->posbuf.addr) { | |
293 | if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE)) | |
294 | snd_hdac_chip_writel(bus, DPLBASE, | |
295 | (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE); | |
296 | } | |
297 | ||
298 | /* set the interrupt enable bits in the descriptor control register */ | |
299 | snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK); | |
300 | ||
7da20788 | 301 | azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1; |
14752412 TI |
302 | |
303 | /* when LPIB delay correction gives a small negative value, | |
304 | * we ignore it; currently set the threshold statically to | |
305 | * 64 frames | |
306 | */ | |
4214c534 | 307 | if (runtime && runtime->period_size > 64) |
14752412 TI |
308 | azx_dev->delay_negative_threshold = |
309 | -frames_to_bytes(runtime, 64); | |
310 | else | |
311 | azx_dev->delay_negative_threshold = 0; | |
312 | ||
313 | /* wallclk has 24Mhz clock source */ | |
4214c534 TI |
314 | if (runtime) |
315 | azx_dev->period_wallclk = (((runtime->period_size * 24000) / | |
14752412 TI |
316 | runtime->rate) * 1000); |
317 | ||
318 | return 0; | |
319 | } | |
320 | EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); | |
321 | ||
322 | /** | |
323 | * snd_hdac_stream_cleanup - cleanup a stream | |
324 | * @azx_dev: HD-audio core stream to clean up | |
325 | */ | |
326 | void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev) | |
327 | { | |
328 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
329 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
330 | snd_hdac_stream_writel(azx_dev, SD_CTL, 0); | |
331 | azx_dev->bufsize = 0; | |
332 | azx_dev->period_bytes = 0; | |
333 | azx_dev->format_val = 0; | |
334 | } | |
335 | EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); | |
336 | ||
337 | /** | |
338 | * snd_hdac_stream_assign - assign a stream for the PCM | |
339 | * @bus: HD-audio core bus | |
340 | * @substream: PCM substream to assign | |
341 | * | |
342 | * Look for an unused stream for the given PCM substream, assign it | |
343 | * and return the stream object. If no stream is free, returns NULL. | |
344 | * The function tries to keep using the same stream object when it's used | |
345 | * beforehand. Also, when bus->reverse_assign flag is set, the last free | |
346 | * or matching entry is returned. This is needed for some strange codecs. | |
347 | */ | |
348 | struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, | |
349 | struct snd_pcm_substream *substream) | |
350 | { | |
351 | struct hdac_stream *azx_dev; | |
352 | struct hdac_stream *res = NULL; | |
353 | ||
354 | /* make a non-zero unique key for the substream */ | |
355 | int key = (substream->pcm->device << 16) | (substream->number << 2) | | |
356 | (substream->stream + 1); | |
357 | ||
1465d06a | 358 | spin_lock_irq(&bus->reg_lock); |
14752412 TI |
359 | list_for_each_entry(azx_dev, &bus->stream_list, list) { |
360 | if (azx_dev->direction != substream->stream) | |
361 | continue; | |
362 | if (azx_dev->opened) | |
363 | continue; | |
364 | if (azx_dev->assigned_key == key) { | |
365 | res = azx_dev; | |
366 | break; | |
367 | } | |
368 | if (!res || bus->reverse_assign) | |
369 | res = azx_dev; | |
370 | } | |
371 | if (res) { | |
14752412 TI |
372 | res->opened = 1; |
373 | res->running = 0; | |
374 | res->assigned_key = key; | |
375 | res->substream = substream; | |
14752412 | 376 | } |
1465d06a | 377 | spin_unlock_irq(&bus->reg_lock); |
14752412 TI |
378 | return res; |
379 | } | |
380 | EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); | |
381 | ||
ac3467ad PLB |
382 | /** |
383 | * snd_hdac_stream_release_locked - release the assigned stream | |
384 | * @azx_dev: HD-audio core stream to release | |
385 | * | |
386 | * Release the stream that has been assigned by snd_hdac_stream_assign(). | |
387 | * The bus->reg_lock needs to be taken at a higher level | |
388 | */ | |
389 | void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev) | |
390 | { | |
391 | azx_dev->opened = 0; | |
392 | azx_dev->running = 0; | |
393 | azx_dev->substream = NULL; | |
394 | } | |
395 | EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked); | |
396 | ||
14752412 TI |
397 | /** |
398 | * snd_hdac_stream_release - release the assigned stream | |
399 | * @azx_dev: HD-audio core stream to release | |
400 | * | |
401 | * Release the stream that has been assigned by snd_hdac_stream_assign(). | |
402 | */ | |
403 | void snd_hdac_stream_release(struct hdac_stream *azx_dev) | |
404 | { | |
405 | struct hdac_bus *bus = azx_dev->bus; | |
406 | ||
407 | spin_lock_irq(&bus->reg_lock); | |
ac3467ad | 408 | snd_hdac_stream_release_locked(azx_dev); |
14752412 TI |
409 | spin_unlock_irq(&bus->reg_lock); |
410 | } | |
411 | EXPORT_SYMBOL_GPL(snd_hdac_stream_release); | |
412 | ||
4308c9b0 JK |
413 | /** |
414 | * snd_hdac_get_stream - return hdac_stream based on stream_tag and | |
415 | * direction | |
416 | * | |
417 | * @bus: HD-audio core bus | |
418 | * @dir: direction for the stream to be found | |
419 | * @stream_tag: stream tag for stream to be found | |
420 | */ | |
421 | struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, | |
422 | int dir, int stream_tag) | |
423 | { | |
424 | struct hdac_stream *s; | |
425 | ||
426 | list_for_each_entry(s, &bus->stream_list, list) { | |
427 | if (s->direction == dir && s->stream_tag == stream_tag) | |
428 | return s; | |
429 | } | |
430 | ||
431 | return NULL; | |
432 | } | |
433 | EXPORT_SYMBOL_GPL(snd_hdac_get_stream); | |
434 | ||
14752412 TI |
435 | /* |
436 | * set up a BDL entry | |
437 | */ | |
438 | static int setup_bdle(struct hdac_bus *bus, | |
439 | struct snd_dma_buffer *dmab, | |
440 | struct hdac_stream *azx_dev, __le32 **bdlp, | |
441 | int ofs, int size, int with_ioc) | |
442 | { | |
443 | __le32 *bdl = *bdlp; | |
444 | ||
445 | while (size > 0) { | |
446 | dma_addr_t addr; | |
447 | int chunk; | |
448 | ||
449 | if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) | |
450 | return -EINVAL; | |
451 | ||
452 | addr = snd_sgbuf_get_addr(dmab, ofs); | |
453 | /* program the address field of the BDL entry */ | |
454 | bdl[0] = cpu_to_le32((u32)addr); | |
455 | bdl[1] = cpu_to_le32(upper_32_bits(addr)); | |
456 | /* program the size field of the BDL entry */ | |
457 | chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); | |
458 | /* one BDLE cannot cross 4K boundary on CTHDA chips */ | |
459 | if (bus->align_bdle_4k) { | |
460 | u32 remain = 0x1000 - (ofs & 0xfff); | |
461 | ||
462 | if (chunk > remain) | |
463 | chunk = remain; | |
464 | } | |
465 | bdl[2] = cpu_to_le32(chunk); | |
466 | /* program the IOC to enable interrupt | |
467 | * only when the whole fragment is processed | |
468 | */ | |
469 | size -= chunk; | |
470 | bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); | |
471 | bdl += 4; | |
472 | azx_dev->frags++; | |
473 | ofs += chunk; | |
474 | } | |
475 | *bdlp = bdl; | |
476 | return ofs; | |
477 | } | |
478 | ||
479 | /** | |
480 | * snd_hdac_stream_setup_periods - set up BDL entries | |
481 | * @azx_dev: HD-audio core stream to set up | |
482 | * | |
483 | * Set up the buffer descriptor table of the given stream based on the | |
484 | * period and buffer sizes of the assigned PCM substream. | |
485 | */ | |
486 | int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev) | |
487 | { | |
488 | struct hdac_bus *bus = azx_dev->bus; | |
489 | struct snd_pcm_substream *substream = azx_dev->substream; | |
f6b12546 CR |
490 | struct snd_pcm_runtime *runtime; |
491 | struct snd_dma_buffer *dmab; | |
14752412 TI |
492 | __le32 *bdl; |
493 | int i, ofs, periods, period_bytes; | |
494 | int pos_adj, pos_align; | |
495 | ||
f6b12546 CR |
496 | runtime = substream->runtime; |
497 | dmab = snd_pcm_get_dma_buf(substream); | |
498 | ||
14752412 TI |
499 | /* reset BDL address */ |
500 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
501 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
502 | ||
503 | period_bytes = azx_dev->period_bytes; | |
504 | periods = azx_dev->bufsize / period_bytes; | |
505 | ||
506 | /* program the initial BDL entries */ | |
507 | bdl = (__le32 *)azx_dev->bdl.area; | |
508 | ofs = 0; | |
509 | azx_dev->frags = 0; | |
510 | ||
511 | pos_adj = bus->bdl_pos_adj; | |
f6b12546 | 512 | if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) { |
14752412 | 513 | pos_align = pos_adj; |
81d0ec43 | 514 | pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000); |
14752412 TI |
515 | if (!pos_adj) |
516 | pos_adj = pos_align; | |
517 | else | |
81d0ec43 | 518 | pos_adj = roundup(pos_adj, pos_align); |
14752412 TI |
519 | pos_adj = frames_to_bytes(runtime, pos_adj); |
520 | if (pos_adj >= period_bytes) { | |
521 | dev_warn(bus->dev, "Too big adjustment %d\n", | |
522 | pos_adj); | |
523 | pos_adj = 0; | |
524 | } else { | |
f6b12546 | 525 | ofs = setup_bdle(bus, dmab, azx_dev, |
14752412 TI |
526 | &bdl, ofs, pos_adj, true); |
527 | if (ofs < 0) | |
528 | goto error; | |
529 | } | |
530 | } else | |
531 | pos_adj = 0; | |
532 | ||
533 | for (i = 0; i < periods; i++) { | |
534 | if (i == periods - 1 && pos_adj) | |
f6b12546 CR |
535 | ofs = setup_bdle(bus, dmab, azx_dev, |
536 | &bdl, ofs, period_bytes - pos_adj, 0); | |
14752412 | 537 | else |
f6b12546 CR |
538 | ofs = setup_bdle(bus, dmab, azx_dev, |
539 | &bdl, ofs, period_bytes, | |
14752412 TI |
540 | !azx_dev->no_period_wakeup); |
541 | if (ofs < 0) | |
542 | goto error; | |
543 | } | |
544 | return 0; | |
545 | ||
546 | error: | |
547 | dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n", | |
548 | azx_dev->bufsize, period_bytes); | |
549 | return -EINVAL; | |
550 | } | |
551 | EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods); | |
552 | ||
78dd5e21 TI |
553 | /** |
554 | * snd_hdac_stream_set_params - set stream parameters | |
86f6501b JK |
555 | * @azx_dev: HD-audio core stream for which parameters are to be set |
556 | * @format_val: format value parameter | |
557 | * | |
558 | * Setup the HD-audio core stream parameters from substream of the stream | |
559 | * and passed format value | |
560 | */ | |
561 | int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, | |
562 | unsigned int format_val) | |
563 | { | |
86f6501b | 564 | struct snd_pcm_substream *substream = azx_dev->substream; |
f6b12546 CR |
565 | unsigned int bufsize, period_bytes; |
566 | unsigned int no_period_wakeup; | |
86f6501b JK |
567 | int err; |
568 | ||
569 | if (!substream) | |
570 | return -EINVAL; | |
86f6501b JK |
571 | bufsize = snd_pcm_lib_buffer_bytes(substream); |
572 | period_bytes = snd_pcm_lib_period_bytes(substream); | |
f6b12546 | 573 | no_period_wakeup = substream->runtime->no_period_wakeup; |
86f6501b JK |
574 | |
575 | if (bufsize != azx_dev->bufsize || | |
576 | period_bytes != azx_dev->period_bytes || | |
577 | format_val != azx_dev->format_val || | |
f6b12546 | 578 | no_period_wakeup != azx_dev->no_period_wakeup) { |
86f6501b JK |
579 | azx_dev->bufsize = bufsize; |
580 | azx_dev->period_bytes = period_bytes; | |
581 | azx_dev->format_val = format_val; | |
f6b12546 | 582 | azx_dev->no_period_wakeup = no_period_wakeup; |
86f6501b JK |
583 | err = snd_hdac_stream_setup_periods(azx_dev); |
584 | if (err < 0) | |
585 | return err; | |
586 | } | |
587 | return 0; | |
588 | } | |
589 | EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params); | |
590 | ||
a5a1d1c2 | 591 | static u64 azx_cc_read(const struct cyclecounter *cc) |
14752412 TI |
592 | { |
593 | struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc); | |
594 | ||
595 | return snd_hdac_chip_readl(azx_dev->bus, WALLCLK); | |
596 | } | |
597 | ||
598 | static void azx_timecounter_init(struct hdac_stream *azx_dev, | |
a5a1d1c2 | 599 | bool force, u64 last) |
14752412 TI |
600 | { |
601 | struct timecounter *tc = &azx_dev->tc; | |
602 | struct cyclecounter *cc = &azx_dev->cc; | |
603 | u64 nsec; | |
604 | ||
605 | cc->read = azx_cc_read; | |
606 | cc->mask = CLOCKSOURCE_MASK(32); | |
607 | ||
608 | /* | |
6dd21ad8 TG |
609 | * Calculate the optimal mult/shift values. The counter wraps |
610 | * around after ~178.9 seconds. | |
14752412 | 611 | */ |
6dd21ad8 TG |
612 | clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000, |
613 | NSEC_PER_SEC, 178); | |
14752412 TI |
614 | |
615 | nsec = 0; /* audio time is elapsed time since trigger */ | |
616 | timecounter_init(tc, cc, nsec); | |
617 | if (force) { | |
618 | /* | |
619 | * force timecounter to use predefined value, | |
620 | * used for synchronized starts | |
621 | */ | |
622 | tc->cycle_last = last; | |
623 | } | |
624 | } | |
625 | ||
626 | /** | |
627 | * snd_hdac_stream_timecounter_init - initialize time counter | |
628 | * @azx_dev: HD-audio core stream (master stream) | |
629 | * @streams: bit flags of streams to set up | |
630 | * | |
631 | * Initializes the time counter of streams marked by the bit flags (each | |
632 | * bit corresponds to the stream index). | |
633 | * The trigger timestamp of PCM substream assigned to the given stream is | |
634 | * updated accordingly, too. | |
635 | */ | |
636 | void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, | |
637 | unsigned int streams) | |
638 | { | |
639 | struct hdac_bus *bus = azx_dev->bus; | |
640 | struct snd_pcm_runtime *runtime = azx_dev->substream->runtime; | |
641 | struct hdac_stream *s; | |
642 | bool inited = false; | |
a5a1d1c2 | 643 | u64 cycle_last = 0; |
14752412 TI |
644 | int i = 0; |
645 | ||
646 | list_for_each_entry(s, &bus->stream_list, list) { | |
647 | if (streams & (1 << i)) { | |
648 | azx_timecounter_init(s, inited, cycle_last); | |
649 | if (!inited) { | |
650 | inited = true; | |
651 | cycle_last = s->tc.cycle_last; | |
652 | } | |
653 | } | |
654 | i++; | |
655 | } | |
656 | ||
657 | snd_pcm_gettime(runtime, &runtime->trigger_tstamp); | |
658 | runtime->trigger_tstamp_latched = true; | |
659 | } | |
660 | EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init); | |
661 | ||
662 | /** | |
663 | * snd_hdac_stream_sync_trigger - turn on/off stream sync register | |
664 | * @azx_dev: HD-audio core stream (master stream) | |
6e57188f | 665 | * @set: true = set, false = clear |
14752412 | 666 | * @streams: bit flags of streams to sync |
6e57188f | 667 | * @reg: the stream sync register address |
14752412 TI |
668 | */ |
669 | void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, | |
670 | unsigned int streams, unsigned int reg) | |
671 | { | |
672 | struct hdac_bus *bus = azx_dev->bus; | |
673 | unsigned int val; | |
674 | ||
675 | if (!reg) | |
676 | reg = AZX_REG_SSYNC; | |
2c1f8138 | 677 | val = _snd_hdac_chip_readl(bus, reg); |
14752412 TI |
678 | if (set) |
679 | val |= streams; | |
680 | else | |
681 | val &= ~streams; | |
2c1f8138 | 682 | _snd_hdac_chip_writel(bus, reg, val); |
14752412 TI |
683 | } |
684 | EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger); | |
685 | ||
686 | /** | |
8518c648 | 687 | * snd_hdac_stream_sync - sync with start/stop trigger operation |
14752412 TI |
688 | * @azx_dev: HD-audio core stream (master stream) |
689 | * @start: true = start, false = stop | |
690 | * @streams: bit flags of streams to sync | |
691 | * | |
692 | * For @start = true, wait until all FIFOs get ready. | |
693 | * For @start = false, wait until all RUN bits are cleared. | |
694 | */ | |
695 | void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, | |
696 | unsigned int streams) | |
697 | { | |
698 | struct hdac_bus *bus = azx_dev->bus; | |
699 | int i, nwait, timeout; | |
700 | struct hdac_stream *s; | |
701 | ||
702 | for (timeout = 5000; timeout; timeout--) { | |
703 | nwait = 0; | |
704 | i = 0; | |
705 | list_for_each_entry(s, &bus->stream_list, list) { | |
7faa26c1 MK |
706 | if (!(streams & (1 << i++))) |
707 | continue; | |
708 | ||
709 | if (start) { | |
710 | /* check FIFO gets ready */ | |
711 | if (!(snd_hdac_stream_readb(s, SD_STS) & | |
712 | SD_STS_FIFO_READY)) | |
713 | nwait++; | |
714 | } else { | |
715 | /* check RUN bit is cleared */ | |
716 | if (snd_hdac_stream_readb(s, SD_CTL) & | |
717 | SD_CTL_DMA_START) { | |
718 | nwait++; | |
719 | /* | |
720 | * Perform stream reset if DMA RUN | |
721 | * bit not cleared within given timeout | |
722 | */ | |
723 | if (timeout == 1) | |
724 | snd_hdac_stream_reset(s); | |
14752412 TI |
725 | } |
726 | } | |
14752412 TI |
727 | } |
728 | if (!nwait) | |
729 | break; | |
730 | cpu_relax(); | |
731 | } | |
732 | } | |
733 | EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); | |
8f3f600b | 734 | |
62582341 PLB |
735 | /** |
736 | * snd_hdac_stream_spbcap_enable - enable SPIB for a stream | |
737 | * @bus: HD-audio core bus | |
738 | * @enable: flag to enable/disable SPIB | |
739 | * @index: stream index for which SPIB need to be enabled | |
740 | */ | |
741 | void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus, | |
742 | bool enable, int index) | |
743 | { | |
744 | u32 mask = 0; | |
745 | ||
746 | if (!bus->spbcap) { | |
747 | dev_err(bus->dev, "Address of SPB capability is NULL\n"); | |
748 | return; | |
749 | } | |
750 | ||
751 | mask |= (1 << index); | |
752 | ||
753 | if (enable) | |
754 | snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask); | |
755 | else | |
756 | snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0); | |
757 | } | |
758 | EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable); | |
759 | ||
760 | /** | |
761 | * snd_hdac_stream_set_spib - sets the spib value of a stream | |
762 | * @bus: HD-audio core bus | |
763 | * @azx_dev: hdac_stream | |
764 | * @value: spib value to set | |
765 | */ | |
766 | int snd_hdac_stream_set_spib(struct hdac_bus *bus, | |
767 | struct hdac_stream *azx_dev, u32 value) | |
768 | { | |
769 | if (!bus->spbcap) { | |
770 | dev_err(bus->dev, "Address of SPB capability is NULL\n"); | |
771 | return -EINVAL; | |
772 | } | |
773 | ||
774 | writel(value, azx_dev->spib_addr); | |
775 | ||
776 | return 0; | |
777 | } | |
778 | EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib); | |
779 | ||
780 | /** | |
781 | * snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream | |
782 | * @bus: HD-audio core bus | |
783 | * @azx_dev: hdac_stream | |
784 | * | |
785 | * Return maxfifo for the stream | |
786 | */ | |
787 | int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus, | |
788 | struct hdac_stream *azx_dev) | |
789 | { | |
790 | if (!bus->spbcap) { | |
791 | dev_err(bus->dev, "Address of SPB capability is NULL\n"); | |
792 | return -EINVAL; | |
793 | } | |
794 | ||
795 | return readl(azx_dev->fifo_addr); | |
796 | } | |
797 | EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo); | |
798 | ||
799 | /** | |
800 | * snd_hdac_stream_drsm_enable - enable DMA resume for a stream | |
801 | * @bus: HD-audio core bus | |
802 | * @enable: flag to enable/disable DRSM | |
803 | * @index: stream index for which DRSM need to be enabled | |
804 | */ | |
805 | void snd_hdac_stream_drsm_enable(struct hdac_bus *bus, | |
806 | bool enable, int index) | |
807 | { | |
808 | u32 mask = 0; | |
809 | ||
810 | if (!bus->drsmcap) { | |
811 | dev_err(bus->dev, "Address of DRSM capability is NULL\n"); | |
812 | return; | |
813 | } | |
814 | ||
815 | mask |= (1 << index); | |
816 | ||
817 | if (enable) | |
818 | snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask); | |
819 | else | |
820 | snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0); | |
821 | } | |
822 | EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable); | |
823 | ||
efffb014 CR |
824 | /* |
825 | * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream | |
826 | * @azx_dev: HD-audio core stream to await RSM for | |
827 | * | |
828 | * Returns 0 on success and -ETIMEDOUT upon a timeout. | |
829 | */ | |
830 | int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev) | |
831 | { | |
832 | struct hdac_bus *bus = azx_dev->bus; | |
833 | u32 mask, reg; | |
834 | int ret; | |
835 | ||
836 | mask = 1 << azx_dev->index; | |
837 | ||
838 | ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus, | |
839 | bus->drsmcap + AZX_REG_DRSM_CTL); | |
840 | if (ret) | |
841 | dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret); | |
842 | return ret; | |
843 | } | |
844 | EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm); | |
845 | ||
62582341 PLB |
846 | /** |
847 | * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream | |
848 | * @bus: HD-audio core bus | |
849 | * @azx_dev: hdac_stream | |
850 | * @value: dpib value to set | |
851 | */ | |
852 | int snd_hdac_stream_set_dpibr(struct hdac_bus *bus, | |
853 | struct hdac_stream *azx_dev, u32 value) | |
854 | { | |
855 | if (!bus->drsmcap) { | |
856 | dev_err(bus->dev, "Address of DRSM capability is NULL\n"); | |
857 | return -EINVAL; | |
858 | } | |
859 | ||
860 | writel(value, azx_dev->dpibr_addr); | |
861 | ||
862 | return 0; | |
863 | } | |
864 | EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr); | |
865 | ||
866 | /** | |
867 | * snd_hdac_stream_set_lpib - sets the lpib value of a stream | |
868 | * @azx_dev: hdac_stream | |
869 | * @value: lpib value to set | |
870 | */ | |
871 | int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value) | |
872 | { | |
873 | snd_hdac_stream_writel(azx_dev, SD_LPIB, value); | |
874 | ||
875 | return 0; | |
876 | } | |
877 | EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib); | |
878 | ||
8f3f600b TI |
879 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
880 | /** | |
881 | * snd_hdac_dsp_prepare - prepare for DSP loading | |
882 | * @azx_dev: HD-audio core stream used for DSP loading | |
883 | * @format: HD-audio stream format | |
884 | * @byte_size: data chunk byte size | |
885 | * @bufp: allocated buffer | |
886 | * | |
887 | * Allocate the buffer for the given size and set up the given stream for | |
888 | * DSP loading. Returns the stream tag (>= 0), or a negative error code. | |
889 | */ | |
890 | int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
891 | unsigned int byte_size, struct snd_dma_buffer *bufp) | |
892 | { | |
893 | struct hdac_bus *bus = azx_dev->bus; | |
7362b0fc | 894 | __le32 *bdl; |
8f3f600b TI |
895 | int err; |
896 | ||
897 | snd_hdac_dsp_lock(azx_dev); | |
898 | spin_lock_irq(&bus->reg_lock); | |
899 | if (azx_dev->running || azx_dev->locked) { | |
900 | spin_unlock_irq(&bus->reg_lock); | |
901 | err = -EBUSY; | |
902 | goto unlock; | |
903 | } | |
904 | azx_dev->locked = true; | |
905 | spin_unlock_irq(&bus->reg_lock); | |
906 | ||
619a1f19 TI |
907 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev, |
908 | byte_size, bufp); | |
8f3f600b TI |
909 | if (err < 0) |
910 | goto err_alloc; | |
911 | ||
4214c534 | 912 | azx_dev->substream = NULL; |
8f3f600b TI |
913 | azx_dev->bufsize = byte_size; |
914 | azx_dev->period_bytes = byte_size; | |
915 | azx_dev->format_val = format; | |
916 | ||
917 | snd_hdac_stream_reset(azx_dev); | |
918 | ||
919 | /* reset BDL address */ | |
920 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
921 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
922 | ||
923 | azx_dev->frags = 0; | |
7362b0fc | 924 | bdl = (__le32 *)azx_dev->bdl.area; |
8f3f600b TI |
925 | err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0); |
926 | if (err < 0) | |
927 | goto error; | |
928 | ||
929 | snd_hdac_stream_setup(azx_dev); | |
930 | snd_hdac_dsp_unlock(azx_dev); | |
931 | return azx_dev->stream_tag; | |
932 | ||
933 | error: | |
619a1f19 | 934 | snd_dma_free_pages(bufp); |
8f3f600b TI |
935 | err_alloc: |
936 | spin_lock_irq(&bus->reg_lock); | |
937 | azx_dev->locked = false; | |
938 | spin_unlock_irq(&bus->reg_lock); | |
939 | unlock: | |
940 | snd_hdac_dsp_unlock(azx_dev); | |
941 | return err; | |
942 | } | |
943 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); | |
944 | ||
945 | /** | |
946 | * snd_hdac_dsp_trigger - start / stop DSP loading | |
947 | * @azx_dev: HD-audio core stream used for DSP loading | |
948 | * @start: trigger start or stop | |
949 | */ | |
950 | void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) | |
951 | { | |
952 | if (start) | |
953 | snd_hdac_stream_start(azx_dev, true); | |
954 | else | |
955 | snd_hdac_stream_stop(azx_dev); | |
956 | } | |
957 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); | |
958 | ||
959 | /** | |
960 | * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal | |
961 | * @azx_dev: HD-audio core stream used for DSP loading | |
962 | * @dmab: buffer used by DSP loading | |
963 | */ | |
964 | void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
965 | struct snd_dma_buffer *dmab) | |
966 | { | |
967 | struct hdac_bus *bus = azx_dev->bus; | |
968 | ||
969 | if (!dmab->area || !azx_dev->locked) | |
970 | return; | |
971 | ||
972 | snd_hdac_dsp_lock(azx_dev); | |
973 | /* reset BDL address */ | |
974 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
975 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
976 | snd_hdac_stream_writel(azx_dev, SD_CTL, 0); | |
977 | azx_dev->bufsize = 0; | |
978 | azx_dev->period_bytes = 0; | |
979 | azx_dev->format_val = 0; | |
980 | ||
619a1f19 | 981 | snd_dma_free_pages(dmab); |
8f3f600b TI |
982 | dmab->area = NULL; |
983 | ||
984 | spin_lock_irq(&bus->reg_lock); | |
985 | azx_dev->locked = false; | |
986 | spin_unlock_irq(&bus->reg_lock); | |
987 | snd_hdac_dsp_unlock(azx_dev); | |
988 | } | |
989 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); | |
990 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ |