Commit | Line | Data |
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14752412 TI |
1 | /* |
2 | * HD-audio stream operations | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/export.h> | |
5f26face | 8 | #include <linux/clocksource.h> |
14752412 TI |
9 | #include <sound/core.h> |
10 | #include <sound/pcm.h> | |
11 | #include <sound/hdaudio.h> | |
12 | #include <sound/hda_register.h> | |
598dfb56 | 13 | #include "trace.h" |
14752412 | 14 | |
5dd3d271 SP |
15 | /** |
16 | * snd_hdac_get_stream_stripe_ctl - get stripe control value | |
17 | * @bus: HD-audio core bus | |
18 | * @substream: PCM substream | |
19 | */ | |
20 | int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, | |
21 | struct snd_pcm_substream *substream) | |
22 | { | |
23 | struct snd_pcm_runtime *runtime = substream->runtime; | |
24 | unsigned int channels = runtime->channels, | |
25 | rate = runtime->rate, | |
26 | bits_per_sample = runtime->sample_bits, | |
27 | max_sdo_lines, value, sdo_line; | |
28 | ||
29 | /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */ | |
30 | max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO; | |
31 | ||
32 | /* following is from HD audio spec */ | |
33 | for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) { | |
34 | if (rate > 48000) | |
35 | value = (channels * bits_per_sample * | |
36 | (rate / 48000)) / sdo_line; | |
37 | else | |
38 | value = (channels * bits_per_sample) / sdo_line; | |
39 | ||
40 | if (value >= 8) | |
41 | break; | |
42 | } | |
43 | ||
44 | /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */ | |
45 | return sdo_line >> 1; | |
46 | } | |
47 | EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl); | |
48 | ||
14752412 TI |
49 | /** |
50 | * snd_hdac_stream_init - initialize each stream (aka device) | |
51 | * @bus: HD-audio core bus | |
52 | * @azx_dev: HD-audio core stream object to initialize | |
53 | * @idx: stream index number | |
54 | * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE) | |
55 | * @tag: the tag id to assign | |
56 | * | |
57 | * Assign the starting bdl address to each stream (device) and initialize. | |
58 | */ | |
59 | void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, | |
60 | int idx, int direction, int tag) | |
61 | { | |
62 | azx_dev->bus = bus; | |
14752412 TI |
63 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
64 | azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80); | |
65 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
66 | azx_dev->sd_int_sta_mask = 1 << idx; | |
67 | azx_dev->index = idx; | |
68 | azx_dev->direction = direction; | |
69 | azx_dev->stream_tag = tag; | |
8f3f600b | 70 | snd_hdac_dsp_lock_init(azx_dev); |
14752412 TI |
71 | list_add_tail(&azx_dev->list, &bus->stream_list); |
72 | } | |
73 | EXPORT_SYMBOL_GPL(snd_hdac_stream_init); | |
74 | ||
75 | /** | |
76 | * snd_hdac_stream_start - start a stream | |
77 | * @azx_dev: HD-audio core stream to start | |
78 | * @fresh_start: false = wallclock timestamp relative to period wallclock | |
79 | * | |
80 | * Start a stream, set start_wallclk and set the running flag. | |
81 | */ | |
82 | void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start) | |
83 | { | |
84 | struct hdac_bus *bus = azx_dev->bus; | |
85 | ||
598dfb56 LY |
86 | trace_snd_hdac_stream_start(bus, azx_dev); |
87 | ||
14752412 TI |
88 | azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK); |
89 | if (!fresh_start) | |
90 | azx_dev->start_wallclk -= azx_dev->period_wallclk; | |
91 | ||
92 | /* enable SIE */ | |
fc2a6cf0 KJ |
93 | snd_hdac_chip_updatel(bus, INTCTL, |
94 | 1 << azx_dev->index, | |
95 | 1 << azx_dev->index); | |
14752412 TI |
96 | /* set DMA start and interrupt mask */ |
97 | snd_hdac_stream_updateb(azx_dev, SD_CTL, | |
98 | 0, SD_CTL_DMA_START | SD_INT_MASK); | |
99 | azx_dev->running = true; | |
100 | } | |
101 | EXPORT_SYMBOL_GPL(snd_hdac_stream_start); | |
102 | ||
103 | /** | |
104 | * snd_hdac_stream_clear - stop a stream DMA | |
105 | * @azx_dev: HD-audio core stream to stop | |
106 | */ | |
107 | void snd_hdac_stream_clear(struct hdac_stream *azx_dev) | |
108 | { | |
109 | snd_hdac_stream_updateb(azx_dev, SD_CTL, | |
110 | SD_CTL_DMA_START | SD_INT_MASK, 0); | |
111 | snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
112 | azx_dev->running = false; | |
113 | } | |
114 | EXPORT_SYMBOL_GPL(snd_hdac_stream_clear); | |
115 | ||
116 | /** | |
117 | * snd_hdac_stream_stop - stop a stream | |
118 | * @azx_dev: HD-audio core stream to stop | |
119 | * | |
120 | * Stop a stream DMA and disable stream interrupt | |
121 | */ | |
122 | void snd_hdac_stream_stop(struct hdac_stream *azx_dev) | |
123 | { | |
598dfb56 LY |
124 | trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev); |
125 | ||
14752412 TI |
126 | snd_hdac_stream_clear(azx_dev); |
127 | /* disable SIE */ | |
128 | snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0); | |
129 | } | |
130 | EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); | |
131 | ||
132 | /** | |
133 | * snd_hdac_stream_reset - reset a stream | |
134 | * @azx_dev: HD-audio core stream to reset | |
135 | */ | |
136 | void snd_hdac_stream_reset(struct hdac_stream *azx_dev) | |
137 | { | |
138 | unsigned char val; | |
139 | int timeout; | |
140 | ||
141 | snd_hdac_stream_clear(azx_dev); | |
142 | ||
143 | snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); | |
144 | udelay(3); | |
145 | timeout = 300; | |
146 | do { | |
147 | val = snd_hdac_stream_readb(azx_dev, SD_CTL) & | |
148 | SD_CTL_STREAM_RESET; | |
149 | if (val) | |
150 | break; | |
151 | } while (--timeout); | |
152 | val &= ~SD_CTL_STREAM_RESET; | |
153 | snd_hdac_stream_writeb(azx_dev, SD_CTL, val); | |
154 | udelay(3); | |
155 | ||
156 | timeout = 300; | |
157 | /* waiting for hardware to report that the stream is out of reset */ | |
158 | do { | |
159 | val = snd_hdac_stream_readb(azx_dev, SD_CTL) & | |
160 | SD_CTL_STREAM_RESET; | |
161 | if (!val) | |
162 | break; | |
163 | } while (--timeout); | |
164 | ||
165 | /* reset first position - may not be synced with hw at this time */ | |
166 | if (azx_dev->posbuf) | |
167 | *azx_dev->posbuf = 0; | |
168 | } | |
169 | EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); | |
170 | ||
171 | /** | |
172 | * snd_hdac_stream_setup - set up the SD for streaming | |
173 | * @azx_dev: HD-audio core stream to set up | |
174 | */ | |
175 | int snd_hdac_stream_setup(struct hdac_stream *azx_dev) | |
176 | { | |
177 | struct hdac_bus *bus = azx_dev->bus; | |
4214c534 | 178 | struct snd_pcm_runtime *runtime; |
14752412 TI |
179 | unsigned int val; |
180 | ||
4214c534 TI |
181 | if (azx_dev->substream) |
182 | runtime = azx_dev->substream->runtime; | |
183 | else | |
184 | runtime = NULL; | |
14752412 TI |
185 | /* make sure the run bit is zero for SD */ |
186 | snd_hdac_stream_clear(azx_dev); | |
187 | /* program the stream_tag */ | |
188 | val = snd_hdac_stream_readl(azx_dev, SD_CTL); | |
189 | val = (val & ~SD_CTL_STREAM_TAG_MASK) | | |
190 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); | |
191 | if (!bus->snoop) | |
192 | val |= SD_CTL_TRAFFIC_PRIO; | |
193 | snd_hdac_stream_writel(azx_dev, SD_CTL, val); | |
194 | ||
195 | /* program the length of samples in cyclic buffer */ | |
196 | snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
197 | ||
198 | /* program the stream format */ | |
199 | /* this value needs to be the same as the one programmed */ | |
200 | snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
201 | ||
202 | /* program the stream LVI (last valid index) of the BDL */ | |
203 | snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
204 | ||
205 | /* program the BDL address */ | |
206 | /* lower BDL address */ | |
207 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); | |
208 | /* upper BDL address */ | |
209 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, | |
210 | upper_32_bits(azx_dev->bdl.addr)); | |
211 | ||
212 | /* enable the position buffer */ | |
213 | if (bus->use_posbuf && bus->posbuf.addr) { | |
214 | if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE)) | |
215 | snd_hdac_chip_writel(bus, DPLBASE, | |
216 | (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE); | |
217 | } | |
218 | ||
219 | /* set the interrupt enable bits in the descriptor control register */ | |
220 | snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK); | |
221 | ||
222 | if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK) | |
223 | azx_dev->fifo_size = | |
224 | snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1; | |
225 | else | |
226 | azx_dev->fifo_size = 0; | |
227 | ||
228 | /* when LPIB delay correction gives a small negative value, | |
229 | * we ignore it; currently set the threshold statically to | |
230 | * 64 frames | |
231 | */ | |
4214c534 | 232 | if (runtime && runtime->period_size > 64) |
14752412 TI |
233 | azx_dev->delay_negative_threshold = |
234 | -frames_to_bytes(runtime, 64); | |
235 | else | |
236 | azx_dev->delay_negative_threshold = 0; | |
237 | ||
238 | /* wallclk has 24Mhz clock source */ | |
4214c534 TI |
239 | if (runtime) |
240 | azx_dev->period_wallclk = (((runtime->period_size * 24000) / | |
14752412 TI |
241 | runtime->rate) * 1000); |
242 | ||
243 | return 0; | |
244 | } | |
245 | EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); | |
246 | ||
247 | /** | |
248 | * snd_hdac_stream_cleanup - cleanup a stream | |
249 | * @azx_dev: HD-audio core stream to clean up | |
250 | */ | |
251 | void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev) | |
252 | { | |
253 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
254 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
255 | snd_hdac_stream_writel(azx_dev, SD_CTL, 0); | |
256 | azx_dev->bufsize = 0; | |
257 | azx_dev->period_bytes = 0; | |
258 | azx_dev->format_val = 0; | |
259 | } | |
260 | EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); | |
261 | ||
262 | /** | |
263 | * snd_hdac_stream_assign - assign a stream for the PCM | |
264 | * @bus: HD-audio core bus | |
265 | * @substream: PCM substream to assign | |
266 | * | |
267 | * Look for an unused stream for the given PCM substream, assign it | |
268 | * and return the stream object. If no stream is free, returns NULL. | |
269 | * The function tries to keep using the same stream object when it's used | |
270 | * beforehand. Also, when bus->reverse_assign flag is set, the last free | |
271 | * or matching entry is returned. This is needed for some strange codecs. | |
272 | */ | |
273 | struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, | |
274 | struct snd_pcm_substream *substream) | |
275 | { | |
276 | struct hdac_stream *azx_dev; | |
277 | struct hdac_stream *res = NULL; | |
278 | ||
279 | /* make a non-zero unique key for the substream */ | |
280 | int key = (substream->pcm->device << 16) | (substream->number << 2) | | |
281 | (substream->stream + 1); | |
282 | ||
283 | list_for_each_entry(azx_dev, &bus->stream_list, list) { | |
284 | if (azx_dev->direction != substream->stream) | |
285 | continue; | |
286 | if (azx_dev->opened) | |
287 | continue; | |
288 | if (azx_dev->assigned_key == key) { | |
289 | res = azx_dev; | |
290 | break; | |
291 | } | |
292 | if (!res || bus->reverse_assign) | |
293 | res = azx_dev; | |
294 | } | |
295 | if (res) { | |
296 | spin_lock_irq(&bus->reg_lock); | |
297 | res->opened = 1; | |
298 | res->running = 0; | |
299 | res->assigned_key = key; | |
300 | res->substream = substream; | |
301 | spin_unlock_irq(&bus->reg_lock); | |
302 | } | |
303 | return res; | |
304 | } | |
305 | EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); | |
306 | ||
307 | /** | |
308 | * snd_hdac_stream_release - release the assigned stream | |
309 | * @azx_dev: HD-audio core stream to release | |
310 | * | |
311 | * Release the stream that has been assigned by snd_hdac_stream_assign(). | |
312 | */ | |
313 | void snd_hdac_stream_release(struct hdac_stream *azx_dev) | |
314 | { | |
315 | struct hdac_bus *bus = azx_dev->bus; | |
316 | ||
317 | spin_lock_irq(&bus->reg_lock); | |
318 | azx_dev->opened = 0; | |
319 | azx_dev->running = 0; | |
320 | azx_dev->substream = NULL; | |
321 | spin_unlock_irq(&bus->reg_lock); | |
322 | } | |
323 | EXPORT_SYMBOL_GPL(snd_hdac_stream_release); | |
324 | ||
4308c9b0 JK |
325 | /** |
326 | * snd_hdac_get_stream - return hdac_stream based on stream_tag and | |
327 | * direction | |
328 | * | |
329 | * @bus: HD-audio core bus | |
330 | * @dir: direction for the stream to be found | |
331 | * @stream_tag: stream tag for stream to be found | |
332 | */ | |
333 | struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, | |
334 | int dir, int stream_tag) | |
335 | { | |
336 | struct hdac_stream *s; | |
337 | ||
338 | list_for_each_entry(s, &bus->stream_list, list) { | |
339 | if (s->direction == dir && s->stream_tag == stream_tag) | |
340 | return s; | |
341 | } | |
342 | ||
343 | return NULL; | |
344 | } | |
345 | EXPORT_SYMBOL_GPL(snd_hdac_get_stream); | |
346 | ||
14752412 TI |
347 | /* |
348 | * set up a BDL entry | |
349 | */ | |
350 | static int setup_bdle(struct hdac_bus *bus, | |
351 | struct snd_dma_buffer *dmab, | |
352 | struct hdac_stream *azx_dev, __le32 **bdlp, | |
353 | int ofs, int size, int with_ioc) | |
354 | { | |
355 | __le32 *bdl = *bdlp; | |
356 | ||
357 | while (size > 0) { | |
358 | dma_addr_t addr; | |
359 | int chunk; | |
360 | ||
361 | if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) | |
362 | return -EINVAL; | |
363 | ||
364 | addr = snd_sgbuf_get_addr(dmab, ofs); | |
365 | /* program the address field of the BDL entry */ | |
366 | bdl[0] = cpu_to_le32((u32)addr); | |
367 | bdl[1] = cpu_to_le32(upper_32_bits(addr)); | |
368 | /* program the size field of the BDL entry */ | |
369 | chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); | |
370 | /* one BDLE cannot cross 4K boundary on CTHDA chips */ | |
371 | if (bus->align_bdle_4k) { | |
372 | u32 remain = 0x1000 - (ofs & 0xfff); | |
373 | ||
374 | if (chunk > remain) | |
375 | chunk = remain; | |
376 | } | |
377 | bdl[2] = cpu_to_le32(chunk); | |
378 | /* program the IOC to enable interrupt | |
379 | * only when the whole fragment is processed | |
380 | */ | |
381 | size -= chunk; | |
382 | bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); | |
383 | bdl += 4; | |
384 | azx_dev->frags++; | |
385 | ofs += chunk; | |
386 | } | |
387 | *bdlp = bdl; | |
388 | return ofs; | |
389 | } | |
390 | ||
391 | /** | |
392 | * snd_hdac_stream_setup_periods - set up BDL entries | |
393 | * @azx_dev: HD-audio core stream to set up | |
394 | * | |
395 | * Set up the buffer descriptor table of the given stream based on the | |
396 | * period and buffer sizes of the assigned PCM substream. | |
397 | */ | |
398 | int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev) | |
399 | { | |
400 | struct hdac_bus *bus = azx_dev->bus; | |
401 | struct snd_pcm_substream *substream = azx_dev->substream; | |
402 | struct snd_pcm_runtime *runtime = substream->runtime; | |
403 | __le32 *bdl; | |
404 | int i, ofs, periods, period_bytes; | |
405 | int pos_adj, pos_align; | |
406 | ||
407 | /* reset BDL address */ | |
408 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
409 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
410 | ||
411 | period_bytes = azx_dev->period_bytes; | |
412 | periods = azx_dev->bufsize / period_bytes; | |
413 | ||
414 | /* program the initial BDL entries */ | |
415 | bdl = (__le32 *)azx_dev->bdl.area; | |
416 | ofs = 0; | |
417 | azx_dev->frags = 0; | |
418 | ||
419 | pos_adj = bus->bdl_pos_adj; | |
420 | if (!azx_dev->no_period_wakeup && pos_adj > 0) { | |
421 | pos_align = pos_adj; | |
422 | pos_adj = (pos_adj * runtime->rate + 47999) / 48000; | |
423 | if (!pos_adj) | |
424 | pos_adj = pos_align; | |
425 | else | |
426 | pos_adj = ((pos_adj + pos_align - 1) / pos_align) * | |
427 | pos_align; | |
428 | pos_adj = frames_to_bytes(runtime, pos_adj); | |
429 | if (pos_adj >= period_bytes) { | |
430 | dev_warn(bus->dev, "Too big adjustment %d\n", | |
431 | pos_adj); | |
432 | pos_adj = 0; | |
433 | } else { | |
434 | ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), | |
435 | azx_dev, | |
436 | &bdl, ofs, pos_adj, true); | |
437 | if (ofs < 0) | |
438 | goto error; | |
439 | } | |
440 | } else | |
441 | pos_adj = 0; | |
442 | ||
443 | for (i = 0; i < periods; i++) { | |
444 | if (i == periods - 1 && pos_adj) | |
445 | ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), | |
446 | azx_dev, &bdl, ofs, | |
447 | period_bytes - pos_adj, 0); | |
448 | else | |
449 | ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), | |
450 | azx_dev, &bdl, ofs, | |
451 | period_bytes, | |
452 | !azx_dev->no_period_wakeup); | |
453 | if (ofs < 0) | |
454 | goto error; | |
455 | } | |
456 | return 0; | |
457 | ||
458 | error: | |
459 | dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n", | |
460 | azx_dev->bufsize, period_bytes); | |
461 | return -EINVAL; | |
462 | } | |
463 | EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods); | |
464 | ||
78dd5e21 TI |
465 | /** |
466 | * snd_hdac_stream_set_params - set stream parameters | |
86f6501b JK |
467 | * @azx_dev: HD-audio core stream for which parameters are to be set |
468 | * @format_val: format value parameter | |
469 | * | |
470 | * Setup the HD-audio core stream parameters from substream of the stream | |
471 | * and passed format value | |
472 | */ | |
473 | int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, | |
474 | unsigned int format_val) | |
475 | { | |
476 | ||
477 | unsigned int bufsize, period_bytes; | |
478 | struct snd_pcm_substream *substream = azx_dev->substream; | |
479 | struct snd_pcm_runtime *runtime; | |
480 | int err; | |
481 | ||
482 | if (!substream) | |
483 | return -EINVAL; | |
484 | runtime = substream->runtime; | |
485 | bufsize = snd_pcm_lib_buffer_bytes(substream); | |
486 | period_bytes = snd_pcm_lib_period_bytes(substream); | |
487 | ||
488 | if (bufsize != azx_dev->bufsize || | |
489 | period_bytes != azx_dev->period_bytes || | |
490 | format_val != azx_dev->format_val || | |
491 | runtime->no_period_wakeup != azx_dev->no_period_wakeup) { | |
492 | azx_dev->bufsize = bufsize; | |
493 | azx_dev->period_bytes = period_bytes; | |
494 | azx_dev->format_val = format_val; | |
495 | azx_dev->no_period_wakeup = runtime->no_period_wakeup; | |
496 | err = snd_hdac_stream_setup_periods(azx_dev); | |
497 | if (err < 0) | |
498 | return err; | |
499 | } | |
500 | return 0; | |
501 | } | |
502 | EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params); | |
503 | ||
a5a1d1c2 | 504 | static u64 azx_cc_read(const struct cyclecounter *cc) |
14752412 TI |
505 | { |
506 | struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc); | |
507 | ||
508 | return snd_hdac_chip_readl(azx_dev->bus, WALLCLK); | |
509 | } | |
510 | ||
511 | static void azx_timecounter_init(struct hdac_stream *azx_dev, | |
a5a1d1c2 | 512 | bool force, u64 last) |
14752412 TI |
513 | { |
514 | struct timecounter *tc = &azx_dev->tc; | |
515 | struct cyclecounter *cc = &azx_dev->cc; | |
516 | u64 nsec; | |
517 | ||
518 | cc->read = azx_cc_read; | |
519 | cc->mask = CLOCKSOURCE_MASK(32); | |
520 | ||
521 | /* | |
522 | * Converting from 24 MHz to ns means applying a 125/3 factor. | |
523 | * To avoid any saturation issues in intermediate operations, | |
524 | * the 125 factor is applied first. The division is applied | |
525 | * last after reading the timecounter value. | |
526 | * Applying the 1/3 factor as part of the multiplication | |
527 | * requires at least 20 bits for a decent precision, however | |
528 | * overflows occur after about 4 hours or less, not a option. | |
529 | */ | |
530 | ||
531 | cc->mult = 125; /* saturation after 195 years */ | |
532 | cc->shift = 0; | |
533 | ||
534 | nsec = 0; /* audio time is elapsed time since trigger */ | |
535 | timecounter_init(tc, cc, nsec); | |
536 | if (force) { | |
537 | /* | |
538 | * force timecounter to use predefined value, | |
539 | * used for synchronized starts | |
540 | */ | |
541 | tc->cycle_last = last; | |
542 | } | |
543 | } | |
544 | ||
545 | /** | |
546 | * snd_hdac_stream_timecounter_init - initialize time counter | |
547 | * @azx_dev: HD-audio core stream (master stream) | |
548 | * @streams: bit flags of streams to set up | |
549 | * | |
550 | * Initializes the time counter of streams marked by the bit flags (each | |
551 | * bit corresponds to the stream index). | |
552 | * The trigger timestamp of PCM substream assigned to the given stream is | |
553 | * updated accordingly, too. | |
554 | */ | |
555 | void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, | |
556 | unsigned int streams) | |
557 | { | |
558 | struct hdac_bus *bus = azx_dev->bus; | |
559 | struct snd_pcm_runtime *runtime = azx_dev->substream->runtime; | |
560 | struct hdac_stream *s; | |
561 | bool inited = false; | |
a5a1d1c2 | 562 | u64 cycle_last = 0; |
14752412 TI |
563 | int i = 0; |
564 | ||
565 | list_for_each_entry(s, &bus->stream_list, list) { | |
566 | if (streams & (1 << i)) { | |
567 | azx_timecounter_init(s, inited, cycle_last); | |
568 | if (!inited) { | |
569 | inited = true; | |
570 | cycle_last = s->tc.cycle_last; | |
571 | } | |
572 | } | |
573 | i++; | |
574 | } | |
575 | ||
576 | snd_pcm_gettime(runtime, &runtime->trigger_tstamp); | |
577 | runtime->trigger_tstamp_latched = true; | |
578 | } | |
579 | EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init); | |
580 | ||
581 | /** | |
582 | * snd_hdac_stream_sync_trigger - turn on/off stream sync register | |
583 | * @azx_dev: HD-audio core stream (master stream) | |
584 | * @streams: bit flags of streams to sync | |
585 | */ | |
586 | void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, | |
587 | unsigned int streams, unsigned int reg) | |
588 | { | |
589 | struct hdac_bus *bus = azx_dev->bus; | |
590 | unsigned int val; | |
591 | ||
592 | if (!reg) | |
593 | reg = AZX_REG_SSYNC; | |
2c1f8138 | 594 | val = _snd_hdac_chip_readl(bus, reg); |
14752412 TI |
595 | if (set) |
596 | val |= streams; | |
597 | else | |
598 | val &= ~streams; | |
2c1f8138 | 599 | _snd_hdac_chip_writel(bus, reg, val); |
14752412 TI |
600 | } |
601 | EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger); | |
602 | ||
603 | /** | |
604 | * snd_hdac_stream_sync - sync with start/strop trigger operation | |
605 | * @azx_dev: HD-audio core stream (master stream) | |
606 | * @start: true = start, false = stop | |
607 | * @streams: bit flags of streams to sync | |
608 | * | |
609 | * For @start = true, wait until all FIFOs get ready. | |
610 | * For @start = false, wait until all RUN bits are cleared. | |
611 | */ | |
612 | void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, | |
613 | unsigned int streams) | |
614 | { | |
615 | struct hdac_bus *bus = azx_dev->bus; | |
616 | int i, nwait, timeout; | |
617 | struct hdac_stream *s; | |
618 | ||
619 | for (timeout = 5000; timeout; timeout--) { | |
620 | nwait = 0; | |
621 | i = 0; | |
622 | list_for_each_entry(s, &bus->stream_list, list) { | |
623 | if (streams & (1 << i)) { | |
624 | if (start) { | |
625 | /* check FIFO gets ready */ | |
626 | if (!(snd_hdac_stream_readb(s, SD_STS) & | |
627 | SD_STS_FIFO_READY)) | |
628 | nwait++; | |
629 | } else { | |
630 | /* check RUN bit is cleared */ | |
631 | if (snd_hdac_stream_readb(s, SD_CTL) & | |
632 | SD_CTL_DMA_START) | |
633 | nwait++; | |
634 | } | |
635 | } | |
636 | i++; | |
637 | } | |
638 | if (!nwait) | |
639 | break; | |
640 | cpu_relax(); | |
641 | } | |
642 | } | |
643 | EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); | |
8f3f600b TI |
644 | |
645 | #ifdef CONFIG_SND_HDA_DSP_LOADER | |
646 | /** | |
647 | * snd_hdac_dsp_prepare - prepare for DSP loading | |
648 | * @azx_dev: HD-audio core stream used for DSP loading | |
649 | * @format: HD-audio stream format | |
650 | * @byte_size: data chunk byte size | |
651 | * @bufp: allocated buffer | |
652 | * | |
653 | * Allocate the buffer for the given size and set up the given stream for | |
654 | * DSP loading. Returns the stream tag (>= 0), or a negative error code. | |
655 | */ | |
656 | int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
657 | unsigned int byte_size, struct snd_dma_buffer *bufp) | |
658 | { | |
659 | struct hdac_bus *bus = azx_dev->bus; | |
7362b0fc | 660 | __le32 *bdl; |
8f3f600b TI |
661 | int err; |
662 | ||
663 | snd_hdac_dsp_lock(azx_dev); | |
664 | spin_lock_irq(&bus->reg_lock); | |
665 | if (azx_dev->running || azx_dev->locked) { | |
666 | spin_unlock_irq(&bus->reg_lock); | |
667 | err = -EBUSY; | |
668 | goto unlock; | |
669 | } | |
670 | azx_dev->locked = true; | |
671 | spin_unlock_irq(&bus->reg_lock); | |
672 | ||
673 | err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG, | |
674 | byte_size, bufp); | |
675 | if (err < 0) | |
676 | goto err_alloc; | |
677 | ||
4214c534 | 678 | azx_dev->substream = NULL; |
8f3f600b TI |
679 | azx_dev->bufsize = byte_size; |
680 | azx_dev->period_bytes = byte_size; | |
681 | azx_dev->format_val = format; | |
682 | ||
683 | snd_hdac_stream_reset(azx_dev); | |
684 | ||
685 | /* reset BDL address */ | |
686 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
687 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
688 | ||
689 | azx_dev->frags = 0; | |
7362b0fc | 690 | bdl = (__le32 *)azx_dev->bdl.area; |
8f3f600b TI |
691 | err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0); |
692 | if (err < 0) | |
693 | goto error; | |
694 | ||
695 | snd_hdac_stream_setup(azx_dev); | |
696 | snd_hdac_dsp_unlock(azx_dev); | |
697 | return azx_dev->stream_tag; | |
698 | ||
699 | error: | |
700 | bus->io_ops->dma_free_pages(bus, bufp); | |
701 | err_alloc: | |
702 | spin_lock_irq(&bus->reg_lock); | |
703 | azx_dev->locked = false; | |
704 | spin_unlock_irq(&bus->reg_lock); | |
705 | unlock: | |
706 | snd_hdac_dsp_unlock(azx_dev); | |
707 | return err; | |
708 | } | |
709 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); | |
710 | ||
711 | /** | |
712 | * snd_hdac_dsp_trigger - start / stop DSP loading | |
713 | * @azx_dev: HD-audio core stream used for DSP loading | |
714 | * @start: trigger start or stop | |
715 | */ | |
716 | void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) | |
717 | { | |
718 | if (start) | |
719 | snd_hdac_stream_start(azx_dev, true); | |
720 | else | |
721 | snd_hdac_stream_stop(azx_dev); | |
722 | } | |
723 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); | |
724 | ||
725 | /** | |
726 | * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal | |
727 | * @azx_dev: HD-audio core stream used for DSP loading | |
728 | * @dmab: buffer used by DSP loading | |
729 | */ | |
730 | void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
731 | struct snd_dma_buffer *dmab) | |
732 | { | |
733 | struct hdac_bus *bus = azx_dev->bus; | |
734 | ||
735 | if (!dmab->area || !azx_dev->locked) | |
736 | return; | |
737 | ||
738 | snd_hdac_dsp_lock(azx_dev); | |
739 | /* reset BDL address */ | |
740 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
741 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
742 | snd_hdac_stream_writel(azx_dev, SD_CTL, 0); | |
743 | azx_dev->bufsize = 0; | |
744 | azx_dev->period_bytes = 0; | |
745 | azx_dev->format_val = 0; | |
746 | ||
747 | bus->io_ops->dma_free_pages(bus, dmab); | |
748 | dmab->area = NULL; | |
749 | ||
750 | spin_lock_irq(&bus->reg_lock); | |
751 | azx_dev->locked = false; | |
752 | spin_unlock_irq(&bus->reg_lock); | |
753 | snd_hdac_dsp_unlock(azx_dev); | |
754 | } | |
755 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); | |
756 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ |