Commit | Line | Data |
---|---|---|
457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
14752412 TI |
2 | /* |
3 | * HD-audio stream operations | |
4 | */ | |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/delay.h> | |
8 | #include <linux/export.h> | |
5f26face | 9 | #include <linux/clocksource.h> |
3e958226 | 10 | #include <sound/compress_driver.h> |
14752412 TI |
11 | #include <sound/core.h> |
12 | #include <sound/pcm.h> | |
13 | #include <sound/hdaudio.h> | |
14 | #include <sound/hda_register.h> | |
598dfb56 | 15 | #include "trace.h" |
14752412 | 16 | |
ea2ddd25 PLB |
17 | /* |
18 | * the hdac_stream library is intended to be used with the following | |
19 | * transitions. The states are not formally defined in the code but loosely | |
20 | * inspired by boolean variables. Note that the 'prepared' field is not used | |
21 | * in this library but by the callers during the hw_params/prepare transitions | |
22 | * | |
23 | * | | |
24 | * stream_init() | | |
25 | * v | |
26 | * +--+-------+ | |
27 | * | unused | | |
28 | * +--+----+--+ | |
29 | * | ^ | |
30 | * stream_assign() | | stream_release() | |
31 | * v | | |
32 | * +--+----+--+ | |
33 | * | opened | | |
34 | * +--+----+--+ | |
35 | * | ^ | |
36 | * stream_reset() | | | |
37 | * stream_setup() | | stream_cleanup() | |
38 | * v | | |
39 | * +--+----+--+ | |
40 | * | prepared | | |
41 | * +--+----+--+ | |
42 | * | ^ | |
43 | * stream_start() | | stream_stop() | |
44 | * v | | |
45 | * +--+----+--+ | |
46 | * | running | | |
47 | * +----------+ | |
48 | */ | |
49 | ||
5dd3d271 SP |
50 | /** |
51 | * snd_hdac_get_stream_stripe_ctl - get stripe control value | |
52 | * @bus: HD-audio core bus | |
53 | * @substream: PCM substream | |
54 | */ | |
55 | int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, | |
56 | struct snd_pcm_substream *substream) | |
57 | { | |
58 | struct snd_pcm_runtime *runtime = substream->runtime; | |
59 | unsigned int channels = runtime->channels, | |
60 | rate = runtime->rate, | |
61 | bits_per_sample = runtime->sample_bits, | |
62 | max_sdo_lines, value, sdo_line; | |
63 | ||
64 | /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */ | |
65 | max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO; | |
66 | ||
67 | /* following is from HD audio spec */ | |
68 | for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) { | |
69 | if (rate > 48000) | |
70 | value = (channels * bits_per_sample * | |
71 | (rate / 48000)) / sdo_line; | |
72 | else | |
73 | value = (channels * bits_per_sample) / sdo_line; | |
74 | ||
67ae482a | 75 | if (value >= bus->sdo_limit) |
5dd3d271 SP |
76 | break; |
77 | } | |
78 | ||
79 | /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */ | |
80 | return sdo_line >> 1; | |
81 | } | |
82 | EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl); | |
83 | ||
14752412 TI |
84 | /** |
85 | * snd_hdac_stream_init - initialize each stream (aka device) | |
86 | * @bus: HD-audio core bus | |
87 | * @azx_dev: HD-audio core stream object to initialize | |
88 | * @idx: stream index number | |
89 | * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE) | |
90 | * @tag: the tag id to assign | |
91 | * | |
92 | * Assign the starting bdl address to each stream (device) and initialize. | |
93 | */ | |
94 | void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, | |
95 | int idx, int direction, int tag) | |
96 | { | |
97 | azx_dev->bus = bus; | |
14752412 TI |
98 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
99 | azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80); | |
100 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
101 | azx_dev->sd_int_sta_mask = 1 << idx; | |
102 | azx_dev->index = idx; | |
103 | azx_dev->direction = direction; | |
104 | azx_dev->stream_tag = tag; | |
8f3f600b | 105 | snd_hdac_dsp_lock_init(azx_dev); |
14752412 | 106 | list_add_tail(&azx_dev->list, &bus->stream_list); |
62582341 PLB |
107 | |
108 | if (bus->spbcap) { | |
109 | azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE + | |
110 | AZX_SPB_INTERVAL * idx + | |
111 | AZX_SPB_SPIB; | |
112 | ||
113 | azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE + | |
114 | AZX_SPB_INTERVAL * idx + | |
115 | AZX_SPB_MAXFIFO; | |
116 | } | |
117 | ||
118 | if (bus->drsmcap) | |
119 | azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE + | |
120 | AZX_DRSM_INTERVAL * idx; | |
14752412 TI |
121 | } |
122 | EXPORT_SYMBOL_GPL(snd_hdac_stream_init); | |
123 | ||
124 | /** | |
125 | * snd_hdac_stream_start - start a stream | |
126 | * @azx_dev: HD-audio core stream to start | |
14752412 TI |
127 | * |
128 | * Start a stream, set start_wallclk and set the running flag. | |
129 | */ | |
4fe20d62 | 130 | void snd_hdac_stream_start(struct hdac_stream *azx_dev) |
14752412 TI |
131 | { |
132 | struct hdac_bus *bus = azx_dev->bus; | |
9b6f7e7a | 133 | int stripe_ctl; |
14752412 | 134 | |
598dfb56 LY |
135 | trace_snd_hdac_stream_start(bus, azx_dev); |
136 | ||
14752412 | 137 | azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK); |
14752412 TI |
138 | |
139 | /* enable SIE */ | |
fc2a6cf0 KJ |
140 | snd_hdac_chip_updatel(bus, INTCTL, |
141 | 1 << azx_dev->index, | |
142 | 1 << azx_dev->index); | |
9b6f7e7a | 143 | /* set stripe control */ |
e38e486d TI |
144 | if (azx_dev->stripe) { |
145 | if (azx_dev->substream) | |
146 | stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream); | |
147 | else | |
148 | stripe_ctl = 0; | |
149 | snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, | |
150 | stripe_ctl); | |
151 | } | |
14752412 | 152 | /* set DMA start and interrupt mask */ |
942ccdd8 YS |
153 | if (bus->access_sdnctl_in_dword) |
154 | snd_hdac_stream_updatel(azx_dev, SD_CTL, | |
155 | 0, SD_CTL_DMA_START | SD_INT_MASK); | |
156 | else | |
157 | snd_hdac_stream_updateb(azx_dev, SD_CTL, | |
14752412 TI |
158 | 0, SD_CTL_DMA_START | SD_INT_MASK); |
159 | azx_dev->running = true; | |
160 | } | |
161 | EXPORT_SYMBOL_GPL(snd_hdac_stream_start); | |
162 | ||
163 | /** | |
2ea13c83 | 164 | * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers |
14752412 TI |
165 | * @azx_dev: HD-audio core stream to stop |
166 | */ | |
2ea13c83 | 167 | static void snd_hdac_stream_clear(struct hdac_stream *azx_dev) |
14752412 TI |
168 | { |
169 | snd_hdac_stream_updateb(azx_dev, SD_CTL, | |
170 | SD_CTL_DMA_START | SD_INT_MASK, 0); | |
171 | snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
6fd739c0 | 172 | if (azx_dev->stripe) |
e38e486d | 173 | snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0); |
14752412 TI |
174 | azx_dev->running = false; |
175 | } | |
14752412 TI |
176 | |
177 | /** | |
178 | * snd_hdac_stream_stop - stop a stream | |
179 | * @azx_dev: HD-audio core stream to stop | |
180 | * | |
181 | * Stop a stream DMA and disable stream interrupt | |
182 | */ | |
183 | void snd_hdac_stream_stop(struct hdac_stream *azx_dev) | |
184 | { | |
598dfb56 LY |
185 | trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev); |
186 | ||
14752412 TI |
187 | snd_hdac_stream_clear(azx_dev); |
188 | /* disable SIE */ | |
189 | snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0); | |
190 | } | |
191 | EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); | |
192 | ||
24ad3835 PLB |
193 | /** |
194 | * snd_hdac_stop_streams - stop all streams | |
195 | * @bus: HD-audio core bus | |
196 | */ | |
197 | void snd_hdac_stop_streams(struct hdac_bus *bus) | |
198 | { | |
199 | struct hdac_stream *stream; | |
200 | ||
201 | list_for_each_entry(stream, &bus->stream_list, list) | |
202 | snd_hdac_stream_stop(stream); | |
203 | } | |
204 | EXPORT_SYMBOL_GPL(snd_hdac_stop_streams); | |
205 | ||
12054f0c PLB |
206 | /** |
207 | * snd_hdac_stop_streams_and_chip - stop all streams and chip if running | |
208 | * @bus: HD-audio core bus | |
209 | */ | |
210 | void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus) | |
211 | { | |
12054f0c PLB |
212 | |
213 | if (bus->chip_init) { | |
24ad3835 | 214 | snd_hdac_stop_streams(bus); |
12054f0c PLB |
215 | snd_hdac_bus_stop_chip(bus); |
216 | } | |
217 | } | |
218 | EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip); | |
219 | ||
14752412 TI |
220 | /** |
221 | * snd_hdac_stream_reset - reset a stream | |
222 | * @azx_dev: HD-audio core stream to reset | |
223 | */ | |
224 | void snd_hdac_stream_reset(struct hdac_stream *azx_dev) | |
225 | { | |
226 | unsigned char val; | |
4106820b | 227 | int dma_run_state; |
14752412 TI |
228 | |
229 | snd_hdac_stream_clear(azx_dev); | |
230 | ||
4106820b MK |
231 | dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START; |
232 | ||
14752412 | 233 | snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); |
d9185705 AS |
234 | |
235 | /* wait for hardware to report that the stream entered reset */ | |
236 | snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300); | |
4106820b MK |
237 | |
238 | if (azx_dev->bus->dma_stop_delay && dma_run_state) | |
239 | udelay(azx_dev->bus->dma_stop_delay); | |
240 | ||
d9185705 | 241 | snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0); |
14752412 | 242 | |
d9185705 AS |
243 | /* wait for hardware to report that the stream is out of reset */ |
244 | snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300); | |
14752412 TI |
245 | |
246 | /* reset first position - may not be synced with hw at this time */ | |
247 | if (azx_dev->posbuf) | |
248 | *azx_dev->posbuf = 0; | |
249 | } | |
250 | EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); | |
251 | ||
252 | /** | |
253 | * snd_hdac_stream_setup - set up the SD for streaming | |
254 | * @azx_dev: HD-audio core stream to set up | |
5eb4ff88 | 255 | * @code_loading: Whether the stream is for PCM or code-loading. |
14752412 | 256 | */ |
5eb4ff88 | 257 | int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading) |
14752412 TI |
258 | { |
259 | struct hdac_bus *bus = azx_dev->bus; | |
4214c534 | 260 | struct snd_pcm_runtime *runtime; |
14752412 | 261 | unsigned int val; |
2ee2c75c CR |
262 | u16 reg; |
263 | int ret; | |
14752412 | 264 | |
4214c534 TI |
265 | if (azx_dev->substream) |
266 | runtime = azx_dev->substream->runtime; | |
267 | else | |
268 | runtime = NULL; | |
14752412 TI |
269 | /* make sure the run bit is zero for SD */ |
270 | snd_hdac_stream_clear(azx_dev); | |
271 | /* program the stream_tag */ | |
272 | val = snd_hdac_stream_readl(azx_dev, SD_CTL); | |
273 | val = (val & ~SD_CTL_STREAM_TAG_MASK) | | |
274 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); | |
275 | if (!bus->snoop) | |
276 | val |= SD_CTL_TRAFFIC_PRIO; | |
277 | snd_hdac_stream_writel(azx_dev, SD_CTL, val); | |
278 | ||
279 | /* program the length of samples in cyclic buffer */ | |
280 | snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
281 | ||
282 | /* program the stream format */ | |
283 | /* this value needs to be the same as the one programmed */ | |
284 | snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
285 | ||
286 | /* program the stream LVI (last valid index) of the BDL */ | |
287 | snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
288 | ||
289 | /* program the BDL address */ | |
290 | /* lower BDL address */ | |
291 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); | |
292 | /* upper BDL address */ | |
293 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, | |
294 | upper_32_bits(azx_dev->bdl.addr)); | |
295 | ||
296 | /* enable the position buffer */ | |
297 | if (bus->use_posbuf && bus->posbuf.addr) { | |
298 | if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE)) | |
299 | snd_hdac_chip_writel(bus, DPLBASE, | |
300 | (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE); | |
301 | } | |
302 | ||
303 | /* set the interrupt enable bits in the descriptor control register */ | |
304 | snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK); | |
305 | ||
5eb4ff88 CR |
306 | if (!code_loading) { |
307 | /* Once SDxFMT is set, the controller programs SDxFIFOS to non-zero value. */ | |
308 | ret = snd_hdac_stream_readw_poll(azx_dev, SD_FIFOSIZE, reg, | |
309 | reg & AZX_SD_FIFOSIZE_MASK, 3, 300); | |
310 | if (ret) | |
311 | dev_dbg(bus->dev, "polling SD_FIFOSIZE 0x%04x failed: %d\n", | |
312 | AZX_REG_SD_FIFOSIZE, ret); | |
313 | azx_dev->fifo_size = reg; | |
314 | } | |
14752412 TI |
315 | |
316 | /* when LPIB delay correction gives a small negative value, | |
317 | * we ignore it; currently set the threshold statically to | |
318 | * 64 frames | |
319 | */ | |
4214c534 | 320 | if (runtime && runtime->period_size > 64) |
14752412 TI |
321 | azx_dev->delay_negative_threshold = |
322 | -frames_to_bytes(runtime, 64); | |
323 | else | |
324 | azx_dev->delay_negative_threshold = 0; | |
325 | ||
326 | /* wallclk has 24Mhz clock source */ | |
4214c534 TI |
327 | if (runtime) |
328 | azx_dev->period_wallclk = (((runtime->period_size * 24000) / | |
14752412 TI |
329 | runtime->rate) * 1000); |
330 | ||
331 | return 0; | |
332 | } | |
333 | EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); | |
334 | ||
335 | /** | |
336 | * snd_hdac_stream_cleanup - cleanup a stream | |
337 | * @azx_dev: HD-audio core stream to clean up | |
338 | */ | |
339 | void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev) | |
340 | { | |
341 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
342 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
343 | snd_hdac_stream_writel(azx_dev, SD_CTL, 0); | |
344 | azx_dev->bufsize = 0; | |
345 | azx_dev->period_bytes = 0; | |
346 | azx_dev->format_val = 0; | |
347 | } | |
348 | EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); | |
349 | ||
350 | /** | |
351 | * snd_hdac_stream_assign - assign a stream for the PCM | |
352 | * @bus: HD-audio core bus | |
353 | * @substream: PCM substream to assign | |
354 | * | |
355 | * Look for an unused stream for the given PCM substream, assign it | |
356 | * and return the stream object. If no stream is free, returns NULL. | |
357 | * The function tries to keep using the same stream object when it's used | |
358 | * beforehand. Also, when bus->reverse_assign flag is set, the last free | |
359 | * or matching entry is returned. This is needed for some strange codecs. | |
360 | */ | |
361 | struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, | |
362 | struct snd_pcm_substream *substream) | |
363 | { | |
364 | struct hdac_stream *azx_dev; | |
365 | struct hdac_stream *res = NULL; | |
366 | ||
367 | /* make a non-zero unique key for the substream */ | |
f93dc90c CR |
368 | int key = (substream->number << 2) | (substream->stream + 1); |
369 | ||
370 | if (substream->pcm) | |
371 | key |= (substream->pcm->device << 16); | |
14752412 | 372 | |
1465d06a | 373 | spin_lock_irq(&bus->reg_lock); |
14752412 TI |
374 | list_for_each_entry(azx_dev, &bus->stream_list, list) { |
375 | if (azx_dev->direction != substream->stream) | |
376 | continue; | |
377 | if (azx_dev->opened) | |
378 | continue; | |
379 | if (azx_dev->assigned_key == key) { | |
380 | res = azx_dev; | |
381 | break; | |
382 | } | |
383 | if (!res || bus->reverse_assign) | |
384 | res = azx_dev; | |
385 | } | |
386 | if (res) { | |
14752412 TI |
387 | res->opened = 1; |
388 | res->running = 0; | |
389 | res->assigned_key = key; | |
390 | res->substream = substream; | |
14752412 | 391 | } |
1465d06a | 392 | spin_unlock_irq(&bus->reg_lock); |
14752412 TI |
393 | return res; |
394 | } | |
395 | EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); | |
396 | ||
ac3467ad PLB |
397 | /** |
398 | * snd_hdac_stream_release_locked - release the assigned stream | |
399 | * @azx_dev: HD-audio core stream to release | |
400 | * | |
401 | * Release the stream that has been assigned by snd_hdac_stream_assign(). | |
402 | * The bus->reg_lock needs to be taken at a higher level | |
403 | */ | |
404 | void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev) | |
405 | { | |
406 | azx_dev->opened = 0; | |
407 | azx_dev->running = 0; | |
408 | azx_dev->substream = NULL; | |
409 | } | |
410 | EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked); | |
411 | ||
14752412 TI |
412 | /** |
413 | * snd_hdac_stream_release - release the assigned stream | |
414 | * @azx_dev: HD-audio core stream to release | |
415 | * | |
416 | * Release the stream that has been assigned by snd_hdac_stream_assign(). | |
417 | */ | |
418 | void snd_hdac_stream_release(struct hdac_stream *azx_dev) | |
419 | { | |
420 | struct hdac_bus *bus = azx_dev->bus; | |
421 | ||
422 | spin_lock_irq(&bus->reg_lock); | |
ac3467ad | 423 | snd_hdac_stream_release_locked(azx_dev); |
14752412 TI |
424 | spin_unlock_irq(&bus->reg_lock); |
425 | } | |
426 | EXPORT_SYMBOL_GPL(snd_hdac_stream_release); | |
427 | ||
4308c9b0 JK |
428 | /** |
429 | * snd_hdac_get_stream - return hdac_stream based on stream_tag and | |
430 | * direction | |
431 | * | |
432 | * @bus: HD-audio core bus | |
433 | * @dir: direction for the stream to be found | |
434 | * @stream_tag: stream tag for stream to be found | |
435 | */ | |
436 | struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, | |
437 | int dir, int stream_tag) | |
438 | { | |
439 | struct hdac_stream *s; | |
440 | ||
441 | list_for_each_entry(s, &bus->stream_list, list) { | |
442 | if (s->direction == dir && s->stream_tag == stream_tag) | |
443 | return s; | |
444 | } | |
445 | ||
446 | return NULL; | |
447 | } | |
448 | EXPORT_SYMBOL_GPL(snd_hdac_get_stream); | |
449 | ||
14752412 TI |
450 | /* |
451 | * set up a BDL entry | |
452 | */ | |
453 | static int setup_bdle(struct hdac_bus *bus, | |
454 | struct snd_dma_buffer *dmab, | |
455 | struct hdac_stream *azx_dev, __le32 **bdlp, | |
456 | int ofs, int size, int with_ioc) | |
457 | { | |
458 | __le32 *bdl = *bdlp; | |
459 | ||
460 | while (size > 0) { | |
461 | dma_addr_t addr; | |
462 | int chunk; | |
463 | ||
464 | if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) | |
465 | return -EINVAL; | |
466 | ||
467 | addr = snd_sgbuf_get_addr(dmab, ofs); | |
468 | /* program the address field of the BDL entry */ | |
469 | bdl[0] = cpu_to_le32((u32)addr); | |
470 | bdl[1] = cpu_to_le32(upper_32_bits(addr)); | |
471 | /* program the size field of the BDL entry */ | |
472 | chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); | |
473 | /* one BDLE cannot cross 4K boundary on CTHDA chips */ | |
474 | if (bus->align_bdle_4k) { | |
475 | u32 remain = 0x1000 - (ofs & 0xfff); | |
476 | ||
477 | if (chunk > remain) | |
478 | chunk = remain; | |
479 | } | |
480 | bdl[2] = cpu_to_le32(chunk); | |
481 | /* program the IOC to enable interrupt | |
482 | * only when the whole fragment is processed | |
483 | */ | |
484 | size -= chunk; | |
485 | bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); | |
486 | bdl += 4; | |
487 | azx_dev->frags++; | |
488 | ofs += chunk; | |
489 | } | |
490 | *bdlp = bdl; | |
491 | return ofs; | |
492 | } | |
493 | ||
494 | /** | |
495 | * snd_hdac_stream_setup_periods - set up BDL entries | |
496 | * @azx_dev: HD-audio core stream to set up | |
497 | * | |
498 | * Set up the buffer descriptor table of the given stream based on the | |
499 | * period and buffer sizes of the assigned PCM substream. | |
500 | */ | |
501 | int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev) | |
502 | { | |
503 | struct hdac_bus *bus = azx_dev->bus; | |
504 | struct snd_pcm_substream *substream = azx_dev->substream; | |
3e958226 CR |
505 | struct snd_compr_stream *cstream = azx_dev->cstream; |
506 | struct snd_pcm_runtime *runtime = NULL; | |
f6b12546 | 507 | struct snd_dma_buffer *dmab; |
14752412 TI |
508 | __le32 *bdl; |
509 | int i, ofs, periods, period_bytes; | |
510 | int pos_adj, pos_align; | |
511 | ||
3e958226 CR |
512 | if (substream) { |
513 | runtime = substream->runtime; | |
514 | dmab = snd_pcm_get_dma_buf(substream); | |
515 | } else if (cstream) { | |
516 | dmab = snd_pcm_get_dma_buf(cstream); | |
084ca216 CR |
517 | } else { |
518 | WARN(1, "No substream or cstream assigned\n"); | |
519 | return -EINVAL; | |
3e958226 | 520 | } |
f6b12546 | 521 | |
14752412 TI |
522 | /* reset BDL address */ |
523 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
524 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
525 | ||
526 | period_bytes = azx_dev->period_bytes; | |
527 | periods = azx_dev->bufsize / period_bytes; | |
528 | ||
529 | /* program the initial BDL entries */ | |
530 | bdl = (__le32 *)azx_dev->bdl.area; | |
531 | ofs = 0; | |
532 | azx_dev->frags = 0; | |
533 | ||
534 | pos_adj = bus->bdl_pos_adj; | |
f6b12546 | 535 | if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) { |
14752412 | 536 | pos_align = pos_adj; |
81d0ec43 | 537 | pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000); |
14752412 TI |
538 | if (!pos_adj) |
539 | pos_adj = pos_align; | |
540 | else | |
81d0ec43 | 541 | pos_adj = roundup(pos_adj, pos_align); |
14752412 TI |
542 | pos_adj = frames_to_bytes(runtime, pos_adj); |
543 | if (pos_adj >= period_bytes) { | |
544 | dev_warn(bus->dev, "Too big adjustment %d\n", | |
545 | pos_adj); | |
546 | pos_adj = 0; | |
547 | } else { | |
f6b12546 | 548 | ofs = setup_bdle(bus, dmab, azx_dev, |
14752412 TI |
549 | &bdl, ofs, pos_adj, true); |
550 | if (ofs < 0) | |
551 | goto error; | |
552 | } | |
553 | } else | |
554 | pos_adj = 0; | |
555 | ||
556 | for (i = 0; i < periods; i++) { | |
557 | if (i == periods - 1 && pos_adj) | |
f6b12546 CR |
558 | ofs = setup_bdle(bus, dmab, azx_dev, |
559 | &bdl, ofs, period_bytes - pos_adj, 0); | |
14752412 | 560 | else |
f6b12546 CR |
561 | ofs = setup_bdle(bus, dmab, azx_dev, |
562 | &bdl, ofs, period_bytes, | |
14752412 TI |
563 | !azx_dev->no_period_wakeup); |
564 | if (ofs < 0) | |
565 | goto error; | |
566 | } | |
567 | return 0; | |
568 | ||
569 | error: | |
5f91a622 | 570 | dev_dbg(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n", |
14752412 TI |
571 | azx_dev->bufsize, period_bytes); |
572 | return -EINVAL; | |
573 | } | |
574 | EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods); | |
575 | ||
78dd5e21 TI |
576 | /** |
577 | * snd_hdac_stream_set_params - set stream parameters | |
86f6501b JK |
578 | * @azx_dev: HD-audio core stream for which parameters are to be set |
579 | * @format_val: format value parameter | |
580 | * | |
581 | * Setup the HD-audio core stream parameters from substream of the stream | |
582 | * and passed format value | |
583 | */ | |
584 | int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, | |
585 | unsigned int format_val) | |
586 | { | |
86f6501b | 587 | struct snd_pcm_substream *substream = azx_dev->substream; |
3e958226 | 588 | struct snd_compr_stream *cstream = azx_dev->cstream; |
f6b12546 CR |
589 | unsigned int bufsize, period_bytes; |
590 | unsigned int no_period_wakeup; | |
86f6501b JK |
591 | int err; |
592 | ||
3e958226 CR |
593 | if (substream) { |
594 | bufsize = snd_pcm_lib_buffer_bytes(substream); | |
595 | period_bytes = snd_pcm_lib_period_bytes(substream); | |
596 | no_period_wakeup = substream->runtime->no_period_wakeup; | |
597 | } else if (cstream) { | |
598 | bufsize = cstream->runtime->buffer_size; | |
599 | period_bytes = cstream->runtime->fragment_size; | |
600 | no_period_wakeup = 0; | |
601 | } else { | |
86f6501b | 602 | return -EINVAL; |
3e958226 | 603 | } |
86f6501b JK |
604 | |
605 | if (bufsize != azx_dev->bufsize || | |
606 | period_bytes != azx_dev->period_bytes || | |
607 | format_val != azx_dev->format_val || | |
f6b12546 | 608 | no_period_wakeup != azx_dev->no_period_wakeup) { |
86f6501b JK |
609 | azx_dev->bufsize = bufsize; |
610 | azx_dev->period_bytes = period_bytes; | |
611 | azx_dev->format_val = format_val; | |
f6b12546 | 612 | azx_dev->no_period_wakeup = no_period_wakeup; |
86f6501b JK |
613 | err = snd_hdac_stream_setup_periods(azx_dev); |
614 | if (err < 0) | |
615 | return err; | |
616 | } | |
617 | return 0; | |
618 | } | |
619 | EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params); | |
620 | ||
a5a1d1c2 | 621 | static u64 azx_cc_read(const struct cyclecounter *cc) |
14752412 TI |
622 | { |
623 | struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc); | |
624 | ||
625 | return snd_hdac_chip_readl(azx_dev->bus, WALLCLK); | |
626 | } | |
627 | ||
628 | static void azx_timecounter_init(struct hdac_stream *azx_dev, | |
a5a1d1c2 | 629 | bool force, u64 last) |
14752412 TI |
630 | { |
631 | struct timecounter *tc = &azx_dev->tc; | |
632 | struct cyclecounter *cc = &azx_dev->cc; | |
633 | u64 nsec; | |
634 | ||
635 | cc->read = azx_cc_read; | |
636 | cc->mask = CLOCKSOURCE_MASK(32); | |
637 | ||
638 | /* | |
6dd21ad8 TG |
639 | * Calculate the optimal mult/shift values. The counter wraps |
640 | * around after ~178.9 seconds. | |
14752412 | 641 | */ |
6dd21ad8 TG |
642 | clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000, |
643 | NSEC_PER_SEC, 178); | |
14752412 TI |
644 | |
645 | nsec = 0; /* audio time is elapsed time since trigger */ | |
646 | timecounter_init(tc, cc, nsec); | |
647 | if (force) { | |
648 | /* | |
649 | * force timecounter to use predefined value, | |
650 | * used for synchronized starts | |
651 | */ | |
652 | tc->cycle_last = last; | |
653 | } | |
654 | } | |
655 | ||
656 | /** | |
657 | * snd_hdac_stream_timecounter_init - initialize time counter | |
658 | * @azx_dev: HD-audio core stream (master stream) | |
659 | * @streams: bit flags of streams to set up | |
660 | * | |
661 | * Initializes the time counter of streams marked by the bit flags (each | |
662 | * bit corresponds to the stream index). | |
663 | * The trigger timestamp of PCM substream assigned to the given stream is | |
664 | * updated accordingly, too. | |
665 | */ | |
666 | void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, | |
667 | unsigned int streams) | |
668 | { | |
669 | struct hdac_bus *bus = azx_dev->bus; | |
670 | struct snd_pcm_runtime *runtime = azx_dev->substream->runtime; | |
671 | struct hdac_stream *s; | |
672 | bool inited = false; | |
a5a1d1c2 | 673 | u64 cycle_last = 0; |
14752412 TI |
674 | |
675 | list_for_each_entry(s, &bus->stream_list, list) { | |
26257869 | 676 | if ((streams & (1 << s->index))) { |
14752412 TI |
677 | azx_timecounter_init(s, inited, cycle_last); |
678 | if (!inited) { | |
679 | inited = true; | |
680 | cycle_last = s->tc.cycle_last; | |
681 | } | |
682 | } | |
14752412 TI |
683 | } |
684 | ||
685 | snd_pcm_gettime(runtime, &runtime->trigger_tstamp); | |
686 | runtime->trigger_tstamp_latched = true; | |
687 | } | |
688 | EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init); | |
689 | ||
690 | /** | |
691 | * snd_hdac_stream_sync_trigger - turn on/off stream sync register | |
692 | * @azx_dev: HD-audio core stream (master stream) | |
6e57188f | 693 | * @set: true = set, false = clear |
14752412 | 694 | * @streams: bit flags of streams to sync |
6e57188f | 695 | * @reg: the stream sync register address |
14752412 TI |
696 | */ |
697 | void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, | |
698 | unsigned int streams, unsigned int reg) | |
699 | { | |
700 | struct hdac_bus *bus = azx_dev->bus; | |
701 | unsigned int val; | |
702 | ||
703 | if (!reg) | |
704 | reg = AZX_REG_SSYNC; | |
2c1f8138 | 705 | val = _snd_hdac_chip_readl(bus, reg); |
14752412 TI |
706 | if (set) |
707 | val |= streams; | |
708 | else | |
709 | val &= ~streams; | |
2c1f8138 | 710 | _snd_hdac_chip_writel(bus, reg, val); |
14752412 TI |
711 | } |
712 | EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger); | |
713 | ||
714 | /** | |
8518c648 | 715 | * snd_hdac_stream_sync - sync with start/stop trigger operation |
14752412 TI |
716 | * @azx_dev: HD-audio core stream (master stream) |
717 | * @start: true = start, false = stop | |
718 | * @streams: bit flags of streams to sync | |
719 | * | |
720 | * For @start = true, wait until all FIFOs get ready. | |
721 | * For @start = false, wait until all RUN bits are cleared. | |
722 | */ | |
723 | void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, | |
724 | unsigned int streams) | |
725 | { | |
726 | struct hdac_bus *bus = azx_dev->bus; | |
26257869 | 727 | int nwait, timeout; |
14752412 TI |
728 | struct hdac_stream *s; |
729 | ||
730 | for (timeout = 5000; timeout; timeout--) { | |
731 | nwait = 0; | |
14752412 | 732 | list_for_each_entry(s, &bus->stream_list, list) { |
26257869 | 733 | if (!(streams & (1 << s->index))) |
7faa26c1 MK |
734 | continue; |
735 | ||
736 | if (start) { | |
737 | /* check FIFO gets ready */ | |
738 | if (!(snd_hdac_stream_readb(s, SD_STS) & | |
739 | SD_STS_FIFO_READY)) | |
740 | nwait++; | |
741 | } else { | |
742 | /* check RUN bit is cleared */ | |
743 | if (snd_hdac_stream_readb(s, SD_CTL) & | |
744 | SD_CTL_DMA_START) { | |
745 | nwait++; | |
746 | /* | |
747 | * Perform stream reset if DMA RUN | |
748 | * bit not cleared within given timeout | |
749 | */ | |
750 | if (timeout == 1) | |
751 | snd_hdac_stream_reset(s); | |
14752412 TI |
752 | } |
753 | } | |
14752412 TI |
754 | } |
755 | if (!nwait) | |
756 | break; | |
757 | cpu_relax(); | |
758 | } | |
759 | } | |
760 | EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); | |
8f3f600b | 761 | |
62582341 PLB |
762 | /** |
763 | * snd_hdac_stream_spbcap_enable - enable SPIB for a stream | |
764 | * @bus: HD-audio core bus | |
765 | * @enable: flag to enable/disable SPIB | |
766 | * @index: stream index for which SPIB need to be enabled | |
767 | */ | |
768 | void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus, | |
769 | bool enable, int index) | |
770 | { | |
771 | u32 mask = 0; | |
772 | ||
773 | if (!bus->spbcap) { | |
774 | dev_err(bus->dev, "Address of SPB capability is NULL\n"); | |
775 | return; | |
776 | } | |
777 | ||
778 | mask |= (1 << index); | |
779 | ||
780 | if (enable) | |
781 | snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask); | |
782 | else | |
783 | snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0); | |
784 | } | |
785 | EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable); | |
786 | ||
787 | /** | |
788 | * snd_hdac_stream_set_spib - sets the spib value of a stream | |
789 | * @bus: HD-audio core bus | |
790 | * @azx_dev: hdac_stream | |
791 | * @value: spib value to set | |
792 | */ | |
793 | int snd_hdac_stream_set_spib(struct hdac_bus *bus, | |
794 | struct hdac_stream *azx_dev, u32 value) | |
795 | { | |
796 | if (!bus->spbcap) { | |
797 | dev_err(bus->dev, "Address of SPB capability is NULL\n"); | |
798 | return -EINVAL; | |
799 | } | |
800 | ||
801 | writel(value, azx_dev->spib_addr); | |
802 | ||
803 | return 0; | |
804 | } | |
805 | EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib); | |
806 | ||
807 | /** | |
808 | * snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream | |
809 | * @bus: HD-audio core bus | |
810 | * @azx_dev: hdac_stream | |
811 | * | |
812 | * Return maxfifo for the stream | |
813 | */ | |
814 | int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus, | |
815 | struct hdac_stream *azx_dev) | |
816 | { | |
817 | if (!bus->spbcap) { | |
818 | dev_err(bus->dev, "Address of SPB capability is NULL\n"); | |
819 | return -EINVAL; | |
820 | } | |
821 | ||
822 | return readl(azx_dev->fifo_addr); | |
823 | } | |
824 | EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo); | |
825 | ||
826 | /** | |
827 | * snd_hdac_stream_drsm_enable - enable DMA resume for a stream | |
828 | * @bus: HD-audio core bus | |
829 | * @enable: flag to enable/disable DRSM | |
830 | * @index: stream index for which DRSM need to be enabled | |
831 | */ | |
832 | void snd_hdac_stream_drsm_enable(struct hdac_bus *bus, | |
833 | bool enable, int index) | |
834 | { | |
835 | u32 mask = 0; | |
836 | ||
837 | if (!bus->drsmcap) { | |
838 | dev_err(bus->dev, "Address of DRSM capability is NULL\n"); | |
839 | return; | |
840 | } | |
841 | ||
842 | mask |= (1 << index); | |
843 | ||
844 | if (enable) | |
845 | snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask); | |
846 | else | |
847 | snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0); | |
848 | } | |
849 | EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable); | |
850 | ||
efffb014 CR |
851 | /* |
852 | * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream | |
853 | * @azx_dev: HD-audio core stream to await RSM for | |
854 | * | |
855 | * Returns 0 on success and -ETIMEDOUT upon a timeout. | |
856 | */ | |
857 | int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev) | |
858 | { | |
859 | struct hdac_bus *bus = azx_dev->bus; | |
860 | u32 mask, reg; | |
861 | int ret; | |
862 | ||
863 | mask = 1 << azx_dev->index; | |
864 | ||
865 | ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus, | |
866 | bus->drsmcap + AZX_REG_DRSM_CTL); | |
867 | if (ret) | |
868 | dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret); | |
869 | return ret; | |
870 | } | |
871 | EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm); | |
872 | ||
62582341 PLB |
873 | /** |
874 | * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream | |
875 | * @bus: HD-audio core bus | |
876 | * @azx_dev: hdac_stream | |
877 | * @value: dpib value to set | |
878 | */ | |
879 | int snd_hdac_stream_set_dpibr(struct hdac_bus *bus, | |
880 | struct hdac_stream *azx_dev, u32 value) | |
881 | { | |
882 | if (!bus->drsmcap) { | |
883 | dev_err(bus->dev, "Address of DRSM capability is NULL\n"); | |
884 | return -EINVAL; | |
885 | } | |
886 | ||
887 | writel(value, azx_dev->dpibr_addr); | |
888 | ||
889 | return 0; | |
890 | } | |
891 | EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr); | |
892 | ||
893 | /** | |
894 | * snd_hdac_stream_set_lpib - sets the lpib value of a stream | |
895 | * @azx_dev: hdac_stream | |
896 | * @value: lpib value to set | |
897 | */ | |
898 | int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value) | |
899 | { | |
900 | snd_hdac_stream_writel(azx_dev, SD_LPIB, value); | |
901 | ||
902 | return 0; | |
903 | } | |
904 | EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib); | |
905 | ||
8f3f600b TI |
906 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
907 | /** | |
908 | * snd_hdac_dsp_prepare - prepare for DSP loading | |
909 | * @azx_dev: HD-audio core stream used for DSP loading | |
910 | * @format: HD-audio stream format | |
911 | * @byte_size: data chunk byte size | |
912 | * @bufp: allocated buffer | |
913 | * | |
914 | * Allocate the buffer for the given size and set up the given stream for | |
915 | * DSP loading. Returns the stream tag (>= 0), or a negative error code. | |
916 | */ | |
917 | int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
918 | unsigned int byte_size, struct snd_dma_buffer *bufp) | |
919 | { | |
920 | struct hdac_bus *bus = azx_dev->bus; | |
7362b0fc | 921 | __le32 *bdl; |
8f3f600b TI |
922 | int err; |
923 | ||
924 | snd_hdac_dsp_lock(azx_dev); | |
925 | spin_lock_irq(&bus->reg_lock); | |
926 | if (azx_dev->running || azx_dev->locked) { | |
927 | spin_unlock_irq(&bus->reg_lock); | |
928 | err = -EBUSY; | |
929 | goto unlock; | |
930 | } | |
931 | azx_dev->locked = true; | |
932 | spin_unlock_irq(&bus->reg_lock); | |
933 | ||
619a1f19 TI |
934 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev, |
935 | byte_size, bufp); | |
8f3f600b TI |
936 | if (err < 0) |
937 | goto err_alloc; | |
938 | ||
4214c534 | 939 | azx_dev->substream = NULL; |
8f3f600b TI |
940 | azx_dev->bufsize = byte_size; |
941 | azx_dev->period_bytes = byte_size; | |
942 | azx_dev->format_val = format; | |
943 | ||
944 | snd_hdac_stream_reset(azx_dev); | |
945 | ||
946 | /* reset BDL address */ | |
947 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
948 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
949 | ||
950 | azx_dev->frags = 0; | |
7362b0fc | 951 | bdl = (__le32 *)azx_dev->bdl.area; |
8f3f600b TI |
952 | err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0); |
953 | if (err < 0) | |
954 | goto error; | |
955 | ||
5eb4ff88 | 956 | snd_hdac_stream_setup(azx_dev, true); |
8f3f600b TI |
957 | snd_hdac_dsp_unlock(azx_dev); |
958 | return azx_dev->stream_tag; | |
959 | ||
960 | error: | |
619a1f19 | 961 | snd_dma_free_pages(bufp); |
8f3f600b TI |
962 | err_alloc: |
963 | spin_lock_irq(&bus->reg_lock); | |
964 | azx_dev->locked = false; | |
965 | spin_unlock_irq(&bus->reg_lock); | |
966 | unlock: | |
967 | snd_hdac_dsp_unlock(azx_dev); | |
968 | return err; | |
969 | } | |
970 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); | |
971 | ||
972 | /** | |
973 | * snd_hdac_dsp_trigger - start / stop DSP loading | |
974 | * @azx_dev: HD-audio core stream used for DSP loading | |
975 | * @start: trigger start or stop | |
976 | */ | |
977 | void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) | |
978 | { | |
979 | if (start) | |
4fe20d62 | 980 | snd_hdac_stream_start(azx_dev); |
8f3f600b TI |
981 | else |
982 | snd_hdac_stream_stop(azx_dev); | |
983 | } | |
984 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); | |
985 | ||
986 | /** | |
987 | * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal | |
988 | * @azx_dev: HD-audio core stream used for DSP loading | |
989 | * @dmab: buffer used by DSP loading | |
990 | */ | |
991 | void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
992 | struct snd_dma_buffer *dmab) | |
993 | { | |
994 | struct hdac_bus *bus = azx_dev->bus; | |
995 | ||
996 | if (!dmab->area || !azx_dev->locked) | |
997 | return; | |
998 | ||
999 | snd_hdac_dsp_lock(azx_dev); | |
1000 | /* reset BDL address */ | |
1001 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
1002 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
1003 | snd_hdac_stream_writel(azx_dev, SD_CTL, 0); | |
1004 | azx_dev->bufsize = 0; | |
1005 | azx_dev->period_bytes = 0; | |
1006 | azx_dev->format_val = 0; | |
1007 | ||
619a1f19 | 1008 | snd_dma_free_pages(dmab); |
8f3f600b TI |
1009 | dmab->area = NULL; |
1010 | ||
1011 | spin_lock_irq(&bus->reg_lock); | |
1012 | azx_dev->locked = false; | |
1013 | spin_unlock_irq(&bus->reg_lock); | |
1014 | snd_hdac_dsp_unlock(azx_dev); | |
1015 | } | |
1016 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); | |
1017 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ |