Commit | Line | Data |
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14752412 TI |
1 | /* |
2 | * HD-audio controller helpers | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/export.h> | |
8 | #include <sound/core.h> | |
9 | #include <sound/hdaudio.h> | |
10 | #include <sound/hda_register.h> | |
11 | ||
12 | /* clear CORB read pointer properly */ | |
13 | static void azx_clear_corbrp(struct hdac_bus *bus) | |
14 | { | |
15 | int timeout; | |
16 | ||
17 | for (timeout = 1000; timeout > 0; timeout--) { | |
18 | if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST) | |
19 | break; | |
20 | udelay(1); | |
21 | } | |
22 | if (timeout <= 0) | |
23 | dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", | |
24 | snd_hdac_chip_readw(bus, CORBRP)); | |
25 | ||
26 | snd_hdac_chip_writew(bus, CORBRP, 0); | |
27 | for (timeout = 1000; timeout > 0; timeout--) { | |
28 | if (snd_hdac_chip_readw(bus, CORBRP) == 0) | |
29 | break; | |
30 | udelay(1); | |
31 | } | |
32 | if (timeout <= 0) | |
33 | dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n", | |
34 | snd_hdac_chip_readw(bus, CORBRP)); | |
35 | } | |
36 | ||
37 | /** | |
38 | * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers | |
39 | * @bus: HD-audio core bus | |
40 | */ | |
41 | void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus) | |
42 | { | |
b61749a8 YZ |
43 | WARN_ON_ONCE(!bus->rb.area); |
44 | ||
14752412 TI |
45 | spin_lock_irq(&bus->reg_lock); |
46 | /* CORB set up */ | |
47 | bus->corb.addr = bus->rb.addr; | |
48 | bus->corb.buf = (__le32 *)bus->rb.area; | |
49 | snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr); | |
50 | snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr)); | |
51 | ||
52 | /* set the corb size to 256 entries (ULI requires explicitly) */ | |
53 | snd_hdac_chip_writeb(bus, CORBSIZE, 0x02); | |
54 | /* set the corb write pointer to 0 */ | |
55 | snd_hdac_chip_writew(bus, CORBWP, 0); | |
56 | ||
57 | /* reset the corb hw read pointer */ | |
58 | snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST); | |
59 | if (!bus->corbrp_self_clear) | |
60 | azx_clear_corbrp(bus); | |
61 | ||
62 | /* enable corb dma */ | |
63 | snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN); | |
64 | ||
65 | /* RIRB set up */ | |
66 | bus->rirb.addr = bus->rb.addr + 2048; | |
67 | bus->rirb.buf = (__le32 *)(bus->rb.area + 2048); | |
68 | bus->rirb.wp = bus->rirb.rp = 0; | |
69 | memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds)); | |
70 | snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr); | |
71 | snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr)); | |
72 | ||
73 | /* set the rirb size to 256 entries (ULI requires explicitly) */ | |
74 | snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02); | |
75 | /* reset the rirb hw write pointer */ | |
76 | snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST); | |
77 | /* set N=1, get RIRB response interrupt for new entry */ | |
78 | snd_hdac_chip_writew(bus, RINTCNT, 1); | |
79 | /* enable rirb dma and response irq */ | |
80 | snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN); | |
81 | spin_unlock_irq(&bus->reg_lock); | |
82 | } | |
83 | EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io); | |
84 | ||
38b19ed7 JK |
85 | /* wait for cmd dmas till they are stopped */ |
86 | static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus) | |
87 | { | |
88 | unsigned long timeout; | |
89 | ||
90 | timeout = jiffies + msecs_to_jiffies(100); | |
91 | while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN) | |
92 | && time_before(jiffies, timeout)) | |
93 | udelay(10); | |
94 | ||
95 | timeout = jiffies + msecs_to_jiffies(100); | |
96 | while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN) | |
97 | && time_before(jiffies, timeout)) | |
98 | udelay(10); | |
99 | } | |
100 | ||
14752412 TI |
101 | /** |
102 | * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers | |
103 | * @bus: HD-audio core bus | |
104 | */ | |
105 | void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus) | |
106 | { | |
107 | spin_lock_irq(&bus->reg_lock); | |
108 | /* disable ringbuffer DMAs */ | |
109 | snd_hdac_chip_writeb(bus, RIRBCTL, 0); | |
110 | snd_hdac_chip_writeb(bus, CORBCTL, 0); | |
96001376 JK |
111 | spin_unlock_irq(&bus->reg_lock); |
112 | ||
38b19ed7 | 113 | hdac_wait_for_cmd_dmas(bus); |
96001376 JK |
114 | |
115 | spin_lock_irq(&bus->reg_lock); | |
14752412 TI |
116 | /* disable unsolicited responses */ |
117 | snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0); | |
118 | spin_unlock_irq(&bus->reg_lock); | |
119 | } | |
120 | EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io); | |
121 | ||
122 | static unsigned int azx_command_addr(u32 cmd) | |
123 | { | |
124 | unsigned int addr = cmd >> 28; | |
125 | ||
126 | if (snd_BUG_ON(addr >= HDA_MAX_CODECS)) | |
127 | addr = 0; | |
128 | return addr; | |
129 | } | |
130 | ||
131 | /** | |
132 | * snd_hdac_bus_send_cmd - send a command verb via CORB | |
133 | * @bus: HD-audio core bus | |
134 | * @val: encoded verb value to send | |
135 | * | |
136 | * Returns zero for success or a negative error code. | |
137 | */ | |
138 | int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val) | |
139 | { | |
140 | unsigned int addr = azx_command_addr(val); | |
141 | unsigned int wp, rp; | |
142 | ||
143 | spin_lock_irq(&bus->reg_lock); | |
144 | ||
145 | bus->last_cmd[azx_command_addr(val)] = val; | |
146 | ||
147 | /* add command to corb */ | |
148 | wp = snd_hdac_chip_readw(bus, CORBWP); | |
149 | if (wp == 0xffff) { | |
150 | /* something wrong, controller likely turned to D3 */ | |
151 | spin_unlock_irq(&bus->reg_lock); | |
152 | return -EIO; | |
153 | } | |
154 | wp++; | |
155 | wp %= AZX_MAX_CORB_ENTRIES; | |
156 | ||
157 | rp = snd_hdac_chip_readw(bus, CORBRP); | |
158 | if (wp == rp) { | |
159 | /* oops, it's full */ | |
160 | spin_unlock_irq(&bus->reg_lock); | |
161 | return -EAGAIN; | |
162 | } | |
163 | ||
164 | bus->rirb.cmds[addr]++; | |
165 | bus->corb.buf[wp] = cpu_to_le32(val); | |
166 | snd_hdac_chip_writew(bus, CORBWP, wp); | |
167 | ||
168 | spin_unlock_irq(&bus->reg_lock); | |
169 | ||
170 | return 0; | |
171 | } | |
172 | EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd); | |
173 | ||
174 | #define AZX_RIRB_EX_UNSOL_EV (1<<4) | |
175 | ||
176 | /** | |
177 | * snd_hdac_bus_update_rirb - retrieve RIRB entries | |
178 | * @bus: HD-audio core bus | |
179 | * | |
180 | * Usually called from interrupt handler. | |
181 | */ | |
182 | void snd_hdac_bus_update_rirb(struct hdac_bus *bus) | |
183 | { | |
184 | unsigned int rp, wp; | |
185 | unsigned int addr; | |
186 | u32 res, res_ex; | |
187 | ||
188 | wp = snd_hdac_chip_readw(bus, RIRBWP); | |
189 | if (wp == 0xffff) { | |
190 | /* something wrong, controller likely turned to D3 */ | |
191 | return; | |
192 | } | |
193 | ||
194 | if (wp == bus->rirb.wp) | |
195 | return; | |
196 | bus->rirb.wp = wp; | |
197 | ||
198 | while (bus->rirb.rp != wp) { | |
199 | bus->rirb.rp++; | |
200 | bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES; | |
201 | ||
202 | rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | |
203 | res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]); | |
204 | res = le32_to_cpu(bus->rirb.buf[rp]); | |
205 | addr = res_ex & 0xf; | |
206 | if (addr >= HDA_MAX_CODECS) { | |
207 | dev_err(bus->dev, | |
208 | "spurious response %#x:%#x, rp = %d, wp = %d", | |
209 | res, res_ex, bus->rirb.rp, wp); | |
210 | snd_BUG(); | |
211 | } else if (res_ex & AZX_RIRB_EX_UNSOL_EV) | |
212 | snd_hdac_bus_queue_event(bus, res, res_ex); | |
213 | else if (bus->rirb.cmds[addr]) { | |
214 | bus->rirb.res[addr] = res; | |
215 | bus->rirb.cmds[addr]--; | |
216 | } else { | |
217 | dev_err_ratelimited(bus->dev, | |
218 | "spurious response %#x:%#x, last cmd=%#08x\n", | |
219 | res, res_ex, bus->last_cmd[addr]); | |
220 | } | |
221 | } | |
222 | } | |
223 | EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb); | |
224 | ||
225 | /** | |
226 | * snd_hdac_bus_get_response - receive a response via RIRB | |
227 | * @bus: HD-audio core bus | |
228 | * @addr: codec address | |
229 | * @res: pointer to store the value, NULL when not needed | |
230 | * | |
231 | * Returns zero if a value is read, or a negative error code. | |
232 | */ | |
233 | int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, | |
234 | unsigned int *res) | |
235 | { | |
236 | unsigned long timeout; | |
237 | unsigned long loopcounter; | |
238 | ||
239 | timeout = jiffies + msecs_to_jiffies(1000); | |
240 | ||
241 | for (loopcounter = 0;; loopcounter++) { | |
5e13cf6c BL |
242 | if (bus->polling_mode) |
243 | snd_hdac_bus_update_rirb(bus); | |
14752412 TI |
244 | spin_lock_irq(&bus->reg_lock); |
245 | if (!bus->rirb.cmds[addr]) { | |
246 | if (res) | |
247 | *res = bus->rirb.res[addr]; /* the last value */ | |
248 | spin_unlock_irq(&bus->reg_lock); | |
249 | return 0; | |
250 | } | |
251 | spin_unlock_irq(&bus->reg_lock); | |
252 | if (time_after(jiffies, timeout)) | |
253 | break; | |
254 | if (loopcounter > 3000) | |
255 | msleep(2); /* temporary workaround */ | |
256 | else { | |
257 | udelay(10); | |
258 | cond_resched(); | |
259 | } | |
260 | } | |
261 | ||
262 | return -EIO; | |
263 | } | |
264 | EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response); | |
265 | ||
6720b384 VK |
266 | #define HDAC_MAX_CAPS 10 |
267 | /** | |
268 | * snd_hdac_bus_parse_capabilities - parse capability structure | |
269 | * @bus: the pointer to bus object | |
270 | * | |
271 | * Returns 0 if successful, or a negative error code. | |
272 | */ | |
273 | int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus) | |
274 | { | |
275 | unsigned int cur_cap; | |
276 | unsigned int offset; | |
277 | unsigned int counter = 0; | |
278 | ||
ccfdf9f6 | 279 | offset = snd_hdac_chip_readw(bus, LLCH); |
6720b384 VK |
280 | |
281 | /* Lets walk the linked capabilities list */ | |
282 | do { | |
2c1f8138 | 283 | cur_cap = _snd_hdac_chip_readl(bus, offset); |
6720b384 VK |
284 | |
285 | dev_dbg(bus->dev, "Capability version: 0x%x\n", | |
286 | (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF); | |
287 | ||
288 | dev_dbg(bus->dev, "HDA capability ID: 0x%x\n", | |
289 | (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF); | |
290 | ||
098a0a62 TI |
291 | if (cur_cap == -1) { |
292 | dev_dbg(bus->dev, "Invalid capability reg read\n"); | |
293 | break; | |
294 | } | |
295 | ||
6720b384 VK |
296 | switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) { |
297 | case AZX_ML_CAP_ID: | |
298 | dev_dbg(bus->dev, "Found ML capability\n"); | |
299 | bus->mlcap = bus->remap_addr + offset; | |
300 | break; | |
301 | ||
302 | case AZX_GTS_CAP_ID: | |
303 | dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset); | |
304 | bus->gtscap = bus->remap_addr + offset; | |
305 | break; | |
306 | ||
307 | case AZX_PP_CAP_ID: | |
308 | /* PP capability found, the Audio DSP is present */ | |
309 | dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset); | |
310 | bus->ppcap = bus->remap_addr + offset; | |
311 | break; | |
312 | ||
313 | case AZX_SPB_CAP_ID: | |
314 | /* SPIB capability found, handler function */ | |
315 | dev_dbg(bus->dev, "Found SPB capability\n"); | |
316 | bus->spbcap = bus->remap_addr + offset; | |
317 | break; | |
318 | ||
319 | case AZX_DRSM_CAP_ID: | |
320 | /* DMA resume capability found, handler function */ | |
321 | dev_dbg(bus->dev, "Found DRSM capability\n"); | |
322 | bus->drsmcap = bus->remap_addr + offset; | |
323 | break; | |
324 | ||
325 | default: | |
b676da70 RU |
326 | dev_err(bus->dev, "Unknown capability %d\n", cur_cap); |
327 | cur_cap = 0; | |
6720b384 VK |
328 | break; |
329 | } | |
330 | ||
331 | counter++; | |
332 | ||
333 | if (counter > HDAC_MAX_CAPS) { | |
334 | dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n"); | |
335 | break; | |
336 | } | |
337 | ||
338 | /* read the offset of next capability */ | |
339 | offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK; | |
340 | ||
341 | } while (offset); | |
342 | ||
343 | return 0; | |
344 | } | |
345 | EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities); | |
346 | ||
14752412 TI |
347 | /* |
348 | * Lowlevel interface | |
349 | */ | |
350 | ||
351 | /** | |
352 | * snd_hdac_bus_enter_link_reset - enter link reset | |
353 | * @bus: HD-audio core bus | |
354 | * | |
355 | * Enter to the link reset state. | |
356 | */ | |
357 | void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus) | |
358 | { | |
359 | unsigned long timeout; | |
360 | ||
361 | /* reset controller */ | |
362 | snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0); | |
363 | ||
364 | timeout = jiffies + msecs_to_jiffies(100); | |
365 | while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) && | |
366 | time_before(jiffies, timeout)) | |
367 | usleep_range(500, 1000); | |
368 | } | |
369 | EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset); | |
370 | ||
371 | /** | |
372 | * snd_hdac_bus_exit_link_reset - exit link reset | |
373 | * @bus: HD-audio core bus | |
374 | * | |
375 | * Exit from the link reset state. | |
376 | */ | |
377 | void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus) | |
378 | { | |
379 | unsigned long timeout; | |
380 | ||
081e01f0 | 381 | snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET); |
14752412 TI |
382 | |
383 | timeout = jiffies + msecs_to_jiffies(100); | |
384 | while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout)) | |
385 | usleep_range(500, 1000); | |
386 | } | |
387 | EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset); | |
388 | ||
389 | /* reset codec link */ | |
75383f8d | 390 | int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset) |
14752412 TI |
391 | { |
392 | if (!full_reset) | |
393 | goto skip_reset; | |
394 | ||
395 | /* clear STATESTS */ | |
396 | snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); | |
397 | ||
398 | /* reset controller */ | |
399 | snd_hdac_bus_enter_link_reset(bus); | |
400 | ||
401 | /* delay for >= 100us for codec PLL to settle per spec | |
402 | * Rev 0.9 section 5.5.1 | |
403 | */ | |
404 | usleep_range(500, 1000); | |
405 | ||
406 | /* Bring controller out of reset */ | |
407 | snd_hdac_bus_exit_link_reset(bus); | |
408 | ||
409 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ | |
410 | usleep_range(1000, 1200); | |
411 | ||
412 | skip_reset: | |
413 | /* check to see if controller is ready */ | |
414 | if (!snd_hdac_chip_readb(bus, GCTL)) { | |
75383f8d | 415 | dev_dbg(bus->dev, "controller not ready!\n"); |
14752412 TI |
416 | return -EBUSY; |
417 | } | |
418 | ||
419 | /* Accept unsolicited responses */ | |
081e01f0 | 420 | snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL); |
14752412 TI |
421 | |
422 | /* detect codecs */ | |
423 | if (!bus->codec_mask) { | |
424 | bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS); | |
425 | dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask); | |
426 | } | |
427 | ||
428 | return 0; | |
429 | } | |
75383f8d | 430 | EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link); |
14752412 TI |
431 | |
432 | /* enable interrupts */ | |
433 | static void azx_int_enable(struct hdac_bus *bus) | |
434 | { | |
435 | /* enable controller CIE and GIE */ | |
081e01f0 KJ |
436 | snd_hdac_chip_updatel(bus, INTCTL, |
437 | AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, | |
438 | AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN); | |
14752412 TI |
439 | } |
440 | ||
441 | /* disable interrupts */ | |
442 | static void azx_int_disable(struct hdac_bus *bus) | |
443 | { | |
444 | struct hdac_stream *azx_dev; | |
445 | ||
446 | /* disable interrupts in stream descriptor */ | |
447 | list_for_each_entry(azx_dev, &bus->stream_list, list) | |
448 | snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0); | |
449 | ||
450 | /* disable SIE for all streams */ | |
451 | snd_hdac_chip_writeb(bus, INTCTL, 0); | |
452 | ||
453 | /* disable controller CIE and GIE */ | |
454 | snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0); | |
455 | } | |
456 | ||
457 | /* clear interrupts */ | |
458 | static void azx_int_clear(struct hdac_bus *bus) | |
459 | { | |
460 | struct hdac_stream *azx_dev; | |
461 | ||
462 | /* clear stream status */ | |
463 | list_for_each_entry(azx_dev, &bus->stream_list, list) | |
464 | snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
465 | ||
466 | /* clear STATESTS */ | |
467 | snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); | |
468 | ||
469 | /* clear rirb status */ | |
470 | snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); | |
471 | ||
472 | /* clear int status */ | |
473 | snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM); | |
474 | } | |
475 | ||
476 | /** | |
477 | * snd_hdac_bus_init_chip - reset and start the controller registers | |
478 | * @bus: HD-audio core bus | |
479 | * @full_reset: Do full reset | |
480 | */ | |
481 | bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset) | |
482 | { | |
483 | if (bus->chip_init) | |
484 | return false; | |
485 | ||
486 | /* reset controller */ | |
75383f8d | 487 | snd_hdac_bus_reset_link(bus, full_reset); |
14752412 | 488 | |
b61749a8 | 489 | /* clear interrupts */ |
14752412 | 490 | azx_int_clear(bus); |
14752412 TI |
491 | |
492 | /* initialize the codec command I/O */ | |
493 | snd_hdac_bus_init_cmd_io(bus); | |
494 | ||
b61749a8 YZ |
495 | /* enable interrupts after CORB/RIRB buffers are initialized above */ |
496 | azx_int_enable(bus); | |
497 | ||
14752412 TI |
498 | /* program the position buffer */ |
499 | if (bus->use_posbuf && bus->posbuf.addr) { | |
500 | snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr); | |
501 | snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr)); | |
502 | } | |
503 | ||
504 | bus->chip_init = true; | |
505 | return true; | |
506 | } | |
507 | EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip); | |
508 | ||
509 | /** | |
510 | * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os | |
511 | * @bus: HD-audio core bus | |
512 | */ | |
513 | void snd_hdac_bus_stop_chip(struct hdac_bus *bus) | |
514 | { | |
515 | if (!bus->chip_init) | |
516 | return; | |
517 | ||
518 | /* disable interrupts */ | |
519 | azx_int_disable(bus); | |
520 | azx_int_clear(bus); | |
521 | ||
522 | /* disable CORB/RIRB */ | |
523 | snd_hdac_bus_stop_cmd_io(bus); | |
524 | ||
525 | /* disable position buffer */ | |
526 | if (bus->posbuf.addr) { | |
527 | snd_hdac_chip_writel(bus, DPLBASE, 0); | |
528 | snd_hdac_chip_writel(bus, DPUBASE, 0); | |
529 | } | |
530 | ||
531 | bus->chip_init = false; | |
532 | } | |
533 | EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip); | |
534 | ||
535 | /** | |
536 | * snd_hdac_bus_handle_stream_irq - interrupt handler for streams | |
537 | * @bus: HD-audio core bus | |
538 | * @status: INTSTS register value | |
539 | * @ask: callback to be called for woken streams | |
473f4145 TI |
540 | * |
541 | * Returns the bits of handled streams, or zero if no stream is handled. | |
14752412 | 542 | */ |
473f4145 | 543 | int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, |
14752412 TI |
544 | void (*ack)(struct hdac_bus *, |
545 | struct hdac_stream *)) | |
546 | { | |
547 | struct hdac_stream *azx_dev; | |
548 | u8 sd_status; | |
473f4145 | 549 | int handled = 0; |
14752412 TI |
550 | |
551 | list_for_each_entry(azx_dev, &bus->stream_list, list) { | |
552 | if (status & azx_dev->sd_int_sta_mask) { | |
553 | sd_status = snd_hdac_stream_readb(azx_dev, SD_STS); | |
554 | snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
473f4145 | 555 | handled |= 1 << azx_dev->index; |
14752412 TI |
556 | if (!azx_dev->substream || !azx_dev->running || |
557 | !(sd_status & SD_INT_COMPLETE)) | |
558 | continue; | |
559 | if (ack) | |
560 | ack(bus, azx_dev); | |
561 | } | |
562 | } | |
473f4145 | 563 | return handled; |
14752412 TI |
564 | } |
565 | EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq); | |
304dad30 JK |
566 | |
567 | /** | |
568 | * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers | |
569 | * @bus: HD-audio core bus | |
570 | * | |
571 | * Call this after assigning the all streams. | |
572 | * Returns zero for success, or a negative error code. | |
573 | */ | |
574 | int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus) | |
575 | { | |
576 | struct hdac_stream *s; | |
577 | int num_streams = 0; | |
578 | int err; | |
579 | ||
580 | list_for_each_entry(s, &bus->stream_list, list) { | |
581 | /* allocate memory for the BDL for each stream */ | |
582 | err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, | |
583 | BDL_SIZE, &s->bdl); | |
584 | num_streams++; | |
585 | if (err < 0) | |
586 | return -ENOMEM; | |
587 | } | |
588 | ||
589 | if (WARN_ON(!num_streams)) | |
590 | return -EINVAL; | |
591 | /* allocate memory for the position buffer */ | |
592 | err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, | |
593 | num_streams * 8, &bus->posbuf); | |
594 | if (err < 0) | |
595 | return -ENOMEM; | |
596 | list_for_each_entry(s, &bus->stream_list, list) | |
597 | s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8); | |
598 | ||
599 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | |
600 | return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, | |
601 | PAGE_SIZE, &bus->rb); | |
602 | } | |
603 | EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages); | |
604 | ||
605 | /** | |
606 | * snd_hdac_bus_free_stream_pages - release BDL and other buffers | |
607 | * @bus: HD-audio core bus | |
608 | */ | |
609 | void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus) | |
610 | { | |
611 | struct hdac_stream *s; | |
612 | ||
613 | list_for_each_entry(s, &bus->stream_list, list) { | |
614 | if (s->bdl.area) | |
615 | bus->io_ops->dma_free_pages(bus, &s->bdl); | |
616 | } | |
617 | ||
618 | if (bus->rb.area) | |
619 | bus->io_ops->dma_free_pages(bus, &bus->rb); | |
620 | if (bus->posbuf.area) | |
621 | bus->io_ops->dma_free_pages(bus, &bus->posbuf); | |
622 | } | |
623 | EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages); |