Commit | Line | Data |
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14752412 TI |
1 | /* |
2 | * HD-audio controller helpers | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/export.h> | |
8 | #include <sound/core.h> | |
9 | #include <sound/hdaudio.h> | |
10 | #include <sound/hda_register.h> | |
11 | ||
12 | /* clear CORB read pointer properly */ | |
13 | static void azx_clear_corbrp(struct hdac_bus *bus) | |
14 | { | |
15 | int timeout; | |
16 | ||
17 | for (timeout = 1000; timeout > 0; timeout--) { | |
18 | if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST) | |
19 | break; | |
20 | udelay(1); | |
21 | } | |
22 | if (timeout <= 0) | |
23 | dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", | |
24 | snd_hdac_chip_readw(bus, CORBRP)); | |
25 | ||
26 | snd_hdac_chip_writew(bus, CORBRP, 0); | |
27 | for (timeout = 1000; timeout > 0; timeout--) { | |
28 | if (snd_hdac_chip_readw(bus, CORBRP) == 0) | |
29 | break; | |
30 | udelay(1); | |
31 | } | |
32 | if (timeout <= 0) | |
33 | dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n", | |
34 | snd_hdac_chip_readw(bus, CORBRP)); | |
35 | } | |
36 | ||
37 | /** | |
38 | * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers | |
39 | * @bus: HD-audio core bus | |
40 | */ | |
41 | void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus) | |
42 | { | |
43 | spin_lock_irq(&bus->reg_lock); | |
44 | /* CORB set up */ | |
45 | bus->corb.addr = bus->rb.addr; | |
46 | bus->corb.buf = (__le32 *)bus->rb.area; | |
47 | snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr); | |
48 | snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr)); | |
49 | ||
50 | /* set the corb size to 256 entries (ULI requires explicitly) */ | |
51 | snd_hdac_chip_writeb(bus, CORBSIZE, 0x02); | |
52 | /* set the corb write pointer to 0 */ | |
53 | snd_hdac_chip_writew(bus, CORBWP, 0); | |
54 | ||
55 | /* reset the corb hw read pointer */ | |
56 | snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST); | |
57 | if (!bus->corbrp_self_clear) | |
58 | azx_clear_corbrp(bus); | |
59 | ||
60 | /* enable corb dma */ | |
61 | snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN); | |
62 | ||
63 | /* RIRB set up */ | |
64 | bus->rirb.addr = bus->rb.addr + 2048; | |
65 | bus->rirb.buf = (__le32 *)(bus->rb.area + 2048); | |
66 | bus->rirb.wp = bus->rirb.rp = 0; | |
67 | memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds)); | |
68 | snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr); | |
69 | snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr)); | |
70 | ||
71 | /* set the rirb size to 256 entries (ULI requires explicitly) */ | |
72 | snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02); | |
73 | /* reset the rirb hw write pointer */ | |
74 | snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST); | |
75 | /* set N=1, get RIRB response interrupt for new entry */ | |
76 | snd_hdac_chip_writew(bus, RINTCNT, 1); | |
77 | /* enable rirb dma and response irq */ | |
78 | snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN); | |
79 | spin_unlock_irq(&bus->reg_lock); | |
80 | } | |
81 | EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io); | |
82 | ||
38b19ed7 JK |
83 | /* wait for cmd dmas till they are stopped */ |
84 | static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus) | |
85 | { | |
86 | unsigned long timeout; | |
87 | ||
88 | timeout = jiffies + msecs_to_jiffies(100); | |
89 | while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN) | |
90 | && time_before(jiffies, timeout)) | |
91 | udelay(10); | |
92 | ||
93 | timeout = jiffies + msecs_to_jiffies(100); | |
94 | while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN) | |
95 | && time_before(jiffies, timeout)) | |
96 | udelay(10); | |
97 | } | |
98 | ||
14752412 TI |
99 | /** |
100 | * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers | |
101 | * @bus: HD-audio core bus | |
102 | */ | |
103 | void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus) | |
104 | { | |
105 | spin_lock_irq(&bus->reg_lock); | |
106 | /* disable ringbuffer DMAs */ | |
107 | snd_hdac_chip_writeb(bus, RIRBCTL, 0); | |
108 | snd_hdac_chip_writeb(bus, CORBCTL, 0); | |
38b19ed7 | 109 | hdac_wait_for_cmd_dmas(bus); |
14752412 TI |
110 | /* disable unsolicited responses */ |
111 | snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0); | |
112 | spin_unlock_irq(&bus->reg_lock); | |
113 | } | |
114 | EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io); | |
115 | ||
116 | static unsigned int azx_command_addr(u32 cmd) | |
117 | { | |
118 | unsigned int addr = cmd >> 28; | |
119 | ||
120 | if (snd_BUG_ON(addr >= HDA_MAX_CODECS)) | |
121 | addr = 0; | |
122 | return addr; | |
123 | } | |
124 | ||
125 | /** | |
126 | * snd_hdac_bus_send_cmd - send a command verb via CORB | |
127 | * @bus: HD-audio core bus | |
128 | * @val: encoded verb value to send | |
129 | * | |
130 | * Returns zero for success or a negative error code. | |
131 | */ | |
132 | int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val) | |
133 | { | |
134 | unsigned int addr = azx_command_addr(val); | |
135 | unsigned int wp, rp; | |
136 | ||
137 | spin_lock_irq(&bus->reg_lock); | |
138 | ||
139 | bus->last_cmd[azx_command_addr(val)] = val; | |
140 | ||
141 | /* add command to corb */ | |
142 | wp = snd_hdac_chip_readw(bus, CORBWP); | |
143 | if (wp == 0xffff) { | |
144 | /* something wrong, controller likely turned to D3 */ | |
145 | spin_unlock_irq(&bus->reg_lock); | |
146 | return -EIO; | |
147 | } | |
148 | wp++; | |
149 | wp %= AZX_MAX_CORB_ENTRIES; | |
150 | ||
151 | rp = snd_hdac_chip_readw(bus, CORBRP); | |
152 | if (wp == rp) { | |
153 | /* oops, it's full */ | |
154 | spin_unlock_irq(&bus->reg_lock); | |
155 | return -EAGAIN; | |
156 | } | |
157 | ||
158 | bus->rirb.cmds[addr]++; | |
159 | bus->corb.buf[wp] = cpu_to_le32(val); | |
160 | snd_hdac_chip_writew(bus, CORBWP, wp); | |
161 | ||
162 | spin_unlock_irq(&bus->reg_lock); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd); | |
167 | ||
168 | #define AZX_RIRB_EX_UNSOL_EV (1<<4) | |
169 | ||
170 | /** | |
171 | * snd_hdac_bus_update_rirb - retrieve RIRB entries | |
172 | * @bus: HD-audio core bus | |
173 | * | |
174 | * Usually called from interrupt handler. | |
175 | */ | |
176 | void snd_hdac_bus_update_rirb(struct hdac_bus *bus) | |
177 | { | |
178 | unsigned int rp, wp; | |
179 | unsigned int addr; | |
180 | u32 res, res_ex; | |
181 | ||
182 | wp = snd_hdac_chip_readw(bus, RIRBWP); | |
183 | if (wp == 0xffff) { | |
184 | /* something wrong, controller likely turned to D3 */ | |
185 | return; | |
186 | } | |
187 | ||
188 | if (wp == bus->rirb.wp) | |
189 | return; | |
190 | bus->rirb.wp = wp; | |
191 | ||
192 | while (bus->rirb.rp != wp) { | |
193 | bus->rirb.rp++; | |
194 | bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES; | |
195 | ||
196 | rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | |
197 | res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]); | |
198 | res = le32_to_cpu(bus->rirb.buf[rp]); | |
199 | addr = res_ex & 0xf; | |
200 | if (addr >= HDA_MAX_CODECS) { | |
201 | dev_err(bus->dev, | |
202 | "spurious response %#x:%#x, rp = %d, wp = %d", | |
203 | res, res_ex, bus->rirb.rp, wp); | |
204 | snd_BUG(); | |
205 | } else if (res_ex & AZX_RIRB_EX_UNSOL_EV) | |
206 | snd_hdac_bus_queue_event(bus, res, res_ex); | |
207 | else if (bus->rirb.cmds[addr]) { | |
208 | bus->rirb.res[addr] = res; | |
209 | bus->rirb.cmds[addr]--; | |
210 | } else { | |
211 | dev_err_ratelimited(bus->dev, | |
212 | "spurious response %#x:%#x, last cmd=%#08x\n", | |
213 | res, res_ex, bus->last_cmd[addr]); | |
214 | } | |
215 | } | |
216 | } | |
217 | EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb); | |
218 | ||
219 | /** | |
220 | * snd_hdac_bus_get_response - receive a response via RIRB | |
221 | * @bus: HD-audio core bus | |
222 | * @addr: codec address | |
223 | * @res: pointer to store the value, NULL when not needed | |
224 | * | |
225 | * Returns zero if a value is read, or a negative error code. | |
226 | */ | |
227 | int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, | |
228 | unsigned int *res) | |
229 | { | |
230 | unsigned long timeout; | |
231 | unsigned long loopcounter; | |
232 | ||
233 | timeout = jiffies + msecs_to_jiffies(1000); | |
234 | ||
235 | for (loopcounter = 0;; loopcounter++) { | |
236 | spin_lock_irq(&bus->reg_lock); | |
237 | if (!bus->rirb.cmds[addr]) { | |
238 | if (res) | |
239 | *res = bus->rirb.res[addr]; /* the last value */ | |
240 | spin_unlock_irq(&bus->reg_lock); | |
241 | return 0; | |
242 | } | |
243 | spin_unlock_irq(&bus->reg_lock); | |
244 | if (time_after(jiffies, timeout)) | |
245 | break; | |
246 | if (loopcounter > 3000) | |
247 | msleep(2); /* temporary workaround */ | |
248 | else { | |
249 | udelay(10); | |
250 | cond_resched(); | |
251 | } | |
252 | } | |
253 | ||
254 | return -EIO; | |
255 | } | |
256 | EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response); | |
257 | ||
258 | /* | |
259 | * Lowlevel interface | |
260 | */ | |
261 | ||
262 | /** | |
263 | * snd_hdac_bus_enter_link_reset - enter link reset | |
264 | * @bus: HD-audio core bus | |
265 | * | |
266 | * Enter to the link reset state. | |
267 | */ | |
268 | void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus) | |
269 | { | |
270 | unsigned long timeout; | |
271 | ||
272 | /* reset controller */ | |
273 | snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0); | |
274 | ||
275 | timeout = jiffies + msecs_to_jiffies(100); | |
276 | while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) && | |
277 | time_before(jiffies, timeout)) | |
278 | usleep_range(500, 1000); | |
279 | } | |
280 | EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset); | |
281 | ||
282 | /** | |
283 | * snd_hdac_bus_exit_link_reset - exit link reset | |
284 | * @bus: HD-audio core bus | |
285 | * | |
286 | * Exit from the link reset state. | |
287 | */ | |
288 | void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus) | |
289 | { | |
290 | unsigned long timeout; | |
291 | ||
292 | snd_hdac_chip_updateb(bus, GCTL, 0, AZX_GCTL_RESET); | |
293 | ||
294 | timeout = jiffies + msecs_to_jiffies(100); | |
295 | while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout)) | |
296 | usleep_range(500, 1000); | |
297 | } | |
298 | EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset); | |
299 | ||
300 | /* reset codec link */ | |
301 | static int azx_reset(struct hdac_bus *bus, bool full_reset) | |
302 | { | |
303 | if (!full_reset) | |
304 | goto skip_reset; | |
305 | ||
306 | /* clear STATESTS */ | |
307 | snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); | |
308 | ||
309 | /* reset controller */ | |
310 | snd_hdac_bus_enter_link_reset(bus); | |
311 | ||
312 | /* delay for >= 100us for codec PLL to settle per spec | |
313 | * Rev 0.9 section 5.5.1 | |
314 | */ | |
315 | usleep_range(500, 1000); | |
316 | ||
317 | /* Bring controller out of reset */ | |
318 | snd_hdac_bus_exit_link_reset(bus); | |
319 | ||
320 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ | |
321 | usleep_range(1000, 1200); | |
322 | ||
323 | skip_reset: | |
324 | /* check to see if controller is ready */ | |
325 | if (!snd_hdac_chip_readb(bus, GCTL)) { | |
326 | dev_dbg(bus->dev, "azx_reset: controller not ready!\n"); | |
327 | return -EBUSY; | |
328 | } | |
329 | ||
330 | /* Accept unsolicited responses */ | |
331 | snd_hdac_chip_updatel(bus, GCTL, 0, AZX_GCTL_UNSOL); | |
332 | ||
333 | /* detect codecs */ | |
334 | if (!bus->codec_mask) { | |
335 | bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS); | |
336 | dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask); | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | /* enable interrupts */ | |
343 | static void azx_int_enable(struct hdac_bus *bus) | |
344 | { | |
345 | /* enable controller CIE and GIE */ | |
346 | snd_hdac_chip_updatel(bus, INTCTL, 0, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN); | |
347 | } | |
348 | ||
349 | /* disable interrupts */ | |
350 | static void azx_int_disable(struct hdac_bus *bus) | |
351 | { | |
352 | struct hdac_stream *azx_dev; | |
353 | ||
354 | /* disable interrupts in stream descriptor */ | |
355 | list_for_each_entry(azx_dev, &bus->stream_list, list) | |
356 | snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0); | |
357 | ||
358 | /* disable SIE for all streams */ | |
359 | snd_hdac_chip_writeb(bus, INTCTL, 0); | |
360 | ||
361 | /* disable controller CIE and GIE */ | |
362 | snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0); | |
363 | } | |
364 | ||
365 | /* clear interrupts */ | |
366 | static void azx_int_clear(struct hdac_bus *bus) | |
367 | { | |
368 | struct hdac_stream *azx_dev; | |
369 | ||
370 | /* clear stream status */ | |
371 | list_for_each_entry(azx_dev, &bus->stream_list, list) | |
372 | snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
373 | ||
374 | /* clear STATESTS */ | |
375 | snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); | |
376 | ||
377 | /* clear rirb status */ | |
378 | snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); | |
379 | ||
380 | /* clear int status */ | |
381 | snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM); | |
382 | } | |
383 | ||
384 | /** | |
385 | * snd_hdac_bus_init_chip - reset and start the controller registers | |
386 | * @bus: HD-audio core bus | |
387 | * @full_reset: Do full reset | |
388 | */ | |
389 | bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset) | |
390 | { | |
391 | if (bus->chip_init) | |
392 | return false; | |
393 | ||
394 | /* reset controller */ | |
395 | azx_reset(bus, full_reset); | |
396 | ||
397 | /* initialize interrupts */ | |
398 | azx_int_clear(bus); | |
399 | azx_int_enable(bus); | |
400 | ||
401 | /* initialize the codec command I/O */ | |
402 | snd_hdac_bus_init_cmd_io(bus); | |
403 | ||
404 | /* program the position buffer */ | |
405 | if (bus->use_posbuf && bus->posbuf.addr) { | |
406 | snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr); | |
407 | snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr)); | |
408 | } | |
409 | ||
410 | bus->chip_init = true; | |
411 | return true; | |
412 | } | |
413 | EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip); | |
414 | ||
415 | /** | |
416 | * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os | |
417 | * @bus: HD-audio core bus | |
418 | */ | |
419 | void snd_hdac_bus_stop_chip(struct hdac_bus *bus) | |
420 | { | |
421 | if (!bus->chip_init) | |
422 | return; | |
423 | ||
424 | /* disable interrupts */ | |
425 | azx_int_disable(bus); | |
426 | azx_int_clear(bus); | |
427 | ||
428 | /* disable CORB/RIRB */ | |
429 | snd_hdac_bus_stop_cmd_io(bus); | |
430 | ||
431 | /* disable position buffer */ | |
432 | if (bus->posbuf.addr) { | |
433 | snd_hdac_chip_writel(bus, DPLBASE, 0); | |
434 | snd_hdac_chip_writel(bus, DPUBASE, 0); | |
435 | } | |
436 | ||
437 | bus->chip_init = false; | |
438 | } | |
439 | EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip); | |
440 | ||
441 | /** | |
442 | * snd_hdac_bus_handle_stream_irq - interrupt handler for streams | |
443 | * @bus: HD-audio core bus | |
444 | * @status: INTSTS register value | |
445 | * @ask: callback to be called for woken streams | |
473f4145 TI |
446 | * |
447 | * Returns the bits of handled streams, or zero if no stream is handled. | |
14752412 | 448 | */ |
473f4145 | 449 | int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, |
14752412 TI |
450 | void (*ack)(struct hdac_bus *, |
451 | struct hdac_stream *)) | |
452 | { | |
453 | struct hdac_stream *azx_dev; | |
454 | u8 sd_status; | |
473f4145 | 455 | int handled = 0; |
14752412 TI |
456 | |
457 | list_for_each_entry(azx_dev, &bus->stream_list, list) { | |
458 | if (status & azx_dev->sd_int_sta_mask) { | |
459 | sd_status = snd_hdac_stream_readb(azx_dev, SD_STS); | |
460 | snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
473f4145 | 461 | handled |= 1 << azx_dev->index; |
14752412 TI |
462 | if (!azx_dev->substream || !azx_dev->running || |
463 | !(sd_status & SD_INT_COMPLETE)) | |
464 | continue; | |
465 | if (ack) | |
466 | ack(bus, azx_dev); | |
467 | } | |
468 | } | |
473f4145 | 469 | return handled; |
14752412 TI |
470 | } |
471 | EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq); | |
304dad30 JK |
472 | |
473 | /** | |
474 | * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers | |
475 | * @bus: HD-audio core bus | |
476 | * | |
477 | * Call this after assigning the all streams. | |
478 | * Returns zero for success, or a negative error code. | |
479 | */ | |
480 | int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus) | |
481 | { | |
482 | struct hdac_stream *s; | |
483 | int num_streams = 0; | |
484 | int err; | |
485 | ||
486 | list_for_each_entry(s, &bus->stream_list, list) { | |
487 | /* allocate memory for the BDL for each stream */ | |
488 | err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, | |
489 | BDL_SIZE, &s->bdl); | |
490 | num_streams++; | |
491 | if (err < 0) | |
492 | return -ENOMEM; | |
493 | } | |
494 | ||
495 | if (WARN_ON(!num_streams)) | |
496 | return -EINVAL; | |
497 | /* allocate memory for the position buffer */ | |
498 | err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, | |
499 | num_streams * 8, &bus->posbuf); | |
500 | if (err < 0) | |
501 | return -ENOMEM; | |
502 | list_for_each_entry(s, &bus->stream_list, list) | |
503 | s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8); | |
504 | ||
505 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | |
506 | return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, | |
507 | PAGE_SIZE, &bus->rb); | |
508 | } | |
509 | EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages); | |
510 | ||
511 | /** | |
512 | * snd_hdac_bus_free_stream_pages - release BDL and other buffers | |
513 | * @bus: HD-audio core bus | |
514 | */ | |
515 | void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus) | |
516 | { | |
517 | struct hdac_stream *s; | |
518 | ||
519 | list_for_each_entry(s, &bus->stream_list, list) { | |
520 | if (s->bdl.area) | |
521 | bus->io_ops->dma_free_pages(bus, &s->bdl); | |
522 | } | |
523 | ||
524 | if (bus->rb.area) | |
525 | bus->io_ops->dma_free_pages(bus, &bus->rb); | |
526 | if (bus->posbuf.area) | |
527 | bus->io_ops->dma_free_pages(bus, &bus->posbuf); | |
528 | } | |
529 | EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages); |