ALSA: hdac: clear link output stream mapping
[linux-2.6-block.git] / sound / hda / ext / hdac_ext_controller.c
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8e8e69d6 1// SPDX-License-Identifier: GPL-2.0-only
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2/*
3 * hdac-ext-controller.c - HD-audio extended controller functions.
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
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9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 */
11
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <sound/hda_register.h>
15#include <sound/hdaudio_ext.h>
16
17/*
18 * maximum HDAC capablities we should parse to avoid endless looping:
19 * currently we have 4 extended caps, so this is future proof for now.
20 * extend when this limit is seen meeting in real HW
21 */
22#define HDAC_MAX_CAPS 10
23
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24/*
25 * processing pipe helpers - these helpers are useful for dealing with HDA
26 * new capability of processing pipelines
27 */
28
29/**
30 * snd_hdac_ext_bus_ppcap_enable - enable/disable processing pipe capability
31 * @ebus: HD-audio extended core bus
32 * @enable: flag to turn on/off the capability
33 */
76f56fae 34void snd_hdac_ext_bus_ppcap_enable(struct hdac_bus *bus, bool enable)
0b00a561 35{
0b00a561 36
ec8ae570 37 if (!bus->ppcap) {
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38 dev_err(bus->dev, "Address of PP capability is NULL");
39 return;
40 }
41
42 if (enable)
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43 snd_hdac_updatel(bus->ppcap, AZX_REG_PP_PPCTL,
44 AZX_PPCTL_GPROCEN, AZX_PPCTL_GPROCEN);
0b00a561 45 else
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46 snd_hdac_updatel(bus->ppcap, AZX_REG_PP_PPCTL,
47 AZX_PPCTL_GPROCEN, 0);
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48}
49EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_ppcap_enable);
50
51/**
52 * snd_hdac_ext_bus_ppcap_int_enable - ppcap interrupt enable/disable
53 * @ebus: HD-audio extended core bus
54 * @enable: flag to enable/disable interrupt
55 */
76f56fae 56void snd_hdac_ext_bus_ppcap_int_enable(struct hdac_bus *bus, bool enable)
0b00a561 57{
0b00a561 58
ec8ae570 59 if (!bus->ppcap) {
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60 dev_err(bus->dev, "Address of PP capability is NULL\n");
61 return;
62 }
63
64 if (enable)
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65 snd_hdac_updatel(bus->ppcap, AZX_REG_PP_PPCTL,
66 AZX_PPCTL_PIE, AZX_PPCTL_PIE);
0b00a561 67 else
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68 snd_hdac_updatel(bus->ppcap, AZX_REG_PP_PPCTL,
69 AZX_PPCTL_PIE, 0);
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70}
71EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_ppcap_int_enable);
72
73/*
74 * Multilink helpers - these helpers are useful for dealing with HDA
75 * new multilink capability
76 */
77
78/**
79 * snd_hdac_ext_bus_get_ml_capabilities - get multilink capability
80 * @ebus: HD-audio extended core bus
81 *
82 * This will parse all links and read the mlink capabilities and add them
83 * in hlink_list of extended hdac bus
84 * Note: this will be freed on bus exit by driver
85 */
76f56fae 86int snd_hdac_ext_bus_get_ml_capabilities(struct hdac_bus *bus)
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87{
88 int idx;
89 u32 link_count;
90 struct hdac_ext_link *hlink;
0b00a561 91
ec8ae570 92 link_count = readl(bus->mlcap + AZX_REG_ML_MLCD) + 1;
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93
94 dev_dbg(bus->dev, "In %s Link count: %d\n", __func__, link_count);
95
96 for (idx = 0; idx < link_count; idx++) {
97 hlink = kzalloc(sizeof(*hlink), GFP_KERNEL);
98 if (!hlink)
99 return -ENOMEM;
100 hlink->index = idx;
101 hlink->bus = bus;
ec8ae570 102 hlink->ml_addr = bus->mlcap + AZX_ML_BASE +
0b00a561 103 (AZX_ML_INTERVAL * idx);
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104 hlink->lcaps = readl(hlink->ml_addr + AZX_REG_ML_LCAP);
105 hlink->lsdiid = readw(hlink->ml_addr + AZX_REG_ML_LSDIID);
0b00a561 106
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107 /* since link in On, update the ref */
108 hlink->ref_count = 1;
109
76f56fae 110 list_add_tail(&hlink->list, &bus->hlink_list);
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111 }
112
113 return 0;
114}
115EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_get_ml_capabilities);
116
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117/**
118 * snd_hdac_link_free_all- free hdac extended link objects
119 *
120 * @ebus: HD-audio ext core bus
121 */
122
76f56fae 123void snd_hdac_link_free_all(struct hdac_bus *bus)
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124{
125 struct hdac_ext_link *l;
126
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127 while (!list_empty(&bus->hlink_list)) {
128 l = list_first_entry(&bus->hlink_list, struct hdac_ext_link, list);
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129 list_del(&l->list);
130 kfree(l);
131 }
132}
133EXPORT_SYMBOL_GPL(snd_hdac_link_free_all);
134
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135/**
136 * snd_hdac_ext_bus_get_link_index - get link based on codec name
137 * @ebus: HD-audio extended core bus
138 * @codec_name: codec name
139 */
76f56fae 140struct hdac_ext_link *snd_hdac_ext_bus_get_link(struct hdac_bus *bus,
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141 const char *codec_name)
142{
143 int i;
144 struct hdac_ext_link *hlink = NULL;
145 int bus_idx, addr;
146
147 if (sscanf(codec_name, "ehdaudio%dD%d", &bus_idx, &addr) != 2)
148 return NULL;
76f56fae 149 if (bus->idx != bus_idx)
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150 return NULL;
151
76f56fae 152 list_for_each_entry(hlink, &bus->hlink_list, list) {
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153 for (i = 0; i < HDA_MAX_CODECS; i++) {
154 if (hlink->lsdiid & (0x1 << addr))
155 return hlink;
156 }
157 }
158
159 return NULL;
160}
161EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_get_link);
162
163static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
164{
165 int timeout;
166 u32 val;
dde5bff5 167 int mask = (1 << AZX_MLCTL_CPA_SHIFT);
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168
169 udelay(3);
cf8fe58b 170 timeout = 150;
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171
172 do {
a7e3dd85 173 val = readl(link->ml_addr + AZX_REG_ML_LCTL);
0b00a561 174 if (enable) {
dde5bff5 175 if (((val & mask) >> AZX_MLCTL_CPA_SHIFT))
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176 return 0;
177 } else {
dde5bff5 178 if (!((val & mask) >> AZX_MLCTL_CPA_SHIFT))
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179 return 0;
180 }
181 udelay(3);
182 } while (--timeout);
183
184 return -EIO;
185}
186
187/**
188 * snd_hdac_ext_bus_link_power_up -power up hda link
189 * @link: HD-audio extended link
190 */
191int snd_hdac_ext_bus_link_power_up(struct hdac_ext_link *link)
192{
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193 snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL,
194 AZX_MLCTL_SPA, AZX_MLCTL_SPA);
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195
196 return check_hdac_link_power_active(link, true);
197}
198EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_up);
199
200/**
201 * snd_hdac_ext_bus_link_power_down -power down hda link
202 * @link: HD-audio extended link
203 */
204int snd_hdac_ext_bus_link_power_down(struct hdac_ext_link *link)
205{
a7e3dd85 206 snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL, AZX_MLCTL_SPA, 0);
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207
208 return check_hdac_link_power_active(link, false);
209}
210EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_down);
c5b0c09b 211
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212/**
213 * snd_hdac_ext_bus_link_power_up_all -power up all hda link
214 * @ebus: HD-audio extended bus
215 */
76f56fae 216int snd_hdac_ext_bus_link_power_up_all(struct hdac_bus *bus)
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217{
218 struct hdac_ext_link *hlink = NULL;
219 int ret;
220
76f56fae 221 list_for_each_entry(hlink, &bus->hlink_list, list) {
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222 snd_hdac_updatel(hlink->ml_addr, AZX_REG_ML_LCTL,
223 AZX_MLCTL_SPA, AZX_MLCTL_SPA);
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224 ret = check_hdac_link_power_active(hlink, true);
225 if (ret < 0)
226 return ret;
227 }
228
229 return 0;
230}
231EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_up_all);
232
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233/**
234 * snd_hdac_ext_bus_link_power_down_all -power down all hda link
235 * @ebus: HD-audio extended bus
236 */
76f56fae 237int snd_hdac_ext_bus_link_power_down_all(struct hdac_bus *bus)
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238{
239 struct hdac_ext_link *hlink = NULL;
240 int ret;
241
76f56fae 242 list_for_each_entry(hlink, &bus->hlink_list, list) {
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243 snd_hdac_updatel(hlink->ml_addr, AZX_REG_ML_LCTL,
244 AZX_MLCTL_SPA, 0);
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245 ret = check_hdac_link_power_active(hlink, false);
246 if (ret < 0)
247 return ret;
248 }
249
250 return 0;
251}
252EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_down_all);
4446085d 253
76f56fae 254int snd_hdac_ext_bus_link_get(struct hdac_bus *bus,
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255 struct hdac_ext_link *link)
256{
257 int ret = 0;
258
76f56fae 259 mutex_lock(&bus->lock);
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260
261 /*
262 * if we move from 0 to 1, count will be 1 so power up this link
263 * as well, also check the dma status and trigger that
264 */
265 if (++link->ref_count == 1) {
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266 if (!bus->cmd_dma_state) {
267 snd_hdac_bus_init_cmd_io(bus);
268 bus->cmd_dma_state = true;
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269 }
270
271 ret = snd_hdac_ext_bus_link_power_up(link);
f8a7fe1a 272
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273 /*
274 * clear the register to invalidate all the output streams
275 */
276 snd_hdac_updatew(link->ml_addr, AZX_REG_ML_LOSIDV,
277 ML_LOSIDV_STREAM_MASK, 0);
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278 /*
279 * wait for 521usec for codec to report status
280 * HDA spec section 4.3 - Codec Discovery
281 */
282 udelay(521);
283 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
284 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
285 snd_hdac_chip_writew(bus, STATESTS, bus->codec_mask);
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286 }
287
76f56fae 288 mutex_unlock(&bus->lock);
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289 return ret;
290}
291EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_get);
292
76f56fae 293int snd_hdac_ext_bus_link_put(struct hdac_bus *bus,
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294 struct hdac_ext_link *link)
295{
296 int ret = 0;
297 struct hdac_ext_link *hlink;
298 bool link_up = false;
299
76f56fae 300 mutex_lock(&bus->lock);
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301
302 /*
303 * if we move from 1 to 0, count will be 0
304 * so power down this link as well
305 */
306 if (--link->ref_count == 0) {
307 ret = snd_hdac_ext_bus_link_power_down(link);
308
309 /*
310 * now check if all links are off, if so turn off
311 * cmd dma as well
312 */
76f56fae 313 list_for_each_entry(hlink, &bus->hlink_list, list) {
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314 if (hlink->ref_count) {
315 link_up = true;
316 break;
317 }
318 }
319
320 if (!link_up) {
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321 snd_hdac_bus_stop_cmd_io(bus);
322 bus->cmd_dma_state = false;
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323 }
324 }
325
76f56fae 326 mutex_unlock(&bus->lock);
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327 return ret;
328}
329EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_put);