[linux-2.6-block.git] / sound / firewire / digi00x / digi00x.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * digi00x.h - a part of driver for Digidesign Digi 002/003 family
 *
 * Copyright (c) 2014-2015 Takashi Sakamoto
 */

#ifndef SOUND_DIGI00X_H_INCLUDED
#define SOUND_DIGI00X_H_INCLUDED

#include <linux/compat.h>
#include <linux/device.h>
#include <linux/firewire.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/sched/signal.h>

#include <sound/core.h>
#include <sound/initval.h>
#include <sound/info.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/firewire.h>
#include <sound/hwdep.h>
#include <sound/rawmidi.h>

#include "../lib.h"
#include "../iso-resources.h"
#include "../amdtp-stream.h"

struct snd_dg00x {
	struct snd_card *card;
	struct fw_unit *unit;

	struct mutex mutex;
	spinlock_t lock;

	bool registered;
	struct delayed_work dwork;

	struct amdtp_stream tx_stream;
	struct fw_iso_resources tx_resources;

	struct amdtp_stream rx_stream;
	struct fw_iso_resources rx_resources;

	unsigned int substreams_counter;

	/* for uapi */
	int dev_lock_count;
	bool dev_lock_changed;
	wait_queue_head_t hwdep_wait;

	/* For asynchronous messages. */
	struct fw_address_handler async_handler;
	u32 msg;

	/* Console models have additional MIDI ports for control surface. */
	bool is_console;

	struct amdtp_domain domain;
};

#define DG00X_ADDR_BASE		0xffffe0000000ull

#define DG00X_OFFSET_STREAMING_STATE	0x0000
#define DG00X_OFFSET_STREAMING_SET	0x0004
/* unknown but address in host space	0x0008 */
/* For LSB of the address		0x000c */
/* unknown				0x0010 */
#define DG00X_OFFSET_MESSAGE_ADDR	0x0014
/* For LSB of the address		0x0018 */
/* unknown				0x001c */
/* unknown				0x0020 */
/* not used			0x0024--0x00ff */
#define DG00X_OFFSET_ISOC_CHANNELS	0x0100
/* unknown				0x0104 */
/* unknown				0x0108 */
/* unknown				0x010c */
#define DG00X_OFFSET_LOCAL_RATE		0x0110
#define DG00X_OFFSET_EXTERNAL_RATE	0x0114
#define DG00X_OFFSET_CLOCK_SOURCE	0x0118
#define DG00X_OFFSET_OPT_IFACE_MODE	0x011c
/* unknown				0x0120 */
/* Mixer control on/off			0x0124 */
/* unknown				0x0128 */
#define DG00X_OFFSET_DETECT_EXTERNAL	0x012c
/* unknown				0x0138 */
#define DG00X_OFFSET_MMC		0x0400

enum snd_dg00x_rate {
	SND_DG00X_RATE_44100 = 0,
	SND_DG00X_RATE_48000,
	SND_DG00X_RATE_88200,
	SND_DG00X_RATE_96000,
	SND_DG00X_RATE_COUNT,
};

enum snd_dg00x_clock {
	SND_DG00X_CLOCK_INTERNAL = 0,
	SND_DG00X_CLOCK_SPDIF,
	SND_DG00X_CLOCK_ADAT,
	SND_DG00X_CLOCK_WORD,
	SND_DG00X_CLOCK_COUNT,
};

enum snd_dg00x_optical_mode {
	SND_DG00X_OPT_IFACE_MODE_ADAT = 0,
	SND_DG00X_OPT_IFACE_MODE_SPDIF,
	SND_DG00X_OPT_IFACE_MODE_COUNT,
};

#define DOT_MIDI_IN_PORTS	1
#define DOT_MIDI_OUT_PORTS	2

int amdtp_dot_init(struct amdtp_stream *s, struct fw_unit *unit,
		   enum amdtp_stream_direction dir);
int amdtp_dot_set_parameters(struct amdtp_stream *s, unsigned int rate,
			     unsigned int pcm_channels);
void amdtp_dot_reset(struct amdtp_stream *s);
int amdtp_dot_add_pcm_hw_constraints(struct amdtp_stream *s,
				     struct snd_pcm_runtime *runtime);
void amdtp_dot_midi_trigger(struct amdtp_stream *s, unsigned int port,
			  struct snd_rawmidi_substream *midi);

int snd_dg00x_transaction_register(struct snd_dg00x *dg00x);
int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x);
void snd_dg00x_transaction_unregister(struct snd_dg00x *dg00x);

extern const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT];
extern const unsigned int snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT];
int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x,
				       unsigned int *rate);
int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x,
				    unsigned int *rate);
int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate);
int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x,
			       enum snd_dg00x_clock *clock);
int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x,
					  bool *detect);
int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x);
int snd_dg00x_stream_reserve_duplex(struct snd_dg00x *dg00x, unsigned int rate,
				    unsigned int frames_per_period,
				    unsigned int frames_per_buffer);
int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x);
void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x);
void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x);
void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x);

void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x);
int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x);
void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x);

void snd_dg00x_proc_init(struct snd_dg00x *dg00x);

int snd_dg00x_create_pcm_devices(struct snd_dg00x *dg00x);

int snd_dg00x_create_midi_devices(struct snd_dg00x *dg00x);

int snd_dg00x_create_hwdep_device(struct snd_dg00x *dg00x);
#endif
Commit	Line	Data
da607e19	1	/* SPDX-License-Identifier: GPL-2.0-only */
9edf723f TS	2	/*
	3	* digi00x.h - a part of driver for Digidesign Digi 002/003 family
	4	*
	5	* Copyright (c) 2014-2015 Takashi Sakamoto
9edf723f TS	6	*/
	7
	8	#ifndef SOUND_DIGI00X_H_INCLUDED
	9	#define SOUND_DIGI00X_H_INCLUDED
	10
	11	#include <linux/compat.h>
	12	#include <linux/device.h>
	13	#include <linux/firewire.h>
	14	#include <linux/module.h>
	15	#include <linux/mod_devicetable.h>
	16	#include <linux/delay.h>
	17	#include <linux/slab.h>
174cd4b1	18	#include <linux/sched/signal.h>
9edf723f TS	19
	20	#include <sound/core.h>
	21	#include <sound/initval.h>
927f17dc	22	#include <sound/info.h>
163ae6f3 TS	23	#include <sound/pcm.h>
163ae6f3 TS	24	#include <sound/pcm_params.h>
660dd3d5 TS	25	#include <sound/firewire.h>
660dd3d5 TS	26	#include <sound/hwdep.h>
9dc5d31c	27	#include <sound/rawmidi.h>
9edf723f TS	28
9edf723f TS	29	#include "../lib.h"
163ae6f3 TS	30	#include "../iso-resources.h"
163ae6f3 TS	31	#include "../amdtp-stream.h"
9edf723f TS	32
	33	struct snd_dg00x {
	34	struct snd_card *card;
	35	struct fw_unit *unit;
	36
	37	struct mutex mutex;
660dd3d5	38	spinlock_t lock;
3a2a1797	39
86c8dd7f TS	40	bool registered;
	41	struct delayed_work dwork;
	42
3a2a1797 TS	43	struct amdtp_stream tx_stream;
	44	struct fw_iso_resources tx_resources;
	45
	46	struct amdtp_stream rx_stream;
	47	struct fw_iso_resources rx_resources;
	48
	49	unsigned int substreams_counter;
660dd3d5 TS	50
	51	/* for uapi */
	52	int dev_lock_count;
	53	bool dev_lock_changed;
	54	wait_queue_head_t hwdep_wait;
	55
44b73088 TS	56	/* For asynchronous messages. */
	57	struct fw_address_handler async_handler;
	58	u32 msg;
3646a54a	59
fdb2b2ee	60	/* Console models have additional MIDI ports for control surface. */
13e005f9	61	bool is_console;
9a08067e TS	62
9a08067e TS	63	struct amdtp_domain domain;
3a2a1797 TS	64	};
	65
	66	#define DG00X_ADDR_BASE 0xffffe0000000ull
	67
	68	#define DG00X_OFFSET_STREAMING_STATE 0x0000
	69	#define DG00X_OFFSET_STREAMING_SET 0x0004
fdb2b2ee	70	/* unknown but address in host space 0x0008 */
3a2a1797 TS	71	/* For LSB of the address 0x000c */
	72	/* unknown 0x0010 */
	73	#define DG00X_OFFSET_MESSAGE_ADDR 0x0014
	74	/* For LSB of the address 0x0018 */
	75	/* unknown 0x001c */
	76	/* unknown 0x0020 */
	77	/* not used 0x0024--0x00ff */
	78	#define DG00X_OFFSET_ISOC_CHANNELS 0x0100
	79	/* unknown 0x0104 */
	80	/* unknown 0x0108 */
	81	/* unknown 0x010c */
	82	#define DG00X_OFFSET_LOCAL_RATE 0x0110
	83	#define DG00X_OFFSET_EXTERNAL_RATE 0x0114
	84	#define DG00X_OFFSET_CLOCK_SOURCE 0x0118
	85	#define DG00X_OFFSET_OPT_IFACE_MODE 0x011c
	86	/* unknown 0x0120 */
	87	/* Mixer control on/off 0x0124 */
	88	/* unknown 0x0128 */
	89	#define DG00X_OFFSET_DETECT_EXTERNAL 0x012c
	90	/* unknown 0x0138 */
	91	#define DG00X_OFFSET_MMC 0x0400
	92
	93	enum snd_dg00x_rate {
	94	SND_DG00X_RATE_44100 = 0,
	95	SND_DG00X_RATE_48000,
	96	SND_DG00X_RATE_88200,
	97	SND_DG00X_RATE_96000,
	98	SND_DG00X_RATE_COUNT,
	99	};
	100
	101	enum snd_dg00x_clock {
	102	SND_DG00X_CLOCK_INTERNAL = 0,
	103	SND_DG00X_CLOCK_SPDIF,
	104	SND_DG00X_CLOCK_ADAT,
	105	SND_DG00X_CLOCK_WORD,
	106	SND_DG00X_CLOCK_COUNT,
9edf723f TS	107	};
9edf723f TS	108
927f17dc TS	109	enum snd_dg00x_optical_mode {
	110	SND_DG00X_OPT_IFACE_MODE_ADAT = 0,
	111	SND_DG00X_OPT_IFACE_MODE_SPDIF,
	112	SND_DG00X_OPT_IFACE_MODE_COUNT,
	113	};
	114
9dc5d31c TS	115	#define DOT_MIDI_IN_PORTS 1
	116	#define DOT_MIDI_OUT_PORTS 2
	117
163ae6f3 TS	118	int amdtp_dot_init(struct amdtp_stream s, struct fw_unit unit,
	119	enum amdtp_stream_direction dir);
	120	int amdtp_dot_set_parameters(struct amdtp_stream *s, unsigned int rate,
9dc5d31c	121	unsigned int pcm_channels);
163ae6f3 TS	122	void amdtp_dot_reset(struct amdtp_stream *s);
	123	int amdtp_dot_add_pcm_hw_constraints(struct amdtp_stream *s,
	124	struct snd_pcm_runtime *runtime);
9dc5d31c TS	125	void amdtp_dot_midi_trigger(struct amdtp_stream *s, unsigned int port,
9dc5d31c TS	126	struct snd_rawmidi_substream *midi);
163ae6f3	127
44b73088 TS	128	int snd_dg00x_transaction_register(struct snd_dg00x *dg00x);
	129	int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x);
	130	void snd_dg00x_transaction_unregister(struct snd_dg00x *dg00x);
	131
3a2a1797 TS	132	extern const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT];
	133	extern const unsigned int snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT];
	134	int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x,
	135	unsigned int *rate);
	136	int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x,
	137	unsigned int *rate);
	138	int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate);
	139	int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x,
	140	enum snd_dg00x_clock *clock);
	141	int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x,
	142	bool *detect);
	143	int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x);
18b7f18f	144	int snd_dg00x_stream_reserve_duplex(struct snd_dg00x *dg00x, unsigned int rate,
76c4ecbe TS	145	unsigned int frames_per_period,
76c4ecbe TS	146	unsigned int frames_per_buffer);
ae8ffbb2	147	int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x);
3a2a1797 TS	148	void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x);
	149	void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x);
	150	void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x);
	151
660dd3d5 TS	152	void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x);
	153	int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x);
	154	void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x);
	155
927f17dc	156	void snd_dg00x_proc_init(struct snd_dg00x *dg00x);
0120d0f1 TS	157
	158	int snd_dg00x_create_pcm_devices(struct snd_dg00x *dg00x);
	159
9fbfd38b TS	160	int snd_dg00x_create_midi_devices(struct snd_dg00x *dg00x);
9fbfd38b TS	161
660dd3d5	162	int snd_dg00x_create_hwdep_device(struct snd_dg00x *dg00x);
9edf723f	163	#endif