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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
54e72f0b CL |
2 | #ifndef SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED |
3 | #define SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED | |
4 | ||
5 | /* | |
6 | * DICE device interface definitions | |
7 | */ | |
8 | ||
9 | /* | |
10 | * Generally, all registers can be read like memory, i.e., with quadlet read or | |
61b8cf02 CL |
11 | * block read transactions with at least quadlet-aligned offset and length. |
12 | * Writes are not allowed except where noted; quadlet-sized registers must be | |
13 | * written with a quadlet write transaction. | |
54e72f0b CL |
14 | * |
15 | * All values are in big endian. The DICE firmware runs on a little-endian CPU | |
16 | * and just byte-swaps _all_ quadlets on the bus, so values without endianness | |
17 | * (e.g. strings) get scrambled and must be byte-swapped again by the driver. | |
18 | */ | |
19 | ||
20 | /* | |
21 | * Streaming is handled by the "DICE driver" interface. Its registers are | |
22 | * located in this private address space. | |
23 | */ | |
24 | #define DICE_PRIVATE_SPACE 0xffffe0000000uLL | |
25 | ||
26 | /* | |
27 | * The registers are organized in several sections, which are organized | |
28 | * separately to allow them to be extended individually. Whether a register is | |
29 | * supported can be detected by checking its offset against its section's size. | |
30 | * | |
31 | * The section offset values are relative to DICE_PRIVATE_SPACE; the offset/ | |
32 | * size values are measured in quadlets. Read-only. | |
33 | */ | |
34 | #define DICE_GLOBAL_OFFSET 0x00 | |
35 | #define DICE_GLOBAL_SIZE 0x04 | |
36 | #define DICE_TX_OFFSET 0x08 | |
37 | #define DICE_TX_SIZE 0x0c | |
38 | #define DICE_RX_OFFSET 0x10 | |
39 | #define DICE_RX_SIZE 0x14 | |
40 | #define DICE_EXT_SYNC_OFFSET 0x18 | |
41 | #define DICE_EXT_SYNC_SIZE 0x1c | |
42 | #define DICE_UNUSED2_OFFSET 0x20 | |
43 | #define DICE_UNUSED2_SIZE 0x24 | |
44 | ||
45 | /* | |
46 | * Global settings. | |
47 | */ | |
48 | ||
49 | /* | |
50 | * Stores the full 64-bit address (node ID and offset in the node's address | |
51 | * space) where the device will send notifications. Must be changed with | |
52 | * a compare/swap transaction by the owner. This register is automatically | |
53 | * cleared on a bus reset. | |
54 | */ | |
55 | #define GLOBAL_OWNER 0x000 | |
56 | #define OWNER_NO_OWNER 0xffff000000000000uLL | |
57 | #define OWNER_NODE_SHIFT 48 | |
58 | ||
59 | /* | |
60 | * A bitmask with asynchronous events; read-only. When any event(s) happen, | |
61 | * the bits of previous events are cleared, and the value of this register is | |
62 | * also written to the address stored in the owner register. | |
63 | */ | |
64 | #define GLOBAL_NOTIFICATION 0x008 | |
65 | /* Some registers in the Rx/Tx sections may have changed. */ | |
66 | #define NOTIFY_RX_CFG_CHG 0x00000001 | |
67 | #define NOTIFY_TX_CFG_CHG 0x00000002 | |
68 | /* Lock status of the current clock source may have changed. */ | |
69 | #define NOTIFY_LOCK_CHG 0x00000010 | |
70 | /* Write to the clock select register has been finished. */ | |
71 | #define NOTIFY_CLOCK_ACCEPTED 0x00000020 | |
72 | /* Lock status of some clock source has changed. */ | |
73 | #define NOTIFY_EXT_STATUS 0x00000040 | |
74 | /* Other bits may be used for device-specific events. */ | |
75 | ||
76 | /* | |
77 | * A name that can be customized for each device; read/write. Padded with zero | |
78 | * bytes. Quadlets are byte-swapped. The encoding is whatever the host driver | |
79 | * happens to be using. | |
80 | */ | |
81 | #define GLOBAL_NICK_NAME 0x00c | |
82 | #define NICK_NAME_SIZE 64 | |
83 | ||
84 | /* | |
85 | * The current sample rate and clock source; read/write. Whether a clock | |
86 | * source or sample rate is supported is device-specific; the internal clock | |
87 | * source is always available. Low/mid/high = up to 48/96/192 kHz. This | |
88 | * register can be changed even while streams are running. | |
89 | */ | |
90 | #define GLOBAL_CLOCK_SELECT 0x04c | |
91 | #define CLOCK_SOURCE_MASK 0x000000ff | |
92 | #define CLOCK_SOURCE_AES1 0x00000000 | |
93 | #define CLOCK_SOURCE_AES2 0x00000001 | |
94 | #define CLOCK_SOURCE_AES3 0x00000002 | |
95 | #define CLOCK_SOURCE_AES4 0x00000003 | |
96 | #define CLOCK_SOURCE_AES_ANY 0x00000004 | |
97 | #define CLOCK_SOURCE_ADAT 0x00000005 | |
98 | #define CLOCK_SOURCE_TDIF 0x00000006 | |
99 | #define CLOCK_SOURCE_WC 0x00000007 | |
100 | #define CLOCK_SOURCE_ARX1 0x00000008 | |
101 | #define CLOCK_SOURCE_ARX2 0x00000009 | |
102 | #define CLOCK_SOURCE_ARX3 0x0000000a | |
103 | #define CLOCK_SOURCE_ARX4 0x0000000b | |
104 | #define CLOCK_SOURCE_INTERNAL 0x0000000c | |
105 | #define CLOCK_RATE_MASK 0x0000ff00 | |
106 | #define CLOCK_RATE_32000 0x00000000 | |
107 | #define CLOCK_RATE_44100 0x00000100 | |
108 | #define CLOCK_RATE_48000 0x00000200 | |
109 | #define CLOCK_RATE_88200 0x00000300 | |
110 | #define CLOCK_RATE_96000 0x00000400 | |
111 | #define CLOCK_RATE_176400 0x00000500 | |
112 | #define CLOCK_RATE_192000 0x00000600 | |
113 | #define CLOCK_RATE_ANY_LOW 0x00000700 | |
114 | #define CLOCK_RATE_ANY_MID 0x00000800 | |
115 | #define CLOCK_RATE_ANY_HIGH 0x00000900 | |
116 | #define CLOCK_RATE_NONE 0x00000a00 | |
117 | #define CLOCK_RATE_SHIFT 8 | |
118 | ||
119 | /* | |
120 | * Enable streaming; read/write. Writing a non-zero value (re)starts all | |
121 | * streams that have a valid iso channel set; zero stops all streams. The | |
122 | * streams' parameters must be configured before starting. This register is | |
123 | * automatically cleared on a bus reset. | |
124 | */ | |
125 | #define GLOBAL_ENABLE 0x050 | |
126 | ||
127 | /* | |
128 | * Status of the sample clock; read-only. | |
129 | */ | |
130 | #define GLOBAL_STATUS 0x054 | |
131 | /* The current clock source is locked. */ | |
132 | #define STATUS_SOURCE_LOCKED 0x00000001 | |
133 | /* The actual sample rate; CLOCK_RATE_32000-_192000 or _NONE. */ | |
134 | #define STATUS_NOMINAL_RATE_MASK 0x0000ff00 | |
135 | ||
136 | /* | |
137 | * Status of all clock sources; read-only. | |
138 | */ | |
139 | #define GLOBAL_EXTENDED_STATUS 0x058 | |
140 | /* | |
141 | * The _LOCKED bits always show the current status; any change generates | |
142 | * a notification. | |
143 | */ | |
144 | #define EXT_STATUS_AES1_LOCKED 0x00000001 | |
145 | #define EXT_STATUS_AES2_LOCKED 0x00000002 | |
146 | #define EXT_STATUS_AES3_LOCKED 0x00000004 | |
147 | #define EXT_STATUS_AES4_LOCKED 0x00000008 | |
148 | #define EXT_STATUS_ADAT_LOCKED 0x00000010 | |
149 | #define EXT_STATUS_TDIF_LOCKED 0x00000020 | |
150 | #define EXT_STATUS_ARX1_LOCKED 0x00000040 | |
151 | #define EXT_STATUS_ARX2_LOCKED 0x00000080 | |
152 | #define EXT_STATUS_ARX3_LOCKED 0x00000100 | |
153 | #define EXT_STATUS_ARX4_LOCKED 0x00000200 | |
154 | #define EXT_STATUS_WC_LOCKED 0x00000400 | |
155 | /* | |
156 | * The _SLIP bits do not generate notifications; a set bit indicates that an | |
157 | * error occurred since the last time when this register was read with | |
158 | * a quadlet read transaction. | |
159 | */ | |
160 | #define EXT_STATUS_AES1_SLIP 0x00010000 | |
161 | #define EXT_STATUS_AES2_SLIP 0x00020000 | |
162 | #define EXT_STATUS_AES3_SLIP 0x00040000 | |
163 | #define EXT_STATUS_AES4_SLIP 0x00080000 | |
164 | #define EXT_STATUS_ADAT_SLIP 0x00100000 | |
165 | #define EXT_STATUS_TDIF_SLIP 0x00200000 | |
166 | #define EXT_STATUS_ARX1_SLIP 0x00400000 | |
167 | #define EXT_STATUS_ARX2_SLIP 0x00800000 | |
168 | #define EXT_STATUS_ARX3_SLIP 0x01000000 | |
169 | #define EXT_STATUS_ARX4_SLIP 0x02000000 | |
170 | #define EXT_STATUS_WC_SLIP 0x04000000 | |
171 | ||
172 | /* | |
173 | * The measured rate of the current clock source, in Hz; read-only. | |
174 | */ | |
175 | #define GLOBAL_SAMPLE_RATE 0x05c | |
176 | ||
c1a36101 TS |
177 | /* |
178 | * Some old firmware versions do not have the following global registers. | |
179 | * Windows drivers produced by TCAT lost backward compatibility in its | |
180 | * early release because they can handle firmware only which supports the | |
181 | * following registers. | |
182 | */ | |
183 | ||
54e72f0b CL |
184 | /* |
185 | * The version of the DICE driver specification that this device conforms to; | |
186 | * read-only. | |
187 | */ | |
188 | #define GLOBAL_VERSION 0x060 | |
189 | ||
54e72f0b CL |
190 | /* |
191 | * Supported sample rates and clock sources; read-only. | |
192 | */ | |
193 | #define GLOBAL_CLOCK_CAPABILITIES 0x064 | |
194 | #define CLOCK_CAP_RATE_32000 0x00000001 | |
195 | #define CLOCK_CAP_RATE_44100 0x00000002 | |
196 | #define CLOCK_CAP_RATE_48000 0x00000004 | |
197 | #define CLOCK_CAP_RATE_88200 0x00000008 | |
198 | #define CLOCK_CAP_RATE_96000 0x00000010 | |
199 | #define CLOCK_CAP_RATE_176400 0x00000020 | |
200 | #define CLOCK_CAP_RATE_192000 0x00000040 | |
201 | #define CLOCK_CAP_SOURCE_AES1 0x00010000 | |
202 | #define CLOCK_CAP_SOURCE_AES2 0x00020000 | |
203 | #define CLOCK_CAP_SOURCE_AES3 0x00040000 | |
204 | #define CLOCK_CAP_SOURCE_AES4 0x00080000 | |
205 | #define CLOCK_CAP_SOURCE_AES_ANY 0x00100000 | |
206 | #define CLOCK_CAP_SOURCE_ADAT 0x00200000 | |
207 | #define CLOCK_CAP_SOURCE_TDIF 0x00400000 | |
208 | #define CLOCK_CAP_SOURCE_WC 0x00800000 | |
209 | #define CLOCK_CAP_SOURCE_ARX1 0x01000000 | |
210 | #define CLOCK_CAP_SOURCE_ARX2 0x02000000 | |
211 | #define CLOCK_CAP_SOURCE_ARX3 0x04000000 | |
212 | #define CLOCK_CAP_SOURCE_ARX4 0x08000000 | |
213 | #define CLOCK_CAP_SOURCE_INTERNAL 0x10000000 | |
214 | ||
215 | /* | |
216 | * Names of all clock sources; read-only. Quadlets are byte-swapped. Names | |
217 | * are separated with one backslash, the list is terminated with two | |
218 | * backslashes. Unused clock sources are included. | |
219 | */ | |
220 | #define GLOBAL_CLOCK_SOURCE_NAMES 0x068 | |
221 | #define CLOCK_SOURCE_NAMES_SIZE 256 | |
222 | ||
223 | /* | |
224 | * Capture stream settings. This section includes the number/size registers | |
225 | * and the registers of all streams. | |
226 | */ | |
227 | ||
228 | /* | |
229 | * The number of supported capture streams; read-only. | |
230 | */ | |
231 | #define TX_NUMBER 0x000 | |
232 | ||
233 | /* | |
234 | * The size of one stream's register block, in quadlets; read-only. The | |
235 | * registers of the first stream follow immediately afterwards; the registers | |
236 | * of the following streams are offset by this register's value. | |
237 | */ | |
238 | #define TX_SIZE 0x004 | |
239 | ||
240 | /* | |
241 | * The isochronous channel number on which packets are sent, or -1 if the | |
242 | * stream is not to be used; read/write. | |
243 | */ | |
244 | #define TX_ISOCHRONOUS 0x008 | |
245 | ||
246 | /* | |
247 | * The number of audio channels; read-only. There will be one quadlet per | |
248 | * channel; the first channel is the first quadlet in a data block. | |
249 | */ | |
250 | #define TX_NUMBER_AUDIO 0x00c | |
251 | ||
252 | /* | |
253 | * The number of MIDI ports, 0-8; read-only. If > 0, there will be one | |
254 | * additional quadlet in each data block, following the audio quadlets. | |
255 | */ | |
256 | #define TX_NUMBER_MIDI 0x010 | |
257 | ||
258 | /* | |
259 | * The speed at which the packets are sent, SCODE_100-_400; read/write. | |
b0e159fe | 260 | * SCODE_800 is only available in Dice III. |
54e72f0b CL |
261 | */ |
262 | #define TX_SPEED 0x014 | |
263 | ||
264 | /* | |
265 | * Names of all audio channels; read-only. Quadlets are byte-swapped. Names | |
266 | * are separated with one backslash, the list is terminated with two | |
267 | * backslashes. | |
268 | */ | |
269 | #define TX_NAMES 0x018 | |
270 | #define TX_NAMES_SIZE 256 | |
271 | ||
272 | /* | |
273 | * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio | |
274 | * channel. | |
275 | */ | |
276 | #define TX_AC3_CAPABILITIES 0x118 | |
277 | ||
278 | /* | |
279 | * Send audio data with IEC60958 label; read/write. Bitmask with one bit per | |
280 | * audio channel. This register can be changed even while the stream is | |
281 | * running. | |
282 | */ | |
283 | #define TX_AC3_ENABLE 0x11c | |
284 | ||
285 | /* | |
286 | * Playback stream settings. This section includes the number/size registers | |
287 | * and the registers of all streams. | |
288 | */ | |
289 | ||
290 | /* | |
291 | * The number of supported playback streams; read-only. | |
292 | */ | |
293 | #define RX_NUMBER 0x000 | |
294 | ||
295 | /* | |
296 | * The size of one stream's register block, in quadlets; read-only. The | |
297 | * registers of the first stream follow immediately afterwards; the registers | |
298 | * of the following streams are offset by this register's value. | |
299 | */ | |
300 | #define RX_SIZE 0x004 | |
301 | ||
302 | /* | |
303 | * The isochronous channel number on which packets are received, or -1 if the | |
304 | * stream is not to be used; read/write. | |
305 | */ | |
306 | #define RX_ISOCHRONOUS 0x008 | |
307 | ||
5b1274ef TS |
308 | /* |
309 | * Index of first quadlet to be interpreted; read/write. If > 0, that many | |
310 | * quadlets at the beginning of each data block will be ignored, and all the | |
311 | * audio and MIDI quadlets will follow. | |
312 | */ | |
313 | #define RX_SEQ_START 0x00c | |
314 | ||
54e72f0b CL |
315 | /* |
316 | * The number of audio channels; read-only. There will be one quadlet per | |
317 | * channel. | |
318 | */ | |
5b1274ef | 319 | #define RX_NUMBER_AUDIO 0x010 |
54e72f0b CL |
320 | |
321 | /* | |
322 | * The number of MIDI ports, 0-8; read-only. If > 0, there will be one | |
323 | * additional quadlet in each data block, following the audio quadlets. | |
324 | */ | |
5b1274ef | 325 | #define RX_NUMBER_MIDI 0x014 |
54e72f0b CL |
326 | |
327 | /* | |
328 | * Names of all audio channels; read-only. Quadlets are byte-swapped. Names | |
329 | * are separated with one backslash, the list is terminated with two | |
330 | * backslashes. | |
331 | */ | |
332 | #define RX_NAMES 0x018 | |
333 | #define RX_NAMES_SIZE 256 | |
334 | ||
335 | /* | |
336 | * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio | |
337 | * channel. | |
338 | */ | |
339 | #define RX_AC3_CAPABILITIES 0x118 | |
340 | ||
341 | /* | |
342 | * Receive audio data with IEC60958 label; read/write. Bitmask with one bit | |
343 | * per audio channel. This register can be changed even while the stream is | |
344 | * running. | |
345 | */ | |
346 | #define RX_AC3_ENABLE 0x11c | |
347 | ||
348 | /* | |
349 | * Extended synchronization information. | |
350 | * This section can be read completely with a block read request. | |
351 | */ | |
352 | ||
353 | /* | |
354 | * Current clock source; read-only. | |
355 | */ | |
356 | #define EXT_SYNC_CLOCK_SOURCE 0x000 | |
357 | ||
358 | /* | |
359 | * Clock source is locked (boolean); read-only. | |
360 | */ | |
361 | #define EXT_SYNC_LOCKED 0x004 | |
362 | ||
363 | /* | |
364 | * Current sample rate (CLOCK_RATE_* >> CLOCK_RATE_SHIFT), _32000-_192000 or | |
365 | * _NONE; read-only. | |
366 | */ | |
367 | #define EXT_SYNC_RATE 0x008 | |
368 | ||
369 | /* | |
370 | * ADAT user data bits; read-only. | |
371 | */ | |
372 | #define EXT_SYNC_ADAT_USER_DATA 0x00c | |
373 | /* The data bits, if available. */ | |
374 | #define ADAT_USER_DATA_MASK 0x0f | |
375 | /* The data bits are not available. */ | |
376 | #define ADAT_USER_DATA_NO_DATA 0x10 | |
377 | ||
378 | #endif |