ALSA: firewire-lib: fix inverted node IDs for amdtp_packet events
[linux-block.git] / sound / firewire / amdtp-stream.c
CommitLineData
31ef9134
CL
1/*
2 * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
3 * with Common Isochronous Packet (IEC 61883-1) headers
4 *
5 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
6 * Licensed under the terms of the GNU General Public License, version 2.
7 */
8
9#include <linux/device.h>
10#include <linux/err.h>
11#include <linux/firewire.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <sound/pcm.h>
7b2d99fa 15#include <sound/pcm_params.h>
d67c46b9 16#include "amdtp-stream.h"
31ef9134
CL
17
18#define TICKS_PER_CYCLE 3072
19#define CYCLES_PER_SECOND 8000
20#define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND)
21
0c95c1d6
TS
22/* Always support Linux tracing subsystem. */
23#define CREATE_TRACE_POINTS
24#include "amdtp-stream-trace.h"
25
ca5b5050 26#define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */
31ef9134 27
b445db44
TS
28/* isochronous header parameters */
29#define ISO_DATA_LENGTH_SHIFT 16
3b196c39 30#define TAG_NO_CIP_HEADER 0
31ef9134
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31#define TAG_CIP 1
32
b445db44 33/* common isochronous packet header parameters */
9a2820c1
TS
34#define CIP_EOH_SHIFT 31
35#define CIP_EOH (1u << CIP_EOH_SHIFT)
b445db44 36#define CIP_EOH_MASK 0x80000000
9a2820c1
TS
37#define CIP_SID_SHIFT 24
38#define CIP_SID_MASK 0x3f000000
39#define CIP_DBS_MASK 0x00ff0000
40#define CIP_DBS_SHIFT 16
9863874f
TS
41#define CIP_SPH_MASK 0x00000400
42#define CIP_SPH_SHIFT 10
9a2820c1
TS
43#define CIP_DBC_MASK 0x000000ff
44#define CIP_FMT_SHIFT 24
b445db44 45#define CIP_FMT_MASK 0x3f000000
9a2820c1
TS
46#define CIP_FDF_MASK 0x00ff0000
47#define CIP_FDF_SHIFT 16
b445db44
TS
48#define CIP_SYT_MASK 0x0000ffff
49#define CIP_SYT_NO_INFO 0xffff
b445db44 50
51c29fd2 51/* Audio and Music transfer protocol specific parameters */
414ba022 52#define CIP_FMT_AM 0x10
2b3fc456 53#define AMDTP_FDF_NO_DATA 0xff
31ef9134
CL
54
55/* TODO: make these configurable */
56#define INTERRUPT_INTERVAL 16
57#define QUEUE_LENGTH 48
58
f11453c7
TS
59// For iso header, tstamp and 2 CIP header.
60#define IR_CTX_HEADER_SIZE_CIP 16
61// For iso header and tstamp.
62#define IR_CTX_HEADER_SIZE_NO_CIP 8
cc4f8e91 63#define HEADER_TSTAMP_MASK 0x0000ffff
4b7da117 64
b18f0cfa
TS
65#define IT_PKT_HEADER_SIZE_CIP 8 // For 2 CIP header.
66#define IT_PKT_HEADER_SIZE_NO_CIP 0 // Nothing.
67
76fb8789
CL
68static void pcm_period_tasklet(unsigned long data);
69
31ef9134 70/**
be4a2894
TS
71 * amdtp_stream_init - initialize an AMDTP stream structure
72 * @s: the AMDTP stream to initialize
31ef9134 73 * @unit: the target of the stream
3ff7e8f0 74 * @dir: the direction of stream
31ef9134 75 * @flags: the packet transmission method to use
5955815e 76 * @fmt: the value of fmt field in CIP header
df075fee
TS
77 * @process_data_blocks: callback handler to process data blocks
78 * @protocol_size: the size to allocate newly for protocol
31ef9134 79 */
be4a2894 80int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit,
5955815e 81 enum amdtp_stream_direction dir, enum cip_flags flags,
df075fee
TS
82 unsigned int fmt,
83 amdtp_stream_process_data_blocks_t process_data_blocks,
84 unsigned int protocol_size)
31ef9134 85{
df075fee
TS
86 if (process_data_blocks == NULL)
87 return -EINVAL;
88
89 s->protocol = kzalloc(protocol_size, GFP_KERNEL);
90 if (!s->protocol)
91 return -ENOMEM;
92
c6f224dc 93 s->unit = unit;
3ff7e8f0 94 s->direction = dir;
31ef9134
CL
95 s->flags = flags;
96 s->context = ERR_PTR(-1);
97 mutex_init(&s->mutex);
76fb8789 98 tasklet_init(&s->period_tasklet, pcm_period_tasklet, (unsigned long)s);
ec00f5e4 99 s->packet_index = 0;
31ef9134 100
7b3b0d85
TS
101 init_waitqueue_head(&s->callback_wait);
102 s->callbacked = false;
7b3b0d85 103
5955815e 104 s->fmt = fmt;
df075fee 105 s->process_data_blocks = process_data_blocks;
414ba022 106
31ef9134
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107 return 0;
108}
be4a2894 109EXPORT_SYMBOL(amdtp_stream_init);
31ef9134
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110
111/**
be4a2894
TS
112 * amdtp_stream_destroy - free stream resources
113 * @s: the AMDTP stream to destroy
31ef9134 114 */
be4a2894 115void amdtp_stream_destroy(struct amdtp_stream *s)
31ef9134 116{
44c376b9
TS
117 /* Not initialized. */
118 if (s->protocol == NULL)
119 return;
120
be4a2894 121 WARN_ON(amdtp_stream_running(s));
df075fee 122 kfree(s->protocol);
31ef9134 123 mutex_destroy(&s->mutex);
31ef9134 124}
be4a2894 125EXPORT_SYMBOL(amdtp_stream_destroy);
31ef9134 126
c5280e99 127const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = {
a7304e3b
CL
128 [CIP_SFC_32000] = 8,
129 [CIP_SFC_44100] = 8,
130 [CIP_SFC_48000] = 8,
131 [CIP_SFC_88200] = 16,
132 [CIP_SFC_96000] = 16,
133 [CIP_SFC_176400] = 32,
134 [CIP_SFC_192000] = 32,
135};
136EXPORT_SYMBOL(amdtp_syt_intervals);
137
f9503a68 138const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = {
1017abed
TS
139 [CIP_SFC_32000] = 32000,
140 [CIP_SFC_44100] = 44100,
141 [CIP_SFC_48000] = 48000,
142 [CIP_SFC_88200] = 88200,
143 [CIP_SFC_96000] = 96000,
144 [CIP_SFC_176400] = 176400,
145 [CIP_SFC_192000] = 192000,
146};
147EXPORT_SYMBOL(amdtp_rate_table);
148
59502295
TS
149static int apply_constraint_to_size(struct snd_pcm_hw_params *params,
150 struct snd_pcm_hw_rule *rule)
151{
152 struct snd_interval *s = hw_param_interval(params, rule->var);
153 const struct snd_interval *r =
154 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
826b5de9
TS
155 struct snd_interval t = {0};
156 unsigned int step = 0;
59502295
TS
157 int i;
158
159 for (i = 0; i < CIP_SFC_COUNT; ++i) {
826b5de9
TS
160 if (snd_interval_test(r, amdtp_rate_table[i]))
161 step = max(step, amdtp_syt_intervals[i]);
59502295
TS
162 }
163
826b5de9
TS
164 t.min = roundup(s->min, step);
165 t.max = rounddown(s->max, step);
166 t.integer = 1;
59502295
TS
167
168 return snd_interval_refine(s, &t);
169}
170
7b2d99fa
TS
171/**
172 * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream
173 * @s: the AMDTP stream, which must be initialized.
174 * @runtime: the PCM substream runtime
175 */
176int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s,
177 struct snd_pcm_runtime *runtime)
178{
55799c5a 179 struct snd_pcm_hardware *hw = &runtime->hw;
7b2d99fa
TS
180 int err;
181
55799c5a
TS
182 hw->info = SNDRV_PCM_INFO_BATCH |
183 SNDRV_PCM_INFO_BLOCK_TRANSFER |
184 SNDRV_PCM_INFO_INTERLEAVED |
185 SNDRV_PCM_INFO_JOINT_DUPLEX |
186 SNDRV_PCM_INFO_MMAP |
187 SNDRV_PCM_INFO_MMAP_VALID;
188
189 /* SNDRV_PCM_INFO_BATCH */
190 hw->periods_min = 2;
191 hw->periods_max = UINT_MAX;
192
193 /* bytes for a frame */
194 hw->period_bytes_min = 4 * hw->channels_max;
195
196 /* Just to prevent from allocating much pages. */
197 hw->period_bytes_max = hw->period_bytes_min * 2048;
198 hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min;
199
7b2d99fa
TS
200 /*
201 * Currently firewire-lib processes 16 packets in one software
202 * interrupt callback. This equals to 2msec but actually the
203 * interval of the interrupts has a jitter.
204 * Additionally, even if adding a constraint to fit period size to
205 * 2msec, actual calculated frames per period doesn't equal to 2msec,
206 * depending on sampling rate.
207 * Anyway, the interval to call snd_pcm_period_elapsed() cannot 2msec.
208 * Here let us use 5msec for safe period interrupt.
209 */
210 err = snd_pcm_hw_constraint_minmax(runtime,
211 SNDRV_PCM_HW_PARAM_PERIOD_TIME,
212 5000, UINT_MAX);
213 if (err < 0)
214 goto end;
215
216 /* Non-Blocking stream has no more constraints */
217 if (!(s->flags & CIP_BLOCKING))
218 goto end;
219
220 /*
221 * One AMDTP packet can include some frames. In blocking mode, the
222 * number equals to SYT_INTERVAL. So the number is 8, 16 or 32,
223 * depending on its sampling rate. For accurate period interrupt, it's
ce991981 224 * preferrable to align period/buffer sizes to current SYT_INTERVAL.
7b2d99fa 225 */
59502295
TS
226 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
227 apply_constraint_to_size, NULL,
826b5de9 228 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
59502295
TS
229 SNDRV_PCM_HW_PARAM_RATE, -1);
230 if (err < 0)
231 goto end;
59502295
TS
232 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
233 apply_constraint_to_size, NULL,
826b5de9 234 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
59502295
TS
235 SNDRV_PCM_HW_PARAM_RATE, -1);
236 if (err < 0)
237 goto end;
7b2d99fa
TS
238end:
239 return err;
240}
241EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints);
242
31ef9134 243/**
be4a2894
TS
244 * amdtp_stream_set_parameters - set stream parameters
245 * @s: the AMDTP stream to configure
31ef9134 246 * @rate: the sample rate
df075fee 247 * @data_block_quadlets: the size of a data block in quadlet unit
31ef9134 248 *
a7304e3b 249 * The parameters must be set before the stream is started, and must not be
31ef9134
CL
250 * changed while the stream is running.
251 */
df075fee
TS
252int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate,
253 unsigned int data_block_quadlets)
31ef9134 254{
df075fee 255 unsigned int sfc;
31ef9134 256
547e631c 257 for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) {
1017abed 258 if (amdtp_rate_table[sfc] == rate)
547e631c
TS
259 break;
260 }
261 if (sfc == ARRAY_SIZE(amdtp_rate_table))
262 return -EINVAL;
e84d15f6 263
e84d15f6 264 s->sfc = sfc;
df075fee 265 s->data_block_quadlets = data_block_quadlets;
a7304e3b 266 s->syt_interval = amdtp_syt_intervals[sfc];
e84d15f6 267
d3d10a4a
TS
268 // default buffering in the device.
269 if (s->direction == AMDTP_OUT_STREAM) {
270 s->ctx_data.rx.transfer_delay =
271 TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
272
273 if (s->flags & CIP_BLOCKING) {
274 // additional buffering needed to adjust for no-data
275 // packets.
276 s->ctx_data.rx.transfer_delay +=
277 TICKS_PER_SECOND * s->syt_interval / rate;
278 }
279 }
77d2a8a4 280
547e631c 281 return 0;
31ef9134 282}
be4a2894 283EXPORT_SYMBOL(amdtp_stream_set_parameters);
31ef9134
CL
284
285/**
be4a2894
TS
286 * amdtp_stream_get_max_payload - get the stream's packet size
287 * @s: the AMDTP stream
31ef9134
CL
288 *
289 * This function must not be called before the stream has been configured
be4a2894 290 * with amdtp_stream_set_parameters().
31ef9134 291 */
be4a2894 292unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s)
31ef9134 293{
a2064710 294 unsigned int multiplier = 1;
07ea238c 295 unsigned int cip_header_size = 0;
a2064710
TS
296
297 if (s->flags & CIP_JUMBO_PAYLOAD)
298 multiplier = 5;
3b196c39 299 if (!(s->flags & CIP_NO_HEADER))
07ea238c 300 cip_header_size = sizeof(__be32) * 2;
a2064710 301
07ea238c
TS
302 return cip_header_size +
303 s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier;
31ef9134 304}
be4a2894 305EXPORT_SYMBOL(amdtp_stream_get_max_payload);
31ef9134 306
76fb8789 307/**
be4a2894
TS
308 * amdtp_stream_pcm_prepare - prepare PCM device for running
309 * @s: the AMDTP stream
76fb8789
CL
310 *
311 * This function should be called from the PCM device's .prepare callback.
312 */
be4a2894 313void amdtp_stream_pcm_prepare(struct amdtp_stream *s)
76fb8789
CL
314{
315 tasklet_kill(&s->period_tasklet);
316 s->pcm_buffer_pointer = 0;
317 s->pcm_period_pointer = 0;
318}
be4a2894 319EXPORT_SYMBOL(amdtp_stream_pcm_prepare);
76fb8789 320
875be091
TS
321static unsigned int calculate_data_blocks(struct amdtp_stream *s,
322 unsigned int syt)
31ef9134
CL
323{
324 unsigned int phase, data_blocks;
325
875be091
TS
326 /* Blocking mode. */
327 if (s->flags & CIP_BLOCKING) {
328 /* This module generate empty packet for 'no data'. */
329 if (syt == CIP_SYT_NO_INFO)
330 data_blocks = 0;
331 else
332 data_blocks = s->syt_interval;
333 /* Non-blocking mode. */
31ef9134 334 } else {
875be091 335 if (!cip_sfc_is_base_44100(s->sfc)) {
d3d10a4a
TS
336 // Sample_rate / 8000 is an integer, and precomputed.
337 data_blocks = s->ctx_data.rx.data_block_state;
875be091 338 } else {
d3d10a4a 339 phase = s->ctx_data.rx.data_block_state;
31ef9134
CL
340
341 /*
342 * This calculates the number of data blocks per packet so that
343 * 1) the overall rate is correct and exactly synchronized to
344 * the bus clock, and
345 * 2) packets with a rounded-up number of blocks occur as early
346 * as possible in the sequence (to prevent underruns of the
347 * device's buffer).
348 */
875be091
TS
349 if (s->sfc == CIP_SFC_44100)
350 /* 6 6 5 6 5 6 5 ... */
351 data_blocks = 5 + ((phase & 1) ^
352 (phase == 0 || phase >= 40));
353 else
354 /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */
355 data_blocks = 11 * (s->sfc >> 1) + (phase == 0);
356 if (++phase >= (80 >> (s->sfc >> 1)))
357 phase = 0;
d3d10a4a 358 s->ctx_data.rx.data_block_state = phase;
875be091 359 }
31ef9134
CL
360 }
361
362 return data_blocks;
363}
364
be4a2894 365static unsigned int calculate_syt(struct amdtp_stream *s,
31ef9134
CL
366 unsigned int cycle)
367{
368 unsigned int syt_offset, phase, index, syt;
369
d3d10a4a 370 if (s->ctx_data.rx.last_syt_offset < TICKS_PER_CYCLE) {
31ef9134 371 if (!cip_sfc_is_base_44100(s->sfc))
d3d10a4a
TS
372 syt_offset = s->ctx_data.rx.last_syt_offset +
373 s->ctx_data.rx.syt_offset_state;
31ef9134
CL
374 else {
375 /*
376 * The time, in ticks, of the n'th SYT_INTERVAL sample is:
377 * n * SYT_INTERVAL * 24576000 / sample_rate
378 * Modulo TICKS_PER_CYCLE, the difference between successive
379 * elements is about 1386.23. Rounding the results of this
380 * formula to the SYT precision results in a sequence of
381 * differences that begins with:
382 * 1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ...
383 * This code generates _exactly_ the same sequence.
384 */
d3d10a4a 385 phase = s->ctx_data.rx.syt_offset_state;
31ef9134 386 index = phase % 13;
d3d10a4a 387 syt_offset = s->ctx_data.rx.last_syt_offset;
31ef9134
CL
388 syt_offset += 1386 + ((index && !(index & 3)) ||
389 phase == 146);
390 if (++phase >= 147)
391 phase = 0;
d3d10a4a 392 s->ctx_data.rx.syt_offset_state = phase;
31ef9134
CL
393 }
394 } else
d3d10a4a
TS
395 syt_offset = s->ctx_data.rx.last_syt_offset - TICKS_PER_CYCLE;
396 s->ctx_data.rx.last_syt_offset = syt_offset;
31ef9134 397
be454366 398 if (syt_offset < TICKS_PER_CYCLE) {
d3d10a4a 399 syt_offset += s->ctx_data.rx.transfer_delay;
be454366
CL
400 syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12;
401 syt += syt_offset % TICKS_PER_CYCLE;
31ef9134 402
b445db44 403 return syt & CIP_SYT_MASK;
be454366 404 } else {
b445db44 405 return CIP_SYT_NO_INFO;
be454366 406 }
31ef9134
CL
407}
408
4b7da117
TS
409static void update_pcm_pointers(struct amdtp_stream *s,
410 struct snd_pcm_substream *pcm,
411 unsigned int frames)
65845f29
TS
412{
413 unsigned int ptr;
414
4b7da117
TS
415 ptr = s->pcm_buffer_pointer + frames;
416 if (ptr >= pcm->runtime->buffer_size)
417 ptr -= pcm->runtime->buffer_size;
6aa7de05 418 WRITE_ONCE(s->pcm_buffer_pointer, ptr);
4b7da117
TS
419
420 s->pcm_period_pointer += frames;
421 if (s->pcm_period_pointer >= pcm->runtime->period_size) {
422 s->pcm_period_pointer -= pcm->runtime->period_size;
4b7da117
TS
423 tasklet_hi_schedule(&s->period_tasklet);
424 }
425}
426
427static void pcm_period_tasklet(unsigned long data)
428{
429 struct amdtp_stream *s = (void *)data;
6aa7de05 430 struct snd_pcm_substream *pcm = READ_ONCE(s->pcm);
4b7da117
TS
431
432 if (pcm)
433 snd_pcm_period_elapsed(pcm);
434}
435
6007bf54 436static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params)
4b7da117 437{
6007bf54 438 int err;
df9160b9 439
6007bf54
TS
440 params->interrupt = IS_ALIGNED(s->packet_index + 1, INTERRUPT_INTERVAL);
441 params->tag = s->tag;
442 params->sy = 0;
df9160b9 443
6007bf54 444 err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer,
4b7da117
TS
445 s->buffer.packets[s->packet_index].offset);
446 if (err < 0) {
447 dev_err(&s->unit->device, "queueing error: %d\n", err);
448 goto end;
449 }
450
451 if (++s->packet_index >= QUEUE_LENGTH)
452 s->packet_index = 0;
453end:
454 return err;
455}
456
457static inline int queue_out_packet(struct amdtp_stream *s,
b18f0cfa 458 struct fw_iso_packet *params)
4b7da117 459{
b18f0cfa
TS
460 params->skip =
461 !!(params->header_length == 0 && params->payload_length == 0);
6007bf54 462 return queue_packet(s, params);
4b7da117
TS
463}
464
6007bf54
TS
465static inline int queue_in_packet(struct amdtp_stream *s,
466 struct fw_iso_packet *params)
2b3fc456 467{
6007bf54
TS
468 // Queue one packet for IR context.
469 params->header_length = s->ctx_data.tx.ctx_header_size;
470 params->payload_length = s->ctx_data.tx.max_ctx_payload_length;
471 params->skip = false;
472 return queue_packet(s, params);
2b3fc456
TS
473}
474
252219c7
TS
475static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2],
476 unsigned int syt)
477{
478 cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) |
479 (s->data_block_quadlets << CIP_DBS_SHIFT) |
480 ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) |
481 s->data_block_counter);
482 cip_header[1] = cpu_to_be32(CIP_EOH |
483 ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) |
484 ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) |
485 (syt & CIP_SYT_MASK));
486}
487
6f3c07d0 488static int handle_out_packet(struct amdtp_stream *s, unsigned int cycle,
8a400b99
TS
489 const __be32 *ctx_header, __be32 *buffer,
490 unsigned int index)
31ef9134 491{
390a1512
TS
492 unsigned int syt;
493 unsigned int data_blocks;
16be4589
TS
494 __be32 *cip_header;
495 unsigned int pcm_frames;
31ef9134 496 struct snd_pcm_substream *pcm;
b18f0cfa
TS
497 struct {
498 struct fw_iso_packet params;
499 __be32 header[IT_PKT_HEADER_SIZE_CIP / sizeof(__be32)];
500 } template = { {0}, {0} };
31ef9134 501
390a1512
TS
502 syt = calculate_syt(s, cycle);
503 data_blocks = calculate_data_blocks(s, syt);
16be4589 504 pcm_frames = s->process_data_blocks(s, buffer, data_blocks, &syt);
20e44577 505
9dae017b
TS
506 if (s->flags & CIP_DBC_IS_END_EVENT)
507 s->data_block_counter =
508 (s->data_block_counter + data_blocks) & 0xff;
509
b18f0cfa
TS
510 if (!(s->flags & CIP_NO_HEADER)) {
511 cip_header = (__be32 *)template.params.header;
16be4589 512 generate_cip_header(s, cip_header, syt);
b18f0cfa
TS
513 template.params.header_length = 2 * sizeof(__be32);
514 } else {
515 cip_header = NULL;
516 }
31ef9134 517
9dae017b
TS
518 if (!(s->flags & CIP_DBC_IS_END_EVENT))
519 s->data_block_counter =
520 (s->data_block_counter + data_blocks) & 0xff;
0c95c1d6 521
b18f0cfa
TS
522 template.params.payload_length =
523 data_blocks * sizeof(__be32) * s->data_block_quadlets;
524
525 trace_amdtp_packet(s, cycle, cip_header, template.params.payload_length,
526 data_blocks, index);
b164d2fd 527
b18f0cfa 528 if (queue_out_packet(s, &template.params) < 0)
3b196c39
TS
529 return -EIO;
530
6aa7de05 531 pcm = READ_ONCE(s->pcm);
3b196c39
TS
532 if (pcm && pcm_frames > 0)
533 update_pcm_pointers(s, pcm, pcm_frames);
534
3b196c39
TS
535 return 0;
536}
537
e335425b
TS
538static int check_cip_header(struct amdtp_stream *s, const __be32 *buf,
539 unsigned int payload_length,
540 unsigned int *data_blocks, unsigned int *syt)
2b3fc456
TS
541{
542 u32 cip_header[2];
e335425b
TS
543 unsigned int sph;
544 unsigned int fmt;
545 unsigned int fdf;
546 unsigned int data_block_counter;
c8bdf49b 547 bool lost;
2b3fc456 548
e335425b
TS
549 cip_header[0] = be32_to_cpu(buf[0]);
550 cip_header[1] = be32_to_cpu(buf[1]);
2b3fc456
TS
551
552 /*
553 * This module supports 'Two-quadlet CIP header with SYT field'.
77d2a8a4 554 * For convenience, also check FMT field is AM824 or not.
2b3fc456 555 */
2128f78f
TS
556 if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) ||
557 ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) &&
558 (!(s->flags & CIP_HEADER_WITHOUT_EOH))) {
2b3fc456
TS
559 dev_info_ratelimited(&s->unit->device,
560 "Invalid CIP header for AMDTP: %08X:%08X\n",
561 cip_header[0], cip_header[1]);
e335425b 562 return -EAGAIN;
2b3fc456
TS
563 }
564
414ba022 565 /* Check valid protocol or not. */
9863874f 566 sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT;
414ba022 567 fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT;
9863874f 568 if (sph != s->sph || fmt != s->fmt) {
2a7e1713
TS
569 dev_info_ratelimited(&s->unit->device,
570 "Detect unexpected protocol: %08x %08x\n",
571 cip_header[0], cip_header[1]);
e335425b 572 return -EAGAIN;
414ba022
TS
573 }
574
2b3fc456 575 /* Calculate data blocks */
414ba022 576 fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT;
e335425b 577 if (payload_length < sizeof(__be32) * 2 ||
414ba022 578 (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) {
e335425b 579 *data_blocks = 0;
2b3fc456 580 } else {
e335425b
TS
581 unsigned int data_block_quadlets =
582 (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT;
2b3fc456
TS
583 /* avoid division by zero */
584 if (data_block_quadlets == 0) {
12e0f438 585 dev_err(&s->unit->device,
2b3fc456
TS
586 "Detect invalid value in dbs field: %08X\n",
587 cip_header[0]);
a9007054 588 return -EPROTO;
2b3fc456 589 }
69702239
TS
590 if (s->flags & CIP_WRONG_DBS)
591 data_block_quadlets = s->data_block_quadlets;
2b3fc456 592
e335425b 593 *data_blocks = (payload_length / sizeof(__be32) - 2) /
ff0fb5aa 594 data_block_quadlets;
2b3fc456
TS
595 }
596
597 /* Check data block counter continuity */
9a2820c1 598 data_block_counter = cip_header[0] & CIP_DBC_MASK;
e335425b 599 if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) &&
9d59124c
TS
600 s->data_block_counter != UINT_MAX)
601 data_block_counter = s->data_block_counter;
602
18f5ed36 603 if (((s->flags & CIP_SKIP_DBC_ZERO_CHECK) &&
d3d10a4a 604 data_block_counter == s->ctx_data.tx.first_dbc) ||
18f5ed36 605 s->data_block_counter == UINT_MAX) {
b84b1a27
TS
606 lost = false;
607 } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) {
c8bdf49b 608 lost = data_block_counter != s->data_block_counter;
d9cd0065 609 } else {
e335425b
TS
610 unsigned int dbc_interval;
611
612 if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0)
d3d10a4a 613 dbc_interval = s->ctx_data.tx.dbc_interval;
d9cd0065 614 else
e335425b 615 dbc_interval = *data_blocks;
d9cd0065 616
c8bdf49b 617 lost = data_block_counter !=
d9cd0065
TS
618 ((s->data_block_counter + dbc_interval) & 0xff);
619 }
c8bdf49b
TS
620
621 if (lost) {
12e0f438
TS
622 dev_err(&s->unit->device,
623 "Detect discontinuity of CIP: %02X %02X\n",
624 s->data_block_counter, data_block_counter);
6fc6b9ce 625 return -EIO;
2b3fc456
TS
626 }
627
e335425b 628 *syt = cip_header[1] & CIP_SYT_MASK;
2b3fc456 629
e335425b 630 if (s->flags & CIP_DBC_IS_END_EVENT) {
c8bdf49b 631 s->data_block_counter = data_block_counter;
e335425b 632 } else {
c8bdf49b 633 s->data_block_counter =
e335425b
TS
634 (data_block_counter + *data_blocks) & 0xff;
635 }
636
637 return 0;
638}
639
640static int handle_in_packet(struct amdtp_stream *s, unsigned int cycle,
641 const __be32 *ctx_header, __be32 *buffer,
642 unsigned int index)
643{
644 unsigned int payload_length;
f11453c7 645 const __be32 *cip_header;
e335425b
TS
646 unsigned int syt;
647 unsigned int data_blocks;
648 struct snd_pcm_substream *pcm;
649 unsigned int pcm_frames;
6007bf54 650 struct fw_iso_packet params = {0};
e335425b
TS
651 int err;
652
653 payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT;
f11453c7
TS
654 if (payload_length > s->ctx_data.tx.ctx_header_size +
655 s->ctx_data.tx.max_ctx_payload_length) {
e335425b
TS
656 dev_err(&s->unit->device,
657 "Detect jumbo payload: %04x %04x\n",
f11453c7 658 payload_length, s->ctx_data.tx.max_ctx_payload_length);
e335425b
TS
659 return -EIO;
660 }
661
f11453c7 662 cip_header = ctx_header + 2;
947b437e
TS
663 if (!(s->flags & CIP_NO_HEADER)) {
664 cip_header = &ctx_header[2];
665 err = check_cip_header(s, cip_header, payload_length,
666 &data_blocks, &syt);
667 if (err < 0) {
668 if (err != -EAGAIN)
669 return err;
670 pcm_frames = 0;
671 goto end;
672 }
673 } else {
674 cip_header = NULL;
675 data_blocks = payload_length / 4 / s->data_block_quadlets;
676 syt = 0;
3c194923
TS
677 s->data_block_counter =
678 (s->data_block_counter + data_blocks) & 0xff;
e335425b
TS
679 }
680
f11453c7
TS
681 trace_amdtp_packet(s, cycle, cip_header, payload_length, data_blocks,
682 index);
e335425b 683
f11453c7 684 pcm_frames = s->process_data_blocks(s, buffer, data_blocks, &syt);
2b3fc456 685end:
6007bf54 686 if (queue_in_packet(s, &params) < 0)
6fc6b9ce 687 return -EIO;
2b3fc456 688
6aa7de05 689 pcm = READ_ONCE(s->pcm);
20e44577
TS
690 if (pcm && pcm_frames > 0)
691 update_pcm_pointers(s, pcm, pcm_frames);
2b3fc456 692
31ea49ba 693 return 0;
2b3fc456
TS
694}
695
26cd1e58
TS
696// In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On
697// the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent
698// it. Thus, via Linux firewire subsystem, we can get the 3 bits for second.
699static inline u32 compute_cycle_count(__be32 ctx_header_tstamp)
73fc7f08 700{
26cd1e58 701 u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK;
73fc7f08
TS
702 return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff);
703}
704
705static inline u32 increment_cycle_count(u32 cycle, unsigned int addend)
706{
707 cycle += addend;
708 if (cycle >= 8 * CYCLES_PER_SECOND)
709 cycle -= 8 * CYCLES_PER_SECOND;
710 return cycle;
711}
712
26cd1e58
TS
713// Align to actual cycle count for the packet which is going to be scheduled.
714// This module queued the same number of isochronous cycle as QUEUE_LENGTH to
715// skip isochronous cycle, therefore it's OK to just increment the cycle by
716// QUEUE_LENGTH for scheduled cycle.
717static inline u32 compute_it_cycle(const __be32 ctx_header_tstamp)
718{
719 u32 cycle = compute_cycle_count(ctx_header_tstamp);
720 return increment_cycle_count(cycle, QUEUE_LENGTH);
721}
722
fce9b013
TS
723static inline void cancel_stream(struct amdtp_stream *s)
724{
725 s->packet_index = -1;
726 if (in_interrupt())
727 amdtp_stream_pcm_abort(s);
728 WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN);
729}
730
73fc7f08 731static void out_stream_callback(struct fw_iso_context *context, u32 tstamp,
4b7da117
TS
732 size_t header_length, void *header,
733 void *private_data)
31ef9134 734{
be4a2894 735 struct amdtp_stream *s = private_data;
26cd1e58
TS
736 const __be32 *ctx_header = header;
737 unsigned int i, packets = header_length / sizeof(*ctx_header);
31ef9134 738
a4103bd7
TS
739 if (s->packet_index < 0)
740 return;
741
26cd1e58
TS
742 for (i = 0; i < packets; ++i) {
743 u32 cycle;
8a400b99 744 __be32 *buffer;
73fc7f08 745
26cd1e58 746 cycle = compute_it_cycle(*ctx_header);
8a400b99 747 buffer = s->buffer.packets[s->packet_index].buffer;
31ef9134 748
16be4589 749 if (handle_out_packet(s, cycle, ctx_header, buffer, i) < 0) {
fce9b013 750 cancel_stream(s);
a4103bd7
TS
751 return;
752 }
26cd1e58
TS
753
754 ++ctx_header;
ccccad86 755 }
a4103bd7 756
13882a82 757 fw_iso_context_queue_flush(s->context);
31ef9134
CL
758}
759
73fc7f08 760static void in_stream_callback(struct fw_iso_context *context, u32 tstamp,
2b3fc456
TS
761 size_t header_length, void *header,
762 void *private_data)
763{
764 struct amdtp_stream *s = private_data;
d9a16fc9 765 unsigned int i, packets;
cc4f8e91 766 __be32 *ctx_header = header;
2b3fc456 767
a4103bd7
TS
768 if (s->packet_index < 0)
769 return;
770
d3d10a4a
TS
771 // The number of packets in buffer.
772 packets = header_length / s->ctx_data.tx.ctx_header_size;
f90e2ded 773
d9a16fc9 774 for (i = 0; i < packets; i++) {
26cd1e58 775 u32 cycle;
8a400b99 776 __be32 *buffer;
cc4f8e91 777
26cd1e58 778 cycle = compute_cycle_count(ctx_header[1]);
8a400b99 779 buffer = s->buffer.packets[s->packet_index].buffer;
2b3fc456 780
947b437e 781 if (handle_in_packet(s, cycle, ctx_header, buffer, i) < 0)
6fc6b9ce 782 break;
cc4f8e91 783
d3d10a4a 784 ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
2b3fc456
TS
785 }
786
dec63cc8 787 /* Queueing error or detecting invalid payload. */
d9a16fc9 788 if (i < packets) {
fce9b013 789 cancel_stream(s);
7b3b0d85
TS
790 return;
791 }
792
2b3fc456
TS
793 fw_iso_context_queue_flush(s->context);
794}
795
7b3b0d85
TS
796/* this is executed one time */
797static void amdtp_stream_first_callback(struct fw_iso_context *context,
73fc7f08 798 u32 tstamp, size_t header_length,
7b3b0d85
TS
799 void *header, void *private_data)
800{
801 struct amdtp_stream *s = private_data;
26cd1e58 802 const __be32 *ctx_header = header;
a04513f8 803 u32 cycle;
7b3b0d85
TS
804
805 /*
806 * For in-stream, first packet has come.
807 * For out-stream, prepared to transmit first packet
808 */
809 s->callbacked = true;
810 wake_up(&s->callback_wait);
811
a04513f8 812 if (s->direction == AMDTP_IN_STREAM) {
26cd1e58 813 cycle = compute_cycle_count(ctx_header[1]);
cc4f8e91 814
7b3b0d85 815 context->callback.sc = in_stream_callback;
a04513f8 816 } else {
26cd1e58
TS
817 cycle = compute_it_cycle(*ctx_header);
818
7b3b0d85 819 context->callback.sc = out_stream_callback;
a04513f8
TS
820 }
821
822 s->start_cycle = cycle;
7b3b0d85 823
73fc7f08 824 context->callback.sc(context, tstamp, header_length, header, s);
7b3b0d85
TS
825}
826
31ef9134 827/**
be4a2894
TS
828 * amdtp_stream_start - start transferring packets
829 * @s: the AMDTP stream to start
31ef9134
CL
830 * @channel: the isochronous channel on the bus
831 * @speed: firewire speed code
832 *
833 * The stream cannot be started until it has been configured with
be4a2894
TS
834 * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI
835 * device can be started.
31ef9134 836 */
be4a2894 837int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed)
31ef9134
CL
838{
839 static const struct {
840 unsigned int data_block;
841 unsigned int syt_offset;
d3d10a4a 842 } *entry, initial_state[] = {
31ef9134
CL
843 [CIP_SFC_32000] = { 4, 3072 },
844 [CIP_SFC_48000] = { 6, 1024 },
845 [CIP_SFC_96000] = { 12, 1024 },
846 [CIP_SFC_192000] = { 24, 1024 },
847 [CIP_SFC_44100] = { 0, 67 },
848 [CIP_SFC_88200] = { 0, 67 },
849 [CIP_SFC_176400] = { 0, 67 },
850 };
d3d10a4a 851 unsigned int ctx_header_size;
f11453c7 852 unsigned int max_ctx_payload_size;
2b3fc456 853 enum dma_data_direction dir;
7ab56645 854 int type, tag, err;
31ef9134
CL
855
856 mutex_lock(&s->mutex);
857
be4a2894 858 if (WARN_ON(amdtp_stream_running(s) ||
4b7da117 859 (s->data_block_quadlets < 1))) {
31ef9134
CL
860 err = -EBADFD;
861 goto err_unlock;
862 }
863
d3d10a4a 864 if (s->direction == AMDTP_IN_STREAM) {
b6bc8123 865 s->data_block_counter = UINT_MAX;
d3d10a4a
TS
866 } else {
867 entry = &initial_state[s->sfc];
868
b6bc8123 869 s->data_block_counter = 0;
d3d10a4a
TS
870 s->ctx_data.rx.data_block_state = entry->data_block;
871 s->ctx_data.rx.syt_offset_state = entry->syt_offset;
872 s->ctx_data.rx.last_syt_offset = TICKS_PER_CYCLE;
873 }
31ef9134 874
2b3fc456
TS
875 /* initialize packet buffer */
876 if (s->direction == AMDTP_IN_STREAM) {
877 dir = DMA_FROM_DEVICE;
878 type = FW_ISO_CONTEXT_RECEIVE;
f11453c7
TS
879 if (!(s->flags & CIP_NO_HEADER))
880 ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
881 else
882 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
b18f0cfa
TS
883
884 max_ctx_payload_size = amdtp_stream_get_max_payload(s) -
885 ctx_header_size;
2b3fc456
TS
886 } else {
887 dir = DMA_TO_DEVICE;
888 type = FW_ISO_CONTEXT_TRANSMIT;
df9160b9 889 ctx_header_size = 0; // No effect for IT context.
f11453c7 890
b18f0cfa
TS
891 max_ctx_payload_size = amdtp_stream_get_max_payload(s);
892 if (!(s->flags & CIP_NO_HEADER))
893 max_ctx_payload_size -= IT_PKT_HEADER_SIZE_CIP;
894 }
f11453c7 895
31ef9134 896 err = iso_packets_buffer_init(&s->buffer, s->unit, QUEUE_LENGTH,
f11453c7 897 max_ctx_payload_size, dir);
31ef9134
CL
898 if (err < 0)
899 goto err_unlock;
900
901 s->context = fw_iso_context_create(fw_parent_device(s->unit)->card,
d3d10a4a
TS
902 type, channel, speed, ctx_header_size,
903 amdtp_stream_first_callback, s);
31ef9134
CL
904 if (IS_ERR(s->context)) {
905 err = PTR_ERR(s->context);
906 if (err == -EBUSY)
907 dev_err(&s->unit->device,
be4a2894 908 "no free stream on this controller\n");
31ef9134
CL
909 goto err_buffer;
910 }
911
be4a2894 912 amdtp_stream_update(s);
31ef9134 913
d3d10a4a 914 if (s->direction == AMDTP_IN_STREAM) {
f11453c7 915 s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size;
d3d10a4a
TS
916 s->ctx_data.tx.ctx_header_size = ctx_header_size;
917 }
52759c09 918
3b196c39
TS
919 if (s->flags & CIP_NO_HEADER)
920 s->tag = TAG_NO_CIP_HEADER;
921 else
922 s->tag = TAG_CIP;
923
ec00f5e4 924 s->packet_index = 0;
4b7da117 925 do {
6007bf54 926 struct fw_iso_packet params;
b18f0cfa 927 if (s->direction == AMDTP_IN_STREAM) {
6007bf54 928 err = queue_in_packet(s, &params);
b18f0cfa
TS
929 } else {
930 params.header_length = 0;
931 params.payload_length = 0;
932 err = queue_out_packet(s, &params);
933 }
4b7da117
TS
934 if (err < 0)
935 goto err_context;
936 } while (s->packet_index > 0);
31ef9134 937
2b3fc456 938 /* NOTE: TAG1 matches CIP. This just affects in stream. */
7ab56645 939 tag = FW_ISO_CONTEXT_MATCH_TAG1;
3b196c39 940 if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER))
7ab56645
TS
941 tag |= FW_ISO_CONTEXT_MATCH_TAG0;
942
7b3b0d85 943 s->callbacked = false;
7ab56645 944 err = fw_iso_context_start(s->context, -1, 0, tag);
31ef9134
CL
945 if (err < 0)
946 goto err_context;
947
948 mutex_unlock(&s->mutex);
949
950 return 0;
951
952err_context:
953 fw_iso_context_destroy(s->context);
954 s->context = ERR_PTR(-1);
955err_buffer:
956 iso_packets_buffer_destroy(&s->buffer, s->unit);
957err_unlock:
958 mutex_unlock(&s->mutex);
959
960 return err;
961}
be4a2894 962EXPORT_SYMBOL(amdtp_stream_start);
31ef9134 963
e9148ddd 964/**
be4a2894
TS
965 * amdtp_stream_pcm_pointer - get the PCM buffer position
966 * @s: the AMDTP stream that transports the PCM data
e9148ddd
CL
967 *
968 * Returns the current buffer position, in frames.
969 */
be4a2894 970unsigned long amdtp_stream_pcm_pointer(struct amdtp_stream *s)
e9148ddd 971{
1dba9db0
TS
972 /*
973 * This function is called in software IRQ context of period_tasklet or
974 * process context.
975 *
976 * When the software IRQ context was scheduled by software IRQ context
977 * of IR/IT contexts, queued packets were already handled. Therefore,
978 * no need to flush the queue in buffer anymore.
979 *
980 * When the process context reach here, some packets will be already
981 * queued in the buffer. These packets should be handled immediately
982 * to keep better granularity of PCM pointer.
983 *
984 * Later, the process context will sometimes schedules software IRQ
985 * context of the period_tasklet. Then, no need to flush the queue by
986 * the same reason as described for IR/IT contexts.
987 */
988 if (!in_interrupt() && amdtp_stream_running(s))
92b862c7 989 fw_iso_context_flush_completions(s->context);
e9148ddd 990
6aa7de05 991 return READ_ONCE(s->pcm_buffer_pointer);
e9148ddd 992}
be4a2894 993EXPORT_SYMBOL(amdtp_stream_pcm_pointer);
e9148ddd 994
875becf8
TS
995/**
996 * amdtp_stream_pcm_ack - acknowledge queued PCM frames
997 * @s: the AMDTP stream that transfers the PCM frames
998 *
999 * Returns zero always.
1000 */
1001int amdtp_stream_pcm_ack(struct amdtp_stream *s)
1002{
1003 /*
1004 * Process isochronous packets for recent isochronous cycle to handle
1005 * queued PCM frames.
1006 */
1007 if (amdtp_stream_running(s))
1008 fw_iso_context_flush_completions(s->context);
1009
1010 return 0;
1011}
1012EXPORT_SYMBOL(amdtp_stream_pcm_ack);
1013
31ef9134 1014/**
be4a2894
TS
1015 * amdtp_stream_update - update the stream after a bus reset
1016 * @s: the AMDTP stream
31ef9134 1017 */
be4a2894 1018void amdtp_stream_update(struct amdtp_stream *s)
31ef9134 1019{
9a2820c1 1020 /* Precomputing. */
6aa7de05
MR
1021 WRITE_ONCE(s->source_node_id_field,
1022 (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK);
31ef9134 1023}
be4a2894 1024EXPORT_SYMBOL(amdtp_stream_update);
31ef9134
CL
1025
1026/**
be4a2894
TS
1027 * amdtp_stream_stop - stop sending packets
1028 * @s: the AMDTP stream to stop
31ef9134
CL
1029 *
1030 * All PCM and MIDI devices of the stream must be stopped before the stream
1031 * itself can be stopped.
1032 */
be4a2894 1033void amdtp_stream_stop(struct amdtp_stream *s)
31ef9134
CL
1034{
1035 mutex_lock(&s->mutex);
1036
be4a2894 1037 if (!amdtp_stream_running(s)) {
31ef9134
CL
1038 mutex_unlock(&s->mutex);
1039 return;
1040 }
1041
76fb8789 1042 tasklet_kill(&s->period_tasklet);
31ef9134
CL
1043 fw_iso_context_stop(s->context);
1044 fw_iso_context_destroy(s->context);
1045 s->context = ERR_PTR(-1);
1046 iso_packets_buffer_destroy(&s->buffer, s->unit);
1047
7b3b0d85
TS
1048 s->callbacked = false;
1049
31ef9134
CL
1050 mutex_unlock(&s->mutex);
1051}
be4a2894 1052EXPORT_SYMBOL(amdtp_stream_stop);
31ef9134
CL
1053
1054/**
be4a2894 1055 * amdtp_stream_pcm_abort - abort the running PCM device
31ef9134
CL
1056 * @s: the AMDTP stream about to be stopped
1057 *
1058 * If the isochronous stream needs to be stopped asynchronously, call this
1059 * function first to stop the PCM device.
1060 */
be4a2894 1061void amdtp_stream_pcm_abort(struct amdtp_stream *s)
31ef9134
CL
1062{
1063 struct snd_pcm_substream *pcm;
1064
6aa7de05 1065 pcm = READ_ONCE(s->pcm);
1fb8510c
TI
1066 if (pcm)
1067 snd_pcm_stop_xrun(pcm);
31ef9134 1068}
be4a2894 1069EXPORT_SYMBOL(amdtp_stream_pcm_abort);