Commit | Line | Data |
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da607e19 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
31ef9134 CL |
2 | /* |
3 | * Audio and Music Data Transmission Protocol (IEC 61883-6) streams | |
4 | * with Common Isochronous Packet (IEC 61883-1) headers | |
5 | * | |
6 | * Copyright (c) Clemens Ladisch <clemens@ladisch.de> | |
31ef9134 CL |
7 | */ |
8 | ||
9 | #include <linux/device.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/firewire.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/slab.h> | |
14 | #include <sound/pcm.h> | |
7b2d99fa | 15 | #include <sound/pcm_params.h> |
d67c46b9 | 16 | #include "amdtp-stream.h" |
31ef9134 CL |
17 | |
18 | #define TICKS_PER_CYCLE 3072 | |
19 | #define CYCLES_PER_SECOND 8000 | |
20 | #define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND) | |
21 | ||
0c95c1d6 TS |
22 | /* Always support Linux tracing subsystem. */ |
23 | #define CREATE_TRACE_POINTS | |
24 | #include "amdtp-stream-trace.h" | |
25 | ||
ca5b5050 | 26 | #define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */ |
31ef9134 | 27 | |
b445db44 TS |
28 | /* isochronous header parameters */ |
29 | #define ISO_DATA_LENGTH_SHIFT 16 | |
3b196c39 | 30 | #define TAG_NO_CIP_HEADER 0 |
31ef9134 CL |
31 | #define TAG_CIP 1 |
32 | ||
b445db44 | 33 | /* common isochronous packet header parameters */ |
9a2820c1 TS |
34 | #define CIP_EOH_SHIFT 31 |
35 | #define CIP_EOH (1u << CIP_EOH_SHIFT) | |
b445db44 | 36 | #define CIP_EOH_MASK 0x80000000 |
9a2820c1 TS |
37 | #define CIP_SID_SHIFT 24 |
38 | #define CIP_SID_MASK 0x3f000000 | |
39 | #define CIP_DBS_MASK 0x00ff0000 | |
40 | #define CIP_DBS_SHIFT 16 | |
9863874f TS |
41 | #define CIP_SPH_MASK 0x00000400 |
42 | #define CIP_SPH_SHIFT 10 | |
9a2820c1 TS |
43 | #define CIP_DBC_MASK 0x000000ff |
44 | #define CIP_FMT_SHIFT 24 | |
b445db44 | 45 | #define CIP_FMT_MASK 0x3f000000 |
9a2820c1 TS |
46 | #define CIP_FDF_MASK 0x00ff0000 |
47 | #define CIP_FDF_SHIFT 16 | |
b445db44 TS |
48 | #define CIP_SYT_MASK 0x0000ffff |
49 | #define CIP_SYT_NO_INFO 0xffff | |
b445db44 | 50 | |
51c29fd2 | 51 | /* Audio and Music transfer protocol specific parameters */ |
414ba022 | 52 | #define CIP_FMT_AM 0x10 |
2b3fc456 | 53 | #define AMDTP_FDF_NO_DATA 0xff |
31ef9134 | 54 | |
f11453c7 TS |
55 | // For iso header, tstamp and 2 CIP header. |
56 | #define IR_CTX_HEADER_SIZE_CIP 16 | |
57 | // For iso header and tstamp. | |
58 | #define IR_CTX_HEADER_SIZE_NO_CIP 8 | |
cc4f8e91 | 59 | #define HEADER_TSTAMP_MASK 0x0000ffff |
4b7da117 | 60 | |
b18f0cfa TS |
61 | #define IT_PKT_HEADER_SIZE_CIP 8 // For 2 CIP header. |
62 | #define IT_PKT_HEADER_SIZE_NO_CIP 0 // Nothing. | |
63 | ||
76fb8789 CL |
64 | static void pcm_period_tasklet(unsigned long data); |
65 | ||
31ef9134 | 66 | /** |
be4a2894 TS |
67 | * amdtp_stream_init - initialize an AMDTP stream structure |
68 | * @s: the AMDTP stream to initialize | |
31ef9134 | 69 | * @unit: the target of the stream |
3ff7e8f0 | 70 | * @dir: the direction of stream |
31ef9134 | 71 | * @flags: the packet transmission method to use |
5955815e | 72 | * @fmt: the value of fmt field in CIP header |
9a738ad1 | 73 | * @process_ctx_payloads: callback handler to process payloads of isoc context |
df075fee | 74 | * @protocol_size: the size to allocate newly for protocol |
31ef9134 | 75 | */ |
be4a2894 | 76 | int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit, |
5955815e | 77 | enum amdtp_stream_direction dir, enum cip_flags flags, |
df075fee | 78 | unsigned int fmt, |
9a738ad1 | 79 | amdtp_stream_process_ctx_payloads_t process_ctx_payloads, |
df075fee | 80 | unsigned int protocol_size) |
31ef9134 | 81 | { |
9a738ad1 | 82 | if (process_ctx_payloads == NULL) |
df075fee TS |
83 | return -EINVAL; |
84 | ||
85 | s->protocol = kzalloc(protocol_size, GFP_KERNEL); | |
86 | if (!s->protocol) | |
87 | return -ENOMEM; | |
88 | ||
c6f224dc | 89 | s->unit = unit; |
3ff7e8f0 | 90 | s->direction = dir; |
31ef9134 CL |
91 | s->flags = flags; |
92 | s->context = ERR_PTR(-1); | |
93 | mutex_init(&s->mutex); | |
76fb8789 | 94 | tasklet_init(&s->period_tasklet, pcm_period_tasklet, (unsigned long)s); |
ec00f5e4 | 95 | s->packet_index = 0; |
31ef9134 | 96 | |
7b3b0d85 TS |
97 | init_waitqueue_head(&s->callback_wait); |
98 | s->callbacked = false; | |
7b3b0d85 | 99 | |
5955815e | 100 | s->fmt = fmt; |
9a738ad1 | 101 | s->process_ctx_payloads = process_ctx_payloads; |
414ba022 | 102 | |
3baf3053 TS |
103 | if (dir == AMDTP_OUT_STREAM) |
104 | s->ctx_data.rx.syt_override = -1; | |
105 | ||
31ef9134 CL |
106 | return 0; |
107 | } | |
be4a2894 | 108 | EXPORT_SYMBOL(amdtp_stream_init); |
31ef9134 CL |
109 | |
110 | /** | |
be4a2894 TS |
111 | * amdtp_stream_destroy - free stream resources |
112 | * @s: the AMDTP stream to destroy | |
31ef9134 | 113 | */ |
be4a2894 | 114 | void amdtp_stream_destroy(struct amdtp_stream *s) |
31ef9134 | 115 | { |
44c376b9 TS |
116 | /* Not initialized. */ |
117 | if (s->protocol == NULL) | |
118 | return; | |
119 | ||
be4a2894 | 120 | WARN_ON(amdtp_stream_running(s)); |
df075fee | 121 | kfree(s->protocol); |
31ef9134 | 122 | mutex_destroy(&s->mutex); |
31ef9134 | 123 | } |
be4a2894 | 124 | EXPORT_SYMBOL(amdtp_stream_destroy); |
31ef9134 | 125 | |
c5280e99 | 126 | const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = { |
a7304e3b CL |
127 | [CIP_SFC_32000] = 8, |
128 | [CIP_SFC_44100] = 8, | |
129 | [CIP_SFC_48000] = 8, | |
130 | [CIP_SFC_88200] = 16, | |
131 | [CIP_SFC_96000] = 16, | |
132 | [CIP_SFC_176400] = 32, | |
133 | [CIP_SFC_192000] = 32, | |
134 | }; | |
135 | EXPORT_SYMBOL(amdtp_syt_intervals); | |
136 | ||
f9503a68 | 137 | const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = { |
1017abed TS |
138 | [CIP_SFC_32000] = 32000, |
139 | [CIP_SFC_44100] = 44100, | |
140 | [CIP_SFC_48000] = 48000, | |
141 | [CIP_SFC_88200] = 88200, | |
142 | [CIP_SFC_96000] = 96000, | |
143 | [CIP_SFC_176400] = 176400, | |
144 | [CIP_SFC_192000] = 192000, | |
145 | }; | |
146 | EXPORT_SYMBOL(amdtp_rate_table); | |
147 | ||
59502295 TS |
148 | static int apply_constraint_to_size(struct snd_pcm_hw_params *params, |
149 | struct snd_pcm_hw_rule *rule) | |
150 | { | |
151 | struct snd_interval *s = hw_param_interval(params, rule->var); | |
152 | const struct snd_interval *r = | |
153 | hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE); | |
826b5de9 TS |
154 | struct snd_interval t = {0}; |
155 | unsigned int step = 0; | |
59502295 TS |
156 | int i; |
157 | ||
158 | for (i = 0; i < CIP_SFC_COUNT; ++i) { | |
826b5de9 TS |
159 | if (snd_interval_test(r, amdtp_rate_table[i])) |
160 | step = max(step, amdtp_syt_intervals[i]); | |
59502295 TS |
161 | } |
162 | ||
826b5de9 TS |
163 | t.min = roundup(s->min, step); |
164 | t.max = rounddown(s->max, step); | |
165 | t.integer = 1; | |
59502295 TS |
166 | |
167 | return snd_interval_refine(s, &t); | |
168 | } | |
169 | ||
7b2d99fa TS |
170 | /** |
171 | * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream | |
172 | * @s: the AMDTP stream, which must be initialized. | |
173 | * @runtime: the PCM substream runtime | |
174 | */ | |
175 | int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s, | |
176 | struct snd_pcm_runtime *runtime) | |
177 | { | |
55799c5a | 178 | struct snd_pcm_hardware *hw = &runtime->hw; |
7b2d99fa TS |
179 | int err; |
180 | ||
55799c5a TS |
181 | hw->info = SNDRV_PCM_INFO_BATCH | |
182 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
183 | SNDRV_PCM_INFO_INTERLEAVED | | |
184 | SNDRV_PCM_INFO_JOINT_DUPLEX | | |
185 | SNDRV_PCM_INFO_MMAP | | |
186 | SNDRV_PCM_INFO_MMAP_VALID; | |
187 | ||
188 | /* SNDRV_PCM_INFO_BATCH */ | |
189 | hw->periods_min = 2; | |
190 | hw->periods_max = UINT_MAX; | |
191 | ||
192 | /* bytes for a frame */ | |
193 | hw->period_bytes_min = 4 * hw->channels_max; | |
194 | ||
195 | /* Just to prevent from allocating much pages. */ | |
196 | hw->period_bytes_max = hw->period_bytes_min * 2048; | |
197 | hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min; | |
198 | ||
7b2d99fa TS |
199 | /* |
200 | * Currently firewire-lib processes 16 packets in one software | |
201 | * interrupt callback. This equals to 2msec but actually the | |
202 | * interval of the interrupts has a jitter. | |
203 | * Additionally, even if adding a constraint to fit period size to | |
204 | * 2msec, actual calculated frames per period doesn't equal to 2msec, | |
205 | * depending on sampling rate. | |
206 | * Anyway, the interval to call snd_pcm_period_elapsed() cannot 2msec. | |
207 | * Here let us use 5msec for safe period interrupt. | |
208 | */ | |
209 | err = snd_pcm_hw_constraint_minmax(runtime, | |
210 | SNDRV_PCM_HW_PARAM_PERIOD_TIME, | |
211 | 5000, UINT_MAX); | |
212 | if (err < 0) | |
213 | goto end; | |
214 | ||
215 | /* Non-Blocking stream has no more constraints */ | |
216 | if (!(s->flags & CIP_BLOCKING)) | |
217 | goto end; | |
218 | ||
219 | /* | |
220 | * One AMDTP packet can include some frames. In blocking mode, the | |
221 | * number equals to SYT_INTERVAL. So the number is 8, 16 or 32, | |
222 | * depending on its sampling rate. For accurate period interrupt, it's | |
ce991981 | 223 | * preferrable to align period/buffer sizes to current SYT_INTERVAL. |
7b2d99fa | 224 | */ |
59502295 TS |
225 | err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, |
226 | apply_constraint_to_size, NULL, | |
826b5de9 | 227 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, |
59502295 TS |
228 | SNDRV_PCM_HW_PARAM_RATE, -1); |
229 | if (err < 0) | |
230 | goto end; | |
59502295 TS |
231 | err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, |
232 | apply_constraint_to_size, NULL, | |
826b5de9 | 233 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, |
59502295 TS |
234 | SNDRV_PCM_HW_PARAM_RATE, -1); |
235 | if (err < 0) | |
236 | goto end; | |
7b2d99fa TS |
237 | end: |
238 | return err; | |
239 | } | |
240 | EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints); | |
241 | ||
31ef9134 | 242 | /** |
be4a2894 TS |
243 | * amdtp_stream_set_parameters - set stream parameters |
244 | * @s: the AMDTP stream to configure | |
31ef9134 | 245 | * @rate: the sample rate |
df075fee | 246 | * @data_block_quadlets: the size of a data block in quadlet unit |
31ef9134 | 247 | * |
a7304e3b | 248 | * The parameters must be set before the stream is started, and must not be |
31ef9134 CL |
249 | * changed while the stream is running. |
250 | */ | |
df075fee TS |
251 | int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate, |
252 | unsigned int data_block_quadlets) | |
31ef9134 | 253 | { |
df075fee | 254 | unsigned int sfc; |
31ef9134 | 255 | |
547e631c | 256 | for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) { |
1017abed | 257 | if (amdtp_rate_table[sfc] == rate) |
547e631c TS |
258 | break; |
259 | } | |
260 | if (sfc == ARRAY_SIZE(amdtp_rate_table)) | |
261 | return -EINVAL; | |
e84d15f6 | 262 | |
e84d15f6 | 263 | s->sfc = sfc; |
df075fee | 264 | s->data_block_quadlets = data_block_quadlets; |
a7304e3b | 265 | s->syt_interval = amdtp_syt_intervals[sfc]; |
e84d15f6 | 266 | |
d3d10a4a TS |
267 | // default buffering in the device. |
268 | if (s->direction == AMDTP_OUT_STREAM) { | |
269 | s->ctx_data.rx.transfer_delay = | |
270 | TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE; | |
271 | ||
272 | if (s->flags & CIP_BLOCKING) { | |
273 | // additional buffering needed to adjust for no-data | |
274 | // packets. | |
275 | s->ctx_data.rx.transfer_delay += | |
276 | TICKS_PER_SECOND * s->syt_interval / rate; | |
277 | } | |
278 | } | |
77d2a8a4 | 279 | |
547e631c | 280 | return 0; |
31ef9134 | 281 | } |
be4a2894 | 282 | EXPORT_SYMBOL(amdtp_stream_set_parameters); |
31ef9134 CL |
283 | |
284 | /** | |
be4a2894 TS |
285 | * amdtp_stream_get_max_payload - get the stream's packet size |
286 | * @s: the AMDTP stream | |
31ef9134 CL |
287 | * |
288 | * This function must not be called before the stream has been configured | |
be4a2894 | 289 | * with amdtp_stream_set_parameters(). |
31ef9134 | 290 | */ |
be4a2894 | 291 | unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s) |
31ef9134 | 292 | { |
a2064710 | 293 | unsigned int multiplier = 1; |
07ea238c | 294 | unsigned int cip_header_size = 0; |
a2064710 TS |
295 | |
296 | if (s->flags & CIP_JUMBO_PAYLOAD) | |
297 | multiplier = 5; | |
3b196c39 | 298 | if (!(s->flags & CIP_NO_HEADER)) |
07ea238c | 299 | cip_header_size = sizeof(__be32) * 2; |
a2064710 | 300 | |
07ea238c TS |
301 | return cip_header_size + |
302 | s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier; | |
31ef9134 | 303 | } |
be4a2894 | 304 | EXPORT_SYMBOL(amdtp_stream_get_max_payload); |
31ef9134 | 305 | |
76fb8789 | 306 | /** |
be4a2894 TS |
307 | * amdtp_stream_pcm_prepare - prepare PCM device for running |
308 | * @s: the AMDTP stream | |
76fb8789 CL |
309 | * |
310 | * This function should be called from the PCM device's .prepare callback. | |
311 | */ | |
be4a2894 | 312 | void amdtp_stream_pcm_prepare(struct amdtp_stream *s) |
76fb8789 CL |
313 | { |
314 | tasklet_kill(&s->period_tasklet); | |
315 | s->pcm_buffer_pointer = 0; | |
316 | s->pcm_period_pointer = 0; | |
317 | } | |
be4a2894 | 318 | EXPORT_SYMBOL(amdtp_stream_pcm_prepare); |
76fb8789 | 319 | |
875be091 TS |
320 | static unsigned int calculate_data_blocks(struct amdtp_stream *s, |
321 | unsigned int syt) | |
31ef9134 CL |
322 | { |
323 | unsigned int phase, data_blocks; | |
324 | ||
875be091 TS |
325 | /* Blocking mode. */ |
326 | if (s->flags & CIP_BLOCKING) { | |
327 | /* This module generate empty packet for 'no data'. */ | |
328 | if (syt == CIP_SYT_NO_INFO) | |
329 | data_blocks = 0; | |
330 | else | |
331 | data_blocks = s->syt_interval; | |
332 | /* Non-blocking mode. */ | |
31ef9134 | 333 | } else { |
875be091 | 334 | if (!cip_sfc_is_base_44100(s->sfc)) { |
d3d10a4a TS |
335 | // Sample_rate / 8000 is an integer, and precomputed. |
336 | data_blocks = s->ctx_data.rx.data_block_state; | |
875be091 | 337 | } else { |
d3d10a4a | 338 | phase = s->ctx_data.rx.data_block_state; |
31ef9134 CL |
339 | |
340 | /* | |
341 | * This calculates the number of data blocks per packet so that | |
342 | * 1) the overall rate is correct and exactly synchronized to | |
343 | * the bus clock, and | |
344 | * 2) packets with a rounded-up number of blocks occur as early | |
345 | * as possible in the sequence (to prevent underruns of the | |
346 | * device's buffer). | |
347 | */ | |
875be091 TS |
348 | if (s->sfc == CIP_SFC_44100) |
349 | /* 6 6 5 6 5 6 5 ... */ | |
350 | data_blocks = 5 + ((phase & 1) ^ | |
351 | (phase == 0 || phase >= 40)); | |
352 | else | |
353 | /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */ | |
354 | data_blocks = 11 * (s->sfc >> 1) + (phase == 0); | |
355 | if (++phase >= (80 >> (s->sfc >> 1))) | |
356 | phase = 0; | |
d3d10a4a | 357 | s->ctx_data.rx.data_block_state = phase; |
875be091 | 358 | } |
31ef9134 CL |
359 | } |
360 | ||
361 | return data_blocks; | |
362 | } | |
363 | ||
be4a2894 | 364 | static unsigned int calculate_syt(struct amdtp_stream *s, |
31ef9134 CL |
365 | unsigned int cycle) |
366 | { | |
367 | unsigned int syt_offset, phase, index, syt; | |
368 | ||
d3d10a4a | 369 | if (s->ctx_data.rx.last_syt_offset < TICKS_PER_CYCLE) { |
31ef9134 | 370 | if (!cip_sfc_is_base_44100(s->sfc)) |
d3d10a4a TS |
371 | syt_offset = s->ctx_data.rx.last_syt_offset + |
372 | s->ctx_data.rx.syt_offset_state; | |
31ef9134 CL |
373 | else { |
374 | /* | |
375 | * The time, in ticks, of the n'th SYT_INTERVAL sample is: | |
376 | * n * SYT_INTERVAL * 24576000 / sample_rate | |
377 | * Modulo TICKS_PER_CYCLE, the difference between successive | |
378 | * elements is about 1386.23. Rounding the results of this | |
379 | * formula to the SYT precision results in a sequence of | |
380 | * differences that begins with: | |
381 | * 1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ... | |
382 | * This code generates _exactly_ the same sequence. | |
383 | */ | |
d3d10a4a | 384 | phase = s->ctx_data.rx.syt_offset_state; |
31ef9134 | 385 | index = phase % 13; |
d3d10a4a | 386 | syt_offset = s->ctx_data.rx.last_syt_offset; |
31ef9134 CL |
387 | syt_offset += 1386 + ((index && !(index & 3)) || |
388 | phase == 146); | |
389 | if (++phase >= 147) | |
390 | phase = 0; | |
d3d10a4a | 391 | s->ctx_data.rx.syt_offset_state = phase; |
31ef9134 CL |
392 | } |
393 | } else | |
d3d10a4a TS |
394 | syt_offset = s->ctx_data.rx.last_syt_offset - TICKS_PER_CYCLE; |
395 | s->ctx_data.rx.last_syt_offset = syt_offset; | |
31ef9134 | 396 | |
be454366 | 397 | if (syt_offset < TICKS_PER_CYCLE) { |
d3d10a4a | 398 | syt_offset += s->ctx_data.rx.transfer_delay; |
be454366 CL |
399 | syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12; |
400 | syt += syt_offset % TICKS_PER_CYCLE; | |
31ef9134 | 401 | |
b445db44 | 402 | return syt & CIP_SYT_MASK; |
be454366 | 403 | } else { |
b445db44 | 404 | return CIP_SYT_NO_INFO; |
be454366 | 405 | } |
31ef9134 CL |
406 | } |
407 | ||
4b7da117 TS |
408 | static void update_pcm_pointers(struct amdtp_stream *s, |
409 | struct snd_pcm_substream *pcm, | |
410 | unsigned int frames) | |
65845f29 TS |
411 | { |
412 | unsigned int ptr; | |
413 | ||
4b7da117 TS |
414 | ptr = s->pcm_buffer_pointer + frames; |
415 | if (ptr >= pcm->runtime->buffer_size) | |
416 | ptr -= pcm->runtime->buffer_size; | |
6aa7de05 | 417 | WRITE_ONCE(s->pcm_buffer_pointer, ptr); |
4b7da117 TS |
418 | |
419 | s->pcm_period_pointer += frames; | |
420 | if (s->pcm_period_pointer >= pcm->runtime->period_size) { | |
421 | s->pcm_period_pointer -= pcm->runtime->period_size; | |
4b7da117 TS |
422 | tasklet_hi_schedule(&s->period_tasklet); |
423 | } | |
424 | } | |
425 | ||
426 | static void pcm_period_tasklet(unsigned long data) | |
427 | { | |
428 | struct amdtp_stream *s = (void *)data; | |
6aa7de05 | 429 | struct snd_pcm_substream *pcm = READ_ONCE(s->pcm); |
4b7da117 TS |
430 | |
431 | if (pcm) | |
432 | snd_pcm_period_elapsed(pcm); | |
433 | } | |
434 | ||
e229853d TS |
435 | static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params, |
436 | bool sched_irq) | |
4b7da117 | 437 | { |
6007bf54 | 438 | int err; |
df9160b9 | 439 | |
e229853d | 440 | params->interrupt = sched_irq; |
6007bf54 TS |
441 | params->tag = s->tag; |
442 | params->sy = 0; | |
df9160b9 | 443 | |
6007bf54 | 444 | err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer, |
4b7da117 TS |
445 | s->buffer.packets[s->packet_index].offset); |
446 | if (err < 0) { | |
447 | dev_err(&s->unit->device, "queueing error: %d\n", err); | |
448 | goto end; | |
449 | } | |
450 | ||
a0e02331 | 451 | if (++s->packet_index >= s->queue_size) |
4b7da117 TS |
452 | s->packet_index = 0; |
453 | end: | |
454 | return err; | |
455 | } | |
456 | ||
457 | static inline int queue_out_packet(struct amdtp_stream *s, | |
e229853d | 458 | struct fw_iso_packet *params, bool sched_irq) |
4b7da117 | 459 | { |
b18f0cfa TS |
460 | params->skip = |
461 | !!(params->header_length == 0 && params->payload_length == 0); | |
e229853d | 462 | return queue_packet(s, params, sched_irq); |
4b7da117 TS |
463 | } |
464 | ||
6007bf54 | 465 | static inline int queue_in_packet(struct amdtp_stream *s, |
e229853d | 466 | struct fw_iso_packet *params, bool sched_irq) |
2b3fc456 | 467 | { |
6007bf54 TS |
468 | // Queue one packet for IR context. |
469 | params->header_length = s->ctx_data.tx.ctx_header_size; | |
470 | params->payload_length = s->ctx_data.tx.max_ctx_payload_length; | |
471 | params->skip = false; | |
e229853d | 472 | return queue_packet(s, params, sched_irq); |
2b3fc456 TS |
473 | } |
474 | ||
252219c7 | 475 | static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2], |
860d798c | 476 | unsigned int data_block_counter, unsigned int syt) |
252219c7 TS |
477 | { |
478 | cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) | | |
479 | (s->data_block_quadlets << CIP_DBS_SHIFT) | | |
480 | ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) | | |
860d798c | 481 | data_block_counter); |
252219c7 TS |
482 | cip_header[1] = cpu_to_be32(CIP_EOH | |
483 | ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) | | |
484 | ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) | | |
485 | (syt & CIP_SYT_MASK)); | |
486 | } | |
487 | ||
6bc1a269 TS |
488 | static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle, |
489 | struct fw_iso_packet *params, | |
860d798c TS |
490 | unsigned int data_blocks, |
491 | unsigned int data_block_counter, | |
492 | unsigned int syt, unsigned int index) | |
31ef9134 | 493 | { |
0ebf3ceb | 494 | unsigned int payload_length; |
16be4589 | 495 | __be32 *cip_header; |
20e44577 | 496 | |
0ebf3ceb TS |
497 | payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets; |
498 | params->payload_length = payload_length; | |
499 | ||
b18f0cfa | 500 | if (!(s->flags & CIP_NO_HEADER)) { |
6bc1a269 | 501 | cip_header = (__be32 *)params->header; |
860d798c | 502 | generate_cip_header(s, cip_header, data_block_counter, syt); |
6bc1a269 | 503 | params->header_length = 2 * sizeof(__be32); |
0ebf3ceb | 504 | payload_length += params->header_length; |
b18f0cfa TS |
505 | } else { |
506 | cip_header = NULL; | |
507 | } | |
31ef9134 | 508 | |
213fa989 | 509 | trace_amdtp_packet(s, cycle, cip_header, payload_length, data_blocks, |
860d798c | 510 | data_block_counter, index); |
3b196c39 TS |
511 | } |
512 | ||
e335425b TS |
513 | static int check_cip_header(struct amdtp_stream *s, const __be32 *buf, |
514 | unsigned int payload_length, | |
a35463d1 TS |
515 | unsigned int *data_blocks, |
516 | unsigned int *data_block_counter, unsigned int *syt) | |
2b3fc456 TS |
517 | { |
518 | u32 cip_header[2]; | |
e335425b TS |
519 | unsigned int sph; |
520 | unsigned int fmt; | |
521 | unsigned int fdf; | |
a35463d1 | 522 | unsigned int dbc; |
c8bdf49b | 523 | bool lost; |
2b3fc456 | 524 | |
e335425b TS |
525 | cip_header[0] = be32_to_cpu(buf[0]); |
526 | cip_header[1] = be32_to_cpu(buf[1]); | |
2b3fc456 TS |
527 | |
528 | /* | |
529 | * This module supports 'Two-quadlet CIP header with SYT field'. | |
77d2a8a4 | 530 | * For convenience, also check FMT field is AM824 or not. |
2b3fc456 | 531 | */ |
2128f78f TS |
532 | if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) || |
533 | ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) && | |
534 | (!(s->flags & CIP_HEADER_WITHOUT_EOH))) { | |
2b3fc456 TS |
535 | dev_info_ratelimited(&s->unit->device, |
536 | "Invalid CIP header for AMDTP: %08X:%08X\n", | |
537 | cip_header[0], cip_header[1]); | |
e335425b | 538 | return -EAGAIN; |
2b3fc456 TS |
539 | } |
540 | ||
414ba022 | 541 | /* Check valid protocol or not. */ |
9863874f | 542 | sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT; |
414ba022 | 543 | fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT; |
9863874f | 544 | if (sph != s->sph || fmt != s->fmt) { |
2a7e1713 TS |
545 | dev_info_ratelimited(&s->unit->device, |
546 | "Detect unexpected protocol: %08x %08x\n", | |
547 | cip_header[0], cip_header[1]); | |
e335425b | 548 | return -EAGAIN; |
414ba022 TS |
549 | } |
550 | ||
2b3fc456 | 551 | /* Calculate data blocks */ |
414ba022 | 552 | fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT; |
e335425b | 553 | if (payload_length < sizeof(__be32) * 2 || |
414ba022 | 554 | (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) { |
e335425b | 555 | *data_blocks = 0; |
2b3fc456 | 556 | } else { |
e335425b TS |
557 | unsigned int data_block_quadlets = |
558 | (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT; | |
2b3fc456 TS |
559 | /* avoid division by zero */ |
560 | if (data_block_quadlets == 0) { | |
12e0f438 | 561 | dev_err(&s->unit->device, |
2b3fc456 TS |
562 | "Detect invalid value in dbs field: %08X\n", |
563 | cip_header[0]); | |
a9007054 | 564 | return -EPROTO; |
2b3fc456 | 565 | } |
69702239 TS |
566 | if (s->flags & CIP_WRONG_DBS) |
567 | data_block_quadlets = s->data_block_quadlets; | |
2b3fc456 | 568 | |
e335425b | 569 | *data_blocks = (payload_length / sizeof(__be32) - 2) / |
ff0fb5aa | 570 | data_block_quadlets; |
2b3fc456 TS |
571 | } |
572 | ||
573 | /* Check data block counter continuity */ | |
a35463d1 | 574 | dbc = cip_header[0] & CIP_DBC_MASK; |
e335425b | 575 | if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) && |
a35463d1 TS |
576 | *data_block_counter != UINT_MAX) |
577 | dbc = *data_block_counter; | |
9d59124c | 578 | |
a35463d1 TS |
579 | if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) || |
580 | *data_block_counter == UINT_MAX) { | |
b84b1a27 TS |
581 | lost = false; |
582 | } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) { | |
a35463d1 | 583 | lost = dbc != *data_block_counter; |
d9cd0065 | 584 | } else { |
e335425b TS |
585 | unsigned int dbc_interval; |
586 | ||
587 | if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0) | |
d3d10a4a | 588 | dbc_interval = s->ctx_data.tx.dbc_interval; |
d9cd0065 | 589 | else |
e335425b | 590 | dbc_interval = *data_blocks; |
d9cd0065 | 591 | |
a35463d1 | 592 | lost = dbc != ((*data_block_counter + dbc_interval) & 0xff); |
d9cd0065 | 593 | } |
c8bdf49b TS |
594 | |
595 | if (lost) { | |
12e0f438 TS |
596 | dev_err(&s->unit->device, |
597 | "Detect discontinuity of CIP: %02X %02X\n", | |
a35463d1 | 598 | *data_block_counter, dbc); |
6fc6b9ce | 599 | return -EIO; |
2b3fc456 TS |
600 | } |
601 | ||
753e7179 TS |
602 | *data_block_counter = dbc; |
603 | ||
e335425b | 604 | *syt = cip_header[1] & CIP_SYT_MASK; |
2b3fc456 | 605 | |
e335425b TS |
606 | return 0; |
607 | } | |
608 | ||
98e3e43b TS |
609 | static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle, |
610 | const __be32 *ctx_header, | |
611 | unsigned int *payload_length, | |
a35463d1 TS |
612 | unsigned int *data_blocks, |
613 | unsigned int *data_block_counter, | |
614 | unsigned int *syt, unsigned int index) | |
e335425b | 615 | { |
f11453c7 | 616 | const __be32 *cip_header; |
e335425b TS |
617 | int err; |
618 | ||
98e3e43b TS |
619 | *payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT; |
620 | if (*payload_length > s->ctx_data.tx.ctx_header_size + | |
f11453c7 | 621 | s->ctx_data.tx.max_ctx_payload_length) { |
e335425b TS |
622 | dev_err(&s->unit->device, |
623 | "Detect jumbo payload: %04x %04x\n", | |
98e3e43b | 624 | *payload_length, s->ctx_data.tx.max_ctx_payload_length); |
e335425b TS |
625 | return -EIO; |
626 | } | |
627 | ||
947b437e | 628 | if (!(s->flags & CIP_NO_HEADER)) { |
98e3e43b TS |
629 | cip_header = ctx_header + 2; |
630 | err = check_cip_header(s, cip_header, *payload_length, | |
a35463d1 | 631 | data_blocks, data_block_counter, syt); |
b8b0e24c TS |
632 | if (err < 0) |
633 | return err; | |
947b437e TS |
634 | } else { |
635 | cip_header = NULL; | |
76864868 | 636 | err = 0; |
98e3e43b TS |
637 | *data_blocks = *payload_length / sizeof(__be32) / |
638 | s->data_block_quadlets; | |
639 | *syt = 0; | |
7fbf9096 | 640 | |
a35463d1 TS |
641 | if (*data_block_counter == UINT_MAX) |
642 | *data_block_counter = 0; | |
e335425b TS |
643 | } |
644 | ||
98e3e43b | 645 | trace_amdtp_packet(s, cycle, cip_header, *payload_length, *data_blocks, |
a35463d1 | 646 | *data_block_counter, index); |
e335425b | 647 | |
76864868 | 648 | return err; |
2b3fc456 TS |
649 | } |
650 | ||
26cd1e58 TS |
651 | // In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On |
652 | // the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent | |
653 | // it. Thus, via Linux firewire subsystem, we can get the 3 bits for second. | |
654 | static inline u32 compute_cycle_count(__be32 ctx_header_tstamp) | |
73fc7f08 | 655 | { |
26cd1e58 | 656 | u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK; |
73fc7f08 TS |
657 | return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff); |
658 | } | |
659 | ||
660 | static inline u32 increment_cycle_count(u32 cycle, unsigned int addend) | |
661 | { | |
662 | cycle += addend; | |
663 | if (cycle >= 8 * CYCLES_PER_SECOND) | |
664 | cycle -= 8 * CYCLES_PER_SECOND; | |
665 | return cycle; | |
666 | } | |
667 | ||
26cd1e58 | 668 | // Align to actual cycle count for the packet which is going to be scheduled. |
a0e02331 TS |
669 | // This module queued the same number of isochronous cycle as the size of queue |
670 | // to kip isochronous cycle, therefore it's OK to just increment the cycle by | |
671 | // the size of queue for scheduled cycle. | |
672 | static inline u32 compute_it_cycle(const __be32 ctx_header_tstamp, | |
673 | unsigned int queue_size) | |
26cd1e58 TS |
674 | { |
675 | u32 cycle = compute_cycle_count(ctx_header_tstamp); | |
a0e02331 | 676 | return increment_cycle_count(cycle, queue_size); |
26cd1e58 TS |
677 | } |
678 | ||
753e7179 TS |
679 | static int generate_device_pkt_descs(struct amdtp_stream *s, |
680 | struct pkt_desc *descs, | |
681 | const __be32 *ctx_header, | |
682 | unsigned int packets) | |
683 | { | |
684 | unsigned int dbc = s->data_block_counter; | |
685 | int i; | |
686 | int err; | |
687 | ||
688 | for (i = 0; i < packets; ++i) { | |
689 | struct pkt_desc *desc = descs + i; | |
a0e02331 | 690 | unsigned int index = (s->packet_index + i) % s->queue_size; |
753e7179 TS |
691 | unsigned int cycle; |
692 | unsigned int payload_length; | |
693 | unsigned int data_blocks; | |
694 | unsigned int syt; | |
695 | ||
696 | cycle = compute_cycle_count(ctx_header[1]); | |
697 | ||
698 | err = parse_ir_ctx_header(s, cycle, ctx_header, &payload_length, | |
699 | &data_blocks, &dbc, &syt, i); | |
700 | if (err < 0) | |
701 | return err; | |
702 | ||
703 | desc->cycle = cycle; | |
704 | desc->syt = syt; | |
705 | desc->data_blocks = data_blocks; | |
706 | desc->data_block_counter = dbc; | |
707 | desc->ctx_payload = s->buffer.packets[index].buffer; | |
708 | ||
709 | if (!(s->flags & CIP_DBC_IS_END_EVENT)) | |
710 | dbc = (dbc + desc->data_blocks) & 0xff; | |
711 | ||
712 | ctx_header += | |
713 | s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header); | |
714 | } | |
715 | ||
716 | s->data_block_counter = dbc; | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
f4f6ae7b TS |
721 | static void generate_ideal_pkt_descs(struct amdtp_stream *s, |
722 | struct pkt_desc *descs, | |
723 | const __be32 *ctx_header, | |
724 | unsigned int packets) | |
725 | { | |
726 | unsigned int dbc = s->data_block_counter; | |
727 | int i; | |
728 | ||
729 | for (i = 0; i < packets; ++i) { | |
730 | struct pkt_desc *desc = descs + i; | |
a0e02331 | 731 | unsigned int index = (s->packet_index + i) % s->queue_size; |
f4f6ae7b | 732 | |
a0e02331 | 733 | desc->cycle = compute_it_cycle(*ctx_header, s->queue_size); |
f4f6ae7b TS |
734 | desc->syt = calculate_syt(s, desc->cycle); |
735 | desc->data_blocks = calculate_data_blocks(s, desc->syt); | |
736 | ||
737 | if (s->flags & CIP_DBC_IS_END_EVENT) | |
738 | dbc = (dbc + desc->data_blocks) & 0xff; | |
739 | ||
740 | desc->data_block_counter = dbc; | |
741 | ||
742 | if (!(s->flags & CIP_DBC_IS_END_EVENT)) | |
743 | dbc = (dbc + desc->data_blocks) & 0xff; | |
744 | ||
745 | desc->ctx_payload = s->buffer.packets[index].buffer; | |
746 | ||
747 | ++ctx_header; | |
748 | } | |
749 | ||
750 | s->data_block_counter = dbc; | |
751 | } | |
752 | ||
fce9b013 TS |
753 | static inline void cancel_stream(struct amdtp_stream *s) |
754 | { | |
755 | s->packet_index = -1; | |
756 | if (in_interrupt()) | |
757 | amdtp_stream_pcm_abort(s); | |
758 | WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN); | |
759 | } | |
760 | ||
0f5cfcb2 TS |
761 | static void process_ctx_payloads(struct amdtp_stream *s, |
762 | const struct pkt_desc *descs, | |
763 | unsigned int packets) | |
31ef9134 | 764 | { |
9a738ad1 TS |
765 | struct snd_pcm_substream *pcm; |
766 | unsigned int pcm_frames; | |
5e2ece0f | 767 | |
9a738ad1 TS |
768 | pcm = READ_ONCE(s->pcm); |
769 | pcm_frames = s->process_ctx_payloads(s, descs, packets, pcm); | |
770 | if (pcm) | |
771 | update_pcm_pointers(s, pcm, pcm_frames); | |
0f5cfcb2 TS |
772 | } |
773 | ||
774 | static void out_stream_callback(struct fw_iso_context *context, u32 tstamp, | |
775 | size_t header_length, void *header, | |
776 | void *private_data) | |
777 | { | |
778 | struct amdtp_stream *s = private_data; | |
779 | const __be32 *ctx_header = header; | |
e229853d TS |
780 | unsigned int events_per_period = s->events_per_period; |
781 | unsigned int event_count = s->event_count; | |
a0e02331 | 782 | unsigned int packets; |
0f5cfcb2 TS |
783 | int i; |
784 | ||
785 | if (s->packet_index < 0) | |
786 | return; | |
787 | ||
a0e02331 TS |
788 | // Calculate the number of packets in buffer and check XRUN. |
789 | packets = header_length / sizeof(*ctx_header); | |
790 | ||
0f5cfcb2 TS |
791 | generate_ideal_pkt_descs(s, s->pkt_descs, ctx_header, packets); |
792 | ||
793 | process_ctx_payloads(s, s->pkt_descs, packets); | |
5e2ece0f TS |
794 | |
795 | for (i = 0; i < packets; ++i) { | |
796 | const struct pkt_desc *desc = s->pkt_descs + i; | |
f4f6ae7b | 797 | unsigned int syt; |
6bc1a269 TS |
798 | struct { |
799 | struct fw_iso_packet params; | |
800 | __be32 header[IT_PKT_HEADER_SIZE_CIP / sizeof(__be32)]; | |
801 | } template = { {0}, {0} }; | |
e229853d | 802 | bool sched_irq = false; |
31ef9134 | 803 | |
f4f6ae7b TS |
804 | if (s->ctx_data.rx.syt_override < 0) |
805 | syt = desc->syt; | |
806 | else | |
3baf3053 TS |
807 | syt = s->ctx_data.rx.syt_override; |
808 | ||
f4f6ae7b TS |
809 | build_it_pkt_header(s, desc->cycle, &template.params, |
810 | desc->data_blocks, desc->data_block_counter, | |
811 | syt, i); | |
6bc1a269 | 812 | |
e229853d TS |
813 | event_count += desc->data_blocks; |
814 | if (event_count >= events_per_period) { | |
815 | event_count -= events_per_period; | |
816 | sched_irq = true; | |
817 | } | |
818 | ||
819 | if (queue_out_packet(s, &template.params, sched_irq) < 0) { | |
fce9b013 | 820 | cancel_stream(s); |
a4103bd7 TS |
821 | return; |
822 | } | |
ccccad86 | 823 | } |
a4103bd7 | 824 | |
e229853d TS |
825 | s->event_count = event_count; |
826 | ||
13882a82 | 827 | fw_iso_context_queue_flush(s->context); |
31ef9134 CL |
828 | } |
829 | ||
73fc7f08 | 830 | static void in_stream_callback(struct fw_iso_context *context, u32 tstamp, |
2b3fc456 TS |
831 | size_t header_length, void *header, |
832 | void *private_data) | |
833 | { | |
834 | struct amdtp_stream *s = private_data; | |
cc4f8e91 | 835 | __be32 *ctx_header = header; |
e229853d TS |
836 | unsigned int events_per_period = s->events_per_period; |
837 | unsigned int event_count = s->event_count; | |
838 | unsigned int packets; | |
753e7179 TS |
839 | int i; |
840 | int err; | |
2b3fc456 | 841 | |
a4103bd7 TS |
842 | if (s->packet_index < 0) |
843 | return; | |
844 | ||
a0e02331 | 845 | // Calculate the number of packets in buffer and check XRUN. |
d3d10a4a | 846 | packets = header_length / s->ctx_data.tx.ctx_header_size; |
f90e2ded | 847 | |
753e7179 TS |
848 | err = generate_device_pkt_descs(s, s->pkt_descs, ctx_header, packets); |
849 | if (err < 0) { | |
850 | if (err != -EAGAIN) { | |
851 | cancel_stream(s); | |
852 | return; | |
853 | } | |
5e2ece0f | 854 | } else { |
0f5cfcb2 | 855 | process_ctx_payloads(s, s->pkt_descs, packets); |
5e2ece0f TS |
856 | } |
857 | ||
858 | for (i = 0; i < packets; ++i) { | |
e229853d | 859 | const struct pkt_desc *desc = s->pkt_descs + i; |
5e2ece0f | 860 | struct fw_iso_packet params = {0}; |
e229853d TS |
861 | bool sched_irq = false; |
862 | ||
863 | if (err >= 0) { | |
864 | event_count += desc->data_blocks; | |
865 | if (event_count >= events_per_period) { | |
866 | event_count -= events_per_period; | |
867 | sched_irq = true; | |
868 | } | |
869 | } else { | |
870 | sched_irq = | |
871 | !((s->packet_index + 1) % s->idle_irq_interval); | |
872 | } | |
2b3fc456 | 873 | |
e229853d | 874 | if (queue_in_packet(s, ¶ms, sched_irq) < 0) { |
753e7179 TS |
875 | cancel_stream(s); |
876 | return; | |
877 | } | |
7b3b0d85 TS |
878 | } |
879 | ||
e229853d TS |
880 | s->event_count = event_count; |
881 | ||
2b3fc456 TS |
882 | fw_iso_context_queue_flush(s->context); |
883 | } | |
884 | ||
7b3b0d85 TS |
885 | /* this is executed one time */ |
886 | static void amdtp_stream_first_callback(struct fw_iso_context *context, | |
73fc7f08 | 887 | u32 tstamp, size_t header_length, |
7b3b0d85 TS |
888 | void *header, void *private_data) |
889 | { | |
890 | struct amdtp_stream *s = private_data; | |
26cd1e58 | 891 | const __be32 *ctx_header = header; |
a04513f8 | 892 | u32 cycle; |
7b3b0d85 TS |
893 | |
894 | /* | |
895 | * For in-stream, first packet has come. | |
896 | * For out-stream, prepared to transmit first packet | |
897 | */ | |
898 | s->callbacked = true; | |
899 | wake_up(&s->callback_wait); | |
900 | ||
a04513f8 | 901 | if (s->direction == AMDTP_IN_STREAM) { |
26cd1e58 | 902 | cycle = compute_cycle_count(ctx_header[1]); |
cc4f8e91 | 903 | |
7b3b0d85 | 904 | context->callback.sc = in_stream_callback; |
a04513f8 | 905 | } else { |
a0e02331 | 906 | cycle = compute_it_cycle(*ctx_header, s->queue_size); |
26cd1e58 | 907 | |
7b3b0d85 | 908 | context->callback.sc = out_stream_callback; |
a04513f8 TS |
909 | } |
910 | ||
911 | s->start_cycle = cycle; | |
7b3b0d85 | 912 | |
73fc7f08 | 913 | context->callback.sc(context, tstamp, header_length, header, s); |
7b3b0d85 TS |
914 | } |
915 | ||
31ef9134 | 916 | /** |
be4a2894 TS |
917 | * amdtp_stream_start - start transferring packets |
918 | * @s: the AMDTP stream to start | |
31ef9134 CL |
919 | * @channel: the isochronous channel on the bus |
920 | * @speed: firewire speed code | |
921 | * | |
922 | * The stream cannot be started until it has been configured with | |
be4a2894 TS |
923 | * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI |
924 | * device can be started. | |
31ef9134 | 925 | */ |
a0e02331 TS |
926 | static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed, |
927 | struct amdtp_domain *d) | |
31ef9134 CL |
928 | { |
929 | static const struct { | |
930 | unsigned int data_block; | |
931 | unsigned int syt_offset; | |
d3d10a4a | 932 | } *entry, initial_state[] = { |
31ef9134 CL |
933 | [CIP_SFC_32000] = { 4, 3072 }, |
934 | [CIP_SFC_48000] = { 6, 1024 }, | |
935 | [CIP_SFC_96000] = { 12, 1024 }, | |
936 | [CIP_SFC_192000] = { 24, 1024 }, | |
937 | [CIP_SFC_44100] = { 0, 67 }, | |
938 | [CIP_SFC_88200] = { 0, 67 }, | |
939 | [CIP_SFC_176400] = { 0, 67 }, | |
940 | }; | |
a0e02331 | 941 | unsigned int events_per_buffer = d->events_per_buffer; |
e229853d | 942 | unsigned int events_per_period = d->events_per_period; |
d3d10a4a | 943 | unsigned int ctx_header_size; |
f11453c7 | 944 | unsigned int max_ctx_payload_size; |
2b3fc456 | 945 | enum dma_data_direction dir; |
7ab56645 | 946 | int type, tag, err; |
31ef9134 CL |
947 | |
948 | mutex_lock(&s->mutex); | |
949 | ||
be4a2894 | 950 | if (WARN_ON(amdtp_stream_running(s) || |
4b7da117 | 951 | (s->data_block_quadlets < 1))) { |
31ef9134 CL |
952 | err = -EBADFD; |
953 | goto err_unlock; | |
954 | } | |
955 | ||
d3d10a4a | 956 | if (s->direction == AMDTP_IN_STREAM) { |
b6bc8123 | 957 | s->data_block_counter = UINT_MAX; |
d3d10a4a TS |
958 | } else { |
959 | entry = &initial_state[s->sfc]; | |
960 | ||
b6bc8123 | 961 | s->data_block_counter = 0; |
d3d10a4a TS |
962 | s->ctx_data.rx.data_block_state = entry->data_block; |
963 | s->ctx_data.rx.syt_offset_state = entry->syt_offset; | |
964 | s->ctx_data.rx.last_syt_offset = TICKS_PER_CYCLE; | |
965 | } | |
31ef9134 | 966 | |
2b3fc456 TS |
967 | /* initialize packet buffer */ |
968 | if (s->direction == AMDTP_IN_STREAM) { | |
969 | dir = DMA_FROM_DEVICE; | |
970 | type = FW_ISO_CONTEXT_RECEIVE; | |
f11453c7 TS |
971 | if (!(s->flags & CIP_NO_HEADER)) |
972 | ctx_header_size = IR_CTX_HEADER_SIZE_CIP; | |
973 | else | |
974 | ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP; | |
b18f0cfa TS |
975 | |
976 | max_ctx_payload_size = amdtp_stream_get_max_payload(s) - | |
977 | ctx_header_size; | |
2b3fc456 TS |
978 | } else { |
979 | dir = DMA_TO_DEVICE; | |
980 | type = FW_ISO_CONTEXT_TRANSMIT; | |
df9160b9 | 981 | ctx_header_size = 0; // No effect for IT context. |
f11453c7 | 982 | |
b18f0cfa TS |
983 | max_ctx_payload_size = amdtp_stream_get_max_payload(s); |
984 | if (!(s->flags & CIP_NO_HEADER)) | |
985 | max_ctx_payload_size -= IT_PKT_HEADER_SIZE_CIP; | |
986 | } | |
f11453c7 | 987 | |
e229853d TS |
988 | // This is a case that AMDTP streams in domain run just for MIDI |
989 | // substream. Use the number of events equivalent to 10 msec as | |
990 | // interval of hardware IRQ. | |
991 | if (events_per_period == 0) | |
992 | events_per_period = amdtp_rate_table[s->sfc] / 100; | |
a0e02331 | 993 | if (events_per_buffer == 0) |
e229853d | 994 | events_per_buffer = events_per_period * 3; |
a0e02331 | 995 | |
e229853d TS |
996 | s->idle_irq_interval = |
997 | DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period, | |
998 | amdtp_rate_table[s->sfc]); | |
a0e02331 TS |
999 | s->queue_size = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_buffer, |
1000 | amdtp_rate_table[s->sfc]); | |
e229853d TS |
1001 | s->events_per_period = events_per_period; |
1002 | s->event_count = 0; | |
a0e02331 TS |
1003 | |
1004 | err = iso_packets_buffer_init(&s->buffer, s->unit, s->queue_size, | |
f11453c7 | 1005 | max_ctx_payload_size, dir); |
31ef9134 CL |
1006 | if (err < 0) |
1007 | goto err_unlock; | |
1008 | ||
1009 | s->context = fw_iso_context_create(fw_parent_device(s->unit)->card, | |
d3d10a4a TS |
1010 | type, channel, speed, ctx_header_size, |
1011 | amdtp_stream_first_callback, s); | |
31ef9134 CL |
1012 | if (IS_ERR(s->context)) { |
1013 | err = PTR_ERR(s->context); | |
1014 | if (err == -EBUSY) | |
1015 | dev_err(&s->unit->device, | |
be4a2894 | 1016 | "no free stream on this controller\n"); |
31ef9134 CL |
1017 | goto err_buffer; |
1018 | } | |
1019 | ||
be4a2894 | 1020 | amdtp_stream_update(s); |
31ef9134 | 1021 | |
d3d10a4a | 1022 | if (s->direction == AMDTP_IN_STREAM) { |
f11453c7 | 1023 | s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size; |
d3d10a4a TS |
1024 | s->ctx_data.tx.ctx_header_size = ctx_header_size; |
1025 | } | |
52759c09 | 1026 | |
3b196c39 TS |
1027 | if (s->flags & CIP_NO_HEADER) |
1028 | s->tag = TAG_NO_CIP_HEADER; | |
1029 | else | |
1030 | s->tag = TAG_CIP; | |
1031 | ||
a0e02331 | 1032 | s->pkt_descs = kcalloc(s->queue_size, sizeof(*s->pkt_descs), |
04130cf8 TS |
1033 | GFP_KERNEL); |
1034 | if (!s->pkt_descs) { | |
1035 | err = -ENOMEM; | |
1036 | goto err_context; | |
1037 | } | |
1038 | ||
ec00f5e4 | 1039 | s->packet_index = 0; |
4b7da117 | 1040 | do { |
6007bf54 | 1041 | struct fw_iso_packet params; |
e229853d TS |
1042 | bool sched_irq; |
1043 | ||
1044 | sched_irq = !((s->packet_index + 1) % s->idle_irq_interval); | |
b18f0cfa | 1045 | if (s->direction == AMDTP_IN_STREAM) { |
e229853d | 1046 | err = queue_in_packet(s, ¶ms, sched_irq); |
b18f0cfa TS |
1047 | } else { |
1048 | params.header_length = 0; | |
1049 | params.payload_length = 0; | |
e229853d | 1050 | err = queue_out_packet(s, ¶ms, sched_irq); |
b18f0cfa | 1051 | } |
4b7da117 | 1052 | if (err < 0) |
04130cf8 | 1053 | goto err_pkt_descs; |
4b7da117 | 1054 | } while (s->packet_index > 0); |
31ef9134 | 1055 | |
2b3fc456 | 1056 | /* NOTE: TAG1 matches CIP. This just affects in stream. */ |
7ab56645 | 1057 | tag = FW_ISO_CONTEXT_MATCH_TAG1; |
3b196c39 | 1058 | if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER)) |
7ab56645 TS |
1059 | tag |= FW_ISO_CONTEXT_MATCH_TAG0; |
1060 | ||
7b3b0d85 | 1061 | s->callbacked = false; |
7ab56645 | 1062 | err = fw_iso_context_start(s->context, -1, 0, tag); |
31ef9134 | 1063 | if (err < 0) |
04130cf8 | 1064 | goto err_pkt_descs; |
31ef9134 CL |
1065 | |
1066 | mutex_unlock(&s->mutex); | |
1067 | ||
1068 | return 0; | |
04130cf8 TS |
1069 | err_pkt_descs: |
1070 | kfree(s->pkt_descs); | |
31ef9134 CL |
1071 | err_context: |
1072 | fw_iso_context_destroy(s->context); | |
1073 | s->context = ERR_PTR(-1); | |
1074 | err_buffer: | |
1075 | iso_packets_buffer_destroy(&s->buffer, s->unit); | |
1076 | err_unlock: | |
1077 | mutex_unlock(&s->mutex); | |
1078 | ||
1079 | return err; | |
1080 | } | |
31ef9134 | 1081 | |
e9148ddd | 1082 | /** |
be4a2894 TS |
1083 | * amdtp_stream_pcm_pointer - get the PCM buffer position |
1084 | * @s: the AMDTP stream that transports the PCM data | |
e9148ddd CL |
1085 | * |
1086 | * Returns the current buffer position, in frames. | |
1087 | */ | |
be4a2894 | 1088 | unsigned long amdtp_stream_pcm_pointer(struct amdtp_stream *s) |
e9148ddd | 1089 | { |
1dba9db0 TS |
1090 | /* |
1091 | * This function is called in software IRQ context of period_tasklet or | |
1092 | * process context. | |
1093 | * | |
1094 | * When the software IRQ context was scheduled by software IRQ context | |
1095 | * of IR/IT contexts, queued packets were already handled. Therefore, | |
1096 | * no need to flush the queue in buffer anymore. | |
1097 | * | |
1098 | * When the process context reach here, some packets will be already | |
1099 | * queued in the buffer. These packets should be handled immediately | |
1100 | * to keep better granularity of PCM pointer. | |
1101 | * | |
1102 | * Later, the process context will sometimes schedules software IRQ | |
1103 | * context of the period_tasklet. Then, no need to flush the queue by | |
1104 | * the same reason as described for IR/IT contexts. | |
1105 | */ | |
1106 | if (!in_interrupt() && amdtp_stream_running(s)) | |
92b862c7 | 1107 | fw_iso_context_flush_completions(s->context); |
e9148ddd | 1108 | |
6aa7de05 | 1109 | return READ_ONCE(s->pcm_buffer_pointer); |
e9148ddd | 1110 | } |
be4a2894 | 1111 | EXPORT_SYMBOL(amdtp_stream_pcm_pointer); |
e9148ddd | 1112 | |
875becf8 TS |
1113 | /** |
1114 | * amdtp_stream_pcm_ack - acknowledge queued PCM frames | |
1115 | * @s: the AMDTP stream that transfers the PCM frames | |
1116 | * | |
1117 | * Returns zero always. | |
1118 | */ | |
1119 | int amdtp_stream_pcm_ack(struct amdtp_stream *s) | |
1120 | { | |
1121 | /* | |
1122 | * Process isochronous packets for recent isochronous cycle to handle | |
1123 | * queued PCM frames. | |
1124 | */ | |
1125 | if (amdtp_stream_running(s)) | |
1126 | fw_iso_context_flush_completions(s->context); | |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | EXPORT_SYMBOL(amdtp_stream_pcm_ack); | |
1131 | ||
31ef9134 | 1132 | /** |
be4a2894 TS |
1133 | * amdtp_stream_update - update the stream after a bus reset |
1134 | * @s: the AMDTP stream | |
31ef9134 | 1135 | */ |
be4a2894 | 1136 | void amdtp_stream_update(struct amdtp_stream *s) |
31ef9134 | 1137 | { |
9a2820c1 | 1138 | /* Precomputing. */ |
6aa7de05 MR |
1139 | WRITE_ONCE(s->source_node_id_field, |
1140 | (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK); | |
31ef9134 | 1141 | } |
be4a2894 | 1142 | EXPORT_SYMBOL(amdtp_stream_update); |
31ef9134 CL |
1143 | |
1144 | /** | |
be4a2894 TS |
1145 | * amdtp_stream_stop - stop sending packets |
1146 | * @s: the AMDTP stream to stop | |
31ef9134 CL |
1147 | * |
1148 | * All PCM and MIDI devices of the stream must be stopped before the stream | |
1149 | * itself can be stopped. | |
1150 | */ | |
74f94e41 | 1151 | static void amdtp_stream_stop(struct amdtp_stream *s) |
31ef9134 CL |
1152 | { |
1153 | mutex_lock(&s->mutex); | |
1154 | ||
be4a2894 | 1155 | if (!amdtp_stream_running(s)) { |
31ef9134 CL |
1156 | mutex_unlock(&s->mutex); |
1157 | return; | |
1158 | } | |
1159 | ||
76fb8789 | 1160 | tasklet_kill(&s->period_tasklet); |
31ef9134 CL |
1161 | fw_iso_context_stop(s->context); |
1162 | fw_iso_context_destroy(s->context); | |
1163 | s->context = ERR_PTR(-1); | |
1164 | iso_packets_buffer_destroy(&s->buffer, s->unit); | |
04130cf8 | 1165 | kfree(s->pkt_descs); |
31ef9134 | 1166 | |
7b3b0d85 TS |
1167 | s->callbacked = false; |
1168 | ||
31ef9134 CL |
1169 | mutex_unlock(&s->mutex); |
1170 | } | |
31ef9134 CL |
1171 | |
1172 | /** | |
be4a2894 | 1173 | * amdtp_stream_pcm_abort - abort the running PCM device |
31ef9134 CL |
1174 | * @s: the AMDTP stream about to be stopped |
1175 | * | |
1176 | * If the isochronous stream needs to be stopped asynchronously, call this | |
1177 | * function first to stop the PCM device. | |
1178 | */ | |
be4a2894 | 1179 | void amdtp_stream_pcm_abort(struct amdtp_stream *s) |
31ef9134 CL |
1180 | { |
1181 | struct snd_pcm_substream *pcm; | |
1182 | ||
6aa7de05 | 1183 | pcm = READ_ONCE(s->pcm); |
1fb8510c TI |
1184 | if (pcm) |
1185 | snd_pcm_stop_xrun(pcm); | |
31ef9134 | 1186 | } |
be4a2894 | 1187 | EXPORT_SYMBOL(amdtp_stream_pcm_abort); |
3ec3d7a3 TS |
1188 | |
1189 | /** | |
1190 | * amdtp_domain_init - initialize an AMDTP domain structure | |
1191 | * @d: the AMDTP domain to initialize. | |
1192 | */ | |
1193 | int amdtp_domain_init(struct amdtp_domain *d) | |
1194 | { | |
1195 | INIT_LIST_HEAD(&d->streams); | |
1196 | ||
d68c3123 TS |
1197 | d->events_per_period = 0; |
1198 | ||
3ec3d7a3 TS |
1199 | return 0; |
1200 | } | |
1201 | EXPORT_SYMBOL_GPL(amdtp_domain_init); | |
1202 | ||
1203 | /** | |
1204 | * amdtp_domain_destroy - destroy an AMDTP domain structure | |
1205 | * @d: the AMDTP domain to destroy. | |
1206 | */ | |
1207 | void amdtp_domain_destroy(struct amdtp_domain *d) | |
1208 | { | |
8d0d5c3f TS |
1209 | // At present nothing to do. |
1210 | return; | |
3ec3d7a3 TS |
1211 | } |
1212 | EXPORT_SYMBOL_GPL(amdtp_domain_destroy); | |
6261f90b | 1213 | |
157a53ee TS |
1214 | /** |
1215 | * amdtp_domain_add_stream - register isoc context into the domain. | |
1216 | * @d: the AMDTP domain. | |
1217 | * @s: the AMDTP stream. | |
1218 | * @channel: the isochronous channel on the bus. | |
1219 | * @speed: firewire speed code. | |
1220 | */ | |
1221 | int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s, | |
1222 | int channel, int speed) | |
1223 | { | |
1224 | struct amdtp_stream *tmp; | |
1225 | ||
1226 | list_for_each_entry(tmp, &d->streams, list) { | |
1227 | if (s == tmp) | |
1228 | return -EBUSY; | |
1229 | } | |
1230 | ||
1231 | list_add(&s->list, &d->streams); | |
1232 | ||
1233 | s->channel = channel; | |
1234 | s->speed = speed; | |
1235 | ||
1236 | return 0; | |
1237 | } | |
1238 | EXPORT_SYMBOL_GPL(amdtp_domain_add_stream); | |
1239 | ||
9b4702b0 TS |
1240 | /** |
1241 | * amdtp_domain_start - start sending packets for isoc context in the domain. | |
1242 | * @d: the AMDTP domain. | |
1243 | */ | |
1244 | int amdtp_domain_start(struct amdtp_domain *d) | |
1245 | { | |
1246 | struct amdtp_stream *s; | |
1247 | int err = 0; | |
1248 | ||
1249 | list_for_each_entry(s, &d->streams, list) { | |
a0e02331 | 1250 | err = amdtp_stream_start(s, s->channel, s->speed, d); |
9b4702b0 TS |
1251 | if (err < 0) |
1252 | break; | |
1253 | } | |
1254 | ||
1255 | if (err < 0) { | |
1256 | list_for_each_entry(s, &d->streams, list) | |
1257 | amdtp_stream_stop(s); | |
1258 | } | |
1259 | ||
1260 | return err; | |
1261 | } | |
1262 | EXPORT_SYMBOL_GPL(amdtp_domain_start); | |
1263 | ||
6261f90b TS |
1264 | /** |
1265 | * amdtp_domain_stop - stop sending packets for isoc context in the same domain. | |
1266 | * @d: the AMDTP domain to which the isoc contexts belong. | |
1267 | */ | |
1268 | void amdtp_domain_stop(struct amdtp_domain *d) | |
1269 | { | |
1270 | struct amdtp_stream *s, *next; | |
1271 | ||
1272 | list_for_each_entry_safe(s, next, &d->streams, list) { | |
1273 | list_del(&s->list); | |
1274 | ||
1275 | amdtp_stream_stop(s); | |
1276 | } | |
d68c3123 TS |
1277 | |
1278 | d->events_per_period = 0; | |
6261f90b TS |
1279 | } |
1280 | EXPORT_SYMBOL_GPL(amdtp_domain_stop); |