Commit | Line | Data |
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da607e19 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
31ef9134 CL |
2 | /* |
3 | * Audio and Music Data Transmission Protocol (IEC 61883-6) streams | |
4 | * with Common Isochronous Packet (IEC 61883-1) headers | |
5 | * | |
6 | * Copyright (c) Clemens Ladisch <clemens@ladisch.de> | |
31ef9134 CL |
7 | */ |
8 | ||
9 | #include <linux/device.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/firewire.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/slab.h> | |
14 | #include <sound/pcm.h> | |
7b2d99fa | 15 | #include <sound/pcm_params.h> |
d67c46b9 | 16 | #include "amdtp-stream.h" |
31ef9134 CL |
17 | |
18 | #define TICKS_PER_CYCLE 3072 | |
19 | #define CYCLES_PER_SECOND 8000 | |
20 | #define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND) | |
21 | ||
0c95c1d6 TS |
22 | /* Always support Linux tracing subsystem. */ |
23 | #define CREATE_TRACE_POINTS | |
24 | #include "amdtp-stream-trace.h" | |
25 | ||
ca5b5050 | 26 | #define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */ |
31ef9134 | 27 | |
b445db44 TS |
28 | /* isochronous header parameters */ |
29 | #define ISO_DATA_LENGTH_SHIFT 16 | |
3b196c39 | 30 | #define TAG_NO_CIP_HEADER 0 |
31ef9134 CL |
31 | #define TAG_CIP 1 |
32 | ||
b445db44 | 33 | /* common isochronous packet header parameters */ |
9a2820c1 TS |
34 | #define CIP_EOH_SHIFT 31 |
35 | #define CIP_EOH (1u << CIP_EOH_SHIFT) | |
b445db44 | 36 | #define CIP_EOH_MASK 0x80000000 |
9a2820c1 TS |
37 | #define CIP_SID_SHIFT 24 |
38 | #define CIP_SID_MASK 0x3f000000 | |
39 | #define CIP_DBS_MASK 0x00ff0000 | |
40 | #define CIP_DBS_SHIFT 16 | |
9863874f TS |
41 | #define CIP_SPH_MASK 0x00000400 |
42 | #define CIP_SPH_SHIFT 10 | |
9a2820c1 TS |
43 | #define CIP_DBC_MASK 0x000000ff |
44 | #define CIP_FMT_SHIFT 24 | |
b445db44 | 45 | #define CIP_FMT_MASK 0x3f000000 |
9a2820c1 TS |
46 | #define CIP_FDF_MASK 0x00ff0000 |
47 | #define CIP_FDF_SHIFT 16 | |
b445db44 TS |
48 | #define CIP_SYT_MASK 0x0000ffff |
49 | #define CIP_SYT_NO_INFO 0xffff | |
b445db44 | 50 | |
51c29fd2 | 51 | /* Audio and Music transfer protocol specific parameters */ |
414ba022 | 52 | #define CIP_FMT_AM 0x10 |
2b3fc456 | 53 | #define AMDTP_FDF_NO_DATA 0xff |
31ef9134 CL |
54 | |
55 | /* TODO: make these configurable */ | |
56 | #define INTERRUPT_INTERVAL 16 | |
31ef9134 | 57 | |
f11453c7 TS |
58 | // For iso header, tstamp and 2 CIP header. |
59 | #define IR_CTX_HEADER_SIZE_CIP 16 | |
60 | // For iso header and tstamp. | |
61 | #define IR_CTX_HEADER_SIZE_NO_CIP 8 | |
cc4f8e91 | 62 | #define HEADER_TSTAMP_MASK 0x0000ffff |
4b7da117 | 63 | |
b18f0cfa TS |
64 | #define IT_PKT_HEADER_SIZE_CIP 8 // For 2 CIP header. |
65 | #define IT_PKT_HEADER_SIZE_NO_CIP 0 // Nothing. | |
66 | ||
76fb8789 CL |
67 | static void pcm_period_tasklet(unsigned long data); |
68 | ||
31ef9134 | 69 | /** |
be4a2894 TS |
70 | * amdtp_stream_init - initialize an AMDTP stream structure |
71 | * @s: the AMDTP stream to initialize | |
31ef9134 | 72 | * @unit: the target of the stream |
3ff7e8f0 | 73 | * @dir: the direction of stream |
31ef9134 | 74 | * @flags: the packet transmission method to use |
5955815e | 75 | * @fmt: the value of fmt field in CIP header |
9a738ad1 | 76 | * @process_ctx_payloads: callback handler to process payloads of isoc context |
df075fee | 77 | * @protocol_size: the size to allocate newly for protocol |
31ef9134 | 78 | */ |
be4a2894 | 79 | int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit, |
5955815e | 80 | enum amdtp_stream_direction dir, enum cip_flags flags, |
df075fee | 81 | unsigned int fmt, |
9a738ad1 | 82 | amdtp_stream_process_ctx_payloads_t process_ctx_payloads, |
df075fee | 83 | unsigned int protocol_size) |
31ef9134 | 84 | { |
9a738ad1 | 85 | if (process_ctx_payloads == NULL) |
df075fee TS |
86 | return -EINVAL; |
87 | ||
88 | s->protocol = kzalloc(protocol_size, GFP_KERNEL); | |
89 | if (!s->protocol) | |
90 | return -ENOMEM; | |
91 | ||
c6f224dc | 92 | s->unit = unit; |
3ff7e8f0 | 93 | s->direction = dir; |
31ef9134 CL |
94 | s->flags = flags; |
95 | s->context = ERR_PTR(-1); | |
96 | mutex_init(&s->mutex); | |
76fb8789 | 97 | tasklet_init(&s->period_tasklet, pcm_period_tasklet, (unsigned long)s); |
ec00f5e4 | 98 | s->packet_index = 0; |
31ef9134 | 99 | |
7b3b0d85 TS |
100 | init_waitqueue_head(&s->callback_wait); |
101 | s->callbacked = false; | |
7b3b0d85 | 102 | |
5955815e | 103 | s->fmt = fmt; |
9a738ad1 | 104 | s->process_ctx_payloads = process_ctx_payloads; |
414ba022 | 105 | |
3baf3053 TS |
106 | if (dir == AMDTP_OUT_STREAM) |
107 | s->ctx_data.rx.syt_override = -1; | |
108 | ||
31ef9134 CL |
109 | return 0; |
110 | } | |
be4a2894 | 111 | EXPORT_SYMBOL(amdtp_stream_init); |
31ef9134 CL |
112 | |
113 | /** | |
be4a2894 TS |
114 | * amdtp_stream_destroy - free stream resources |
115 | * @s: the AMDTP stream to destroy | |
31ef9134 | 116 | */ |
be4a2894 | 117 | void amdtp_stream_destroy(struct amdtp_stream *s) |
31ef9134 | 118 | { |
44c376b9 TS |
119 | /* Not initialized. */ |
120 | if (s->protocol == NULL) | |
121 | return; | |
122 | ||
be4a2894 | 123 | WARN_ON(amdtp_stream_running(s)); |
df075fee | 124 | kfree(s->protocol); |
31ef9134 | 125 | mutex_destroy(&s->mutex); |
31ef9134 | 126 | } |
be4a2894 | 127 | EXPORT_SYMBOL(amdtp_stream_destroy); |
31ef9134 | 128 | |
c5280e99 | 129 | const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = { |
a7304e3b CL |
130 | [CIP_SFC_32000] = 8, |
131 | [CIP_SFC_44100] = 8, | |
132 | [CIP_SFC_48000] = 8, | |
133 | [CIP_SFC_88200] = 16, | |
134 | [CIP_SFC_96000] = 16, | |
135 | [CIP_SFC_176400] = 32, | |
136 | [CIP_SFC_192000] = 32, | |
137 | }; | |
138 | EXPORT_SYMBOL(amdtp_syt_intervals); | |
139 | ||
f9503a68 | 140 | const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = { |
1017abed TS |
141 | [CIP_SFC_32000] = 32000, |
142 | [CIP_SFC_44100] = 44100, | |
143 | [CIP_SFC_48000] = 48000, | |
144 | [CIP_SFC_88200] = 88200, | |
145 | [CIP_SFC_96000] = 96000, | |
146 | [CIP_SFC_176400] = 176400, | |
147 | [CIP_SFC_192000] = 192000, | |
148 | }; | |
149 | EXPORT_SYMBOL(amdtp_rate_table); | |
150 | ||
59502295 TS |
151 | static int apply_constraint_to_size(struct snd_pcm_hw_params *params, |
152 | struct snd_pcm_hw_rule *rule) | |
153 | { | |
154 | struct snd_interval *s = hw_param_interval(params, rule->var); | |
155 | const struct snd_interval *r = | |
156 | hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE); | |
826b5de9 TS |
157 | struct snd_interval t = {0}; |
158 | unsigned int step = 0; | |
59502295 TS |
159 | int i; |
160 | ||
161 | for (i = 0; i < CIP_SFC_COUNT; ++i) { | |
826b5de9 TS |
162 | if (snd_interval_test(r, amdtp_rate_table[i])) |
163 | step = max(step, amdtp_syt_intervals[i]); | |
59502295 TS |
164 | } |
165 | ||
826b5de9 TS |
166 | t.min = roundup(s->min, step); |
167 | t.max = rounddown(s->max, step); | |
168 | t.integer = 1; | |
59502295 TS |
169 | |
170 | return snd_interval_refine(s, &t); | |
171 | } | |
172 | ||
7b2d99fa TS |
173 | /** |
174 | * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream | |
175 | * @s: the AMDTP stream, which must be initialized. | |
176 | * @runtime: the PCM substream runtime | |
177 | */ | |
178 | int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s, | |
179 | struct snd_pcm_runtime *runtime) | |
180 | { | |
55799c5a | 181 | struct snd_pcm_hardware *hw = &runtime->hw; |
7b2d99fa TS |
182 | int err; |
183 | ||
55799c5a TS |
184 | hw->info = SNDRV_PCM_INFO_BATCH | |
185 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
186 | SNDRV_PCM_INFO_INTERLEAVED | | |
187 | SNDRV_PCM_INFO_JOINT_DUPLEX | | |
188 | SNDRV_PCM_INFO_MMAP | | |
189 | SNDRV_PCM_INFO_MMAP_VALID; | |
190 | ||
191 | /* SNDRV_PCM_INFO_BATCH */ | |
192 | hw->periods_min = 2; | |
193 | hw->periods_max = UINT_MAX; | |
194 | ||
195 | /* bytes for a frame */ | |
196 | hw->period_bytes_min = 4 * hw->channels_max; | |
197 | ||
198 | /* Just to prevent from allocating much pages. */ | |
199 | hw->period_bytes_max = hw->period_bytes_min * 2048; | |
200 | hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min; | |
201 | ||
7b2d99fa TS |
202 | /* |
203 | * Currently firewire-lib processes 16 packets in one software | |
204 | * interrupt callback. This equals to 2msec but actually the | |
205 | * interval of the interrupts has a jitter. | |
206 | * Additionally, even if adding a constraint to fit period size to | |
207 | * 2msec, actual calculated frames per period doesn't equal to 2msec, | |
208 | * depending on sampling rate. | |
209 | * Anyway, the interval to call snd_pcm_period_elapsed() cannot 2msec. | |
210 | * Here let us use 5msec for safe period interrupt. | |
211 | */ | |
212 | err = snd_pcm_hw_constraint_minmax(runtime, | |
213 | SNDRV_PCM_HW_PARAM_PERIOD_TIME, | |
214 | 5000, UINT_MAX); | |
215 | if (err < 0) | |
216 | goto end; | |
217 | ||
218 | /* Non-Blocking stream has no more constraints */ | |
219 | if (!(s->flags & CIP_BLOCKING)) | |
220 | goto end; | |
221 | ||
222 | /* | |
223 | * One AMDTP packet can include some frames. In blocking mode, the | |
224 | * number equals to SYT_INTERVAL. So the number is 8, 16 or 32, | |
225 | * depending on its sampling rate. For accurate period interrupt, it's | |
ce991981 | 226 | * preferrable to align period/buffer sizes to current SYT_INTERVAL. |
7b2d99fa | 227 | */ |
59502295 TS |
228 | err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, |
229 | apply_constraint_to_size, NULL, | |
826b5de9 | 230 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, |
59502295 TS |
231 | SNDRV_PCM_HW_PARAM_RATE, -1); |
232 | if (err < 0) | |
233 | goto end; | |
59502295 TS |
234 | err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, |
235 | apply_constraint_to_size, NULL, | |
826b5de9 | 236 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, |
59502295 TS |
237 | SNDRV_PCM_HW_PARAM_RATE, -1); |
238 | if (err < 0) | |
239 | goto end; | |
7b2d99fa TS |
240 | end: |
241 | return err; | |
242 | } | |
243 | EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints); | |
244 | ||
31ef9134 | 245 | /** |
be4a2894 TS |
246 | * amdtp_stream_set_parameters - set stream parameters |
247 | * @s: the AMDTP stream to configure | |
31ef9134 | 248 | * @rate: the sample rate |
df075fee | 249 | * @data_block_quadlets: the size of a data block in quadlet unit |
31ef9134 | 250 | * |
a7304e3b | 251 | * The parameters must be set before the stream is started, and must not be |
31ef9134 CL |
252 | * changed while the stream is running. |
253 | */ | |
df075fee TS |
254 | int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate, |
255 | unsigned int data_block_quadlets) | |
31ef9134 | 256 | { |
df075fee | 257 | unsigned int sfc; |
31ef9134 | 258 | |
547e631c | 259 | for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) { |
1017abed | 260 | if (amdtp_rate_table[sfc] == rate) |
547e631c TS |
261 | break; |
262 | } | |
263 | if (sfc == ARRAY_SIZE(amdtp_rate_table)) | |
264 | return -EINVAL; | |
e84d15f6 | 265 | |
e84d15f6 | 266 | s->sfc = sfc; |
df075fee | 267 | s->data_block_quadlets = data_block_quadlets; |
a7304e3b | 268 | s->syt_interval = amdtp_syt_intervals[sfc]; |
e84d15f6 | 269 | |
d3d10a4a TS |
270 | // default buffering in the device. |
271 | if (s->direction == AMDTP_OUT_STREAM) { | |
272 | s->ctx_data.rx.transfer_delay = | |
273 | TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE; | |
274 | ||
275 | if (s->flags & CIP_BLOCKING) { | |
276 | // additional buffering needed to adjust for no-data | |
277 | // packets. | |
278 | s->ctx_data.rx.transfer_delay += | |
279 | TICKS_PER_SECOND * s->syt_interval / rate; | |
280 | } | |
281 | } | |
77d2a8a4 | 282 | |
547e631c | 283 | return 0; |
31ef9134 | 284 | } |
be4a2894 | 285 | EXPORT_SYMBOL(amdtp_stream_set_parameters); |
31ef9134 CL |
286 | |
287 | /** | |
be4a2894 TS |
288 | * amdtp_stream_get_max_payload - get the stream's packet size |
289 | * @s: the AMDTP stream | |
31ef9134 CL |
290 | * |
291 | * This function must not be called before the stream has been configured | |
be4a2894 | 292 | * with amdtp_stream_set_parameters(). |
31ef9134 | 293 | */ |
be4a2894 | 294 | unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s) |
31ef9134 | 295 | { |
a2064710 | 296 | unsigned int multiplier = 1; |
07ea238c | 297 | unsigned int cip_header_size = 0; |
a2064710 TS |
298 | |
299 | if (s->flags & CIP_JUMBO_PAYLOAD) | |
300 | multiplier = 5; | |
3b196c39 | 301 | if (!(s->flags & CIP_NO_HEADER)) |
07ea238c | 302 | cip_header_size = sizeof(__be32) * 2; |
a2064710 | 303 | |
07ea238c TS |
304 | return cip_header_size + |
305 | s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier; | |
31ef9134 | 306 | } |
be4a2894 | 307 | EXPORT_SYMBOL(amdtp_stream_get_max_payload); |
31ef9134 | 308 | |
76fb8789 | 309 | /** |
be4a2894 TS |
310 | * amdtp_stream_pcm_prepare - prepare PCM device for running |
311 | * @s: the AMDTP stream | |
76fb8789 CL |
312 | * |
313 | * This function should be called from the PCM device's .prepare callback. | |
314 | */ | |
be4a2894 | 315 | void amdtp_stream_pcm_prepare(struct amdtp_stream *s) |
76fb8789 CL |
316 | { |
317 | tasklet_kill(&s->period_tasklet); | |
318 | s->pcm_buffer_pointer = 0; | |
319 | s->pcm_period_pointer = 0; | |
320 | } | |
be4a2894 | 321 | EXPORT_SYMBOL(amdtp_stream_pcm_prepare); |
76fb8789 | 322 | |
875be091 TS |
323 | static unsigned int calculate_data_blocks(struct amdtp_stream *s, |
324 | unsigned int syt) | |
31ef9134 CL |
325 | { |
326 | unsigned int phase, data_blocks; | |
327 | ||
875be091 TS |
328 | /* Blocking mode. */ |
329 | if (s->flags & CIP_BLOCKING) { | |
330 | /* This module generate empty packet for 'no data'. */ | |
331 | if (syt == CIP_SYT_NO_INFO) | |
332 | data_blocks = 0; | |
333 | else | |
334 | data_blocks = s->syt_interval; | |
335 | /* Non-blocking mode. */ | |
31ef9134 | 336 | } else { |
875be091 | 337 | if (!cip_sfc_is_base_44100(s->sfc)) { |
d3d10a4a TS |
338 | // Sample_rate / 8000 is an integer, and precomputed. |
339 | data_blocks = s->ctx_data.rx.data_block_state; | |
875be091 | 340 | } else { |
d3d10a4a | 341 | phase = s->ctx_data.rx.data_block_state; |
31ef9134 CL |
342 | |
343 | /* | |
344 | * This calculates the number of data blocks per packet so that | |
345 | * 1) the overall rate is correct and exactly synchronized to | |
346 | * the bus clock, and | |
347 | * 2) packets with a rounded-up number of blocks occur as early | |
348 | * as possible in the sequence (to prevent underruns of the | |
349 | * device's buffer). | |
350 | */ | |
875be091 TS |
351 | if (s->sfc == CIP_SFC_44100) |
352 | /* 6 6 5 6 5 6 5 ... */ | |
353 | data_blocks = 5 + ((phase & 1) ^ | |
354 | (phase == 0 || phase >= 40)); | |
355 | else | |
356 | /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */ | |
357 | data_blocks = 11 * (s->sfc >> 1) + (phase == 0); | |
358 | if (++phase >= (80 >> (s->sfc >> 1))) | |
359 | phase = 0; | |
d3d10a4a | 360 | s->ctx_data.rx.data_block_state = phase; |
875be091 | 361 | } |
31ef9134 CL |
362 | } |
363 | ||
364 | return data_blocks; | |
365 | } | |
366 | ||
be4a2894 | 367 | static unsigned int calculate_syt(struct amdtp_stream *s, |
31ef9134 CL |
368 | unsigned int cycle) |
369 | { | |
370 | unsigned int syt_offset, phase, index, syt; | |
371 | ||
d3d10a4a | 372 | if (s->ctx_data.rx.last_syt_offset < TICKS_PER_CYCLE) { |
31ef9134 | 373 | if (!cip_sfc_is_base_44100(s->sfc)) |
d3d10a4a TS |
374 | syt_offset = s->ctx_data.rx.last_syt_offset + |
375 | s->ctx_data.rx.syt_offset_state; | |
31ef9134 CL |
376 | else { |
377 | /* | |
378 | * The time, in ticks, of the n'th SYT_INTERVAL sample is: | |
379 | * n * SYT_INTERVAL * 24576000 / sample_rate | |
380 | * Modulo TICKS_PER_CYCLE, the difference between successive | |
381 | * elements is about 1386.23. Rounding the results of this | |
382 | * formula to the SYT precision results in a sequence of | |
383 | * differences that begins with: | |
384 | * 1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ... | |
385 | * This code generates _exactly_ the same sequence. | |
386 | */ | |
d3d10a4a | 387 | phase = s->ctx_data.rx.syt_offset_state; |
31ef9134 | 388 | index = phase % 13; |
d3d10a4a | 389 | syt_offset = s->ctx_data.rx.last_syt_offset; |
31ef9134 CL |
390 | syt_offset += 1386 + ((index && !(index & 3)) || |
391 | phase == 146); | |
392 | if (++phase >= 147) | |
393 | phase = 0; | |
d3d10a4a | 394 | s->ctx_data.rx.syt_offset_state = phase; |
31ef9134 CL |
395 | } |
396 | } else | |
d3d10a4a TS |
397 | syt_offset = s->ctx_data.rx.last_syt_offset - TICKS_PER_CYCLE; |
398 | s->ctx_data.rx.last_syt_offset = syt_offset; | |
31ef9134 | 399 | |
be454366 | 400 | if (syt_offset < TICKS_PER_CYCLE) { |
d3d10a4a | 401 | syt_offset += s->ctx_data.rx.transfer_delay; |
be454366 CL |
402 | syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12; |
403 | syt += syt_offset % TICKS_PER_CYCLE; | |
31ef9134 | 404 | |
b445db44 | 405 | return syt & CIP_SYT_MASK; |
be454366 | 406 | } else { |
b445db44 | 407 | return CIP_SYT_NO_INFO; |
be454366 | 408 | } |
31ef9134 CL |
409 | } |
410 | ||
4b7da117 TS |
411 | static void update_pcm_pointers(struct amdtp_stream *s, |
412 | struct snd_pcm_substream *pcm, | |
413 | unsigned int frames) | |
65845f29 TS |
414 | { |
415 | unsigned int ptr; | |
416 | ||
4b7da117 TS |
417 | ptr = s->pcm_buffer_pointer + frames; |
418 | if (ptr >= pcm->runtime->buffer_size) | |
419 | ptr -= pcm->runtime->buffer_size; | |
6aa7de05 | 420 | WRITE_ONCE(s->pcm_buffer_pointer, ptr); |
4b7da117 TS |
421 | |
422 | s->pcm_period_pointer += frames; | |
423 | if (s->pcm_period_pointer >= pcm->runtime->period_size) { | |
424 | s->pcm_period_pointer -= pcm->runtime->period_size; | |
4b7da117 TS |
425 | tasklet_hi_schedule(&s->period_tasklet); |
426 | } | |
427 | } | |
428 | ||
429 | static void pcm_period_tasklet(unsigned long data) | |
430 | { | |
431 | struct amdtp_stream *s = (void *)data; | |
6aa7de05 | 432 | struct snd_pcm_substream *pcm = READ_ONCE(s->pcm); |
4b7da117 TS |
433 | |
434 | if (pcm) | |
435 | snd_pcm_period_elapsed(pcm); | |
436 | } | |
437 | ||
6007bf54 | 438 | static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params) |
4b7da117 | 439 | { |
6007bf54 | 440 | int err; |
df9160b9 | 441 | |
6007bf54 TS |
442 | params->interrupt = IS_ALIGNED(s->packet_index + 1, INTERRUPT_INTERVAL); |
443 | params->tag = s->tag; | |
444 | params->sy = 0; | |
df9160b9 | 445 | |
6007bf54 | 446 | err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer, |
4b7da117 TS |
447 | s->buffer.packets[s->packet_index].offset); |
448 | if (err < 0) { | |
449 | dev_err(&s->unit->device, "queueing error: %d\n", err); | |
450 | goto end; | |
451 | } | |
452 | ||
a0e02331 | 453 | if (++s->packet_index >= s->queue_size) |
4b7da117 TS |
454 | s->packet_index = 0; |
455 | end: | |
456 | return err; | |
457 | } | |
458 | ||
459 | static inline int queue_out_packet(struct amdtp_stream *s, | |
b18f0cfa | 460 | struct fw_iso_packet *params) |
4b7da117 | 461 | { |
b18f0cfa TS |
462 | params->skip = |
463 | !!(params->header_length == 0 && params->payload_length == 0); | |
6007bf54 | 464 | return queue_packet(s, params); |
4b7da117 TS |
465 | } |
466 | ||
6007bf54 TS |
467 | static inline int queue_in_packet(struct amdtp_stream *s, |
468 | struct fw_iso_packet *params) | |
2b3fc456 | 469 | { |
6007bf54 TS |
470 | // Queue one packet for IR context. |
471 | params->header_length = s->ctx_data.tx.ctx_header_size; | |
472 | params->payload_length = s->ctx_data.tx.max_ctx_payload_length; | |
473 | params->skip = false; | |
474 | return queue_packet(s, params); | |
2b3fc456 TS |
475 | } |
476 | ||
252219c7 | 477 | static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2], |
860d798c | 478 | unsigned int data_block_counter, unsigned int syt) |
252219c7 TS |
479 | { |
480 | cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) | | |
481 | (s->data_block_quadlets << CIP_DBS_SHIFT) | | |
482 | ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) | | |
860d798c | 483 | data_block_counter); |
252219c7 TS |
484 | cip_header[1] = cpu_to_be32(CIP_EOH | |
485 | ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) | | |
486 | ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) | | |
487 | (syt & CIP_SYT_MASK)); | |
488 | } | |
489 | ||
6bc1a269 TS |
490 | static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle, |
491 | struct fw_iso_packet *params, | |
860d798c TS |
492 | unsigned int data_blocks, |
493 | unsigned int data_block_counter, | |
494 | unsigned int syt, unsigned int index) | |
31ef9134 | 495 | { |
0ebf3ceb | 496 | unsigned int payload_length; |
16be4589 | 497 | __be32 *cip_header; |
20e44577 | 498 | |
0ebf3ceb TS |
499 | payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets; |
500 | params->payload_length = payload_length; | |
501 | ||
b18f0cfa | 502 | if (!(s->flags & CIP_NO_HEADER)) { |
6bc1a269 | 503 | cip_header = (__be32 *)params->header; |
860d798c | 504 | generate_cip_header(s, cip_header, data_block_counter, syt); |
6bc1a269 | 505 | params->header_length = 2 * sizeof(__be32); |
0ebf3ceb | 506 | payload_length += params->header_length; |
b18f0cfa TS |
507 | } else { |
508 | cip_header = NULL; | |
509 | } | |
31ef9134 | 510 | |
213fa989 | 511 | trace_amdtp_packet(s, cycle, cip_header, payload_length, data_blocks, |
860d798c | 512 | data_block_counter, index); |
3b196c39 TS |
513 | } |
514 | ||
e335425b TS |
515 | static int check_cip_header(struct amdtp_stream *s, const __be32 *buf, |
516 | unsigned int payload_length, | |
a35463d1 TS |
517 | unsigned int *data_blocks, |
518 | unsigned int *data_block_counter, unsigned int *syt) | |
2b3fc456 TS |
519 | { |
520 | u32 cip_header[2]; | |
e335425b TS |
521 | unsigned int sph; |
522 | unsigned int fmt; | |
523 | unsigned int fdf; | |
a35463d1 | 524 | unsigned int dbc; |
c8bdf49b | 525 | bool lost; |
2b3fc456 | 526 | |
e335425b TS |
527 | cip_header[0] = be32_to_cpu(buf[0]); |
528 | cip_header[1] = be32_to_cpu(buf[1]); | |
2b3fc456 TS |
529 | |
530 | /* | |
531 | * This module supports 'Two-quadlet CIP header with SYT field'. | |
77d2a8a4 | 532 | * For convenience, also check FMT field is AM824 or not. |
2b3fc456 | 533 | */ |
2128f78f TS |
534 | if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) || |
535 | ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) && | |
536 | (!(s->flags & CIP_HEADER_WITHOUT_EOH))) { | |
2b3fc456 TS |
537 | dev_info_ratelimited(&s->unit->device, |
538 | "Invalid CIP header for AMDTP: %08X:%08X\n", | |
539 | cip_header[0], cip_header[1]); | |
e335425b | 540 | return -EAGAIN; |
2b3fc456 TS |
541 | } |
542 | ||
414ba022 | 543 | /* Check valid protocol or not. */ |
9863874f | 544 | sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT; |
414ba022 | 545 | fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT; |
9863874f | 546 | if (sph != s->sph || fmt != s->fmt) { |
2a7e1713 TS |
547 | dev_info_ratelimited(&s->unit->device, |
548 | "Detect unexpected protocol: %08x %08x\n", | |
549 | cip_header[0], cip_header[1]); | |
e335425b | 550 | return -EAGAIN; |
414ba022 TS |
551 | } |
552 | ||
2b3fc456 | 553 | /* Calculate data blocks */ |
414ba022 | 554 | fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT; |
e335425b | 555 | if (payload_length < sizeof(__be32) * 2 || |
414ba022 | 556 | (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) { |
e335425b | 557 | *data_blocks = 0; |
2b3fc456 | 558 | } else { |
e335425b TS |
559 | unsigned int data_block_quadlets = |
560 | (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT; | |
2b3fc456 TS |
561 | /* avoid division by zero */ |
562 | if (data_block_quadlets == 0) { | |
12e0f438 | 563 | dev_err(&s->unit->device, |
2b3fc456 TS |
564 | "Detect invalid value in dbs field: %08X\n", |
565 | cip_header[0]); | |
a9007054 | 566 | return -EPROTO; |
2b3fc456 | 567 | } |
69702239 TS |
568 | if (s->flags & CIP_WRONG_DBS) |
569 | data_block_quadlets = s->data_block_quadlets; | |
2b3fc456 | 570 | |
e335425b | 571 | *data_blocks = (payload_length / sizeof(__be32) - 2) / |
ff0fb5aa | 572 | data_block_quadlets; |
2b3fc456 TS |
573 | } |
574 | ||
575 | /* Check data block counter continuity */ | |
a35463d1 | 576 | dbc = cip_header[0] & CIP_DBC_MASK; |
e335425b | 577 | if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) && |
a35463d1 TS |
578 | *data_block_counter != UINT_MAX) |
579 | dbc = *data_block_counter; | |
9d59124c | 580 | |
a35463d1 TS |
581 | if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) || |
582 | *data_block_counter == UINT_MAX) { | |
b84b1a27 TS |
583 | lost = false; |
584 | } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) { | |
a35463d1 | 585 | lost = dbc != *data_block_counter; |
d9cd0065 | 586 | } else { |
e335425b TS |
587 | unsigned int dbc_interval; |
588 | ||
589 | if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0) | |
d3d10a4a | 590 | dbc_interval = s->ctx_data.tx.dbc_interval; |
d9cd0065 | 591 | else |
e335425b | 592 | dbc_interval = *data_blocks; |
d9cd0065 | 593 | |
a35463d1 | 594 | lost = dbc != ((*data_block_counter + dbc_interval) & 0xff); |
d9cd0065 | 595 | } |
c8bdf49b TS |
596 | |
597 | if (lost) { | |
12e0f438 TS |
598 | dev_err(&s->unit->device, |
599 | "Detect discontinuity of CIP: %02X %02X\n", | |
a35463d1 | 600 | *data_block_counter, dbc); |
6fc6b9ce | 601 | return -EIO; |
2b3fc456 TS |
602 | } |
603 | ||
753e7179 TS |
604 | *data_block_counter = dbc; |
605 | ||
e335425b | 606 | *syt = cip_header[1] & CIP_SYT_MASK; |
2b3fc456 | 607 | |
e335425b TS |
608 | return 0; |
609 | } | |
610 | ||
98e3e43b TS |
611 | static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle, |
612 | const __be32 *ctx_header, | |
613 | unsigned int *payload_length, | |
a35463d1 TS |
614 | unsigned int *data_blocks, |
615 | unsigned int *data_block_counter, | |
616 | unsigned int *syt, unsigned int index) | |
e335425b | 617 | { |
f11453c7 | 618 | const __be32 *cip_header; |
e335425b TS |
619 | int err; |
620 | ||
98e3e43b TS |
621 | *payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT; |
622 | if (*payload_length > s->ctx_data.tx.ctx_header_size + | |
f11453c7 | 623 | s->ctx_data.tx.max_ctx_payload_length) { |
e335425b TS |
624 | dev_err(&s->unit->device, |
625 | "Detect jumbo payload: %04x %04x\n", | |
98e3e43b | 626 | *payload_length, s->ctx_data.tx.max_ctx_payload_length); |
e335425b TS |
627 | return -EIO; |
628 | } | |
629 | ||
947b437e | 630 | if (!(s->flags & CIP_NO_HEADER)) { |
98e3e43b TS |
631 | cip_header = ctx_header + 2; |
632 | err = check_cip_header(s, cip_header, *payload_length, | |
a35463d1 | 633 | data_blocks, data_block_counter, syt); |
b8b0e24c TS |
634 | if (err < 0) |
635 | return err; | |
947b437e TS |
636 | } else { |
637 | cip_header = NULL; | |
76864868 | 638 | err = 0; |
98e3e43b TS |
639 | *data_blocks = *payload_length / sizeof(__be32) / |
640 | s->data_block_quadlets; | |
641 | *syt = 0; | |
7fbf9096 | 642 | |
a35463d1 TS |
643 | if (*data_block_counter == UINT_MAX) |
644 | *data_block_counter = 0; | |
e335425b TS |
645 | } |
646 | ||
98e3e43b | 647 | trace_amdtp_packet(s, cycle, cip_header, *payload_length, *data_blocks, |
a35463d1 | 648 | *data_block_counter, index); |
e335425b | 649 | |
76864868 | 650 | return err; |
2b3fc456 TS |
651 | } |
652 | ||
26cd1e58 TS |
653 | // In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On |
654 | // the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent | |
655 | // it. Thus, via Linux firewire subsystem, we can get the 3 bits for second. | |
656 | static inline u32 compute_cycle_count(__be32 ctx_header_tstamp) | |
73fc7f08 | 657 | { |
26cd1e58 | 658 | u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK; |
73fc7f08 TS |
659 | return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff); |
660 | } | |
661 | ||
662 | static inline u32 increment_cycle_count(u32 cycle, unsigned int addend) | |
663 | { | |
664 | cycle += addend; | |
665 | if (cycle >= 8 * CYCLES_PER_SECOND) | |
666 | cycle -= 8 * CYCLES_PER_SECOND; | |
667 | return cycle; | |
668 | } | |
669 | ||
26cd1e58 | 670 | // Align to actual cycle count for the packet which is going to be scheduled. |
a0e02331 TS |
671 | // This module queued the same number of isochronous cycle as the size of queue |
672 | // to kip isochronous cycle, therefore it's OK to just increment the cycle by | |
673 | // the size of queue for scheduled cycle. | |
674 | static inline u32 compute_it_cycle(const __be32 ctx_header_tstamp, | |
675 | unsigned int queue_size) | |
26cd1e58 TS |
676 | { |
677 | u32 cycle = compute_cycle_count(ctx_header_tstamp); | |
a0e02331 | 678 | return increment_cycle_count(cycle, queue_size); |
26cd1e58 TS |
679 | } |
680 | ||
753e7179 TS |
681 | static int generate_device_pkt_descs(struct amdtp_stream *s, |
682 | struct pkt_desc *descs, | |
683 | const __be32 *ctx_header, | |
684 | unsigned int packets) | |
685 | { | |
686 | unsigned int dbc = s->data_block_counter; | |
687 | int i; | |
688 | int err; | |
689 | ||
690 | for (i = 0; i < packets; ++i) { | |
691 | struct pkt_desc *desc = descs + i; | |
a0e02331 | 692 | unsigned int index = (s->packet_index + i) % s->queue_size; |
753e7179 TS |
693 | unsigned int cycle; |
694 | unsigned int payload_length; | |
695 | unsigned int data_blocks; | |
696 | unsigned int syt; | |
697 | ||
698 | cycle = compute_cycle_count(ctx_header[1]); | |
699 | ||
700 | err = parse_ir_ctx_header(s, cycle, ctx_header, &payload_length, | |
701 | &data_blocks, &dbc, &syt, i); | |
702 | if (err < 0) | |
703 | return err; | |
704 | ||
705 | desc->cycle = cycle; | |
706 | desc->syt = syt; | |
707 | desc->data_blocks = data_blocks; | |
708 | desc->data_block_counter = dbc; | |
709 | desc->ctx_payload = s->buffer.packets[index].buffer; | |
710 | ||
711 | if (!(s->flags & CIP_DBC_IS_END_EVENT)) | |
712 | dbc = (dbc + desc->data_blocks) & 0xff; | |
713 | ||
714 | ctx_header += | |
715 | s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header); | |
716 | } | |
717 | ||
718 | s->data_block_counter = dbc; | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
f4f6ae7b TS |
723 | static void generate_ideal_pkt_descs(struct amdtp_stream *s, |
724 | struct pkt_desc *descs, | |
725 | const __be32 *ctx_header, | |
726 | unsigned int packets) | |
727 | { | |
728 | unsigned int dbc = s->data_block_counter; | |
729 | int i; | |
730 | ||
731 | for (i = 0; i < packets; ++i) { | |
732 | struct pkt_desc *desc = descs + i; | |
a0e02331 | 733 | unsigned int index = (s->packet_index + i) % s->queue_size; |
f4f6ae7b | 734 | |
a0e02331 | 735 | desc->cycle = compute_it_cycle(*ctx_header, s->queue_size); |
f4f6ae7b TS |
736 | desc->syt = calculate_syt(s, desc->cycle); |
737 | desc->data_blocks = calculate_data_blocks(s, desc->syt); | |
738 | ||
739 | if (s->flags & CIP_DBC_IS_END_EVENT) | |
740 | dbc = (dbc + desc->data_blocks) & 0xff; | |
741 | ||
742 | desc->data_block_counter = dbc; | |
743 | ||
744 | if (!(s->flags & CIP_DBC_IS_END_EVENT)) | |
745 | dbc = (dbc + desc->data_blocks) & 0xff; | |
746 | ||
747 | desc->ctx_payload = s->buffer.packets[index].buffer; | |
748 | ||
749 | ++ctx_header; | |
750 | } | |
751 | ||
752 | s->data_block_counter = dbc; | |
753 | } | |
754 | ||
fce9b013 TS |
755 | static inline void cancel_stream(struct amdtp_stream *s) |
756 | { | |
757 | s->packet_index = -1; | |
758 | if (in_interrupt()) | |
759 | amdtp_stream_pcm_abort(s); | |
760 | WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN); | |
761 | } | |
762 | ||
0f5cfcb2 TS |
763 | static void process_ctx_payloads(struct amdtp_stream *s, |
764 | const struct pkt_desc *descs, | |
765 | unsigned int packets) | |
31ef9134 | 766 | { |
9a738ad1 TS |
767 | struct snd_pcm_substream *pcm; |
768 | unsigned int pcm_frames; | |
5e2ece0f | 769 | |
9a738ad1 TS |
770 | pcm = READ_ONCE(s->pcm); |
771 | pcm_frames = s->process_ctx_payloads(s, descs, packets, pcm); | |
772 | if (pcm) | |
773 | update_pcm_pointers(s, pcm, pcm_frames); | |
0f5cfcb2 TS |
774 | } |
775 | ||
776 | static void out_stream_callback(struct fw_iso_context *context, u32 tstamp, | |
777 | size_t header_length, void *header, | |
778 | void *private_data) | |
779 | { | |
780 | struct amdtp_stream *s = private_data; | |
781 | const __be32 *ctx_header = header; | |
a0e02331 | 782 | unsigned int packets; |
0f5cfcb2 TS |
783 | int i; |
784 | ||
785 | if (s->packet_index < 0) | |
786 | return; | |
787 | ||
a0e02331 TS |
788 | // Calculate the number of packets in buffer and check XRUN. |
789 | packets = header_length / sizeof(*ctx_header); | |
790 | ||
0f5cfcb2 TS |
791 | generate_ideal_pkt_descs(s, s->pkt_descs, ctx_header, packets); |
792 | ||
793 | process_ctx_payloads(s, s->pkt_descs, packets); | |
5e2ece0f TS |
794 | |
795 | for (i = 0; i < packets; ++i) { | |
796 | const struct pkt_desc *desc = s->pkt_descs + i; | |
f4f6ae7b | 797 | unsigned int syt; |
6bc1a269 TS |
798 | struct { |
799 | struct fw_iso_packet params; | |
800 | __be32 header[IT_PKT_HEADER_SIZE_CIP / sizeof(__be32)]; | |
801 | } template = { {0}, {0} }; | |
31ef9134 | 802 | |
f4f6ae7b TS |
803 | if (s->ctx_data.rx.syt_override < 0) |
804 | syt = desc->syt; | |
805 | else | |
3baf3053 TS |
806 | syt = s->ctx_data.rx.syt_override; |
807 | ||
f4f6ae7b TS |
808 | build_it_pkt_header(s, desc->cycle, &template.params, |
809 | desc->data_blocks, desc->data_block_counter, | |
810 | syt, i); | |
6bc1a269 TS |
811 | |
812 | if (queue_out_packet(s, &template.params) < 0) { | |
fce9b013 | 813 | cancel_stream(s); |
a4103bd7 TS |
814 | return; |
815 | } | |
ccccad86 | 816 | } |
a4103bd7 | 817 | |
13882a82 | 818 | fw_iso_context_queue_flush(s->context); |
31ef9134 CL |
819 | } |
820 | ||
73fc7f08 | 821 | static void in_stream_callback(struct fw_iso_context *context, u32 tstamp, |
2b3fc456 TS |
822 | size_t header_length, void *header, |
823 | void *private_data) | |
824 | { | |
825 | struct amdtp_stream *s = private_data; | |
753e7179 | 826 | unsigned int packets; |
cc4f8e91 | 827 | __be32 *ctx_header = header; |
753e7179 TS |
828 | int i; |
829 | int err; | |
2b3fc456 | 830 | |
a4103bd7 TS |
831 | if (s->packet_index < 0) |
832 | return; | |
833 | ||
a0e02331 | 834 | // Calculate the number of packets in buffer and check XRUN. |
d3d10a4a | 835 | packets = header_length / s->ctx_data.tx.ctx_header_size; |
f90e2ded | 836 | |
753e7179 TS |
837 | err = generate_device_pkt_descs(s, s->pkt_descs, ctx_header, packets); |
838 | if (err < 0) { | |
839 | if (err != -EAGAIN) { | |
840 | cancel_stream(s); | |
841 | return; | |
842 | } | |
5e2ece0f | 843 | } else { |
0f5cfcb2 | 844 | process_ctx_payloads(s, s->pkt_descs, packets); |
5e2ece0f TS |
845 | } |
846 | ||
847 | for (i = 0; i < packets; ++i) { | |
848 | struct fw_iso_packet params = {0}; | |
2b3fc456 | 849 | |
753e7179 TS |
850 | if (queue_in_packet(s, ¶ms) < 0) { |
851 | cancel_stream(s); | |
852 | return; | |
853 | } | |
7b3b0d85 TS |
854 | } |
855 | ||
2b3fc456 TS |
856 | fw_iso_context_queue_flush(s->context); |
857 | } | |
858 | ||
7b3b0d85 TS |
859 | /* this is executed one time */ |
860 | static void amdtp_stream_first_callback(struct fw_iso_context *context, | |
73fc7f08 | 861 | u32 tstamp, size_t header_length, |
7b3b0d85 TS |
862 | void *header, void *private_data) |
863 | { | |
864 | struct amdtp_stream *s = private_data; | |
26cd1e58 | 865 | const __be32 *ctx_header = header; |
a04513f8 | 866 | u32 cycle; |
7b3b0d85 TS |
867 | |
868 | /* | |
869 | * For in-stream, first packet has come. | |
870 | * For out-stream, prepared to transmit first packet | |
871 | */ | |
872 | s->callbacked = true; | |
873 | wake_up(&s->callback_wait); | |
874 | ||
a04513f8 | 875 | if (s->direction == AMDTP_IN_STREAM) { |
26cd1e58 | 876 | cycle = compute_cycle_count(ctx_header[1]); |
cc4f8e91 | 877 | |
7b3b0d85 | 878 | context->callback.sc = in_stream_callback; |
a04513f8 | 879 | } else { |
a0e02331 | 880 | cycle = compute_it_cycle(*ctx_header, s->queue_size); |
26cd1e58 | 881 | |
7b3b0d85 | 882 | context->callback.sc = out_stream_callback; |
a04513f8 TS |
883 | } |
884 | ||
885 | s->start_cycle = cycle; | |
7b3b0d85 | 886 | |
73fc7f08 | 887 | context->callback.sc(context, tstamp, header_length, header, s); |
7b3b0d85 TS |
888 | } |
889 | ||
31ef9134 | 890 | /** |
be4a2894 TS |
891 | * amdtp_stream_start - start transferring packets |
892 | * @s: the AMDTP stream to start | |
31ef9134 CL |
893 | * @channel: the isochronous channel on the bus |
894 | * @speed: firewire speed code | |
895 | * | |
896 | * The stream cannot be started until it has been configured with | |
be4a2894 TS |
897 | * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI |
898 | * device can be started. | |
31ef9134 | 899 | */ |
a0e02331 TS |
900 | static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed, |
901 | struct amdtp_domain *d) | |
31ef9134 CL |
902 | { |
903 | static const struct { | |
904 | unsigned int data_block; | |
905 | unsigned int syt_offset; | |
d3d10a4a | 906 | } *entry, initial_state[] = { |
31ef9134 CL |
907 | [CIP_SFC_32000] = { 4, 3072 }, |
908 | [CIP_SFC_48000] = { 6, 1024 }, | |
909 | [CIP_SFC_96000] = { 12, 1024 }, | |
910 | [CIP_SFC_192000] = { 24, 1024 }, | |
911 | [CIP_SFC_44100] = { 0, 67 }, | |
912 | [CIP_SFC_88200] = { 0, 67 }, | |
913 | [CIP_SFC_176400] = { 0, 67 }, | |
914 | }; | |
a0e02331 | 915 | unsigned int events_per_buffer = d->events_per_buffer; |
d3d10a4a | 916 | unsigned int ctx_header_size; |
f11453c7 | 917 | unsigned int max_ctx_payload_size; |
2b3fc456 | 918 | enum dma_data_direction dir; |
7ab56645 | 919 | int type, tag, err; |
31ef9134 CL |
920 | |
921 | mutex_lock(&s->mutex); | |
922 | ||
be4a2894 | 923 | if (WARN_ON(amdtp_stream_running(s) || |
4b7da117 | 924 | (s->data_block_quadlets < 1))) { |
31ef9134 CL |
925 | err = -EBADFD; |
926 | goto err_unlock; | |
927 | } | |
928 | ||
d3d10a4a | 929 | if (s->direction == AMDTP_IN_STREAM) { |
b6bc8123 | 930 | s->data_block_counter = UINT_MAX; |
d3d10a4a TS |
931 | } else { |
932 | entry = &initial_state[s->sfc]; | |
933 | ||
b6bc8123 | 934 | s->data_block_counter = 0; |
d3d10a4a TS |
935 | s->ctx_data.rx.data_block_state = entry->data_block; |
936 | s->ctx_data.rx.syt_offset_state = entry->syt_offset; | |
937 | s->ctx_data.rx.last_syt_offset = TICKS_PER_CYCLE; | |
938 | } | |
31ef9134 | 939 | |
2b3fc456 TS |
940 | /* initialize packet buffer */ |
941 | if (s->direction == AMDTP_IN_STREAM) { | |
942 | dir = DMA_FROM_DEVICE; | |
943 | type = FW_ISO_CONTEXT_RECEIVE; | |
f11453c7 TS |
944 | if (!(s->flags & CIP_NO_HEADER)) |
945 | ctx_header_size = IR_CTX_HEADER_SIZE_CIP; | |
946 | else | |
947 | ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP; | |
b18f0cfa TS |
948 | |
949 | max_ctx_payload_size = amdtp_stream_get_max_payload(s) - | |
950 | ctx_header_size; | |
2b3fc456 TS |
951 | } else { |
952 | dir = DMA_TO_DEVICE; | |
953 | type = FW_ISO_CONTEXT_TRANSMIT; | |
df9160b9 | 954 | ctx_header_size = 0; // No effect for IT context. |
f11453c7 | 955 | |
b18f0cfa TS |
956 | max_ctx_payload_size = amdtp_stream_get_max_payload(s); |
957 | if (!(s->flags & CIP_NO_HEADER)) | |
958 | max_ctx_payload_size -= IT_PKT_HEADER_SIZE_CIP; | |
959 | } | |
f11453c7 | 960 | |
a0e02331 TS |
961 | if (events_per_buffer == 0) |
962 | events_per_buffer = INTERRUPT_INTERVAL * 3; | |
963 | ||
964 | s->queue_size = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_buffer, | |
965 | amdtp_rate_table[s->sfc]); | |
966 | ||
967 | err = iso_packets_buffer_init(&s->buffer, s->unit, s->queue_size, | |
f11453c7 | 968 | max_ctx_payload_size, dir); |
31ef9134 CL |
969 | if (err < 0) |
970 | goto err_unlock; | |
971 | ||
972 | s->context = fw_iso_context_create(fw_parent_device(s->unit)->card, | |
d3d10a4a TS |
973 | type, channel, speed, ctx_header_size, |
974 | amdtp_stream_first_callback, s); | |
31ef9134 CL |
975 | if (IS_ERR(s->context)) { |
976 | err = PTR_ERR(s->context); | |
977 | if (err == -EBUSY) | |
978 | dev_err(&s->unit->device, | |
be4a2894 | 979 | "no free stream on this controller\n"); |
31ef9134 CL |
980 | goto err_buffer; |
981 | } | |
982 | ||
be4a2894 | 983 | amdtp_stream_update(s); |
31ef9134 | 984 | |
d3d10a4a | 985 | if (s->direction == AMDTP_IN_STREAM) { |
f11453c7 | 986 | s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size; |
d3d10a4a TS |
987 | s->ctx_data.tx.ctx_header_size = ctx_header_size; |
988 | } | |
52759c09 | 989 | |
3b196c39 TS |
990 | if (s->flags & CIP_NO_HEADER) |
991 | s->tag = TAG_NO_CIP_HEADER; | |
992 | else | |
993 | s->tag = TAG_CIP; | |
994 | ||
a0e02331 | 995 | s->pkt_descs = kcalloc(s->queue_size, sizeof(*s->pkt_descs), |
04130cf8 TS |
996 | GFP_KERNEL); |
997 | if (!s->pkt_descs) { | |
998 | err = -ENOMEM; | |
999 | goto err_context; | |
1000 | } | |
1001 | ||
ec00f5e4 | 1002 | s->packet_index = 0; |
4b7da117 | 1003 | do { |
6007bf54 | 1004 | struct fw_iso_packet params; |
b18f0cfa | 1005 | if (s->direction == AMDTP_IN_STREAM) { |
6007bf54 | 1006 | err = queue_in_packet(s, ¶ms); |
b18f0cfa TS |
1007 | } else { |
1008 | params.header_length = 0; | |
1009 | params.payload_length = 0; | |
1010 | err = queue_out_packet(s, ¶ms); | |
1011 | } | |
4b7da117 | 1012 | if (err < 0) |
04130cf8 | 1013 | goto err_pkt_descs; |
4b7da117 | 1014 | } while (s->packet_index > 0); |
31ef9134 | 1015 | |
2b3fc456 | 1016 | /* NOTE: TAG1 matches CIP. This just affects in stream. */ |
7ab56645 | 1017 | tag = FW_ISO_CONTEXT_MATCH_TAG1; |
3b196c39 | 1018 | if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER)) |
7ab56645 TS |
1019 | tag |= FW_ISO_CONTEXT_MATCH_TAG0; |
1020 | ||
7b3b0d85 | 1021 | s->callbacked = false; |
7ab56645 | 1022 | err = fw_iso_context_start(s->context, -1, 0, tag); |
31ef9134 | 1023 | if (err < 0) |
04130cf8 | 1024 | goto err_pkt_descs; |
31ef9134 CL |
1025 | |
1026 | mutex_unlock(&s->mutex); | |
1027 | ||
1028 | return 0; | |
04130cf8 TS |
1029 | err_pkt_descs: |
1030 | kfree(s->pkt_descs); | |
31ef9134 CL |
1031 | err_context: |
1032 | fw_iso_context_destroy(s->context); | |
1033 | s->context = ERR_PTR(-1); | |
1034 | err_buffer: | |
1035 | iso_packets_buffer_destroy(&s->buffer, s->unit); | |
1036 | err_unlock: | |
1037 | mutex_unlock(&s->mutex); | |
1038 | ||
1039 | return err; | |
1040 | } | |
31ef9134 | 1041 | |
e9148ddd | 1042 | /** |
be4a2894 TS |
1043 | * amdtp_stream_pcm_pointer - get the PCM buffer position |
1044 | * @s: the AMDTP stream that transports the PCM data | |
e9148ddd CL |
1045 | * |
1046 | * Returns the current buffer position, in frames. | |
1047 | */ | |
be4a2894 | 1048 | unsigned long amdtp_stream_pcm_pointer(struct amdtp_stream *s) |
e9148ddd | 1049 | { |
1dba9db0 TS |
1050 | /* |
1051 | * This function is called in software IRQ context of period_tasklet or | |
1052 | * process context. | |
1053 | * | |
1054 | * When the software IRQ context was scheduled by software IRQ context | |
1055 | * of IR/IT contexts, queued packets were already handled. Therefore, | |
1056 | * no need to flush the queue in buffer anymore. | |
1057 | * | |
1058 | * When the process context reach here, some packets will be already | |
1059 | * queued in the buffer. These packets should be handled immediately | |
1060 | * to keep better granularity of PCM pointer. | |
1061 | * | |
1062 | * Later, the process context will sometimes schedules software IRQ | |
1063 | * context of the period_tasklet. Then, no need to flush the queue by | |
1064 | * the same reason as described for IR/IT contexts. | |
1065 | */ | |
1066 | if (!in_interrupt() && amdtp_stream_running(s)) | |
92b862c7 | 1067 | fw_iso_context_flush_completions(s->context); |
e9148ddd | 1068 | |
6aa7de05 | 1069 | return READ_ONCE(s->pcm_buffer_pointer); |
e9148ddd | 1070 | } |
be4a2894 | 1071 | EXPORT_SYMBOL(amdtp_stream_pcm_pointer); |
e9148ddd | 1072 | |
875becf8 TS |
1073 | /** |
1074 | * amdtp_stream_pcm_ack - acknowledge queued PCM frames | |
1075 | * @s: the AMDTP stream that transfers the PCM frames | |
1076 | * | |
1077 | * Returns zero always. | |
1078 | */ | |
1079 | int amdtp_stream_pcm_ack(struct amdtp_stream *s) | |
1080 | { | |
1081 | /* | |
1082 | * Process isochronous packets for recent isochronous cycle to handle | |
1083 | * queued PCM frames. | |
1084 | */ | |
1085 | if (amdtp_stream_running(s)) | |
1086 | fw_iso_context_flush_completions(s->context); | |
1087 | ||
1088 | return 0; | |
1089 | } | |
1090 | EXPORT_SYMBOL(amdtp_stream_pcm_ack); | |
1091 | ||
31ef9134 | 1092 | /** |
be4a2894 TS |
1093 | * amdtp_stream_update - update the stream after a bus reset |
1094 | * @s: the AMDTP stream | |
31ef9134 | 1095 | */ |
be4a2894 | 1096 | void amdtp_stream_update(struct amdtp_stream *s) |
31ef9134 | 1097 | { |
9a2820c1 | 1098 | /* Precomputing. */ |
6aa7de05 MR |
1099 | WRITE_ONCE(s->source_node_id_field, |
1100 | (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK); | |
31ef9134 | 1101 | } |
be4a2894 | 1102 | EXPORT_SYMBOL(amdtp_stream_update); |
31ef9134 CL |
1103 | |
1104 | /** | |
be4a2894 TS |
1105 | * amdtp_stream_stop - stop sending packets |
1106 | * @s: the AMDTP stream to stop | |
31ef9134 CL |
1107 | * |
1108 | * All PCM and MIDI devices of the stream must be stopped before the stream | |
1109 | * itself can be stopped. | |
1110 | */ | |
74f94e41 | 1111 | static void amdtp_stream_stop(struct amdtp_stream *s) |
31ef9134 CL |
1112 | { |
1113 | mutex_lock(&s->mutex); | |
1114 | ||
be4a2894 | 1115 | if (!amdtp_stream_running(s)) { |
31ef9134 CL |
1116 | mutex_unlock(&s->mutex); |
1117 | return; | |
1118 | } | |
1119 | ||
76fb8789 | 1120 | tasklet_kill(&s->period_tasklet); |
31ef9134 CL |
1121 | fw_iso_context_stop(s->context); |
1122 | fw_iso_context_destroy(s->context); | |
1123 | s->context = ERR_PTR(-1); | |
1124 | iso_packets_buffer_destroy(&s->buffer, s->unit); | |
04130cf8 | 1125 | kfree(s->pkt_descs); |
31ef9134 | 1126 | |
7b3b0d85 TS |
1127 | s->callbacked = false; |
1128 | ||
31ef9134 CL |
1129 | mutex_unlock(&s->mutex); |
1130 | } | |
31ef9134 CL |
1131 | |
1132 | /** | |
be4a2894 | 1133 | * amdtp_stream_pcm_abort - abort the running PCM device |
31ef9134 CL |
1134 | * @s: the AMDTP stream about to be stopped |
1135 | * | |
1136 | * If the isochronous stream needs to be stopped asynchronously, call this | |
1137 | * function first to stop the PCM device. | |
1138 | */ | |
be4a2894 | 1139 | void amdtp_stream_pcm_abort(struct amdtp_stream *s) |
31ef9134 CL |
1140 | { |
1141 | struct snd_pcm_substream *pcm; | |
1142 | ||
6aa7de05 | 1143 | pcm = READ_ONCE(s->pcm); |
1fb8510c TI |
1144 | if (pcm) |
1145 | snd_pcm_stop_xrun(pcm); | |
31ef9134 | 1146 | } |
be4a2894 | 1147 | EXPORT_SYMBOL(amdtp_stream_pcm_abort); |
3ec3d7a3 TS |
1148 | |
1149 | /** | |
1150 | * amdtp_domain_init - initialize an AMDTP domain structure | |
1151 | * @d: the AMDTP domain to initialize. | |
1152 | */ | |
1153 | int amdtp_domain_init(struct amdtp_domain *d) | |
1154 | { | |
1155 | INIT_LIST_HEAD(&d->streams); | |
1156 | ||
d68c3123 TS |
1157 | d->events_per_period = 0; |
1158 | ||
3ec3d7a3 TS |
1159 | return 0; |
1160 | } | |
1161 | EXPORT_SYMBOL_GPL(amdtp_domain_init); | |
1162 | ||
1163 | /** | |
1164 | * amdtp_domain_destroy - destroy an AMDTP domain structure | |
1165 | * @d: the AMDTP domain to destroy. | |
1166 | */ | |
1167 | void amdtp_domain_destroy(struct amdtp_domain *d) | |
1168 | { | |
8d0d5c3f TS |
1169 | // At present nothing to do. |
1170 | return; | |
3ec3d7a3 TS |
1171 | } |
1172 | EXPORT_SYMBOL_GPL(amdtp_domain_destroy); | |
6261f90b | 1173 | |
157a53ee TS |
1174 | /** |
1175 | * amdtp_domain_add_stream - register isoc context into the domain. | |
1176 | * @d: the AMDTP domain. | |
1177 | * @s: the AMDTP stream. | |
1178 | * @channel: the isochronous channel on the bus. | |
1179 | * @speed: firewire speed code. | |
1180 | */ | |
1181 | int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s, | |
1182 | int channel, int speed) | |
1183 | { | |
1184 | struct amdtp_stream *tmp; | |
1185 | ||
1186 | list_for_each_entry(tmp, &d->streams, list) { | |
1187 | if (s == tmp) | |
1188 | return -EBUSY; | |
1189 | } | |
1190 | ||
1191 | list_add(&s->list, &d->streams); | |
1192 | ||
1193 | s->channel = channel; | |
1194 | s->speed = speed; | |
1195 | ||
1196 | return 0; | |
1197 | } | |
1198 | EXPORT_SYMBOL_GPL(amdtp_domain_add_stream); | |
1199 | ||
9b4702b0 TS |
1200 | /** |
1201 | * amdtp_domain_start - start sending packets for isoc context in the domain. | |
1202 | * @d: the AMDTP domain. | |
1203 | */ | |
1204 | int amdtp_domain_start(struct amdtp_domain *d) | |
1205 | { | |
1206 | struct amdtp_stream *s; | |
1207 | int err = 0; | |
1208 | ||
1209 | list_for_each_entry(s, &d->streams, list) { | |
a0e02331 | 1210 | err = amdtp_stream_start(s, s->channel, s->speed, d); |
9b4702b0 TS |
1211 | if (err < 0) |
1212 | break; | |
1213 | } | |
1214 | ||
1215 | if (err < 0) { | |
1216 | list_for_each_entry(s, &d->streams, list) | |
1217 | amdtp_stream_stop(s); | |
1218 | } | |
1219 | ||
1220 | return err; | |
1221 | } | |
1222 | EXPORT_SYMBOL_GPL(amdtp_domain_start); | |
1223 | ||
6261f90b TS |
1224 | /** |
1225 | * amdtp_domain_stop - stop sending packets for isoc context in the same domain. | |
1226 | * @d: the AMDTP domain to which the isoc contexts belong. | |
1227 | */ | |
1228 | void amdtp_domain_stop(struct amdtp_domain *d) | |
1229 | { | |
1230 | struct amdtp_stream *s, *next; | |
1231 | ||
1232 | list_for_each_entry_safe(s, next, &d->streams, list) { | |
1233 | list_del(&s->list); | |
1234 | ||
1235 | amdtp_stream_stop(s); | |
1236 | } | |
d68c3123 TS |
1237 | |
1238 | d->events_per_period = 0; | |
6261f90b TS |
1239 | } |
1240 | EXPORT_SYMBOL_GPL(amdtp_domain_stop); |