Commit | Line | Data |
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da607e19 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
31ef9134 CL |
2 | /* |
3 | * Audio and Music Data Transmission Protocol (IEC 61883-6) streams | |
4 | * with Common Isochronous Packet (IEC 61883-1) headers | |
5 | * | |
6 | * Copyright (c) Clemens Ladisch <clemens@ladisch.de> | |
31ef9134 CL |
7 | */ |
8 | ||
9 | #include <linux/device.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/firewire.h> | |
acfedcbe | 12 | #include <linux/firewire-constants.h> |
31ef9134 CL |
13 | #include <linux/module.h> |
14 | #include <linux/slab.h> | |
15 | #include <sound/pcm.h> | |
7b2d99fa | 16 | #include <sound/pcm_params.h> |
d67c46b9 | 17 | #include "amdtp-stream.h" |
31ef9134 CL |
18 | |
19 | #define TICKS_PER_CYCLE 3072 | |
20 | #define CYCLES_PER_SECOND 8000 | |
21 | #define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND) | |
22 | ||
10aa8e4a TS |
23 | #define OHCI_MAX_SECOND 8 |
24 | ||
0c95c1d6 TS |
25 | /* Always support Linux tracing subsystem. */ |
26 | #define CREATE_TRACE_POINTS | |
27 | #include "amdtp-stream-trace.h" | |
28 | ||
ca5b5050 | 29 | #define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */ |
31ef9134 | 30 | |
b445db44 TS |
31 | /* isochronous header parameters */ |
32 | #define ISO_DATA_LENGTH_SHIFT 16 | |
3b196c39 | 33 | #define TAG_NO_CIP_HEADER 0 |
31ef9134 CL |
34 | #define TAG_CIP 1 |
35 | ||
b445db44 | 36 | /* common isochronous packet header parameters */ |
9a2820c1 TS |
37 | #define CIP_EOH_SHIFT 31 |
38 | #define CIP_EOH (1u << CIP_EOH_SHIFT) | |
b445db44 | 39 | #define CIP_EOH_MASK 0x80000000 |
9a2820c1 TS |
40 | #define CIP_SID_SHIFT 24 |
41 | #define CIP_SID_MASK 0x3f000000 | |
42 | #define CIP_DBS_MASK 0x00ff0000 | |
43 | #define CIP_DBS_SHIFT 16 | |
9863874f TS |
44 | #define CIP_SPH_MASK 0x00000400 |
45 | #define CIP_SPH_SHIFT 10 | |
9a2820c1 TS |
46 | #define CIP_DBC_MASK 0x000000ff |
47 | #define CIP_FMT_SHIFT 24 | |
b445db44 | 48 | #define CIP_FMT_MASK 0x3f000000 |
9a2820c1 TS |
49 | #define CIP_FDF_MASK 0x00ff0000 |
50 | #define CIP_FDF_SHIFT 16 | |
b445db44 TS |
51 | #define CIP_SYT_MASK 0x0000ffff |
52 | #define CIP_SYT_NO_INFO 0xffff | |
b445db44 | 53 | |
51c29fd2 | 54 | /* Audio and Music transfer protocol specific parameters */ |
414ba022 | 55 | #define CIP_FMT_AM 0x10 |
2b3fc456 | 56 | #define AMDTP_FDF_NO_DATA 0xff |
31ef9134 | 57 | |
f11453c7 TS |
58 | // For iso header, tstamp and 2 CIP header. |
59 | #define IR_CTX_HEADER_SIZE_CIP 16 | |
60 | // For iso header and tstamp. | |
61 | #define IR_CTX_HEADER_SIZE_NO_CIP 8 | |
cc4f8e91 | 62 | #define HEADER_TSTAMP_MASK 0x0000ffff |
4b7da117 | 63 | |
b18f0cfa TS |
64 | #define IT_PKT_HEADER_SIZE_CIP 8 // For 2 CIP header. |
65 | #define IT_PKT_HEADER_SIZE_NO_CIP 0 // Nothing. | |
66 | ||
2b3d2987 | 67 | static void pcm_period_work(struct work_struct *work); |
76fb8789 | 68 | |
31ef9134 | 69 | /** |
be4a2894 TS |
70 | * amdtp_stream_init - initialize an AMDTP stream structure |
71 | * @s: the AMDTP stream to initialize | |
31ef9134 | 72 | * @unit: the target of the stream |
3ff7e8f0 | 73 | * @dir: the direction of stream |
31ef9134 | 74 | * @flags: the packet transmission method to use |
5955815e | 75 | * @fmt: the value of fmt field in CIP header |
9a738ad1 | 76 | * @process_ctx_payloads: callback handler to process payloads of isoc context |
df075fee | 77 | * @protocol_size: the size to allocate newly for protocol |
31ef9134 | 78 | */ |
be4a2894 | 79 | int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit, |
5955815e | 80 | enum amdtp_stream_direction dir, enum cip_flags flags, |
df075fee | 81 | unsigned int fmt, |
9a738ad1 | 82 | amdtp_stream_process_ctx_payloads_t process_ctx_payloads, |
df075fee | 83 | unsigned int protocol_size) |
31ef9134 | 84 | { |
9a738ad1 | 85 | if (process_ctx_payloads == NULL) |
df075fee TS |
86 | return -EINVAL; |
87 | ||
88 | s->protocol = kzalloc(protocol_size, GFP_KERNEL); | |
89 | if (!s->protocol) | |
90 | return -ENOMEM; | |
91 | ||
c6f224dc | 92 | s->unit = unit; |
3ff7e8f0 | 93 | s->direction = dir; |
31ef9134 CL |
94 | s->flags = flags; |
95 | s->context = ERR_PTR(-1); | |
96 | mutex_init(&s->mutex); | |
2b3d2987 | 97 | INIT_WORK(&s->period_work, pcm_period_work); |
ec00f5e4 | 98 | s->packet_index = 0; |
31ef9134 | 99 | |
7b3b0d85 TS |
100 | init_waitqueue_head(&s->callback_wait); |
101 | s->callbacked = false; | |
7b3b0d85 | 102 | |
5955815e | 103 | s->fmt = fmt; |
9a738ad1 | 104 | s->process_ctx_payloads = process_ctx_payloads; |
414ba022 | 105 | |
3baf3053 TS |
106 | if (dir == AMDTP_OUT_STREAM) |
107 | s->ctx_data.rx.syt_override = -1; | |
108 | ||
31ef9134 CL |
109 | return 0; |
110 | } | |
be4a2894 | 111 | EXPORT_SYMBOL(amdtp_stream_init); |
31ef9134 CL |
112 | |
113 | /** | |
be4a2894 TS |
114 | * amdtp_stream_destroy - free stream resources |
115 | * @s: the AMDTP stream to destroy | |
31ef9134 | 116 | */ |
be4a2894 | 117 | void amdtp_stream_destroy(struct amdtp_stream *s) |
31ef9134 | 118 | { |
44c376b9 TS |
119 | /* Not initialized. */ |
120 | if (s->protocol == NULL) | |
121 | return; | |
122 | ||
be4a2894 | 123 | WARN_ON(amdtp_stream_running(s)); |
df075fee | 124 | kfree(s->protocol); |
31ef9134 | 125 | mutex_destroy(&s->mutex); |
31ef9134 | 126 | } |
be4a2894 | 127 | EXPORT_SYMBOL(amdtp_stream_destroy); |
31ef9134 | 128 | |
c5280e99 | 129 | const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = { |
a7304e3b CL |
130 | [CIP_SFC_32000] = 8, |
131 | [CIP_SFC_44100] = 8, | |
132 | [CIP_SFC_48000] = 8, | |
133 | [CIP_SFC_88200] = 16, | |
134 | [CIP_SFC_96000] = 16, | |
135 | [CIP_SFC_176400] = 32, | |
136 | [CIP_SFC_192000] = 32, | |
137 | }; | |
138 | EXPORT_SYMBOL(amdtp_syt_intervals); | |
139 | ||
f9503a68 | 140 | const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = { |
1017abed TS |
141 | [CIP_SFC_32000] = 32000, |
142 | [CIP_SFC_44100] = 44100, | |
143 | [CIP_SFC_48000] = 48000, | |
144 | [CIP_SFC_88200] = 88200, | |
145 | [CIP_SFC_96000] = 96000, | |
146 | [CIP_SFC_176400] = 176400, | |
147 | [CIP_SFC_192000] = 192000, | |
148 | }; | |
149 | EXPORT_SYMBOL(amdtp_rate_table); | |
150 | ||
59502295 TS |
151 | static int apply_constraint_to_size(struct snd_pcm_hw_params *params, |
152 | struct snd_pcm_hw_rule *rule) | |
153 | { | |
154 | struct snd_interval *s = hw_param_interval(params, rule->var); | |
155 | const struct snd_interval *r = | |
156 | hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE); | |
826b5de9 TS |
157 | struct snd_interval t = {0}; |
158 | unsigned int step = 0; | |
59502295 TS |
159 | int i; |
160 | ||
161 | for (i = 0; i < CIP_SFC_COUNT; ++i) { | |
826b5de9 TS |
162 | if (snd_interval_test(r, amdtp_rate_table[i])) |
163 | step = max(step, amdtp_syt_intervals[i]); | |
59502295 TS |
164 | } |
165 | ||
826b5de9 TS |
166 | t.min = roundup(s->min, step); |
167 | t.max = rounddown(s->max, step); | |
168 | t.integer = 1; | |
59502295 TS |
169 | |
170 | return snd_interval_refine(s, &t); | |
171 | } | |
172 | ||
7b2d99fa TS |
173 | /** |
174 | * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream | |
175 | * @s: the AMDTP stream, which must be initialized. | |
176 | * @runtime: the PCM substream runtime | |
177 | */ | |
178 | int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s, | |
179 | struct snd_pcm_runtime *runtime) | |
180 | { | |
55799c5a | 181 | struct snd_pcm_hardware *hw = &runtime->hw; |
99921ec6 TS |
182 | unsigned int ctx_header_size; |
183 | unsigned int maximum_usec_per_period; | |
7b2d99fa TS |
184 | int err; |
185 | ||
55799c5a TS |
186 | hw->info = SNDRV_PCM_INFO_BATCH | |
187 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
188 | SNDRV_PCM_INFO_INTERLEAVED | | |
189 | SNDRV_PCM_INFO_JOINT_DUPLEX | | |
190 | SNDRV_PCM_INFO_MMAP | | |
191 | SNDRV_PCM_INFO_MMAP_VALID; | |
192 | ||
193 | /* SNDRV_PCM_INFO_BATCH */ | |
194 | hw->periods_min = 2; | |
195 | hw->periods_max = UINT_MAX; | |
196 | ||
197 | /* bytes for a frame */ | |
198 | hw->period_bytes_min = 4 * hw->channels_max; | |
199 | ||
200 | /* Just to prevent from allocating much pages. */ | |
201 | hw->period_bytes_max = hw->period_bytes_min * 2048; | |
202 | hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min; | |
203 | ||
99921ec6 TS |
204 | // Linux driver for 1394 OHCI controller voluntarily flushes isoc |
205 | // context when total size of accumulated context header reaches | |
2b3d2987 | 206 | // PAGE_SIZE. This kicks work for the isoc context and brings |
99921ec6 TS |
207 | // callback in the middle of scheduled interrupts. |
208 | // Although AMDTP streams in the same domain use the same events per | |
209 | // IRQ, use the largest size of context header between IT/IR contexts. | |
210 | // Here, use the value of context header in IR context is for both | |
211 | // contexts. | |
212 | if (!(s->flags & CIP_NO_HEADER)) | |
213 | ctx_header_size = IR_CTX_HEADER_SIZE_CIP; | |
214 | else | |
215 | ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP; | |
216 | maximum_usec_per_period = USEC_PER_SEC * PAGE_SIZE / | |
217 | CYCLES_PER_SECOND / ctx_header_size; | |
218 | ||
f706df4f TS |
219 | // In IEC 61883-6, one isoc packet can transfer events up to the value |
220 | // of syt interval. This comes from the interval of isoc cycle. As 1394 | |
221 | // OHCI controller can generate hardware IRQ per isoc packet, the | |
222 | // interval is 125 usec. | |
223 | // However, there are two ways of transmission in IEC 61883-6; blocking | |
224 | // and non-blocking modes. In blocking mode, the sequence of isoc packet | |
225 | // includes 'empty' or 'NODATA' packets which include no event. In | |
226 | // non-blocking mode, the number of events per packet is variable up to | |
227 | // the syt interval. | |
228 | // Due to the above protocol design, the minimum PCM frames per | |
229 | // interrupt should be double of the value of syt interval, thus it is | |
230 | // 250 usec. | |
7b2d99fa TS |
231 | err = snd_pcm_hw_constraint_minmax(runtime, |
232 | SNDRV_PCM_HW_PARAM_PERIOD_TIME, | |
f706df4f | 233 | 250, maximum_usec_per_period); |
7b2d99fa TS |
234 | if (err < 0) |
235 | goto end; | |
236 | ||
237 | /* Non-Blocking stream has no more constraints */ | |
238 | if (!(s->flags & CIP_BLOCKING)) | |
239 | goto end; | |
240 | ||
241 | /* | |
242 | * One AMDTP packet can include some frames. In blocking mode, the | |
243 | * number equals to SYT_INTERVAL. So the number is 8, 16 or 32, | |
244 | * depending on its sampling rate. For accurate period interrupt, it's | |
ce991981 | 245 | * preferrable to align period/buffer sizes to current SYT_INTERVAL. |
7b2d99fa | 246 | */ |
59502295 TS |
247 | err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, |
248 | apply_constraint_to_size, NULL, | |
826b5de9 | 249 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, |
59502295 TS |
250 | SNDRV_PCM_HW_PARAM_RATE, -1); |
251 | if (err < 0) | |
252 | goto end; | |
59502295 TS |
253 | err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, |
254 | apply_constraint_to_size, NULL, | |
826b5de9 | 255 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, |
59502295 TS |
256 | SNDRV_PCM_HW_PARAM_RATE, -1); |
257 | if (err < 0) | |
258 | goto end; | |
7b2d99fa TS |
259 | end: |
260 | return err; | |
261 | } | |
262 | EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints); | |
263 | ||
31ef9134 | 264 | /** |
be4a2894 TS |
265 | * amdtp_stream_set_parameters - set stream parameters |
266 | * @s: the AMDTP stream to configure | |
31ef9134 | 267 | * @rate: the sample rate |
df075fee | 268 | * @data_block_quadlets: the size of a data block in quadlet unit |
31ef9134 | 269 | * |
a7304e3b | 270 | * The parameters must be set before the stream is started, and must not be |
31ef9134 CL |
271 | * changed while the stream is running. |
272 | */ | |
df075fee TS |
273 | int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate, |
274 | unsigned int data_block_quadlets) | |
31ef9134 | 275 | { |
df075fee | 276 | unsigned int sfc; |
31ef9134 | 277 | |
547e631c | 278 | for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) { |
1017abed | 279 | if (amdtp_rate_table[sfc] == rate) |
547e631c TS |
280 | break; |
281 | } | |
282 | if (sfc == ARRAY_SIZE(amdtp_rate_table)) | |
283 | return -EINVAL; | |
e84d15f6 | 284 | |
e84d15f6 | 285 | s->sfc = sfc; |
df075fee | 286 | s->data_block_quadlets = data_block_quadlets; |
a7304e3b | 287 | s->syt_interval = amdtp_syt_intervals[sfc]; |
e84d15f6 | 288 | |
d3d10a4a TS |
289 | // default buffering in the device. |
290 | if (s->direction == AMDTP_OUT_STREAM) { | |
291 | s->ctx_data.rx.transfer_delay = | |
292 | TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE; | |
293 | ||
294 | if (s->flags & CIP_BLOCKING) { | |
295 | // additional buffering needed to adjust for no-data | |
296 | // packets. | |
297 | s->ctx_data.rx.transfer_delay += | |
298 | TICKS_PER_SECOND * s->syt_interval / rate; | |
299 | } | |
300 | } | |
77d2a8a4 | 301 | |
547e631c | 302 | return 0; |
31ef9134 | 303 | } |
be4a2894 | 304 | EXPORT_SYMBOL(amdtp_stream_set_parameters); |
31ef9134 CL |
305 | |
306 | /** | |
be4a2894 TS |
307 | * amdtp_stream_get_max_payload - get the stream's packet size |
308 | * @s: the AMDTP stream | |
31ef9134 CL |
309 | * |
310 | * This function must not be called before the stream has been configured | |
be4a2894 | 311 | * with amdtp_stream_set_parameters(). |
31ef9134 | 312 | */ |
be4a2894 | 313 | unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s) |
31ef9134 | 314 | { |
a2064710 | 315 | unsigned int multiplier = 1; |
07ea238c | 316 | unsigned int cip_header_size = 0; |
a2064710 TS |
317 | |
318 | if (s->flags & CIP_JUMBO_PAYLOAD) | |
319 | multiplier = 5; | |
3b196c39 | 320 | if (!(s->flags & CIP_NO_HEADER)) |
07ea238c | 321 | cip_header_size = sizeof(__be32) * 2; |
a2064710 | 322 | |
07ea238c TS |
323 | return cip_header_size + |
324 | s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier; | |
31ef9134 | 325 | } |
be4a2894 | 326 | EXPORT_SYMBOL(amdtp_stream_get_max_payload); |
31ef9134 | 327 | |
76fb8789 | 328 | /** |
be4a2894 TS |
329 | * amdtp_stream_pcm_prepare - prepare PCM device for running |
330 | * @s: the AMDTP stream | |
76fb8789 CL |
331 | * |
332 | * This function should be called from the PCM device's .prepare callback. | |
333 | */ | |
be4a2894 | 334 | void amdtp_stream_pcm_prepare(struct amdtp_stream *s) |
76fb8789 | 335 | { |
2b3d2987 | 336 | cancel_work_sync(&s->period_work); |
76fb8789 CL |
337 | s->pcm_buffer_pointer = 0; |
338 | s->pcm_period_pointer = 0; | |
339 | } | |
be4a2894 | 340 | EXPORT_SYMBOL(amdtp_stream_pcm_prepare); |
76fb8789 | 341 | |
274fc355 TS |
342 | static unsigned int calculate_data_blocks(unsigned int *data_block_state, |
343 | bool is_blocking, bool is_no_info, | |
344 | unsigned int syt_interval, enum cip_sfc sfc) | |
31ef9134 | 345 | { |
274fc355 | 346 | unsigned int data_blocks; |
31ef9134 | 347 | |
875be091 | 348 | /* Blocking mode. */ |
274fc355 | 349 | if (is_blocking) { |
875be091 | 350 | /* This module generate empty packet for 'no data'. */ |
274fc355 | 351 | if (is_no_info) |
875be091 TS |
352 | data_blocks = 0; |
353 | else | |
274fc355 | 354 | data_blocks = syt_interval; |
875be091 | 355 | /* Non-blocking mode. */ |
31ef9134 | 356 | } else { |
274fc355 | 357 | if (!cip_sfc_is_base_44100(sfc)) { |
d3d10a4a | 358 | // Sample_rate / 8000 is an integer, and precomputed. |
274fc355 | 359 | data_blocks = *data_block_state; |
875be091 | 360 | } else { |
274fc355 | 361 | unsigned int phase = *data_block_state; |
31ef9134 CL |
362 | |
363 | /* | |
364 | * This calculates the number of data blocks per packet so that | |
365 | * 1) the overall rate is correct and exactly synchronized to | |
366 | * the bus clock, and | |
367 | * 2) packets with a rounded-up number of blocks occur as early | |
368 | * as possible in the sequence (to prevent underruns of the | |
369 | * device's buffer). | |
370 | */ | |
274fc355 | 371 | if (sfc == CIP_SFC_44100) |
875be091 TS |
372 | /* 6 6 5 6 5 6 5 ... */ |
373 | data_blocks = 5 + ((phase & 1) ^ | |
374 | (phase == 0 || phase >= 40)); | |
375 | else | |
376 | /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */ | |
274fc355 TS |
377 | data_blocks = 11 * (sfc >> 1) + (phase == 0); |
378 | if (++phase >= (80 >> (sfc >> 1))) | |
875be091 | 379 | phase = 0; |
274fc355 | 380 | *data_block_state = phase; |
875be091 | 381 | } |
31ef9134 CL |
382 | } |
383 | ||
384 | return data_blocks; | |
385 | } | |
386 | ||
816d8482 TS |
387 | static unsigned int calculate_syt_offset(unsigned int *last_syt_offset, |
388 | unsigned int *syt_offset_state, enum cip_sfc sfc) | |
31ef9134 | 389 | { |
816d8482 | 390 | unsigned int syt_offset; |
31ef9134 | 391 | |
816d8482 TS |
392 | if (*last_syt_offset < TICKS_PER_CYCLE) { |
393 | if (!cip_sfc_is_base_44100(sfc)) | |
394 | syt_offset = *last_syt_offset + *syt_offset_state; | |
31ef9134 CL |
395 | else { |
396 | /* | |
397 | * The time, in ticks, of the n'th SYT_INTERVAL sample is: | |
398 | * n * SYT_INTERVAL * 24576000 / sample_rate | |
399 | * Modulo TICKS_PER_CYCLE, the difference between successive | |
400 | * elements is about 1386.23. Rounding the results of this | |
401 | * formula to the SYT precision results in a sequence of | |
402 | * differences that begins with: | |
403 | * 1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ... | |
404 | * This code generates _exactly_ the same sequence. | |
405 | */ | |
816d8482 TS |
406 | unsigned int phase = *syt_offset_state; |
407 | unsigned int index = phase % 13; | |
408 | ||
409 | syt_offset = *last_syt_offset; | |
31ef9134 CL |
410 | syt_offset += 1386 + ((index && !(index & 3)) || |
411 | phase == 146); | |
412 | if (++phase >= 147) | |
413 | phase = 0; | |
816d8482 | 414 | *syt_offset_state = phase; |
31ef9134 CL |
415 | } |
416 | } else | |
816d8482 TS |
417 | syt_offset = *last_syt_offset - TICKS_PER_CYCLE; |
418 | *last_syt_offset = syt_offset; | |
31ef9134 | 419 | |
83cfb5c5 TS |
420 | if (syt_offset >= TICKS_PER_CYCLE) |
421 | syt_offset = CIP_SYT_NO_INFO; | |
31ef9134 | 422 | |
83cfb5c5 | 423 | return syt_offset; |
31ef9134 CL |
424 | } |
425 | ||
4b7da117 TS |
426 | static void update_pcm_pointers(struct amdtp_stream *s, |
427 | struct snd_pcm_substream *pcm, | |
428 | unsigned int frames) | |
65845f29 TS |
429 | { |
430 | unsigned int ptr; | |
431 | ||
4b7da117 TS |
432 | ptr = s->pcm_buffer_pointer + frames; |
433 | if (ptr >= pcm->runtime->buffer_size) | |
434 | ptr -= pcm->runtime->buffer_size; | |
6aa7de05 | 435 | WRITE_ONCE(s->pcm_buffer_pointer, ptr); |
4b7da117 TS |
436 | |
437 | s->pcm_period_pointer += frames; | |
438 | if (s->pcm_period_pointer >= pcm->runtime->period_size) { | |
439 | s->pcm_period_pointer -= pcm->runtime->period_size; | |
2b3d2987 | 440 | queue_work(system_highpri_wq, &s->period_work); |
4b7da117 TS |
441 | } |
442 | } | |
443 | ||
2b3d2987 | 444 | static void pcm_period_work(struct work_struct *work) |
4b7da117 | 445 | { |
2b3d2987 TI |
446 | struct amdtp_stream *s = container_of(work, struct amdtp_stream, |
447 | period_work); | |
6aa7de05 | 448 | struct snd_pcm_substream *pcm = READ_ONCE(s->pcm); |
4b7da117 TS |
449 | |
450 | if (pcm) | |
451 | snd_pcm_period_elapsed(pcm); | |
452 | } | |
453 | ||
e229853d TS |
454 | static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params, |
455 | bool sched_irq) | |
4b7da117 | 456 | { |
6007bf54 | 457 | int err; |
df9160b9 | 458 | |
e229853d | 459 | params->interrupt = sched_irq; |
6007bf54 TS |
460 | params->tag = s->tag; |
461 | params->sy = 0; | |
df9160b9 | 462 | |
6007bf54 | 463 | err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer, |
4b7da117 TS |
464 | s->buffer.packets[s->packet_index].offset); |
465 | if (err < 0) { | |
466 | dev_err(&s->unit->device, "queueing error: %d\n", err); | |
467 | goto end; | |
468 | } | |
469 | ||
a0e02331 | 470 | if (++s->packet_index >= s->queue_size) |
4b7da117 TS |
471 | s->packet_index = 0; |
472 | end: | |
473 | return err; | |
474 | } | |
475 | ||
476 | static inline int queue_out_packet(struct amdtp_stream *s, | |
e229853d | 477 | struct fw_iso_packet *params, bool sched_irq) |
4b7da117 | 478 | { |
b18f0cfa TS |
479 | params->skip = |
480 | !!(params->header_length == 0 && params->payload_length == 0); | |
e229853d | 481 | return queue_packet(s, params, sched_irq); |
4b7da117 TS |
482 | } |
483 | ||
6007bf54 | 484 | static inline int queue_in_packet(struct amdtp_stream *s, |
60dd4929 | 485 | struct fw_iso_packet *params) |
2b3fc456 | 486 | { |
6007bf54 TS |
487 | // Queue one packet for IR context. |
488 | params->header_length = s->ctx_data.tx.ctx_header_size; | |
489 | params->payload_length = s->ctx_data.tx.max_ctx_payload_length; | |
490 | params->skip = false; | |
60dd4929 | 491 | return queue_packet(s, params, false); |
2b3fc456 TS |
492 | } |
493 | ||
252219c7 | 494 | static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2], |
860d798c | 495 | unsigned int data_block_counter, unsigned int syt) |
252219c7 TS |
496 | { |
497 | cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) | | |
498 | (s->data_block_quadlets << CIP_DBS_SHIFT) | | |
499 | ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) | | |
860d798c | 500 | data_block_counter); |
252219c7 TS |
501 | cip_header[1] = cpu_to_be32(CIP_EOH | |
502 | ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) | | |
503 | ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) | | |
504 | (syt & CIP_SYT_MASK)); | |
505 | } | |
506 | ||
6bc1a269 TS |
507 | static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle, |
508 | struct fw_iso_packet *params, | |
860d798c TS |
509 | unsigned int data_blocks, |
510 | unsigned int data_block_counter, | |
511 | unsigned int syt, unsigned int index) | |
31ef9134 | 512 | { |
0ebf3ceb | 513 | unsigned int payload_length; |
16be4589 | 514 | __be32 *cip_header; |
20e44577 | 515 | |
0ebf3ceb TS |
516 | payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets; |
517 | params->payload_length = payload_length; | |
518 | ||
b18f0cfa | 519 | if (!(s->flags & CIP_NO_HEADER)) { |
6bc1a269 | 520 | cip_header = (__be32 *)params->header; |
860d798c | 521 | generate_cip_header(s, cip_header, data_block_counter, syt); |
6bc1a269 | 522 | params->header_length = 2 * sizeof(__be32); |
0ebf3ceb | 523 | payload_length += params->header_length; |
b18f0cfa TS |
524 | } else { |
525 | cip_header = NULL; | |
526 | } | |
31ef9134 | 527 | |
213fa989 | 528 | trace_amdtp_packet(s, cycle, cip_header, payload_length, data_blocks, |
814b4312 | 529 | data_block_counter, s->packet_index, index); |
3b196c39 TS |
530 | } |
531 | ||
e335425b TS |
532 | static int check_cip_header(struct amdtp_stream *s, const __be32 *buf, |
533 | unsigned int payload_length, | |
a35463d1 TS |
534 | unsigned int *data_blocks, |
535 | unsigned int *data_block_counter, unsigned int *syt) | |
2b3fc456 TS |
536 | { |
537 | u32 cip_header[2]; | |
e335425b TS |
538 | unsigned int sph; |
539 | unsigned int fmt; | |
540 | unsigned int fdf; | |
a35463d1 | 541 | unsigned int dbc; |
c8bdf49b | 542 | bool lost; |
2b3fc456 | 543 | |
e335425b TS |
544 | cip_header[0] = be32_to_cpu(buf[0]); |
545 | cip_header[1] = be32_to_cpu(buf[1]); | |
2b3fc456 TS |
546 | |
547 | /* | |
548 | * This module supports 'Two-quadlet CIP header with SYT field'. | |
77d2a8a4 | 549 | * For convenience, also check FMT field is AM824 or not. |
2b3fc456 | 550 | */ |
2128f78f TS |
551 | if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) || |
552 | ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) && | |
553 | (!(s->flags & CIP_HEADER_WITHOUT_EOH))) { | |
2b3fc456 TS |
554 | dev_info_ratelimited(&s->unit->device, |
555 | "Invalid CIP header for AMDTP: %08X:%08X\n", | |
556 | cip_header[0], cip_header[1]); | |
e335425b | 557 | return -EAGAIN; |
2b3fc456 TS |
558 | } |
559 | ||
414ba022 | 560 | /* Check valid protocol or not. */ |
9863874f | 561 | sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT; |
414ba022 | 562 | fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT; |
9863874f | 563 | if (sph != s->sph || fmt != s->fmt) { |
2a7e1713 TS |
564 | dev_info_ratelimited(&s->unit->device, |
565 | "Detect unexpected protocol: %08x %08x\n", | |
566 | cip_header[0], cip_header[1]); | |
e335425b | 567 | return -EAGAIN; |
414ba022 TS |
568 | } |
569 | ||
2b3fc456 | 570 | /* Calculate data blocks */ |
414ba022 | 571 | fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT; |
e335425b | 572 | if (payload_length < sizeof(__be32) * 2 || |
414ba022 | 573 | (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) { |
e335425b | 574 | *data_blocks = 0; |
2b3fc456 | 575 | } else { |
e335425b TS |
576 | unsigned int data_block_quadlets = |
577 | (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT; | |
2b3fc456 TS |
578 | /* avoid division by zero */ |
579 | if (data_block_quadlets == 0) { | |
12e0f438 | 580 | dev_err(&s->unit->device, |
2b3fc456 TS |
581 | "Detect invalid value in dbs field: %08X\n", |
582 | cip_header[0]); | |
a9007054 | 583 | return -EPROTO; |
2b3fc456 | 584 | } |
69702239 TS |
585 | if (s->flags & CIP_WRONG_DBS) |
586 | data_block_quadlets = s->data_block_quadlets; | |
2b3fc456 | 587 | |
e335425b | 588 | *data_blocks = (payload_length / sizeof(__be32) - 2) / |
ff0fb5aa | 589 | data_block_quadlets; |
2b3fc456 TS |
590 | } |
591 | ||
592 | /* Check data block counter continuity */ | |
a35463d1 | 593 | dbc = cip_header[0] & CIP_DBC_MASK; |
e335425b | 594 | if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) && |
a35463d1 TS |
595 | *data_block_counter != UINT_MAX) |
596 | dbc = *data_block_counter; | |
9d59124c | 597 | |
a35463d1 TS |
598 | if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) || |
599 | *data_block_counter == UINT_MAX) { | |
b84b1a27 TS |
600 | lost = false; |
601 | } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) { | |
a35463d1 | 602 | lost = dbc != *data_block_counter; |
d9cd0065 | 603 | } else { |
e335425b TS |
604 | unsigned int dbc_interval; |
605 | ||
606 | if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0) | |
d3d10a4a | 607 | dbc_interval = s->ctx_data.tx.dbc_interval; |
d9cd0065 | 608 | else |
e335425b | 609 | dbc_interval = *data_blocks; |
d9cd0065 | 610 | |
a35463d1 | 611 | lost = dbc != ((*data_block_counter + dbc_interval) & 0xff); |
d9cd0065 | 612 | } |
c8bdf49b TS |
613 | |
614 | if (lost) { | |
12e0f438 TS |
615 | dev_err(&s->unit->device, |
616 | "Detect discontinuity of CIP: %02X %02X\n", | |
a35463d1 | 617 | *data_block_counter, dbc); |
6fc6b9ce | 618 | return -EIO; |
2b3fc456 TS |
619 | } |
620 | ||
753e7179 TS |
621 | *data_block_counter = dbc; |
622 | ||
e335425b | 623 | *syt = cip_header[1] & CIP_SYT_MASK; |
2b3fc456 | 624 | |
e335425b TS |
625 | return 0; |
626 | } | |
627 | ||
98e3e43b TS |
628 | static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle, |
629 | const __be32 *ctx_header, | |
630 | unsigned int *payload_length, | |
a35463d1 TS |
631 | unsigned int *data_blocks, |
632 | unsigned int *data_block_counter, | |
814b4312 | 633 | unsigned int *syt, unsigned int packet_index, unsigned int index) |
e335425b | 634 | { |
f11453c7 | 635 | const __be32 *cip_header; |
395f41e2 | 636 | unsigned int cip_header_size; |
e335425b TS |
637 | int err; |
638 | ||
98e3e43b | 639 | *payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT; |
395f41e2 TS |
640 | |
641 | if (!(s->flags & CIP_NO_HEADER)) | |
642 | cip_header_size = 8; | |
643 | else | |
644 | cip_header_size = 0; | |
645 | ||
646 | if (*payload_length > cip_header_size + s->ctx_data.tx.max_ctx_payload_length) { | |
e335425b TS |
647 | dev_err(&s->unit->device, |
648 | "Detect jumbo payload: %04x %04x\n", | |
395f41e2 | 649 | *payload_length, cip_header_size + s->ctx_data.tx.max_ctx_payload_length); |
e335425b TS |
650 | return -EIO; |
651 | } | |
652 | ||
395f41e2 | 653 | if (cip_header_size > 0) { |
98e3e43b TS |
654 | cip_header = ctx_header + 2; |
655 | err = check_cip_header(s, cip_header, *payload_length, | |
a35463d1 | 656 | data_blocks, data_block_counter, syt); |
b8b0e24c TS |
657 | if (err < 0) |
658 | return err; | |
947b437e TS |
659 | } else { |
660 | cip_header = NULL; | |
76864868 | 661 | err = 0; |
98e3e43b TS |
662 | *data_blocks = *payload_length / sizeof(__be32) / |
663 | s->data_block_quadlets; | |
664 | *syt = 0; | |
7fbf9096 | 665 | |
a35463d1 TS |
666 | if (*data_block_counter == UINT_MAX) |
667 | *data_block_counter = 0; | |
e335425b TS |
668 | } |
669 | ||
98e3e43b | 670 | trace_amdtp_packet(s, cycle, cip_header, *payload_length, *data_blocks, |
814b4312 | 671 | *data_block_counter, packet_index, index); |
e335425b | 672 | |
76864868 | 673 | return err; |
2b3fc456 TS |
674 | } |
675 | ||
26cd1e58 TS |
676 | // In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On |
677 | // the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent | |
678 | // it. Thus, via Linux firewire subsystem, we can get the 3 bits for second. | |
679 | static inline u32 compute_cycle_count(__be32 ctx_header_tstamp) | |
73fc7f08 | 680 | { |
26cd1e58 | 681 | u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK; |
73fc7f08 TS |
682 | return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff); |
683 | } | |
684 | ||
685 | static inline u32 increment_cycle_count(u32 cycle, unsigned int addend) | |
686 | { | |
687 | cycle += addend; | |
10aa8e4a TS |
688 | if (cycle >= OHCI_MAX_SECOND * CYCLES_PER_SECOND) |
689 | cycle -= OHCI_MAX_SECOND * CYCLES_PER_SECOND; | |
73fc7f08 TS |
690 | return cycle; |
691 | } | |
692 | ||
26cd1e58 | 693 | // Align to actual cycle count for the packet which is going to be scheduled. |
a0e02331 TS |
694 | // This module queued the same number of isochronous cycle as the size of queue |
695 | // to kip isochronous cycle, therefore it's OK to just increment the cycle by | |
696 | // the size of queue for scheduled cycle. | |
697 | static inline u32 compute_it_cycle(const __be32 ctx_header_tstamp, | |
698 | unsigned int queue_size) | |
26cd1e58 TS |
699 | { |
700 | u32 cycle = compute_cycle_count(ctx_header_tstamp); | |
a0e02331 | 701 | return increment_cycle_count(cycle, queue_size); |
26cd1e58 TS |
702 | } |
703 | ||
753e7179 TS |
704 | static int generate_device_pkt_descs(struct amdtp_stream *s, |
705 | struct pkt_desc *descs, | |
706 | const __be32 *ctx_header, | |
707 | unsigned int packets) | |
708 | { | |
709 | unsigned int dbc = s->data_block_counter; | |
814b4312 TS |
710 | unsigned int packet_index = s->packet_index; |
711 | unsigned int queue_size = s->queue_size; | |
753e7179 TS |
712 | int i; |
713 | int err; | |
714 | ||
715 | for (i = 0; i < packets; ++i) { | |
716 | struct pkt_desc *desc = descs + i; | |
753e7179 TS |
717 | unsigned int cycle; |
718 | unsigned int payload_length; | |
719 | unsigned int data_blocks; | |
720 | unsigned int syt; | |
721 | ||
722 | cycle = compute_cycle_count(ctx_header[1]); | |
723 | ||
724 | err = parse_ir_ctx_header(s, cycle, ctx_header, &payload_length, | |
814b4312 | 725 | &data_blocks, &dbc, &syt, packet_index, i); |
753e7179 TS |
726 | if (err < 0) |
727 | return err; | |
728 | ||
729 | desc->cycle = cycle; | |
730 | desc->syt = syt; | |
731 | desc->data_blocks = data_blocks; | |
732 | desc->data_block_counter = dbc; | |
814b4312 | 733 | desc->ctx_payload = s->buffer.packets[packet_index].buffer; |
753e7179 TS |
734 | |
735 | if (!(s->flags & CIP_DBC_IS_END_EVENT)) | |
736 | dbc = (dbc + desc->data_blocks) & 0xff; | |
737 | ||
738 | ctx_header += | |
739 | s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header); | |
814b4312 TS |
740 | |
741 | packet_index = (packet_index + 1) % queue_size; | |
753e7179 TS |
742 | } |
743 | ||
744 | s->data_block_counter = dbc; | |
745 | ||
746 | return 0; | |
747 | } | |
748 | ||
83cfb5c5 TS |
749 | static unsigned int compute_syt(unsigned int syt_offset, unsigned int cycle, |
750 | unsigned int transfer_delay) | |
751 | { | |
752 | unsigned int syt; | |
753 | ||
754 | syt_offset += transfer_delay; | |
755 | syt = ((cycle + syt_offset / TICKS_PER_CYCLE) << 12) | | |
756 | (syt_offset % TICKS_PER_CYCLE); | |
757 | return syt & CIP_SYT_MASK; | |
758 | } | |
759 | ||
69efd5c4 TS |
760 | static void generate_pkt_descs(struct amdtp_stream *s, struct pkt_desc *descs, |
761 | const __be32 *ctx_header, unsigned int packets, | |
762 | const struct seq_desc *seq_descs, | |
763 | unsigned int seq_size) | |
f4f6ae7b TS |
764 | { |
765 | unsigned int dbc = s->data_block_counter; | |
69efd5c4 | 766 | unsigned int seq_index = s->ctx_data.rx.seq_index; |
f4f6ae7b TS |
767 | int i; |
768 | ||
769 | for (i = 0; i < packets; ++i) { | |
770 | struct pkt_desc *desc = descs + i; | |
a0e02331 | 771 | unsigned int index = (s->packet_index + i) % s->queue_size; |
69efd5c4 TS |
772 | const struct seq_desc *seq = seq_descs + seq_index; |
773 | unsigned int syt; | |
f4f6ae7b | 774 | |
a0e02331 | 775 | desc->cycle = compute_it_cycle(*ctx_header, s->queue_size); |
69efd5c4 TS |
776 | |
777 | syt = seq->syt_offset; | |
778 | if (syt != CIP_SYT_NO_INFO) { | |
779 | syt = compute_syt(syt, desc->cycle, | |
780 | s->ctx_data.rx.transfer_delay); | |
83cfb5c5 | 781 | } |
69efd5c4 TS |
782 | desc->syt = syt; |
783 | desc->data_blocks = seq->data_blocks; | |
f4f6ae7b TS |
784 | |
785 | if (s->flags & CIP_DBC_IS_END_EVENT) | |
786 | dbc = (dbc + desc->data_blocks) & 0xff; | |
787 | ||
788 | desc->data_block_counter = dbc; | |
789 | ||
790 | if (!(s->flags & CIP_DBC_IS_END_EVENT)) | |
791 | dbc = (dbc + desc->data_blocks) & 0xff; | |
792 | ||
793 | desc->ctx_payload = s->buffer.packets[index].buffer; | |
794 | ||
69efd5c4 TS |
795 | seq_index = (seq_index + 1) % seq_size; |
796 | ||
f4f6ae7b TS |
797 | ++ctx_header; |
798 | } | |
799 | ||
800 | s->data_block_counter = dbc; | |
69efd5c4 | 801 | s->ctx_data.rx.seq_index = seq_index; |
f4f6ae7b TS |
802 | } |
803 | ||
fce9b013 TS |
804 | static inline void cancel_stream(struct amdtp_stream *s) |
805 | { | |
806 | s->packet_index = -1; | |
2b3d2987 | 807 | if (current_work() == &s->period_work) |
fce9b013 TS |
808 | amdtp_stream_pcm_abort(s); |
809 | WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN); | |
810 | } | |
811 | ||
0f5cfcb2 TS |
812 | static void process_ctx_payloads(struct amdtp_stream *s, |
813 | const struct pkt_desc *descs, | |
814 | unsigned int packets) | |
31ef9134 | 815 | { |
9a738ad1 TS |
816 | struct snd_pcm_substream *pcm; |
817 | unsigned int pcm_frames; | |
5e2ece0f | 818 | |
9a738ad1 TS |
819 | pcm = READ_ONCE(s->pcm); |
820 | pcm_frames = s->process_ctx_payloads(s, descs, packets, pcm); | |
821 | if (pcm) | |
822 | update_pcm_pointers(s, pcm, pcm_frames); | |
0f5cfcb2 TS |
823 | } |
824 | ||
825 | static void out_stream_callback(struct fw_iso_context *context, u32 tstamp, | |
826 | size_t header_length, void *header, | |
827 | void *private_data) | |
828 | { | |
829 | struct amdtp_stream *s = private_data; | |
69efd5c4 | 830 | const struct amdtp_domain *d = s->domain; |
0f5cfcb2 | 831 | const __be32 *ctx_header = header; |
60dd4929 TS |
832 | unsigned int events_per_period = s->ctx_data.rx.events_per_period; |
833 | unsigned int event_count = s->ctx_data.rx.event_count; | |
a0e02331 | 834 | unsigned int packets; |
0f5cfcb2 TS |
835 | int i; |
836 | ||
837 | if (s->packet_index < 0) | |
838 | return; | |
839 | ||
a0e02331 TS |
840 | // Calculate the number of packets in buffer and check XRUN. |
841 | packets = header_length / sizeof(*ctx_header); | |
842 | ||
69efd5c4 TS |
843 | generate_pkt_descs(s, s->pkt_descs, ctx_header, packets, d->seq_descs, |
844 | d->seq_size); | |
0f5cfcb2 TS |
845 | |
846 | process_ctx_payloads(s, s->pkt_descs, packets); | |
5e2ece0f TS |
847 | |
848 | for (i = 0; i < packets; ++i) { | |
849 | const struct pkt_desc *desc = s->pkt_descs + i; | |
f4f6ae7b | 850 | unsigned int syt; |
6bc1a269 TS |
851 | struct { |
852 | struct fw_iso_packet params; | |
853 | __be32 header[IT_PKT_HEADER_SIZE_CIP / sizeof(__be32)]; | |
854 | } template = { {0}, {0} }; | |
e229853d | 855 | bool sched_irq = false; |
31ef9134 | 856 | |
f4f6ae7b TS |
857 | if (s->ctx_data.rx.syt_override < 0) |
858 | syt = desc->syt; | |
859 | else | |
3baf3053 TS |
860 | syt = s->ctx_data.rx.syt_override; |
861 | ||
f4f6ae7b TS |
862 | build_it_pkt_header(s, desc->cycle, &template.params, |
863 | desc->data_blocks, desc->data_block_counter, | |
864 | syt, i); | |
6bc1a269 | 865 | |
2472cfb3 | 866 | if (s == s->domain->irq_target) { |
60dd4929 TS |
867 | event_count += desc->data_blocks; |
868 | if (event_count >= events_per_period) { | |
869 | event_count -= events_per_period; | |
870 | sched_irq = true; | |
871 | } | |
e229853d TS |
872 | } |
873 | ||
874 | if (queue_out_packet(s, &template.params, sched_irq) < 0) { | |
fce9b013 | 875 | cancel_stream(s); |
a4103bd7 TS |
876 | return; |
877 | } | |
ccccad86 | 878 | } |
a4103bd7 | 879 | |
60dd4929 | 880 | s->ctx_data.rx.event_count = event_count; |
31ef9134 CL |
881 | } |
882 | ||
73fc7f08 | 883 | static void in_stream_callback(struct fw_iso_context *context, u32 tstamp, |
2b3fc456 TS |
884 | size_t header_length, void *header, |
885 | void *private_data) | |
886 | { | |
887 | struct amdtp_stream *s = private_data; | |
cc4f8e91 | 888 | __be32 *ctx_header = header; |
e229853d | 889 | unsigned int packets; |
753e7179 TS |
890 | int i; |
891 | int err; | |
2b3fc456 | 892 | |
a4103bd7 TS |
893 | if (s->packet_index < 0) |
894 | return; | |
895 | ||
a0e02331 | 896 | // Calculate the number of packets in buffer and check XRUN. |
d3d10a4a | 897 | packets = header_length / s->ctx_data.tx.ctx_header_size; |
f90e2ded | 898 | |
753e7179 TS |
899 | err = generate_device_pkt_descs(s, s->pkt_descs, ctx_header, packets); |
900 | if (err < 0) { | |
901 | if (err != -EAGAIN) { | |
902 | cancel_stream(s); | |
903 | return; | |
904 | } | |
5e2ece0f | 905 | } else { |
0f5cfcb2 | 906 | process_ctx_payloads(s, s->pkt_descs, packets); |
5e2ece0f TS |
907 | } |
908 | ||
909 | for (i = 0; i < packets; ++i) { | |
910 | struct fw_iso_packet params = {0}; | |
2b3fc456 | 911 | |
60dd4929 | 912 | if (queue_in_packet(s, ¶ms) < 0) { |
753e7179 TS |
913 | cancel_stream(s); |
914 | return; | |
915 | } | |
7b3b0d85 | 916 | } |
60dd4929 TS |
917 | } |
918 | ||
1a4be183 TS |
919 | static void pool_ideal_seq_descs(struct amdtp_domain *d, unsigned int packets) |
920 | { | |
921 | struct amdtp_stream *irq_target = d->irq_target; | |
922 | unsigned int seq_tail = d->seq_tail; | |
923 | unsigned int seq_size = d->seq_size; | |
924 | unsigned int min_avail; | |
925 | struct amdtp_stream *s; | |
926 | ||
927 | min_avail = d->seq_size; | |
928 | list_for_each_entry(s, &d->streams, list) { | |
929 | unsigned int seq_index; | |
930 | unsigned int avail; | |
931 | ||
932 | if (s->direction == AMDTP_IN_STREAM) | |
933 | continue; | |
934 | ||
935 | seq_index = s->ctx_data.rx.seq_index; | |
936 | avail = d->seq_tail; | |
937 | if (seq_index > avail) | |
938 | avail += d->seq_size; | |
939 | avail -= seq_index; | |
940 | ||
941 | if (avail < min_avail) | |
942 | min_avail = avail; | |
943 | } | |
944 | ||
945 | while (min_avail < packets) { | |
946 | struct seq_desc *desc = d->seq_descs + seq_tail; | |
947 | ||
948 | desc->syt_offset = calculate_syt_offset(&d->last_syt_offset, | |
949 | &d->syt_offset_state, irq_target->sfc); | |
950 | desc->data_blocks = calculate_data_blocks(&d->data_block_state, | |
951 | !!(irq_target->flags & CIP_BLOCKING), | |
952 | desc->syt_offset == CIP_SYT_NO_INFO, | |
953 | irq_target->syt_interval, irq_target->sfc); | |
954 | ||
955 | ++seq_tail; | |
956 | seq_tail %= seq_size; | |
957 | ||
958 | ++min_avail; | |
959 | } | |
960 | ||
961 | d->seq_tail = seq_tail; | |
962 | } | |
963 | ||
2472cfb3 TS |
964 | static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, |
965 | size_t header_length, void *header, | |
966 | void *private_data) | |
60dd4929 | 967 | { |
2472cfb3 TS |
968 | struct amdtp_stream *irq_target = private_data; |
969 | struct amdtp_domain *d = irq_target->domain; | |
1a4be183 | 970 | unsigned int packets = header_length / sizeof(__be32); |
60dd4929 TS |
971 | struct amdtp_stream *s; |
972 | ||
1a4be183 TS |
973 | // Record enough entries with extra 3 cycles at least. |
974 | pool_ideal_seq_descs(d, packets + 3); | |
975 | ||
60dd4929 TS |
976 | out_stream_callback(context, tstamp, header_length, header, irq_target); |
977 | if (amdtp_streaming_error(irq_target)) | |
978 | goto error; | |
7b3b0d85 | 979 | |
60dd4929 TS |
980 | list_for_each_entry(s, &d->streams, list) { |
981 | if (s != irq_target && amdtp_stream_running(s)) { | |
982 | fw_iso_context_flush_completions(s->context); | |
983 | if (amdtp_streaming_error(s)) | |
984 | goto error; | |
985 | } | |
986 | } | |
987 | ||
988 | return; | |
989 | error: | |
990 | if (amdtp_stream_running(irq_target)) | |
991 | cancel_stream(irq_target); | |
992 | ||
993 | list_for_each_entry(s, &d->streams, list) { | |
994 | if (amdtp_stream_running(s)) | |
995 | cancel_stream(s); | |
996 | } | |
2b3fc456 TS |
997 | } |
998 | ||
60dd4929 | 999 | // this is executed one time. |
7b3b0d85 | 1000 | static void amdtp_stream_first_callback(struct fw_iso_context *context, |
73fc7f08 | 1001 | u32 tstamp, size_t header_length, |
7b3b0d85 TS |
1002 | void *header, void *private_data) |
1003 | { | |
1004 | struct amdtp_stream *s = private_data; | |
26cd1e58 | 1005 | const __be32 *ctx_header = header; |
a04513f8 | 1006 | u32 cycle; |
7b3b0d85 TS |
1007 | |
1008 | /* | |
1009 | * For in-stream, first packet has come. | |
1010 | * For out-stream, prepared to transmit first packet | |
1011 | */ | |
1012 | s->callbacked = true; | |
1013 | wake_up(&s->callback_wait); | |
1014 | ||
a04513f8 | 1015 | if (s->direction == AMDTP_IN_STREAM) { |
26cd1e58 | 1016 | cycle = compute_cycle_count(ctx_header[1]); |
cc4f8e91 | 1017 | |
7b3b0d85 | 1018 | context->callback.sc = in_stream_callback; |
a04513f8 | 1019 | } else { |
a0e02331 | 1020 | cycle = compute_it_cycle(*ctx_header, s->queue_size); |
26cd1e58 | 1021 | |
2472cfb3 TS |
1022 | if (s == s->domain->irq_target) |
1023 | context->callback.sc = irq_target_callback; | |
1024 | else | |
1025 | context->callback.sc = out_stream_callback; | |
a04513f8 TS |
1026 | } |
1027 | ||
1028 | s->start_cycle = cycle; | |
7b3b0d85 | 1029 | |
73fc7f08 | 1030 | context->callback.sc(context, tstamp, header_length, header, s); |
7b3b0d85 TS |
1031 | } |
1032 | ||
31ef9134 | 1033 | /** |
be4a2894 TS |
1034 | * amdtp_stream_start - start transferring packets |
1035 | * @s: the AMDTP stream to start | |
31ef9134 CL |
1036 | * @channel: the isochronous channel on the bus |
1037 | * @speed: firewire speed code | |
acfedcbe TS |
1038 | * @start_cycle: the isochronous cycle to start the context. Start immediately |
1039 | * if negative value is given. | |
af86b0b1 TS |
1040 | * @queue_size: The number of packets in the queue. |
1041 | * @idle_irq_interval: the interval to queue packet during initial state. | |
31ef9134 CL |
1042 | * |
1043 | * The stream cannot be started until it has been configured with | |
be4a2894 TS |
1044 | * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI |
1045 | * device can be started. | |
31ef9134 | 1046 | */ |
a0e02331 | 1047 | static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed, |
af86b0b1 TS |
1048 | int start_cycle, unsigned int queue_size, |
1049 | unsigned int idle_irq_interval) | |
31ef9134 | 1050 | { |
2472cfb3 | 1051 | bool is_irq_target = (s == s->domain->irq_target); |
d3d10a4a | 1052 | unsigned int ctx_header_size; |
f11453c7 | 1053 | unsigned int max_ctx_payload_size; |
2b3fc456 | 1054 | enum dma_data_direction dir; |
7ab56645 | 1055 | int type, tag, err; |
31ef9134 CL |
1056 | |
1057 | mutex_lock(&s->mutex); | |
1058 | ||
be4a2894 | 1059 | if (WARN_ON(amdtp_stream_running(s) || |
4b7da117 | 1060 | (s->data_block_quadlets < 1))) { |
31ef9134 CL |
1061 | err = -EBADFD; |
1062 | goto err_unlock; | |
1063 | } | |
1064 | ||
d3d10a4a | 1065 | if (s->direction == AMDTP_IN_STREAM) { |
60dd4929 TS |
1066 | // NOTE: IT context should be used for constant IRQ. |
1067 | if (is_irq_target) { | |
1068 | err = -EINVAL; | |
1069 | goto err_unlock; | |
1070 | } | |
1071 | ||
b6bc8123 | 1072 | s->data_block_counter = UINT_MAX; |
d3d10a4a | 1073 | } else { |
b6bc8123 | 1074 | s->data_block_counter = 0; |
d3d10a4a | 1075 | } |
31ef9134 | 1076 | |
1be4f21d TS |
1077 | // initialize packet buffer. |
1078 | max_ctx_payload_size = amdtp_stream_get_max_payload(s); | |
2b3fc456 TS |
1079 | if (s->direction == AMDTP_IN_STREAM) { |
1080 | dir = DMA_FROM_DEVICE; | |
1081 | type = FW_ISO_CONTEXT_RECEIVE; | |
1be4f21d TS |
1082 | if (!(s->flags & CIP_NO_HEADER)) { |
1083 | max_ctx_payload_size -= 8; | |
f11453c7 | 1084 | ctx_header_size = IR_CTX_HEADER_SIZE_CIP; |
1be4f21d | 1085 | } else { |
f11453c7 | 1086 | ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP; |
1be4f21d | 1087 | } |
2b3fc456 TS |
1088 | } else { |
1089 | dir = DMA_TO_DEVICE; | |
1090 | type = FW_ISO_CONTEXT_TRANSMIT; | |
df9160b9 | 1091 | ctx_header_size = 0; // No effect for IT context. |
f11453c7 | 1092 | |
b18f0cfa TS |
1093 | if (!(s->flags & CIP_NO_HEADER)) |
1094 | max_ctx_payload_size -= IT_PKT_HEADER_SIZE_CIP; | |
1095 | } | |
f11453c7 | 1096 | |
af86b0b1 | 1097 | err = iso_packets_buffer_init(&s->buffer, s->unit, queue_size, |
f11453c7 | 1098 | max_ctx_payload_size, dir); |
31ef9134 CL |
1099 | if (err < 0) |
1100 | goto err_unlock; | |
af86b0b1 | 1101 | s->queue_size = queue_size; |
60dd4929 | 1102 | |
31ef9134 | 1103 | s->context = fw_iso_context_create(fw_parent_device(s->unit)->card, |
d3d10a4a | 1104 | type, channel, speed, ctx_header_size, |
2472cfb3 | 1105 | amdtp_stream_first_callback, s); |
31ef9134 CL |
1106 | if (IS_ERR(s->context)) { |
1107 | err = PTR_ERR(s->context); | |
1108 | if (err == -EBUSY) | |
1109 | dev_err(&s->unit->device, | |
be4a2894 | 1110 | "no free stream on this controller\n"); |
31ef9134 CL |
1111 | goto err_buffer; |
1112 | } | |
1113 | ||
be4a2894 | 1114 | amdtp_stream_update(s); |
31ef9134 | 1115 | |
d3d10a4a | 1116 | if (s->direction == AMDTP_IN_STREAM) { |
f11453c7 | 1117 | s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size; |
d3d10a4a TS |
1118 | s->ctx_data.tx.ctx_header_size = ctx_header_size; |
1119 | } | |
52759c09 | 1120 | |
3b196c39 TS |
1121 | if (s->flags & CIP_NO_HEADER) |
1122 | s->tag = TAG_NO_CIP_HEADER; | |
1123 | else | |
1124 | s->tag = TAG_CIP; | |
1125 | ||
a0e02331 | 1126 | s->pkt_descs = kcalloc(s->queue_size, sizeof(*s->pkt_descs), |
04130cf8 TS |
1127 | GFP_KERNEL); |
1128 | if (!s->pkt_descs) { | |
1129 | err = -ENOMEM; | |
1130 | goto err_context; | |
1131 | } | |
1132 | ||
ec00f5e4 | 1133 | s->packet_index = 0; |
4b7da117 | 1134 | do { |
6007bf54 | 1135 | struct fw_iso_packet params; |
e229853d | 1136 | |
b18f0cfa | 1137 | if (s->direction == AMDTP_IN_STREAM) { |
60dd4929 | 1138 | err = queue_in_packet(s, ¶ms); |
b18f0cfa | 1139 | } else { |
60dd4929 TS |
1140 | bool sched_irq = false; |
1141 | ||
b18f0cfa TS |
1142 | params.header_length = 0; |
1143 | params.payload_length = 0; | |
60dd4929 TS |
1144 | |
1145 | if (is_irq_target) { | |
1146 | sched_irq = !((s->packet_index + 1) % | |
1147 | idle_irq_interval); | |
1148 | } | |
1149 | ||
e229853d | 1150 | err = queue_out_packet(s, ¶ms, sched_irq); |
b18f0cfa | 1151 | } |
4b7da117 | 1152 | if (err < 0) |
04130cf8 | 1153 | goto err_pkt_descs; |
4b7da117 | 1154 | } while (s->packet_index > 0); |
31ef9134 | 1155 | |
2b3fc456 | 1156 | /* NOTE: TAG1 matches CIP. This just affects in stream. */ |
7ab56645 | 1157 | tag = FW_ISO_CONTEXT_MATCH_TAG1; |
3b196c39 | 1158 | if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER)) |
7ab56645 TS |
1159 | tag |= FW_ISO_CONTEXT_MATCH_TAG0; |
1160 | ||
7b3b0d85 | 1161 | s->callbacked = false; |
acfedcbe | 1162 | err = fw_iso_context_start(s->context, start_cycle, 0, tag); |
31ef9134 | 1163 | if (err < 0) |
04130cf8 | 1164 | goto err_pkt_descs; |
31ef9134 CL |
1165 | |
1166 | mutex_unlock(&s->mutex); | |
1167 | ||
1168 | return 0; | |
04130cf8 TS |
1169 | err_pkt_descs: |
1170 | kfree(s->pkt_descs); | |
31ef9134 CL |
1171 | err_context: |
1172 | fw_iso_context_destroy(s->context); | |
1173 | s->context = ERR_PTR(-1); | |
1174 | err_buffer: | |
1175 | iso_packets_buffer_destroy(&s->buffer, s->unit); | |
1176 | err_unlock: | |
1177 | mutex_unlock(&s->mutex); | |
1178 | ||
1179 | return err; | |
1180 | } | |
31ef9134 | 1181 | |
e9148ddd | 1182 | /** |
f890f9a0 TS |
1183 | * amdtp_domain_stream_pcm_pointer - get the PCM buffer position |
1184 | * @d: the AMDTP domain. | |
be4a2894 | 1185 | * @s: the AMDTP stream that transports the PCM data |
e9148ddd CL |
1186 | * |
1187 | * Returns the current buffer position, in frames. | |
1188 | */ | |
f890f9a0 TS |
1189 | unsigned long amdtp_domain_stream_pcm_pointer(struct amdtp_domain *d, |
1190 | struct amdtp_stream *s) | |
e9148ddd | 1191 | { |
f890f9a0 TS |
1192 | struct amdtp_stream *irq_target = d->irq_target; |
1193 | ||
1194 | if (irq_target && amdtp_stream_running(irq_target)) { | |
1195 | // This function is called in software IRQ context of | |
2b3d2987 | 1196 | // period_work or process context. |
f890f9a0 TS |
1197 | // |
1198 | // When the software IRQ context was scheduled by software IRQ | |
1199 | // context of IT contexts, queued packets were already handled. | |
1200 | // Therefore, no need to flush the queue in buffer furthermore. | |
1201 | // | |
1202 | // When the process context reach here, some packets will be | |
1203 | // already queued in the buffer. These packets should be handled | |
1204 | // immediately to keep better granularity of PCM pointer. | |
1205 | // | |
1206 | // Later, the process context will sometimes schedules software | |
2b3d2987 | 1207 | // IRQ context of the period_work. Then, no need to flush the |
f890f9a0 | 1208 | // queue by the same reason as described in the above |
2b3d2987 | 1209 | if (current_work() != &s->period_work) { |
f890f9a0 TS |
1210 | // Queued packet should be processed without any kernel |
1211 | // preemption to keep latency against bus cycle. | |
1212 | preempt_disable(); | |
1213 | fw_iso_context_flush_completions(irq_target->context); | |
1214 | preempt_enable(); | |
1215 | } | |
1216 | } | |
e9148ddd | 1217 | |
6aa7de05 | 1218 | return READ_ONCE(s->pcm_buffer_pointer); |
e9148ddd | 1219 | } |
f890f9a0 | 1220 | EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_pointer); |
e9148ddd | 1221 | |
875becf8 | 1222 | /** |
e6dcc92f TS |
1223 | * amdtp_domain_stream_pcm_ack - acknowledge queued PCM frames |
1224 | * @d: the AMDTP domain. | |
875becf8 TS |
1225 | * @s: the AMDTP stream that transfers the PCM frames |
1226 | * | |
1227 | * Returns zero always. | |
1228 | */ | |
e6dcc92f | 1229 | int amdtp_domain_stream_pcm_ack(struct amdtp_domain *d, struct amdtp_stream *s) |
875becf8 | 1230 | { |
e6dcc92f TS |
1231 | struct amdtp_stream *irq_target = d->irq_target; |
1232 | ||
1233 | // Process isochronous packets for recent isochronous cycle to handle | |
1234 | // queued PCM frames. | |
1235 | if (irq_target && amdtp_stream_running(irq_target)) { | |
1236 | // Queued packet should be processed without any kernel | |
1237 | // preemption to keep latency against bus cycle. | |
1238 | preempt_disable(); | |
1239 | fw_iso_context_flush_completions(irq_target->context); | |
1240 | preempt_enable(); | |
1241 | } | |
875becf8 TS |
1242 | |
1243 | return 0; | |
1244 | } | |
e6dcc92f | 1245 | EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_ack); |
875becf8 | 1246 | |
31ef9134 | 1247 | /** |
be4a2894 TS |
1248 | * amdtp_stream_update - update the stream after a bus reset |
1249 | * @s: the AMDTP stream | |
31ef9134 | 1250 | */ |
be4a2894 | 1251 | void amdtp_stream_update(struct amdtp_stream *s) |
31ef9134 | 1252 | { |
9a2820c1 | 1253 | /* Precomputing. */ |
6aa7de05 MR |
1254 | WRITE_ONCE(s->source_node_id_field, |
1255 | (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK); | |
31ef9134 | 1256 | } |
be4a2894 | 1257 | EXPORT_SYMBOL(amdtp_stream_update); |
31ef9134 CL |
1258 | |
1259 | /** | |
be4a2894 TS |
1260 | * amdtp_stream_stop - stop sending packets |
1261 | * @s: the AMDTP stream to stop | |
31ef9134 CL |
1262 | * |
1263 | * All PCM and MIDI devices of the stream must be stopped before the stream | |
1264 | * itself can be stopped. | |
1265 | */ | |
74f94e41 | 1266 | static void amdtp_stream_stop(struct amdtp_stream *s) |
31ef9134 CL |
1267 | { |
1268 | mutex_lock(&s->mutex); | |
1269 | ||
be4a2894 | 1270 | if (!amdtp_stream_running(s)) { |
31ef9134 CL |
1271 | mutex_unlock(&s->mutex); |
1272 | return; | |
1273 | } | |
1274 | ||
2b3d2987 | 1275 | cancel_work_sync(&s->period_work); |
31ef9134 CL |
1276 | fw_iso_context_stop(s->context); |
1277 | fw_iso_context_destroy(s->context); | |
1278 | s->context = ERR_PTR(-1); | |
1279 | iso_packets_buffer_destroy(&s->buffer, s->unit); | |
04130cf8 | 1280 | kfree(s->pkt_descs); |
31ef9134 | 1281 | |
7b3b0d85 TS |
1282 | s->callbacked = false; |
1283 | ||
31ef9134 CL |
1284 | mutex_unlock(&s->mutex); |
1285 | } | |
31ef9134 CL |
1286 | |
1287 | /** | |
be4a2894 | 1288 | * amdtp_stream_pcm_abort - abort the running PCM device |
31ef9134 CL |
1289 | * @s: the AMDTP stream about to be stopped |
1290 | * | |
1291 | * If the isochronous stream needs to be stopped asynchronously, call this | |
1292 | * function first to stop the PCM device. | |
1293 | */ | |
be4a2894 | 1294 | void amdtp_stream_pcm_abort(struct amdtp_stream *s) |
31ef9134 CL |
1295 | { |
1296 | struct snd_pcm_substream *pcm; | |
1297 | ||
6aa7de05 | 1298 | pcm = READ_ONCE(s->pcm); |
1fb8510c TI |
1299 | if (pcm) |
1300 | snd_pcm_stop_xrun(pcm); | |
31ef9134 | 1301 | } |
be4a2894 | 1302 | EXPORT_SYMBOL(amdtp_stream_pcm_abort); |
3ec3d7a3 TS |
1303 | |
1304 | /** | |
1305 | * amdtp_domain_init - initialize an AMDTP domain structure | |
1306 | * @d: the AMDTP domain to initialize. | |
1307 | */ | |
1308 | int amdtp_domain_init(struct amdtp_domain *d) | |
1309 | { | |
1310 | INIT_LIST_HEAD(&d->streams); | |
1311 | ||
d68c3123 TS |
1312 | d->events_per_period = 0; |
1313 | ||
25babf29 TS |
1314 | d->seq_descs = NULL; |
1315 | ||
3ec3d7a3 TS |
1316 | return 0; |
1317 | } | |
1318 | EXPORT_SYMBOL_GPL(amdtp_domain_init); | |
1319 | ||
1320 | /** | |
1321 | * amdtp_domain_destroy - destroy an AMDTP domain structure | |
1322 | * @d: the AMDTP domain to destroy. | |
1323 | */ | |
1324 | void amdtp_domain_destroy(struct amdtp_domain *d) | |
1325 | { | |
8d0d5c3f TS |
1326 | // At present nothing to do. |
1327 | return; | |
3ec3d7a3 TS |
1328 | } |
1329 | EXPORT_SYMBOL_GPL(amdtp_domain_destroy); | |
6261f90b | 1330 | |
157a53ee TS |
1331 | /** |
1332 | * amdtp_domain_add_stream - register isoc context into the domain. | |
1333 | * @d: the AMDTP domain. | |
1334 | * @s: the AMDTP stream. | |
1335 | * @channel: the isochronous channel on the bus. | |
1336 | * @speed: firewire speed code. | |
1337 | */ | |
1338 | int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s, | |
1339 | int channel, int speed) | |
1340 | { | |
1341 | struct amdtp_stream *tmp; | |
1342 | ||
1343 | list_for_each_entry(tmp, &d->streams, list) { | |
1344 | if (s == tmp) | |
1345 | return -EBUSY; | |
1346 | } | |
1347 | ||
1348 | list_add(&s->list, &d->streams); | |
1349 | ||
1350 | s->channel = channel; | |
1351 | s->speed = speed; | |
2472cfb3 | 1352 | s->domain = d; |
157a53ee TS |
1353 | |
1354 | return 0; | |
1355 | } | |
1356 | EXPORT_SYMBOL_GPL(amdtp_domain_add_stream); | |
1357 | ||
acfedcbe TS |
1358 | static int get_current_cycle_time(struct fw_card *fw_card, int *cur_cycle) |
1359 | { | |
1360 | int generation; | |
1361 | int rcode; | |
1362 | __be32 reg; | |
1363 | u32 data; | |
1364 | ||
1365 | // This is a request to local 1394 OHCI controller and expected to | |
1366 | // complete without any event waiting. | |
1367 | generation = fw_card->generation; | |
1368 | smp_rmb(); // node_id vs. generation. | |
1369 | rcode = fw_run_transaction(fw_card, TCODE_READ_QUADLET_REQUEST, | |
1370 | fw_card->node_id, generation, SCODE_100, | |
1371 | CSR_REGISTER_BASE + CSR_CYCLE_TIME, | |
1372 | ®, sizeof(reg)); | |
1373 | if (rcode != RCODE_COMPLETE) | |
1374 | return -EIO; | |
1375 | ||
1376 | data = be32_to_cpu(reg); | |
1377 | *cur_cycle = data >> 12; | |
1378 | ||
1379 | return 0; | |
1380 | } | |
1381 | ||
9b4702b0 TS |
1382 | /** |
1383 | * amdtp_domain_start - start sending packets for isoc context in the domain. | |
1384 | * @d: the AMDTP domain. | |
acfedcbe | 1385 | * @ir_delay_cycle: the cycle delay to start all IR contexts. |
9b4702b0 | 1386 | */ |
acfedcbe | 1387 | int amdtp_domain_start(struct amdtp_domain *d, unsigned int ir_delay_cycle) |
9b4702b0 | 1388 | { |
1a4be183 TS |
1389 | static const struct { |
1390 | unsigned int data_block; | |
1391 | unsigned int syt_offset; | |
1392 | } *entry, initial_state[] = { | |
1393 | [CIP_SFC_32000] = { 4, 3072 }, | |
1394 | [CIP_SFC_48000] = { 6, 1024 }, | |
1395 | [CIP_SFC_96000] = { 12, 1024 }, | |
1396 | [CIP_SFC_192000] = { 24, 1024 }, | |
1397 | [CIP_SFC_44100] = { 0, 67 }, | |
1398 | [CIP_SFC_88200] = { 0, 67 }, | |
1399 | [CIP_SFC_176400] = { 0, 67 }, | |
1400 | }; | |
af86b0b1 TS |
1401 | unsigned int events_per_buffer = d->events_per_buffer; |
1402 | unsigned int events_per_period = d->events_per_period; | |
1403 | unsigned int idle_irq_interval; | |
1404 | unsigned int queue_size; | |
9b4702b0 | 1405 | struct amdtp_stream *s; |
acfedcbe TS |
1406 | int cycle; |
1407 | int err; | |
9b4702b0 | 1408 | |
60dd4929 | 1409 | // Select an IT context as IRQ target. |
9b4702b0 | 1410 | list_for_each_entry(s, &d->streams, list) { |
60dd4929 | 1411 | if (s->direction == AMDTP_OUT_STREAM) |
9b4702b0 TS |
1412 | break; |
1413 | } | |
60dd4929 TS |
1414 | if (!s) |
1415 | return -ENXIO; | |
1416 | d->irq_target = s; | |
9b4702b0 | 1417 | |
af86b0b1 TS |
1418 | // This is a case that AMDTP streams in domain run just for MIDI |
1419 | // substream. Use the number of events equivalent to 10 msec as | |
1420 | // interval of hardware IRQ. | |
1421 | if (events_per_period == 0) | |
1422 | events_per_period = amdtp_rate_table[d->irq_target->sfc] / 100; | |
1423 | if (events_per_buffer == 0) | |
1424 | events_per_buffer = events_per_period * 3; | |
1425 | ||
1426 | queue_size = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_buffer, | |
1427 | amdtp_rate_table[d->irq_target->sfc]); | |
1428 | ||
25babf29 TS |
1429 | d->seq_descs = kcalloc(queue_size, sizeof(*d->seq_descs), GFP_KERNEL); |
1430 | if (!d->seq_descs) | |
1431 | return -ENOMEM; | |
1432 | d->seq_size = queue_size; | |
1433 | d->seq_tail = 0; | |
1434 | ||
1a4be183 TS |
1435 | entry = &initial_state[s->sfc]; |
1436 | d->data_block_state = entry->data_block; | |
1437 | d->syt_offset_state = entry->syt_offset; | |
1438 | d->last_syt_offset = TICKS_PER_CYCLE; | |
1439 | ||
acfedcbe TS |
1440 | if (ir_delay_cycle > 0) { |
1441 | struct fw_card *fw_card = fw_parent_device(s->unit)->card; | |
1442 | ||
1443 | err = get_current_cycle_time(fw_card, &cycle); | |
1444 | if (err < 0) | |
25babf29 | 1445 | goto error; |
acfedcbe TS |
1446 | |
1447 | // No need to care overflow in cycle field because of enough | |
1448 | // width. | |
1449 | cycle += ir_delay_cycle; | |
1450 | ||
1451 | // Round up to sec field. | |
1452 | if ((cycle & 0x00001fff) >= CYCLES_PER_SECOND) { | |
1453 | unsigned int sec; | |
1454 | ||
1455 | // The sec field can overflow. | |
1456 | sec = (cycle & 0xffffe000) >> 13; | |
1457 | cycle = (++sec << 13) | | |
1458 | ((cycle & 0x00001fff) / CYCLES_PER_SECOND); | |
1459 | } | |
1460 | ||
1461 | // In OHCI 1394 specification, lower 2 bits are available for | |
1462 | // sec field. | |
1463 | cycle &= 0x00007fff; | |
1464 | } else { | |
1465 | cycle = -1; | |
1466 | } | |
1467 | ||
60dd4929 | 1468 | list_for_each_entry(s, &d->streams, list) { |
acfedcbe TS |
1469 | int cycle_match; |
1470 | ||
1471 | if (s->direction == AMDTP_IN_STREAM) { | |
1472 | cycle_match = cycle; | |
1473 | } else { | |
1474 | // IT context starts immediately. | |
1475 | cycle_match = -1; | |
1a4be183 | 1476 | s->ctx_data.rx.seq_index = 0; |
acfedcbe TS |
1477 | } |
1478 | ||
60dd4929 | 1479 | if (s != d->irq_target) { |
2472cfb3 | 1480 | err = amdtp_stream_start(s, s->channel, s->speed, |
af86b0b1 | 1481 | cycle_match, queue_size, 0); |
60dd4929 TS |
1482 | if (err < 0) |
1483 | goto error; | |
1484 | } | |
9b4702b0 TS |
1485 | } |
1486 | ||
60dd4929 | 1487 | s = d->irq_target; |
af86b0b1 TS |
1488 | s->ctx_data.rx.events_per_period = events_per_period; |
1489 | s->ctx_data.rx.event_count = 0; | |
1a4be183 | 1490 | s->ctx_data.rx.seq_index = 0; |
af86b0b1 TS |
1491 | |
1492 | idle_irq_interval = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period, | |
1493 | amdtp_rate_table[d->irq_target->sfc]); | |
1494 | err = amdtp_stream_start(s, s->channel, s->speed, -1, queue_size, | |
1495 | idle_irq_interval); | |
60dd4929 TS |
1496 | if (err < 0) |
1497 | goto error; | |
1498 | ||
1499 | return 0; | |
1500 | error: | |
1501 | list_for_each_entry(s, &d->streams, list) | |
1502 | amdtp_stream_stop(s); | |
25babf29 TS |
1503 | kfree(d->seq_descs); |
1504 | d->seq_descs = NULL; | |
9b4702b0 TS |
1505 | return err; |
1506 | } | |
1507 | EXPORT_SYMBOL_GPL(amdtp_domain_start); | |
1508 | ||
6261f90b TS |
1509 | /** |
1510 | * amdtp_domain_stop - stop sending packets for isoc context in the same domain. | |
1511 | * @d: the AMDTP domain to which the isoc contexts belong. | |
1512 | */ | |
1513 | void amdtp_domain_stop(struct amdtp_domain *d) | |
1514 | { | |
1515 | struct amdtp_stream *s, *next; | |
1516 | ||
60dd4929 TS |
1517 | if (d->irq_target) |
1518 | amdtp_stream_stop(d->irq_target); | |
1519 | ||
6261f90b TS |
1520 | list_for_each_entry_safe(s, next, &d->streams, list) { |
1521 | list_del(&s->list); | |
1522 | ||
60dd4929 TS |
1523 | if (s != d->irq_target) |
1524 | amdtp_stream_stop(s); | |
6261f90b | 1525 | } |
d68c3123 TS |
1526 | |
1527 | d->events_per_period = 0; | |
60dd4929 | 1528 | d->irq_target = NULL; |
25babf29 TS |
1529 | |
1530 | kfree(d->seq_descs); | |
1531 | d->seq_descs = NULL; | |
6261f90b TS |
1532 | } |
1533 | EXPORT_SYMBOL_GPL(amdtp_domain_stop); |