[linux-2.6-block.git] / sound / arm / pxa2xx-ac97-lib.c

/*
 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
 * which contain:
 *
 * Author:	Nicolas Pitre
 * Created:	Dec 02, 2004
 * Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>

#include <sound/ac97_codec.h>
#include <sound/pxa2xx-lib.h>

#include <asm/irq.h>
#include <mach/regs-ac97.h>
#include <mach/audio.h>

static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;
static struct clk *ac97_clk;
static struct clk *ac97conf_clk;
static int reset_gpio;

extern void pxa27x_assert_ac97reset(int reset_gpio, int on);

/*
 * Beware PXA27x bugs:
 *
 *   o Slot 12 read from modem space will hang controller.
 *   o CDONE, SDONE interrupt fails after any slot 12 IO.
 *
 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
 * 1 jiffy timeout if interrupt never comes).
 */

unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
{
	unsigned short val = -1;
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	/* start read access across the ac97 link */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	if (reg == AC97_GPIO_STATUS)
		goto out;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_SDONE)) {
		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);
		val = -1;
		goto out;
	}

	/* valid data now */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	/* but we've just started another cycle... */
	wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);

out:	mutex_unlock(&car_mutex);
	return val;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);

void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
			unsigned short val)
{
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	*reg_addr = val;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_CDONE))
		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);

	mutex_unlock(&car_mutex);
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);

#ifdef CONFIG_PXA25x
static inline void pxa_ac97_warm_pxa25x(void)
{
	gsr_bits = 0;

	GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
}

static inline void pxa_ac97_cold_pxa25x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	GCR = GCR_COLD_RST;
	GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
}
#endif

#ifdef CONFIG_PXA27x
static inline void pxa_ac97_warm_pxa27x(void)
{
	gsr_bits = 0;

	/* warm reset broken on Bulverde, so manually keep AC97 reset high */
	pxa27x_assert_ac97reset(reset_gpio, 1);
	udelay(10);
	GCR |= GCR_WARM_RST;
	pxa27x_assert_ac97reset(reset_gpio, 0);
	udelay(500);
}

static inline void pxa_ac97_cold_pxa27x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* PXA27x Developers Manual section 13.5.2.2.1 */
	clk_enable(ac97conf_clk);
	udelay(5);
	clk_disable(ac97conf_clk);
	GCR = GCR_COLD_RST;
	udelay(50);
}
#endif

#ifdef CONFIG_PXA3xx
static inline void pxa_ac97_warm_pxa3xx(void)
{
	int timeout = 100;

	gsr_bits = 0;

	/* Can't use interrupts */
	GCR |= GCR_WARM_RST;
	while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(1);
}

static inline void pxa_ac97_cold_pxa3xx(void)
{
	int timeout = 1000;

	/* Hold CLKBPB for 100us */
	GCR = 0;
	GCR = GCR_CLKBPB;
	udelay(100);
	GCR = 0;

	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* Can't use interrupts on PXA3xx */
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);

	GCR = GCR_WARM_RST | GCR_COLD_RST;
	while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(10);
}
#endif

bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
{
	unsigned long gsr;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_warm_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_warm_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_warm_pxa3xx();
	else
#endif
		BUG();
	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);

bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
{
	unsigned long gsr;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_cold_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_cold_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_cold_pxa3xx();
	else
#endif
		BUG();

	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);


void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
{
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);

static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
{
	long status;

	status = GSR;
	if (status) {
		GSR = status;
		gsr_bits |= status;
		wake_up(&gsr_wq);

		/* Although we don't use those we still need to clear them
		   since they tend to spuriously trigger when MMC is used
		   (hardware bug? go figure)... */
		if (cpu_is_pxa27x()) {
			MISR = MISR_EOC;
			PISR = PISR_EOC;
			MCSR = MCSR_EOC;
		}

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

#ifdef CONFIG_PM
int pxa2xx_ac97_hw_suspend(void)
{
	GCR |= GCR_ACLINK_OFF;
	clk_disable(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);

int pxa2xx_ac97_hw_resume(void)
{
	clk_enable(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
#endif

int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
{
	int ret;
	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;

	if (pdata) {
		switch (pdata->reset_gpio) {
		case 95:
		case 113:
			reset_gpio = pdata->reset_gpio;
			break;
		case 0:
			reset_gpio = 113;
			break;
		case -1:
			break;
		default:
			dev_err(&dev->dev, "Invalid reset GPIO %d\n",
				pdata->reset_gpio);
		}
	} else {
		if (cpu_is_pxa27x())
			reset_gpio = 113;
	}

	if (cpu_is_pxa27x()) {
		/* Use GPIO 113 as AC97 Reset on Bulverde */
		pxa27x_assert_ac97reset(reset_gpio, 0);
		ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
		if (IS_ERR(ac97conf_clk)) {
			ret = PTR_ERR(ac97conf_clk);
			ac97conf_clk = NULL;
			goto err_conf;
		}
	}

	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	if (IS_ERR(ac97_clk)) {
		ret = PTR_ERR(ac97_clk);
		ac97_clk = NULL;
		goto err_clk;
	}

	ret = clk_enable(ac97_clk);
	if (ret)
		goto err_clk2;

	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
	if (ret < 0)
		goto err_irq;

	return 0;

err_irq:
	GCR |= GCR_ACLINK_OFF;
err_clk2:
	clk_put(ac97_clk);
	ac97_clk = NULL;
err_clk:
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
err_conf:
	return ret;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);

void pxa2xx_ac97_hw_remove(struct platform_device *dev)
{
	GCR |= GCR_ACLINK_OFF;
	free_irq(IRQ_AC97, NULL);
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
	clk_disable(ac97_clk);
	clk_put(ac97_clk);
	ac97_clk = NULL;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);

MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
MODULE_LICENSE("GPL");
Commit	Line	Data
9c636342 DB	1	/*
	2	* Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
	3	* which contain:
	4	*
	5	* Author: Nicolas Pitre
	6	* Created: Dec 02, 2004
	7	* Copyright: MontaVista Software Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/clk.h>
	18	#include <linux/delay.h>
da155d5b	19	#include <linux/module.h>
9c636342 DB	20
	21	#include <sound/ac97_codec.h>
	22	#include <sound/pxa2xx-lib.h>
	23
	24	#include <asm/irq.h>
1f017a99	25	#include <mach/regs-ac97.h>
9c636342 DB	26	#include <mach/audio.h>
	27
	28	static DEFINE_MUTEX(car_mutex);
	29	static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
	30	static volatile long gsr_bits;
	31	static struct clk *ac97_clk;
9c636342	32	static struct clk *ac97conf_clk;
26ade896	33	static int reset_gpio;
9c636342	34
fb1bf8cd EM	35	extern void pxa27x_assert_ac97reset(int reset_gpio, int on);
fb1bf8cd EM	36
9c636342 DB	37	/*
	38	* Beware PXA27x bugs:
	39	*
	40	* o Slot 12 read from modem space will hang controller.
	41	* o CDONE, SDONE interrupt fails after any slot 12 IO.
	42	*
	43	* We therefore have an hybrid approach for waiting on SDONE (interrupt or
	44	* 1 jiffy timeout if interrupt never comes).
	45	*/
	46
	47	unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
	48	{
	49	unsigned short val = -1;
	50	volatile u32 *reg_addr;
	51
	52	mutex_lock(&car_mutex);
	53
	54	/* set up primary or secondary codec space */
8825e8e8	55	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
9c636342 DB	56	reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	57	else
	58	reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DB	59	reg_addr += (reg >> 1);
	60
	61	/* start read access across the ac97 link */
	62	GSR = GSR_CDONE \| GSR_SDONE;
	63	gsr_bits = 0;
	64	val = *reg_addr;
	65	if (reg == AC97_GPIO_STATUS)
	66	goto out;
	67	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1) <= 0 &&
	68	!((GSR \| gsr_bits) & GSR_SDONE)) {
	69	printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
	70	__func__, reg, GSR \| gsr_bits);
	71	val = -1;
	72	goto out;
	73	}
	74
	75	/* valid data now */
	76	GSR = GSR_CDONE \| GSR_SDONE;
	77	gsr_bits = 0;
	78	val = *reg_addr;
	79	/* but we've just started another cycle... */
	80	wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1);
	81
	82	out: mutex_unlock(&car_mutex);
	83	return val;
	84	}
	85	EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
	86
	87	void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	88	unsigned short val)
	89	{
	90	volatile u32 *reg_addr;
	91
	92	mutex_lock(&car_mutex);
	93
	94	/* set up primary or secondary codec space */
8825e8e8	95	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
9c636342 DB	96	reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	97	else
	98	reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DB	99	reg_addr += (reg >> 1);
	100
	101	GSR = GSR_CDONE \| GSR_SDONE;
	102	gsr_bits = 0;
	103	*reg_addr = val;
	104	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_CDONE, 1) <= 0 &&
	105	!((GSR \| gsr_bits) & GSR_CDONE))
	106	printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
	107	__func__, reg, GSR \| gsr_bits);
	108
	109	mutex_unlock(&car_mutex);
	110	}
	111	EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
	112
9d1cf39b DB	113	#ifdef CONFIG_PXA25x
9d1cf39b DB	114	static inline void pxa_ac97_warm_pxa25x(void)
9c636342	115	{
9c636342 DB	116	gsr_bits = 0;
9c636342 DB	117
9d1cf39b DB	118	GCR \|= GCR_WARM_RST \| GCR_PRIRDY_IEN \| GCR_SECRDY_IEN;
	119	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	120	}
	121
	122	static inline void pxa_ac97_cold_pxa25x(void)
	123	{
	124	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	125	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	126
	127	gsr_bits = 0;
	128
	129	GCR = GCR_COLD_RST;
	130	GCR \|= GCR_CDONE_IE\|GCR_SDONE_IE;
	131	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	132	}
	133	#endif
	134
9c636342	135	#ifdef CONFIG_PXA27x
9d1cf39b DB	136	static inline void pxa_ac97_warm_pxa27x(void)
	137	{
	138	gsr_bits = 0;
	139
fb1bf8cd EM	140	/* warm reset broken on Bulverde, so manually keep AC97 reset high */
fb1bf8cd EM	141	pxa27x_assert_ac97reset(reset_gpio, 1);
9c636342 DB	142	udelay(10);
9c636342 DB	143	GCR \|= GCR_WARM_RST;
fb1bf8cd	144	pxa27x_assert_ac97reset(reset_gpio, 0);
9c636342	145	udelay(500);
9d1cf39b DB	146	}
	147
	148	static inline void pxa_ac97_cold_pxa27x(void)
	149	{
	150	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	151	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	152
	153	gsr_bits = 0;
	154
	155	/* PXA27x Developers Manual section 13.5.2.2.1 */
	156	clk_enable(ac97conf_clk);
	157	udelay(5);
	158	clk_disable(ac97conf_clk);
	159	GCR = GCR_COLD_RST;
	160	udelay(50);
	161	}
9c636342 DB	162	#endif
9c636342 DB	163
9d1cf39b DB	164	#ifdef CONFIG_PXA3xx
	165	static inline void pxa_ac97_warm_pxa3xx(void)
	166	{
	167	int timeout = 100;
9c636342	168
9d1cf39b	169	gsr_bits = 0;
9c636342	170
9d1cf39b DB	171	/* Can't use interrupts */
	172	GCR \|= GCR_WARM_RST;
	173	while (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)) && timeout--)
	174	mdelay(1);
9c636342	175	}
9c636342	176
9d1cf39b	177	static inline void pxa_ac97_cold_pxa3xx(void)
9c636342	178	{
9c636342 DB	179	int timeout = 1000;
	180
	181	/* Hold CLKBPB for 100us */
	182	GCR = 0;
	183	GCR = GCR_CLKBPB;
	184	udelay(100);
	185	GCR = 0;
9c636342 DB	186
	187	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	188	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	189
	190	gsr_bits = 0;
9d1cf39b	191
9c636342 DB	192	/* Can't use interrupts on PXA3xx */
	193	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	194
	195	GCR = GCR_WARM_RST \| GCR_COLD_RST;
	196	while (!(GSR & (GSR_PCR \| GSR_SCR)) && timeout--)
	197	mdelay(10);
9d1cf39b DB	198	}
	199	#endif
	200
	201	bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
	202	{
057de50c LF	203	unsigned long gsr;
057de50c LF	204
9d1cf39b	205	#ifdef CONFIG_PXA25x
8825e8e8	206	if (cpu_is_pxa25x())
9d1cf39b DB	207	pxa_ac97_warm_pxa25x();
9d1cf39b DB	208	else
9c636342	209	#endif
9d1cf39b DB	210	#ifdef CONFIG_PXA27x
	211	if (cpu_is_pxa27x())
	212	pxa_ac97_warm_pxa27x();
	213	else
	214	#endif
	215	#ifdef CONFIG_PXA3xx
	216	if (cpu_is_pxa3xx())
	217	pxa_ac97_warm_pxa3xx();
	218	else
	219	#endif
	220	BUG();
057de50c LF	221	gsr = GSR \| gsr_bits;
057de50c LF	222	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9d1cf39b	223	printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
057de50c	224	__func__, gsr);
9d1cf39b DB	225
	226	return false;
	227	}
	228
	229	return true;
	230	}
	231	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
	232
	233	bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
	234	{
057de50c LF	235	unsigned long gsr;
057de50c LF	236
9d1cf39b	237	#ifdef CONFIG_PXA25x
8825e8e8	238	if (cpu_is_pxa25x())
9d1cf39b DB	239	pxa_ac97_cold_pxa25x();
	240	else
	241	#endif
	242	#ifdef CONFIG_PXA27x
	243	if (cpu_is_pxa27x())
	244	pxa_ac97_cold_pxa27x();
	245	else
	246	#endif
	247	#ifdef CONFIG_PXA3xx
	248	if (cpu_is_pxa3xx())
	249	pxa_ac97_cold_pxa3xx();
	250	else
	251	#endif
	252	BUG();
9c636342	253
057de50c LF	254	gsr = GSR \| gsr_bits;
057de50c LF	255	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9c636342	256	printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
057de50c	257	__func__, gsr);
9c636342 DB	258
	259	return false;
	260	}
	261
	262	return true;
	263	}
	264	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
	265
	266
	267	void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
	268	{
	269	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	270	GCR \|= GCR_SDONE_IE\|GCR_CDONE_IE;
	271	}
	272	EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
	273
	274	static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
	275	{
	276	long status;
	277
	278	status = GSR;
	279	if (status) {
	280	GSR = status;
	281	gsr_bits \|= status;
	282	wake_up(&gsr_wq);
	283
9c636342 DB	284	/* Although we don't use those we still need to clear them
	285	since they tend to spuriously trigger when MMC is used
	286	(hardware bug? go figure)... */
9d1cf39b DB	287	if (cpu_is_pxa27x()) {
	288	MISR = MISR_EOC;
	289	PISR = PISR_EOC;
	290	MCSR = MCSR_EOC;
	291	}
9c636342 DB	292
	293	return IRQ_HANDLED;
	294	}
	295
	296	return IRQ_NONE;
	297	}
	298
	299	#ifdef CONFIG_PM
	300	int pxa2xx_ac97_hw_suspend(void)
	301	{
	302	GCR \|= GCR_ACLINK_OFF;
	303	clk_disable(ac97_clk);
	304	return 0;
	305	}
	306	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
	307
	308	int pxa2xx_ac97_hw_resume(void)
	309	{
9c636342 DB	310	clk_enable(ac97_clk);
	311	return 0;
	312	}
	313	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
	314	#endif
	315
	316	int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
	317	{
	318	int ret;
eae17754	319	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
26ade896 RJ	320
	321	if (pdata) {
	322	switch (pdata->reset_gpio) {
	323	case 95:
	324	case 113:
	325	reset_gpio = pdata->reset_gpio;
	326	break;
	327	case 0:
	328	reset_gpio = 113;
	329	break;
	330	case -1:
	331	break;
	332	default:
1f218695	333	dev_err(&dev->dev, "Invalid reset GPIO %d\n",
26ade896 RJ	334	pdata->reset_gpio);
	335	}
	336	} else {
	337	if (cpu_is_pxa27x())
	338	reset_gpio = 113;
	339	}
9c636342	340
9d1cf39b DB	341	if (cpu_is_pxa27x()) {
9d1cf39b DB	342	/* Use GPIO 113 as AC97 Reset on Bulverde */
fb1bf8cd	343	pxa27x_assert_ac97reset(reset_gpio, 0);
9d1cf39b DB	344	ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
	345	if (IS_ERR(ac97conf_clk)) {
	346	ret = PTR_ERR(ac97conf_clk);
	347	ac97conf_clk = NULL;
79612336	348	goto err_conf;
9d1cf39b	349	}
9c636342	350	}
9c636342 DB	351
	352	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	353	if (IS_ERR(ac97_clk)) {
	354	ret = PTR_ERR(ac97_clk);
	355	ac97_clk = NULL;
79612336	356	goto err_clk;
9c636342 DB	357	}
9c636342 DB	358
79612336 DB	359	ret = clk_enable(ac97_clk);
	360	if (ret)
	361	goto err_clk2;
	362
88e24c3a	363	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
79612336 DB	364	if (ret < 0)
	365	goto err_irq;
	366
	367	return 0;
9c636342 DB	368
	369	err_irq:
	370	GCR \|= GCR_ACLINK_OFF;
79612336 DB	371	err_clk2:
	372	clk_put(ac97_clk);
	373	ac97_clk = NULL;
	374	err_clk:
9c636342 DB	375	if (ac97conf_clk) {
	376	clk_put(ac97conf_clk);
	377	ac97conf_clk = NULL;
	378	}
79612336	379	err_conf:
9c636342 DB	380	return ret;
	381	}
	382	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
	383
	384	void pxa2xx_ac97_hw_remove(struct platform_device *dev)
	385	{
	386	GCR \|= GCR_ACLINK_OFF;
	387	free_irq(IRQ_AC97, NULL);
9d1cf39b DB	388	if (ac97conf_clk) {
	389	clk_put(ac97conf_clk);
	390	ac97conf_clk = NULL;
	391	}
9c636342 DB	392	clk_disable(ac97_clk);
	393	clk_put(ac97_clk);
	394	ac97_clk = NULL;
	395	}
	396	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
	397
	398	MODULE_AUTHOR("Nicolas Pitre");
	399	MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
	400	MODULE_LICENSE("GPL");
	401