[linux-block.git] / sound / arm / pxa2xx-ac97-lib.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
 * which contain:
 *
 * Author:	Nicolas Pitre
 * Created:	Dec 02, 2004
 * Copyright:	MontaVista Software Inc.
 */

#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>

#include <sound/pxa2xx-lib.h>

#include <mach/irqs.h>
#include <mach/regs-ac97.h>
#include <mach/audio.h>

static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;
static struct clk *ac97_clk;
static struct clk *ac97conf_clk;
static int reset_gpio;

extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);

/*
 * Beware PXA27x bugs:
 *
 *   o Slot 12 read from modem space will hang controller.
 *   o CDONE, SDONE interrupt fails after any slot 12 IO.
 *
 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
 * 1 jiffy timeout if interrupt never comes).
 */

int pxa2xx_ac97_read(int slot, unsigned short reg)
{
	int val = -ENODEV;
	volatile u32 *reg_addr;

	if (slot > 0)
		return -ENODEV;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	/* start read access across the ac97 link */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = (*reg_addr & 0xffff);
	if (reg == AC97_GPIO_STATUS)
		goto out;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_SDONE)) {
		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);
		val = -ETIMEDOUT;
		goto out;
	}

	/* valid data now */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = (*reg_addr & 0xffff);
	/* but we've just started another cycle... */
	wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);

out:	mutex_unlock(&car_mutex);
	return val;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);

int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
{
	volatile u32 *reg_addr;
	int ret = 0;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	*reg_addr = val;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_CDONE)) {
		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);
		ret = -EIO;
	}

	mutex_unlock(&car_mutex);
	return ret;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);

#ifdef CONFIG_PXA25x
static inline void pxa_ac97_warm_pxa25x(void)
{
	gsr_bits = 0;

	GCR |= GCR_WARM_RST;
}

static inline void pxa_ac97_cold_pxa25x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	GCR = GCR_COLD_RST;
}
#endif

#ifdef CONFIG_PXA27x
static inline void pxa_ac97_warm_pxa27x(void)
{
	gsr_bits = 0;

	/* warm reset broken on Bulverde, so manually keep AC97 reset high */
	pxa27x_configure_ac97reset(reset_gpio, true);
	udelay(10);
	GCR |= GCR_WARM_RST;
	pxa27x_configure_ac97reset(reset_gpio, false);
	udelay(500);
}

static inline void pxa_ac97_cold_pxa27x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* PXA27x Developers Manual section 13.5.2.2.1 */
	clk_prepare_enable(ac97conf_clk);
	udelay(5);
	clk_disable_unprepare(ac97conf_clk);
	GCR = GCR_COLD_RST | GCR_WARM_RST;
}
#endif

#ifdef CONFIG_PXA3xx
static inline void pxa_ac97_warm_pxa3xx(void)
{
	gsr_bits = 0;

	/* Can't use interrupts */
	GCR |= GCR_WARM_RST;
}

static inline void pxa_ac97_cold_pxa3xx(void)
{
	/* Hold CLKBPB for 100us */
	GCR = 0;
	GCR = GCR_CLKBPB;
	udelay(100);
	GCR = 0;

	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* Can't use interrupts on PXA3xx */
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);

	GCR = GCR_WARM_RST | GCR_COLD_RST;
}
#endif

bool pxa2xx_ac97_try_warm_reset(void)
{
	unsigned long gsr;
	unsigned int timeout = 100;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_warm_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_warm_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_warm_pxa3xx();
	else
#endif
		snd_BUG();

	while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(1);

	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);

bool pxa2xx_ac97_try_cold_reset(void)
{
	unsigned long gsr;
	unsigned int timeout = 1000;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_cold_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_cold_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_cold_pxa3xx();
	else
#endif
		snd_BUG();

	while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(1);

	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);


void pxa2xx_ac97_finish_reset(void)
{
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);

static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
{
	long status;

	status = GSR;
	if (status) {
		GSR = status;
		gsr_bits |= status;
		wake_up(&gsr_wq);

		/* Although we don't use those we still need to clear them
		   since they tend to spuriously trigger when MMC is used
		   (hardware bug? go figure)... */
		if (cpu_is_pxa27x()) {
			MISR = MISR_EOC;
			PISR = PISR_EOC;
			MCSR = MCSR_EOC;
		}

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

#ifdef CONFIG_PM
int pxa2xx_ac97_hw_suspend(void)
{
	GCR |= GCR_ACLINK_OFF;
	clk_disable_unprepare(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);

int pxa2xx_ac97_hw_resume(void)
{
	clk_prepare_enable(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
#endif

int pxa2xx_ac97_hw_probe(struct platform_device *dev)
{
	int ret;
	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;

	if (pdata) {
		switch (pdata->reset_gpio) {
		case 95:
		case 113:
			reset_gpio = pdata->reset_gpio;
			break;
		case 0:
			reset_gpio = 113;
			break;
		case -1:
			break;
		default:
			dev_err(&dev->dev, "Invalid reset GPIO %d\n",
				pdata->reset_gpio);
		}
	} else if (!pdata && dev->dev.of_node) {
		pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
		if (!pdata)
			return -ENOMEM;
		pdata->reset_gpio = of_get_named_gpio(dev->dev.of_node,
						      "reset-gpios", 0);
		if (pdata->reset_gpio == -ENOENT)
			pdata->reset_gpio = -1;
		else if (pdata->reset_gpio < 0)
			return pdata->reset_gpio;
		reset_gpio = pdata->reset_gpio;
	} else {
		if (cpu_is_pxa27x())
			reset_gpio = 113;
	}

	if (cpu_is_pxa27x()) {
		/*
		 * This gpio is needed for a work-around to a bug in the ac97
		 * controller during warm reset.  The direction and level is set
		 * here so that it is an output driven high when switching from
		 * AC97_nRESET alt function to generic gpio.
		 */
		ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
				       "pxa27x ac97 reset");
		if (ret < 0) {
			pr_err("%s: gpio_request_one() failed: %d\n",
			       __func__, ret);
			goto err_conf;
		}
		pxa27x_configure_ac97reset(reset_gpio, false);

		ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
		if (IS_ERR(ac97conf_clk)) {
			ret = PTR_ERR(ac97conf_clk);
			ac97conf_clk = NULL;
			goto err_conf;
		}
	}

	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	if (IS_ERR(ac97_clk)) {
		ret = PTR_ERR(ac97_clk);
		ac97_clk = NULL;
		goto err_clk;
	}

	ret = clk_prepare_enable(ac97_clk);
	if (ret)
		goto err_clk2;

	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
	if (ret < 0)
		goto err_irq;

	return 0;

err_irq:
	GCR |= GCR_ACLINK_OFF;
err_clk2:
	clk_put(ac97_clk);
	ac97_clk = NULL;
err_clk:
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
err_conf:
	return ret;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);

void pxa2xx_ac97_hw_remove(struct platform_device *dev)
{
	if (cpu_is_pxa27x())
		gpio_free(reset_gpio);
	GCR |= GCR_ACLINK_OFF;
	free_irq(IRQ_AC97, NULL);
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
	clk_disable_unprepare(ac97_clk);
	clk_put(ac97_clk);
	ac97_clk = NULL;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);

MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
9c636342 DB	2	/*
	3	* Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
	4	* which contain:
	5	*
	6	* Author: Nicolas Pitre
	7	* Created: Dec 02, 2004
	8	* Copyright: MontaVista Software Inc.
9c636342 DB	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/clk.h>
	15	#include <linux/delay.h>
da155d5b	16	#include <linux/module.h>
23019a73	17	#include <linux/io.h>
3b4bc7bc	18	#include <linux/gpio.h>
a4519526	19	#include <linux/of_gpio.h>
9c636342	20
9c636342 DB	21	#include <sound/pxa2xx-lib.h>
9c636342 DB	22
9482ee71	23	#include <mach/irqs.h>
1f017a99	24	#include <mach/regs-ac97.h>
9c636342 DB	25	#include <mach/audio.h>
	26
	27	static DEFINE_MUTEX(car_mutex);
	28	static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
	29	static volatile long gsr_bits;
	30	static struct clk *ac97_clk;
9c636342	31	static struct clk *ac97conf_clk;
26ade896	32	static int reset_gpio;
9c636342	33
053fe0f1	34	extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
fb1bf8cd	35
9c636342 DB	36	/*
	37	* Beware PXA27x bugs:
	38	*
	39	* o Slot 12 read from modem space will hang controller.
	40	* o CDONE, SDONE interrupt fails after any slot 12 IO.
	41	*
	42	* We therefore have an hybrid approach for waiting on SDONE (interrupt or
	43	* 1 jiffy timeout if interrupt never comes).
	44	*/
	45
6f8acad6	46	int pxa2xx_ac97_read(int slot, unsigned short reg)
9c636342	47	{
6f8acad6	48	int val = -ENODEV;
9c636342 DB	49	volatile u32 *reg_addr;
9c636342 DB	50
6f8acad6 RJ	51	if (slot > 0)
	52	return -ENODEV;
	53
9c636342 DB	54	mutex_lock(&car_mutex);
	55
	56	/* set up primary or secondary codec space */
8825e8e8	57	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
6f8acad6	58	reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
9c636342	59	else
6f8acad6	60	reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DB	61	reg_addr += (reg >> 1);
	62
	63	/* start read access across the ac97 link */
	64	GSR = GSR_CDONE \| GSR_SDONE;
	65	gsr_bits = 0;
6f8acad6	66	val = (*reg_addr & 0xffff);
9c636342 DB	67	if (reg == AC97_GPIO_STATUS)
	68	goto out;
	69	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1) <= 0 &&
	70	!((GSR \| gsr_bits) & GSR_SDONE)) {
	71	printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
	72	__func__, reg, GSR \| gsr_bits);
6f8acad6	73	val = -ETIMEDOUT;
9c636342 DB	74	goto out;
	75	}
	76
	77	/* valid data now */
	78	GSR = GSR_CDONE \| GSR_SDONE;
	79	gsr_bits = 0;
6f8acad6	80	val = (*reg_addr & 0xffff);
9c636342 DB	81	/* but we've just started another cycle... */
	82	wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1);
	83
	84	out: mutex_unlock(&car_mutex);
	85	return val;
	86	}
	87	EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
	88
6f8acad6	89	int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
9c636342 DB	90	{
9c636342 DB	91	volatile u32 *reg_addr;
6f8acad6	92	int ret = 0;
9c636342 DB	93
	94	mutex_lock(&car_mutex);
	95
	96	/* set up primary or secondary codec space */
8825e8e8	97	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
6f8acad6	98	reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
9c636342	99	else
6f8acad6	100	reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DB	101	reg_addr += (reg >> 1);
	102
	103	GSR = GSR_CDONE \| GSR_SDONE;
	104	gsr_bits = 0;
	105	*reg_addr = val;
	106	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_CDONE, 1) <= 0 &&
6f8acad6	107	!((GSR \| gsr_bits) & GSR_CDONE)) {
9c636342 DB	108	printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
9c636342 DB	109	__func__, reg, GSR \| gsr_bits);
6f8acad6 RJ	110	ret = -EIO;
6f8acad6 RJ	111	}
9c636342 DB	112
9c636342 DB	113	mutex_unlock(&car_mutex);
6f8acad6	114	return ret;
9c636342 DB	115	}
	116	EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
	117
9d1cf39b DB	118	#ifdef CONFIG_PXA25x
9d1cf39b DB	119	static inline void pxa_ac97_warm_pxa25x(void)
9c636342	120	{
9c636342 DB	121	gsr_bits = 0;
9c636342 DB	122
beb02cdd	123	GCR \|= GCR_WARM_RST;
9d1cf39b DB	124	}
	125
	126	static inline void pxa_ac97_cold_pxa25x(void)
	127	{
	128	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	129	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	130
	131	gsr_bits = 0;
	132
	133	GCR = GCR_COLD_RST;
9d1cf39b DB	134	}
	135	#endif
	136
9c636342	137	#ifdef CONFIG_PXA27x
9d1cf39b DB	138	static inline void pxa_ac97_warm_pxa27x(void)
	139	{
	140	gsr_bits = 0;
	141
fb1bf8cd	142	/* warm reset broken on Bulverde, so manually keep AC97 reset high */
053fe0f1	143	pxa27x_configure_ac97reset(reset_gpio, true);
9c636342 DB	144	udelay(10);
9c636342 DB	145	GCR \|= GCR_WARM_RST;
053fe0f1	146	pxa27x_configure_ac97reset(reset_gpio, false);
9c636342	147	udelay(500);
9d1cf39b DB	148	}
	149
	150	static inline void pxa_ac97_cold_pxa27x(void)
	151	{
	152	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	153	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	154
	155	gsr_bits = 0;
	156
	157	/* PXA27x Developers Manual section 13.5.2.2.1 */
4091d342	158	clk_prepare_enable(ac97conf_clk);
9d1cf39b	159	udelay(5);
4091d342	160	clk_disable_unprepare(ac97conf_clk);
41b645c8	161	GCR = GCR_COLD_RST \| GCR_WARM_RST;
9d1cf39b	162	}
9c636342 DB	163	#endif
9c636342 DB	164
9d1cf39b DB	165	#ifdef CONFIG_PXA3xx
	166	static inline void pxa_ac97_warm_pxa3xx(void)
	167	{
9d1cf39b	168	gsr_bits = 0;
9c636342	169
9d1cf39b DB	170	/* Can't use interrupts */
9d1cf39b DB	171	GCR \|= GCR_WARM_RST;
9c636342	172	}
9c636342	173
9d1cf39b	174	static inline void pxa_ac97_cold_pxa3xx(void)
9c636342	175	{
9c636342 DB	176	/* Hold CLKBPB for 100us */
	177	GCR = 0;
	178	GCR = GCR_CLKBPB;
	179	udelay(100);
	180	GCR = 0;
9c636342 DB	181
	182	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	183	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	184
	185	gsr_bits = 0;
9d1cf39b	186
9c636342 DB	187	/* Can't use interrupts on PXA3xx */
	188	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	189
	190	GCR = GCR_WARM_RST \| GCR_COLD_RST;
9d1cf39b DB	191	}
	192	#endif
	193
6f8acad6	194	bool pxa2xx_ac97_try_warm_reset(void)
9d1cf39b	195	{
057de50c	196	unsigned long gsr;
beb02cdd	197	unsigned int timeout = 100;
057de50c	198
9d1cf39b	199	#ifdef CONFIG_PXA25x
8825e8e8	200	if (cpu_is_pxa25x())
9d1cf39b DB	201	pxa_ac97_warm_pxa25x();
9d1cf39b DB	202	else
9c636342	203	#endif
9d1cf39b DB	204	#ifdef CONFIG_PXA27x
	205	if (cpu_is_pxa27x())
	206	pxa_ac97_warm_pxa27x();
	207	else
	208	#endif
	209	#ifdef CONFIG_PXA3xx
	210	if (cpu_is_pxa3xx())
	211	pxa_ac97_warm_pxa3xx();
	212	else
	213	#endif
88ec7ae8	214	snd_BUG();
beb02cdd DES	215
	216	while (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)) && timeout--)
	217	mdelay(1);
	218
057de50c LF	219	gsr = GSR \| gsr_bits;
057de50c LF	220	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9d1cf39b	221	printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
057de50c	222	__func__, gsr);
9d1cf39b DB	223
	224	return false;
	225	}
	226
	227	return true;
	228	}
	229	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
	230
6f8acad6	231	bool pxa2xx_ac97_try_cold_reset(void)
9d1cf39b	232	{
057de50c	233	unsigned long gsr;
beb02cdd	234	unsigned int timeout = 1000;
057de50c	235
9d1cf39b	236	#ifdef CONFIG_PXA25x
8825e8e8	237	if (cpu_is_pxa25x())
9d1cf39b DB	238	pxa_ac97_cold_pxa25x();
	239	else
	240	#endif
	241	#ifdef CONFIG_PXA27x
	242	if (cpu_is_pxa27x())
	243	pxa_ac97_cold_pxa27x();
	244	else
	245	#endif
	246	#ifdef CONFIG_PXA3xx
	247	if (cpu_is_pxa3xx())
	248	pxa_ac97_cold_pxa3xx();
	249	else
	250	#endif
88ec7ae8	251	snd_BUG();
9c636342	252
beb02cdd DES	253	while (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)) && timeout--)
	254	mdelay(1);
	255
057de50c LF	256	gsr = GSR \| gsr_bits;
057de50c LF	257	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9c636342	258	printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
057de50c	259	__func__, gsr);
9c636342 DB	260
	261	return false;
	262	}
	263
	264	return true;
	265	}
	266	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
	267
	268
6f8acad6	269	void pxa2xx_ac97_finish_reset(void)
9c636342 DB	270	{
	271	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	272	GCR \|= GCR_SDONE_IE\|GCR_CDONE_IE;
	273	}
	274	EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
	275
	276	static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
	277	{
	278	long status;
	279
	280	status = GSR;
	281	if (status) {
	282	GSR = status;
	283	gsr_bits \|= status;
	284	wake_up(&gsr_wq);
	285
9c636342 DB	286	/* Although we don't use those we still need to clear them
	287	since they tend to spuriously trigger when MMC is used
	288	(hardware bug? go figure)... */
9d1cf39b DB	289	if (cpu_is_pxa27x()) {
	290	MISR = MISR_EOC;
	291	PISR = PISR_EOC;
	292	MCSR = MCSR_EOC;
	293	}
9c636342 DB	294
	295	return IRQ_HANDLED;
	296	}
	297
	298	return IRQ_NONE;
	299	}
	300
	301	#ifdef CONFIG_PM
	302	int pxa2xx_ac97_hw_suspend(void)
	303	{
	304	GCR \|= GCR_ACLINK_OFF;
4091d342	305	clk_disable_unprepare(ac97_clk);
9c636342 DB	306	return 0;
	307	}
	308	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
	309
	310	int pxa2xx_ac97_hw_resume(void)
	311	{
4091d342	312	clk_prepare_enable(ac97_clk);
9c636342 DB	313	return 0;
	314	}
	315	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
	316	#endif
	317
e21596bb	318	int pxa2xx_ac97_hw_probe(struct platform_device *dev)
9c636342 DB	319	{
9c636342 DB	320	int ret;
eae17754	321	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
26ade896 RJ	322
	323	if (pdata) {
	324	switch (pdata->reset_gpio) {
	325	case 95:
	326	case 113:
	327	reset_gpio = pdata->reset_gpio;
	328	break;
	329	case 0:
	330	reset_gpio = 113;
	331	break;
	332	case -1:
	333	break;
	334	default:
1f218695	335	dev_err(&dev->dev, "Invalid reset GPIO %d\n",
26ade896 RJ	336	pdata->reset_gpio);
26ade896 RJ	337	}
a4519526 RJ	338	} else if (!pdata && dev->dev.of_node) {
	339	pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
	340	if (!pdata)
	341	return -ENOMEM;
	342	pdata->reset_gpio = of_get_named_gpio(dev->dev.of_node,
	343	"reset-gpios", 0);
	344	if (pdata->reset_gpio == -ENOENT)
	345	pdata->reset_gpio = -1;
	346	else if (pdata->reset_gpio < 0)
	347	return pdata->reset_gpio;
	348	reset_gpio = pdata->reset_gpio;
26ade896 RJ	349	} else {
	350	if (cpu_is_pxa27x())
	351	reset_gpio = 113;
	352	}
9c636342	353
9d1cf39b	354	if (cpu_is_pxa27x()) {
3b4bc7bc MD	355	/*
	356	* This gpio is needed for a work-around to a bug in the ac97
	357	* controller during warm reset. The direction and level is set
	358	* here so that it is an output driven high when switching from
	359	* AC97_nRESET alt function to generic gpio.
	360	*/
	361	ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
	362	"pxa27x ac97 reset");
	363	if (ret < 0) {
	364	pr_err("%s: gpio_request_one() failed: %d\n",
	365	__func__, ret);
	366	goto err_conf;
	367	}
053fe0f1	368	pxa27x_configure_ac97reset(reset_gpio, false);
3b4bc7bc	369
9d1cf39b DB	370	ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
	371	if (IS_ERR(ac97conf_clk)) {
	372	ret = PTR_ERR(ac97conf_clk);
	373	ac97conf_clk = NULL;
79612336	374	goto err_conf;
9d1cf39b	375	}
9c636342	376	}
9c636342 DB	377
	378	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	379	if (IS_ERR(ac97_clk)) {
	380	ret = PTR_ERR(ac97_clk);
	381	ac97_clk = NULL;
79612336	382	goto err_clk;
9c636342 DB	383	}
9c636342 DB	384
4091d342	385	ret = clk_prepare_enable(ac97_clk);
79612336 DB	386	if (ret)
	387	goto err_clk2;
	388
88e24c3a	389	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
79612336 DB	390	if (ret < 0)
	391	goto err_irq;
	392
	393	return 0;
9c636342 DB	394
	395	err_irq:
	396	GCR \|= GCR_ACLINK_OFF;
79612336 DB	397	err_clk2:
	398	clk_put(ac97_clk);
	399	ac97_clk = NULL;
	400	err_clk:
9c636342 DB	401	if (ac97conf_clk) {
	402	clk_put(ac97conf_clk);
	403	ac97conf_clk = NULL;
	404	}
79612336	405	err_conf:
9c636342 DB	406	return ret;
	407	}
	408	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
	409
	410	void pxa2xx_ac97_hw_remove(struct platform_device *dev)
	411	{
3b4bc7bc MD	412	if (cpu_is_pxa27x())
3b4bc7bc MD	413	gpio_free(reset_gpio);
9c636342 DB	414	GCR \|= GCR_ACLINK_OFF;
9c636342 DB	415	free_irq(IRQ_AC97, NULL);
9d1cf39b DB	416	if (ac97conf_clk) {
	417	clk_put(ac97conf_clk);
	418	ac97conf_clk = NULL;
	419	}
4091d342	420	clk_disable_unprepare(ac97_clk);
9c636342 DB	421	clk_put(ac97_clk);
	422	ac97_clk = NULL;
	423	}
	424	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
	425
	426	MODULE_AUTHOR("Nicolas Pitre");
	427	MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
	428	MODULE_LICENSE("GPL");
	429