Commit | Line | Data |
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41e9a804 TQ |
1 | #define _GNU_SOURCE |
2 | ||
3 | #include <assert.h> | |
47efb302 | 4 | #include <fcntl.h> |
47efb302 KX |
5 | #include <linux/perf_event.h> |
6 | #include <linux/bpf.h> | |
41e9a804 TQ |
7 | #include <sched.h> |
8 | #include <stdio.h> | |
9 | #include <stdlib.h> | |
10 | #include <sys/ioctl.h> | |
11 | #include <sys/resource.h> | |
12 | #include <sys/time.h> | |
13 | #include <sys/types.h> | |
14 | #include <sys/wait.h> | |
15 | #include <unistd.h> | |
16 | ||
47efb302 | 17 | #include "bpf_load.h" |
41e9a804 | 18 | #include "libbpf.h" |
205c8ada | 19 | #include "perf-sys.h" |
47efb302 KX |
20 | |
21 | #define SAMPLE_PERIOD 0x7fffffffffffffffULL | |
22 | ||
41e9a804 | 23 | static void check_on_cpu(int cpu, struct perf_event_attr *attr) |
47efb302 | 24 | { |
41e9a804 TQ |
25 | int pmu_fd, error = 0; |
26 | cpu_set_t set; | |
27 | __u64 value; | |
47efb302 | 28 | |
41e9a804 TQ |
29 | /* Move to target CPU */ |
30 | CPU_ZERO(&set); | |
31 | CPU_SET(cpu, &set); | |
32 | assert(sched_setaffinity(0, sizeof(set), &set) == 0); | |
33 | /* Open perf event and attach to the perf_event_array */ | |
34 | pmu_fd = sys_perf_event_open(attr, -1/*pid*/, cpu/*cpu*/, -1/*group_fd*/, 0); | |
35 | if (pmu_fd < 0) { | |
36 | fprintf(stderr, "sys_perf_event_open failed on CPU %d\n", cpu); | |
37 | error = 1; | |
38 | goto on_exit; | |
39 | } | |
40 | assert(bpf_map_update_elem(map_fd[0], &cpu, &pmu_fd, BPF_ANY) == 0); | |
41 | assert(ioctl(pmu_fd, PERF_EVENT_IOC_ENABLE, 0) == 0); | |
42 | /* Trigger the kprobe */ | |
43 | bpf_map_get_next_key(map_fd[1], &cpu, NULL); | |
44 | /* Check the value */ | |
45 | if (bpf_map_lookup_elem(map_fd[1], &cpu, &value)) { | |
46 | fprintf(stderr, "Value missing for CPU %d\n", cpu); | |
47 | error = 1; | |
48 | goto on_exit; | |
49 | } | |
50 | fprintf(stderr, "CPU %d: %llu\n", cpu, value); | |
51 | ||
52 | on_exit: | |
53 | assert(bpf_map_delete_elem(map_fd[0], &cpu) == 0 || error); | |
54 | assert(ioctl(pmu_fd, PERF_EVENT_IOC_DISABLE, 0) == 0 || error); | |
55 | assert(close(pmu_fd) == 0 || error); | |
56 | assert(bpf_map_delete_elem(map_fd[1], &cpu) == 0 || error); | |
57 | exit(error); | |
58 | } | |
59 | ||
60 | static void test_perf_event_array(struct perf_event_attr *attr, | |
61 | const char *name) | |
62 | { | |
63 | int i, status, nr_cpus = sysconf(_SC_NPROCESSORS_CONF); | |
64 | pid_t pid[nr_cpus]; | |
65 | int err = 0; | |
66 | ||
67 | printf("Test reading %s counters\n", name); | |
68 | ||
69 | for (i = 0; i < nr_cpus; i++) { | |
70 | pid[i] = fork(); | |
71 | assert(pid[i] >= 0); | |
72 | if (pid[i] == 0) { | |
73 | check_on_cpu(i, attr); | |
74 | exit(1); | |
75 | } | |
76 | } | |
77 | ||
78 | for (i = 0; i < nr_cpus; i++) { | |
79 | assert(waitpid(pid[i], &status, 0) == pid[i]); | |
80 | err |= status; | |
81 | } | |
82 | ||
83 | if (err) | |
84 | printf("Test: %s FAILED\n", name); | |
85 | } | |
86 | ||
87 | static void test_bpf_perf_event(void) | |
88 | { | |
89 | struct perf_event_attr attr_cycles = { | |
47efb302 KX |
90 | .freq = 0, |
91 | .sample_period = SAMPLE_PERIOD, | |
92 | .inherit = 0, | |
93 | .type = PERF_TYPE_HARDWARE, | |
94 | .read_format = 0, | |
95 | .sample_type = 0, | |
41e9a804 TQ |
96 | .config = PERF_COUNT_HW_CPU_CYCLES, |
97 | }; | |
98 | struct perf_event_attr attr_clock = { | |
99 | .freq = 0, | |
100 | .sample_period = SAMPLE_PERIOD, | |
101 | .inherit = 0, | |
102 | .type = PERF_TYPE_SOFTWARE, | |
103 | .read_format = 0, | |
104 | .sample_type = 0, | |
105 | .config = PERF_COUNT_SW_CPU_CLOCK, | |
106 | }; | |
107 | struct perf_event_attr attr_raw = { | |
108 | .freq = 0, | |
109 | .sample_period = SAMPLE_PERIOD, | |
110 | .inherit = 0, | |
111 | .type = PERF_TYPE_RAW, | |
112 | .read_format = 0, | |
113 | .sample_type = 0, | |
114 | /* Intel Instruction Retired */ | |
115 | .config = 0xc0, | |
116 | }; | |
117 | struct perf_event_attr attr_l1d_load = { | |
118 | .freq = 0, | |
119 | .sample_period = SAMPLE_PERIOD, | |
120 | .inherit = 0, | |
121 | .type = PERF_TYPE_HW_CACHE, | |
122 | .read_format = 0, | |
123 | .sample_type = 0, | |
124 | .config = | |
125 | PERF_COUNT_HW_CACHE_L1D | | |
126 | (PERF_COUNT_HW_CACHE_OP_READ << 8) | | |
127 | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16), | |
128 | }; | |
129 | struct perf_event_attr attr_llc_miss = { | |
130 | .freq = 0, | |
131 | .sample_period = SAMPLE_PERIOD, | |
132 | .inherit = 0, | |
133 | .type = PERF_TYPE_HW_CACHE, | |
134 | .read_format = 0, | |
135 | .sample_type = 0, | |
136 | .config = | |
137 | PERF_COUNT_HW_CACHE_LL | | |
138 | (PERF_COUNT_HW_CACHE_OP_READ << 8) | | |
139 | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16), | |
140 | }; | |
141 | struct perf_event_attr attr_msr_tsc = { | |
142 | .freq = 0, | |
143 | .sample_period = 0, | |
144 | .inherit = 0, | |
145 | /* From /sys/bus/event_source/devices/msr/ */ | |
146 | .type = 7, | |
147 | .read_format = 0, | |
148 | .sample_type = 0, | |
149 | .config = 0, | |
47efb302 KX |
150 | }; |
151 | ||
41e9a804 TQ |
152 | test_perf_event_array(&attr_cycles, "HARDWARE-cycles"); |
153 | test_perf_event_array(&attr_clock, "SOFTWARE-clock"); | |
154 | test_perf_event_array(&attr_raw, "RAW-instruction-retired"); | |
155 | test_perf_event_array(&attr_l1d_load, "HW_CACHE-L1D-load"); | |
47efb302 | 156 | |
41e9a804 TQ |
157 | /* below tests may fail in qemu */ |
158 | test_perf_event_array(&attr_llc_miss, "HW_CACHE-LLC-miss"); | |
159 | test_perf_event_array(&attr_msr_tsc, "Dynamic-msr-tsc"); | |
47efb302 KX |
160 | } |
161 | ||
162 | int main(int argc, char **argv) | |
163 | { | |
41e9a804 | 164 | struct rlimit r = {RLIM_INFINITY, RLIM_INFINITY}; |
47efb302 KX |
165 | char filename[256]; |
166 | ||
167 | snprintf(filename, sizeof(filename), "%s_kern.o", argv[0]); | |
168 | ||
41e9a804 | 169 | setrlimit(RLIMIT_MEMLOCK, &r); |
47efb302 KX |
170 | if (load_bpf_file(filename)) { |
171 | printf("%s", bpf_log_buf); | |
172 | return 1; | |
173 | } | |
174 | ||
175 | test_bpf_perf_event(); | |
47efb302 KX |
176 | return 0; |
177 | } |