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2e5f0320 | 1 | /* |
076d3e10 LB |
2 | * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support |
3 | * Copyright (c) 2008-2009 Marvell Semiconductor | |
2e5f0320 LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
11 | #include <linux/list.h> | |
12 | #include <linux/netdevice.h> | |
13 | #include <linux/phy.h> | |
14 | #include "dsa_priv.h" | |
15 | #include "mv88e6xxx.h" | |
16 | ||
17 | static char *mv88e6131_probe(struct mii_bus *bus, int sw_addr) | |
18 | { | |
19 | int ret; | |
20 | ||
21 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03); | |
22 | if (ret >= 0) { | |
23 | ret &= 0xfff0; | |
076d3e10 LB |
24 | if (ret == 0x0950) |
25 | return "Marvell 88E6095/88E6095F"; | |
2e5f0320 LB |
26 | if (ret == 0x1060) |
27 | return "Marvell 88E6131"; | |
28 | } | |
29 | ||
30 | return NULL; | |
31 | } | |
32 | ||
33 | static int mv88e6131_switch_reset(struct dsa_switch *ds) | |
34 | { | |
35 | int i; | |
36 | int ret; | |
37 | ||
38 | /* | |
39 | * Set all ports to the disabled state. | |
40 | */ | |
076d3e10 | 41 | for (i = 0; i < 11; i++) { |
2e5f0320 LB |
42 | ret = REG_READ(REG_PORT(i), 0x04); |
43 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); | |
44 | } | |
45 | ||
46 | /* | |
47 | * Wait for transmit queues to drain. | |
48 | */ | |
49 | msleep(2); | |
50 | ||
51 | /* | |
52 | * Reset the switch. | |
53 | */ | |
54 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); | |
55 | ||
56 | /* | |
57 | * Wait up to one second for reset to complete. | |
58 | */ | |
59 | for (i = 0; i < 1000; i++) { | |
60 | ret = REG_READ(REG_GLOBAL, 0x00); | |
61 | if ((ret & 0xc800) == 0xc800) | |
62 | break; | |
63 | ||
64 | msleep(1); | |
65 | } | |
66 | if (i == 1000) | |
67 | return -ETIMEDOUT; | |
68 | ||
69 | return 0; | |
70 | } | |
71 | ||
72 | static int mv88e6131_setup_global(struct dsa_switch *ds) | |
73 | { | |
74 | int ret; | |
75 | int i; | |
76 | ||
77 | /* | |
78 | * Enable the PHY polling unit, don't discard packets with | |
79 | * excessive collisions, use a weighted fair queueing scheme | |
80 | * to arbitrate between packet queues, set the maximum frame | |
81 | * size to 1632, and mask all interrupt sources. | |
82 | */ | |
83 | REG_WRITE(REG_GLOBAL, 0x04, 0x4400); | |
84 | ||
85 | /* | |
86 | * Set the default address aging time to 5 minutes, and | |
87 | * enable address learn messages to be sent to all message | |
88 | * ports. | |
89 | */ | |
90 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); | |
91 | ||
92 | /* | |
93 | * Configure the priority mapping registers. | |
94 | */ | |
95 | ret = mv88e6xxx_config_prio(ds); | |
96 | if (ret < 0) | |
97 | return ret; | |
98 | ||
99 | /* | |
100 | * Set the VLAN ethertype to 0x8100. | |
101 | */ | |
102 | REG_WRITE(REG_GLOBAL, 0x19, 0x8100); | |
103 | ||
104 | /* | |
105 | * Disable ARP mirroring, and configure the cpu port as the | |
106 | * port to which ingress and egress monitor frames are to be | |
107 | * sent. | |
108 | */ | |
109 | REG_WRITE(REG_GLOBAL, 0x1a, (ds->cpu_port * 0x1100) | 0x00f0); | |
110 | ||
111 | /* | |
112 | * Disable cascade port functionality, and set the switch's | |
113 | * DSA device number to zero. | |
114 | */ | |
115 | REG_WRITE(REG_GLOBAL, 0x1c, 0xe000); | |
116 | ||
117 | /* | |
118 | * Send all frames with destination addresses matching | |
119 | * 01:80:c2:00:00:0x to the CPU port. | |
120 | */ | |
121 | REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); | |
122 | ||
123 | /* | |
124 | * Ignore removed tag data on doubly tagged packets, disable | |
125 | * flow control messages, force flow control priority to the | |
126 | * highest, and send all special multicast frames to the CPU | |
127 | * port at the higest priority. | |
128 | */ | |
129 | REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); | |
130 | ||
131 | /* | |
132 | * Map all DSA device IDs to the CPU port. | |
133 | */ | |
134 | for (i = 0; i < 32; i++) | |
135 | REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | ds->cpu_port); | |
136 | ||
137 | /* | |
138 | * Clear all trunk masks. | |
139 | */ | |
140 | for (i = 0; i < 8; i++) | |
076d3e10 | 141 | REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff); |
2e5f0320 LB |
142 | |
143 | /* | |
144 | * Clear all trunk mappings. | |
145 | */ | |
146 | for (i = 0; i < 16; i++) | |
147 | REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); | |
148 | ||
149 | /* | |
150 | * Force the priority of IGMP/MLD snoop frames and ARP frames | |
151 | * to the highest setting. | |
152 | */ | |
153 | REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff); | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
158 | static int mv88e6131_setup_port(struct dsa_switch *ds, int p) | |
159 | { | |
160 | int addr = REG_PORT(p); | |
161 | ||
162 | /* | |
163 | * MAC Forcing register: don't force link, speed, duplex | |
076d3e10 LB |
164 | * or flow control state to any particular values on physical |
165 | * ports, but force the CPU port to 1000 Mb/s full duplex. | |
2e5f0320 | 166 | */ |
076d3e10 LB |
167 | if (p == ds->cpu_port) |
168 | REG_WRITE(addr, 0x01, 0x003e); | |
169 | else | |
170 | REG_WRITE(addr, 0x01, 0x0003); | |
2e5f0320 LB |
171 | |
172 | /* | |
173 | * Port Control: disable Core Tag, disable Drop-on-Lock, | |
174 | * transmit frames unmodified, disable Header mode, | |
175 | * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN | |
176 | * tunneling, determine priority by looking at 802.1p and | |
177 | * IP priority fields (IP prio has precedence), and set STP | |
178 | * state to Forwarding. Finally, if this is the CPU port, | |
179 | * additionally enable DSA tagging and forwarding of unknown | |
180 | * unicast addresses. | |
181 | */ | |
182 | REG_WRITE(addr, 0x04, (p == ds->cpu_port) ? 0x0537 : 0x0433); | |
183 | ||
184 | /* | |
185 | * Port Control 1: disable trunking. Also, if this is the | |
186 | * CPU port, enable learn messages to be sent to this port. | |
187 | */ | |
188 | REG_WRITE(addr, 0x05, (p == ds->cpu_port) ? 0x8000 : 0x0000); | |
189 | ||
190 | /* | |
191 | * Port based VLAN map: give each port its own address | |
192 | * database, allow the CPU port to talk to each of the 'real' | |
193 | * ports, and allow each of the 'real' ports to only talk to | |
194 | * the CPU port. | |
195 | */ | |
196 | REG_WRITE(addr, 0x06, | |
197 | ((p & 0xf) << 12) | | |
198 | ((p == ds->cpu_port) ? | |
199 | ds->valid_port_mask : | |
200 | (1 << ds->cpu_port))); | |
201 | ||
202 | /* | |
203 | * Default VLAN ID and priority: don't set a default VLAN | |
204 | * ID, and set the default packet priority to zero. | |
205 | */ | |
206 | REG_WRITE(addr, 0x07, 0x0000); | |
207 | ||
208 | /* | |
209 | * Port Control 2: don't force a good FCS, don't use | |
210 | * VLAN-based, source address-based or destination | |
211 | * address-based priority overrides, don't let the switch | |
212 | * add or strip 802.1q tags, don't discard tagged or | |
213 | * untagged frames on this port, do a destination address | |
214 | * lookup on received packets as usual, don't send a copy | |
215 | * of all transmitted/received frames on this port to the | |
216 | * CPU, and configure the CPU port number. Also, if this | |
217 | * is the CPU port, enable forwarding of unknown multicast | |
218 | * addresses. | |
219 | */ | |
220 | REG_WRITE(addr, 0x08, | |
221 | ((p == ds->cpu_port) ? 0x00c0 : 0x0080) | | |
222 | ds->cpu_port); | |
223 | ||
224 | /* | |
225 | * Rate Control: disable ingress rate limiting. | |
226 | */ | |
227 | REG_WRITE(addr, 0x09, 0x0000); | |
228 | ||
229 | /* | |
230 | * Rate Control 2: disable egress rate limiting. | |
231 | */ | |
232 | REG_WRITE(addr, 0x0a, 0x0000); | |
233 | ||
234 | /* | |
235 | * Port Association Vector: when learning source addresses | |
236 | * of packets, add the address to the address database using | |
237 | * a port bitmap that has only the bit for this port set and | |
238 | * the other bits clear. | |
239 | */ | |
240 | REG_WRITE(addr, 0x0b, 1 << p); | |
241 | ||
242 | /* | |
243 | * Tag Remap: use an identity 802.1p prio -> switch prio | |
244 | * mapping. | |
245 | */ | |
246 | REG_WRITE(addr, 0x18, 0x3210); | |
247 | ||
248 | /* | |
249 | * Tag Remap 2: use an identity 802.1p prio -> switch prio | |
250 | * mapping. | |
251 | */ | |
252 | REG_WRITE(addr, 0x19, 0x7654); | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
257 | static int mv88e6131_setup(struct dsa_switch *ds) | |
258 | { | |
259 | struct mv88e6xxx_priv_state *ps = (void *)(ds + 1); | |
260 | int i; | |
261 | int ret; | |
262 | ||
263 | mutex_init(&ps->smi_mutex); | |
264 | mv88e6xxx_ppu_state_init(ds); | |
265 | mutex_init(&ps->stats_mutex); | |
266 | ||
267 | ret = mv88e6131_switch_reset(ds); | |
268 | if (ret < 0) | |
269 | return ret; | |
270 | ||
271 | /* @@@ initialise vtu and atu */ | |
272 | ||
273 | ret = mv88e6131_setup_global(ds); | |
274 | if (ret < 0) | |
275 | return ret; | |
276 | ||
076d3e10 | 277 | for (i = 0; i < 11; i++) { |
2e5f0320 LB |
278 | ret = mv88e6131_setup_port(ds, i); |
279 | if (ret < 0) | |
280 | return ret; | |
281 | } | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | static int mv88e6131_port_to_phy_addr(int port) | |
287 | { | |
076d3e10 | 288 | if (port >= 0 && port <= 11) |
2e5f0320 LB |
289 | return port; |
290 | return -1; | |
291 | } | |
292 | ||
293 | static int | |
294 | mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum) | |
295 | { | |
296 | int addr = mv88e6131_port_to_phy_addr(port); | |
297 | return mv88e6xxx_phy_read_ppu(ds, addr, regnum); | |
298 | } | |
299 | ||
300 | static int | |
301 | mv88e6131_phy_write(struct dsa_switch *ds, | |
302 | int port, int regnum, u16 val) | |
303 | { | |
304 | int addr = mv88e6131_port_to_phy_addr(port); | |
305 | return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val); | |
306 | } | |
307 | ||
308 | static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = { | |
309 | { "in_good_octets", 8, 0x00, }, | |
310 | { "in_bad_octets", 4, 0x02, }, | |
311 | { "in_unicast", 4, 0x04, }, | |
312 | { "in_broadcasts", 4, 0x06, }, | |
313 | { "in_multicasts", 4, 0x07, }, | |
314 | { "in_pause", 4, 0x16, }, | |
315 | { "in_undersize", 4, 0x18, }, | |
316 | { "in_fragments", 4, 0x19, }, | |
317 | { "in_oversize", 4, 0x1a, }, | |
318 | { "in_jabber", 4, 0x1b, }, | |
319 | { "in_rx_error", 4, 0x1c, }, | |
320 | { "in_fcs_error", 4, 0x1d, }, | |
321 | { "out_octets", 8, 0x0e, }, | |
322 | { "out_unicast", 4, 0x10, }, | |
323 | { "out_broadcasts", 4, 0x13, }, | |
324 | { "out_multicasts", 4, 0x12, }, | |
325 | { "out_pause", 4, 0x15, }, | |
326 | { "excessive", 4, 0x11, }, | |
327 | { "collisions", 4, 0x1e, }, | |
328 | { "deferred", 4, 0x05, }, | |
329 | { "single", 4, 0x14, }, | |
330 | { "multiple", 4, 0x17, }, | |
331 | { "out_fcs_error", 4, 0x03, }, | |
332 | { "late", 4, 0x1f, }, | |
333 | { "hist_64bytes", 4, 0x08, }, | |
334 | { "hist_65_127bytes", 4, 0x09, }, | |
335 | { "hist_128_255bytes", 4, 0x0a, }, | |
336 | { "hist_256_511bytes", 4, 0x0b, }, | |
337 | { "hist_512_1023bytes", 4, 0x0c, }, | |
338 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
339 | }; | |
340 | ||
341 | static void | |
342 | mv88e6131_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
343 | { | |
344 | mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats), | |
345 | mv88e6131_hw_stats, port, data); | |
346 | } | |
347 | ||
348 | static void | |
349 | mv88e6131_get_ethtool_stats(struct dsa_switch *ds, | |
350 | int port, uint64_t *data) | |
351 | { | |
352 | mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats), | |
353 | mv88e6131_hw_stats, port, data); | |
354 | } | |
355 | ||
356 | static int mv88e6131_get_sset_count(struct dsa_switch *ds) | |
357 | { | |
358 | return ARRAY_SIZE(mv88e6131_hw_stats); | |
359 | } | |
360 | ||
361 | static struct dsa_switch_driver mv88e6131_switch_driver = { | |
09640e63 | 362 | .tag_protocol = cpu_to_be16(ETH_P_DSA), |
2e5f0320 LB |
363 | .priv_size = sizeof(struct mv88e6xxx_priv_state), |
364 | .probe = mv88e6131_probe, | |
365 | .setup = mv88e6131_setup, | |
366 | .set_addr = mv88e6xxx_set_addr_direct, | |
367 | .phy_read = mv88e6131_phy_read, | |
368 | .phy_write = mv88e6131_phy_write, | |
369 | .poll_link = mv88e6xxx_poll_link, | |
370 | .get_strings = mv88e6131_get_strings, | |
371 | .get_ethtool_stats = mv88e6131_get_ethtool_stats, | |
372 | .get_sset_count = mv88e6131_get_sset_count, | |
373 | }; | |
374 | ||
5eaa65b2 | 375 | static int __init mv88e6131_init(void) |
2e5f0320 LB |
376 | { |
377 | register_switch_driver(&mv88e6131_switch_driver); | |
378 | return 0; | |
379 | } | |
380 | module_init(mv88e6131_init); | |
381 | ||
5eaa65b2 | 382 | static void __exit mv88e6131_cleanup(void) |
2e5f0320 LB |
383 | { |
384 | unregister_switch_driver(&mv88e6131_switch_driver); | |
385 | } | |
386 | module_exit(mv88e6131_cleanup); |