Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
7 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
1da177e4 LT |
17 | */ |
18 | ||
19 | #include <linux/cache.h> | |
17e5ad6c | 20 | #include <linux/dma-mapping.h> |
1da177e4 LT |
21 | #include <linux/mm.h> |
22 | #include <linux/module.h> | |
1da177e4 | 23 | #include <linux/spinlock.h> |
8c5df16b | 24 | #include <linux/swiotlb.h> |
1da177e4 | 25 | #include <linux/string.h> |
0016fdee | 26 | #include <linux/swiotlb.h> |
1da177e4 LT |
27 | #include <linux/types.h> |
28 | #include <linux/ctype.h> | |
ef9b1893 | 29 | #include <linux/highmem.h> |
1da177e4 LT |
30 | |
31 | #include <asm/io.h> | |
1da177e4 | 32 | #include <asm/dma.h> |
17e5ad6c | 33 | #include <asm/scatterlist.h> |
1da177e4 LT |
34 | |
35 | #include <linux/init.h> | |
36 | #include <linux/bootmem.h> | |
a8522509 | 37 | #include <linux/iommu-helper.h> |
1da177e4 LT |
38 | |
39 | #define OFFSET(val,align) ((unsigned long) \ | |
40 | ( (val) & ( (align) - 1))) | |
41 | ||
0b9afede AW |
42 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
43 | ||
44 | /* | |
45 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
46 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
47 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
48 | */ | |
49 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
50 | ||
de69e0f0 JL |
51 | /* |
52 | * Enumeration for sync targets | |
53 | */ | |
54 | enum dma_sync_target { | |
55 | SYNC_FOR_CPU = 0, | |
56 | SYNC_FOR_DEVICE = 1, | |
57 | }; | |
58 | ||
1da177e4 LT |
59 | int swiotlb_force; |
60 | ||
61 | /* | |
62 | * Used to do a quick range check in swiotlb_unmap_single and | |
63 | * swiotlb_sync_single_*, to see if the memory was in fact allocated by this | |
64 | * API. | |
65 | */ | |
66 | static char *io_tlb_start, *io_tlb_end; | |
67 | ||
68 | /* | |
69 | * The number of IO TLB blocks (in groups of 64) betweeen io_tlb_start and | |
70 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. | |
71 | */ | |
72 | static unsigned long io_tlb_nslabs; | |
73 | ||
74 | /* | |
75 | * When the IOMMU overflows we return a fallback buffer. This sets the size. | |
76 | */ | |
77 | static unsigned long io_tlb_overflow = 32*1024; | |
78 | ||
79 | void *io_tlb_overflow_buffer; | |
80 | ||
81 | /* | |
82 | * This is a free list describing the number of free entries available from | |
83 | * each index | |
84 | */ | |
85 | static unsigned int *io_tlb_list; | |
86 | static unsigned int io_tlb_index; | |
87 | ||
88 | /* | |
89 | * We need to save away the original address corresponding to a mapped entry | |
90 | * for the sync operations. | |
91 | */ | |
bc40ac66 | 92 | static phys_addr_t *io_tlb_orig_addr; |
1da177e4 LT |
93 | |
94 | /* | |
95 | * Protect the above data structures in the map and unmap calls | |
96 | */ | |
97 | static DEFINE_SPINLOCK(io_tlb_lock); | |
98 | ||
99 | static int __init | |
100 | setup_io_tlb_npages(char *str) | |
101 | { | |
102 | if (isdigit(*str)) { | |
e8579e72 | 103 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
104 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
105 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
106 | } | |
107 | if (*str == ',') | |
108 | ++str; | |
109 | if (!strcmp(str, "force")) | |
110 | swiotlb_force = 1; | |
111 | return 1; | |
112 | } | |
113 | __setup("swiotlb=", setup_io_tlb_npages); | |
114 | /* make io_tlb_overflow tunable too? */ | |
115 | ||
8c5df16b JF |
116 | void * __weak swiotlb_alloc_boot(size_t size, unsigned long nslabs) |
117 | { | |
118 | return alloc_bootmem_low_pages(size); | |
119 | } | |
120 | ||
121 | void * __weak swiotlb_alloc(unsigned order, unsigned long nslabs) | |
122 | { | |
123 | return (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, order); | |
124 | } | |
125 | ||
70a7d3cc | 126 | dma_addr_t __weak swiotlb_phys_to_bus(struct device *hwdev, phys_addr_t paddr) |
e08e1f7a IC |
127 | { |
128 | return paddr; | |
129 | } | |
130 | ||
131 | phys_addr_t __weak swiotlb_bus_to_phys(dma_addr_t baddr) | |
132 | { | |
133 | return baddr; | |
134 | } | |
135 | ||
70a7d3cc JF |
136 | static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev, |
137 | volatile void *address) | |
e08e1f7a | 138 | { |
70a7d3cc | 139 | return swiotlb_phys_to_bus(hwdev, virt_to_phys(address)); |
e08e1f7a IC |
140 | } |
141 | ||
142 | static void *swiotlb_bus_to_virt(dma_addr_t address) | |
143 | { | |
144 | return phys_to_virt(swiotlb_bus_to_phys(address)); | |
145 | } | |
146 | ||
b81ea27b IC |
147 | int __weak swiotlb_arch_range_needs_mapping(void *ptr, size_t size) |
148 | { | |
149 | return 0; | |
150 | } | |
151 | ||
70a7d3cc | 152 | static dma_addr_t swiotlb_sg_to_bus(struct device *hwdev, struct scatterlist *sg) |
ef9b1893 | 153 | { |
70a7d3cc | 154 | return swiotlb_phys_to_bus(hwdev, page_to_phys(sg_page(sg)) + sg->offset); |
ef9b1893 JF |
155 | } |
156 | ||
2e5b2b86 IC |
157 | static void swiotlb_print_info(unsigned long bytes) |
158 | { | |
159 | phys_addr_t pstart, pend; | |
2e5b2b86 IC |
160 | |
161 | pstart = virt_to_phys(io_tlb_start); | |
162 | pend = virt_to_phys(io_tlb_end); | |
163 | ||
2e5b2b86 IC |
164 | printk(KERN_INFO "Placing %luMB software IO TLB between %p - %p\n", |
165 | bytes >> 20, io_tlb_start, io_tlb_end); | |
70a7d3cc JF |
166 | printk(KERN_INFO "software IO TLB at phys %#llx - %#llx\n", |
167 | (unsigned long long)pstart, | |
168 | (unsigned long long)pend); | |
2e5b2b86 IC |
169 | } |
170 | ||
1da177e4 LT |
171 | /* |
172 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
17e5ad6c | 173 | * structures for the software IO TLB used to implement the DMA API. |
1da177e4 | 174 | */ |
563aaf06 JB |
175 | void __init |
176 | swiotlb_init_with_default_size(size_t default_size) | |
1da177e4 | 177 | { |
563aaf06 | 178 | unsigned long i, bytes; |
1da177e4 LT |
179 | |
180 | if (!io_tlb_nslabs) { | |
e8579e72 | 181 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); |
1da177e4 LT |
182 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); |
183 | } | |
184 | ||
563aaf06 JB |
185 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
186 | ||
1da177e4 LT |
187 | /* |
188 | * Get IO TLB memory from the low pages | |
189 | */ | |
8c5df16b | 190 | io_tlb_start = swiotlb_alloc_boot(bytes, io_tlb_nslabs); |
1da177e4 LT |
191 | if (!io_tlb_start) |
192 | panic("Cannot allocate SWIOTLB buffer"); | |
563aaf06 | 193 | io_tlb_end = io_tlb_start + bytes; |
1da177e4 LT |
194 | |
195 | /* | |
196 | * Allocate and initialize the free list array. This array is used | |
197 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
198 | * between io_tlb_start and io_tlb_end. | |
199 | */ | |
200 | io_tlb_list = alloc_bootmem(io_tlb_nslabs * sizeof(int)); | |
25667d67 | 201 | for (i = 0; i < io_tlb_nslabs; i++) |
1da177e4 LT |
202 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); |
203 | io_tlb_index = 0; | |
bc40ac66 | 204 | io_tlb_orig_addr = alloc_bootmem(io_tlb_nslabs * sizeof(phys_addr_t)); |
1da177e4 LT |
205 | |
206 | /* | |
207 | * Get the overflow emergency buffer | |
208 | */ | |
209 | io_tlb_overflow_buffer = alloc_bootmem_low(io_tlb_overflow); | |
563aaf06 JB |
210 | if (!io_tlb_overflow_buffer) |
211 | panic("Cannot allocate SWIOTLB overflow buffer!\n"); | |
212 | ||
2e5b2b86 | 213 | swiotlb_print_info(bytes); |
1da177e4 LT |
214 | } |
215 | ||
563aaf06 JB |
216 | void __init |
217 | swiotlb_init(void) | |
1da177e4 | 218 | { |
25667d67 | 219 | swiotlb_init_with_default_size(64 * (1<<20)); /* default to 64MB */ |
1da177e4 LT |
220 | } |
221 | ||
0b9afede AW |
222 | /* |
223 | * Systems with larger DMA zones (those that don't support ISA) can | |
224 | * initialize the swiotlb later using the slab allocator if needed. | |
225 | * This should be just like above, but with some error catching. | |
226 | */ | |
227 | int | |
563aaf06 | 228 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 229 | { |
563aaf06 | 230 | unsigned long i, bytes, req_nslabs = io_tlb_nslabs; |
0b9afede AW |
231 | unsigned int order; |
232 | ||
233 | if (!io_tlb_nslabs) { | |
234 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
235 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
236 | } | |
237 | ||
238 | /* | |
239 | * Get IO TLB memory from the low pages | |
240 | */ | |
563aaf06 | 241 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 242 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 243 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
244 | |
245 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
8c5df16b | 246 | io_tlb_start = swiotlb_alloc(order, io_tlb_nslabs); |
0b9afede AW |
247 | if (io_tlb_start) |
248 | break; | |
249 | order--; | |
250 | } | |
251 | ||
252 | if (!io_tlb_start) | |
253 | goto cleanup1; | |
254 | ||
563aaf06 | 255 | if (order != get_order(bytes)) { |
0b9afede AW |
256 | printk(KERN_WARNING "Warning: only able to allocate %ld MB " |
257 | "for software IO TLB\n", (PAGE_SIZE << order) >> 20); | |
258 | io_tlb_nslabs = SLABS_PER_PAGE << order; | |
563aaf06 | 259 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede | 260 | } |
563aaf06 JB |
261 | io_tlb_end = io_tlb_start + bytes; |
262 | memset(io_tlb_start, 0, bytes); | |
0b9afede AW |
263 | |
264 | /* | |
265 | * Allocate and initialize the free list array. This array is used | |
266 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
267 | * between io_tlb_start and io_tlb_end. | |
268 | */ | |
269 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
270 | get_order(io_tlb_nslabs * sizeof(int))); | |
271 | if (!io_tlb_list) | |
272 | goto cleanup2; | |
273 | ||
274 | for (i = 0; i < io_tlb_nslabs; i++) | |
275 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
276 | io_tlb_index = 0; | |
277 | ||
bc40ac66 BB |
278 | io_tlb_orig_addr = (phys_addr_t *) |
279 | __get_free_pages(GFP_KERNEL, | |
280 | get_order(io_tlb_nslabs * | |
281 | sizeof(phys_addr_t))); | |
0b9afede AW |
282 | if (!io_tlb_orig_addr) |
283 | goto cleanup3; | |
284 | ||
bc40ac66 | 285 | memset(io_tlb_orig_addr, 0, io_tlb_nslabs * sizeof(phys_addr_t)); |
0b9afede AW |
286 | |
287 | /* | |
288 | * Get the overflow emergency buffer | |
289 | */ | |
290 | io_tlb_overflow_buffer = (void *)__get_free_pages(GFP_DMA, | |
291 | get_order(io_tlb_overflow)); | |
292 | if (!io_tlb_overflow_buffer) | |
293 | goto cleanup4; | |
294 | ||
2e5b2b86 | 295 | swiotlb_print_info(bytes); |
0b9afede AW |
296 | |
297 | return 0; | |
298 | ||
299 | cleanup4: | |
bc40ac66 BB |
300 | free_pages((unsigned long)io_tlb_orig_addr, |
301 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
0b9afede AW |
302 | io_tlb_orig_addr = NULL; |
303 | cleanup3: | |
25667d67 TL |
304 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
305 | sizeof(int))); | |
0b9afede | 306 | io_tlb_list = NULL; |
0b9afede | 307 | cleanup2: |
563aaf06 | 308 | io_tlb_end = NULL; |
0b9afede AW |
309 | free_pages((unsigned long)io_tlb_start, order); |
310 | io_tlb_start = NULL; | |
311 | cleanup1: | |
312 | io_tlb_nslabs = req_nslabs; | |
313 | return -ENOMEM; | |
314 | } | |
315 | ||
be6b0267 | 316 | static int |
2797982e | 317 | address_needs_mapping(struct device *hwdev, dma_addr_t addr, size_t size) |
1da177e4 | 318 | { |
07a2c01a | 319 | return !is_buffer_dma_capable(dma_get_mask(hwdev), addr, size); |
1da177e4 LT |
320 | } |
321 | ||
b81ea27b IC |
322 | static inline int range_needs_mapping(void *ptr, size_t size) |
323 | { | |
324 | return swiotlb_force || swiotlb_arch_range_needs_mapping(ptr, size); | |
325 | } | |
326 | ||
640aebfe FT |
327 | static int is_swiotlb_buffer(char *addr) |
328 | { | |
329 | return addr >= io_tlb_start && addr < io_tlb_end; | |
330 | } | |
331 | ||
1da177e4 LT |
332 | /* |
333 | * Allocates bounce buffer and returns its kernel virtual address. | |
334 | */ | |
335 | static void * | |
bc40ac66 | 336 | map_single(struct device *hwdev, phys_addr_t phys, size_t size, int dir) |
1da177e4 LT |
337 | { |
338 | unsigned long flags; | |
339 | char *dma_addr; | |
340 | unsigned int nslots, stride, index, wrap; | |
341 | int i; | |
681cc5cd FT |
342 | unsigned long start_dma_addr; |
343 | unsigned long mask; | |
344 | unsigned long offset_slots; | |
345 | unsigned long max_slots; | |
346 | ||
347 | mask = dma_get_seg_boundary(hwdev); | |
70a7d3cc | 348 | start_dma_addr = swiotlb_virt_to_bus(hwdev, io_tlb_start) & mask; |
681cc5cd FT |
349 | |
350 | offset_slots = ALIGN(start_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
a5ddde4a IC |
351 | |
352 | /* | |
353 | * Carefully handle integer overflow which can occur when mask == ~0UL. | |
354 | */ | |
b15a3891 JB |
355 | max_slots = mask + 1 |
356 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
357 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
358 | |
359 | /* | |
360 | * For mappings greater than a page, we limit the stride (and | |
361 | * hence alignment) to a page size. | |
362 | */ | |
363 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
364 | if (size > PAGE_SIZE) | |
365 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); | |
366 | else | |
367 | stride = 1; | |
368 | ||
34814545 | 369 | BUG_ON(!nslots); |
1da177e4 LT |
370 | |
371 | /* | |
372 | * Find suitable number of IO TLB entries size that will fit this | |
373 | * request and allocate a buffer from that IO TLB pool. | |
374 | */ | |
375 | spin_lock_irqsave(&io_tlb_lock, flags); | |
a7133a15 AM |
376 | index = ALIGN(io_tlb_index, stride); |
377 | if (index >= io_tlb_nslabs) | |
378 | index = 0; | |
379 | wrap = index; | |
380 | ||
381 | do { | |
a8522509 FT |
382 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
383 | max_slots)) { | |
b15a3891 JB |
384 | index += stride; |
385 | if (index >= io_tlb_nslabs) | |
386 | index = 0; | |
a7133a15 AM |
387 | if (index == wrap) |
388 | goto not_found; | |
389 | } | |
390 | ||
391 | /* | |
392 | * If we find a slot that indicates we have 'nslots' number of | |
393 | * contiguous buffers, we allocate the buffers from that slot | |
394 | * and mark the entries as '0' indicating unavailable. | |
395 | */ | |
396 | if (io_tlb_list[index] >= nslots) { | |
397 | int count = 0; | |
398 | ||
399 | for (i = index; i < (int) (index + nslots); i++) | |
400 | io_tlb_list[i] = 0; | |
401 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
402 | io_tlb_list[i] = ++count; | |
403 | dma_addr = io_tlb_start + (index << IO_TLB_SHIFT); | |
1da177e4 | 404 | |
a7133a15 AM |
405 | /* |
406 | * Update the indices to avoid searching in the next | |
407 | * round. | |
408 | */ | |
409 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
410 | ? (index + nslots) : 0); | |
411 | ||
412 | goto found; | |
413 | } | |
414 | index += stride; | |
415 | if (index >= io_tlb_nslabs) | |
416 | index = 0; | |
417 | } while (index != wrap); | |
418 | ||
419 | not_found: | |
420 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
421 | return NULL; | |
422 | found: | |
1da177e4 LT |
423 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
424 | ||
425 | /* | |
426 | * Save away the mapping from the original address to the DMA address. | |
427 | * This is needed when we sync the memory. Then we sync the buffer if | |
428 | * needed. | |
429 | */ | |
bc40ac66 BB |
430 | for (i = 0; i < nslots; i++) |
431 | io_tlb_orig_addr[index+i] = phys + (i << IO_TLB_SHIFT); | |
1da177e4 | 432 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) |
bc40ac66 | 433 | memcpy(dma_addr, phys_to_virt(phys), size); |
1da177e4 LT |
434 | |
435 | return dma_addr; | |
436 | } | |
437 | ||
438 | /* | |
439 | * dma_addr is the kernel virtual address of the bounce buffer to unmap. | |
440 | */ | |
441 | static void | |
442 | unmap_single(struct device *hwdev, char *dma_addr, size_t size, int dir) | |
443 | { | |
444 | unsigned long flags; | |
445 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
446 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; | |
bc40ac66 | 447 | phys_addr_t phys = io_tlb_orig_addr[index]; |
1da177e4 LT |
448 | |
449 | /* | |
450 | * First, sync the memory before unmapping the entry | |
451 | */ | |
bc40ac66 | 452 | if (phys && ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
1da177e4 LT |
453 | /* |
454 | * bounce... copy the data back into the original buffer * and | |
455 | * delete the bounce buffer. | |
456 | */ | |
bc40ac66 | 457 | memcpy(phys_to_virt(phys), dma_addr, size); |
1da177e4 LT |
458 | |
459 | /* | |
460 | * Return the buffer to the free list by setting the corresponding | |
461 | * entries to indicate the number of contigous entries available. | |
462 | * While returning the entries to the free list, we merge the entries | |
463 | * with slots below and above the pool being returned. | |
464 | */ | |
465 | spin_lock_irqsave(&io_tlb_lock, flags); | |
466 | { | |
467 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
468 | io_tlb_list[index + nslots] : 0); | |
469 | /* | |
470 | * Step 1: return the slots to the free list, merging the | |
471 | * slots with superceeding slots | |
472 | */ | |
473 | for (i = index + nslots - 1; i >= index; i--) | |
474 | io_tlb_list[i] = ++count; | |
475 | /* | |
476 | * Step 2: merge the returned slots with the preceding slots, | |
477 | * if available (non zero) | |
478 | */ | |
479 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
480 | io_tlb_list[i] = ++count; | |
481 | } | |
482 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
483 | } | |
484 | ||
485 | static void | |
de69e0f0 JL |
486 | sync_single(struct device *hwdev, char *dma_addr, size_t size, |
487 | int dir, int target) | |
1da177e4 | 488 | { |
bc40ac66 BB |
489 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; |
490 | phys_addr_t phys = io_tlb_orig_addr[index]; | |
491 | ||
492 | phys += ((unsigned long)dma_addr & ((1 << IO_TLB_SHIFT) - 1)); | |
df336d1c | 493 | |
de69e0f0 JL |
494 | switch (target) { |
495 | case SYNC_FOR_CPU: | |
496 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
bc40ac66 | 497 | memcpy(phys_to_virt(phys), dma_addr, size); |
34814545 ES |
498 | else |
499 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
500 | break; |
501 | case SYNC_FOR_DEVICE: | |
502 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
bc40ac66 | 503 | memcpy(dma_addr, phys_to_virt(phys), size); |
34814545 ES |
504 | else |
505 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
506 | break; |
507 | default: | |
1da177e4 | 508 | BUG(); |
de69e0f0 | 509 | } |
1da177e4 LT |
510 | } |
511 | ||
512 | void * | |
513 | swiotlb_alloc_coherent(struct device *hwdev, size_t size, | |
06a54497 | 514 | dma_addr_t *dma_handle, gfp_t flags) |
1da177e4 | 515 | { |
563aaf06 | 516 | dma_addr_t dev_addr; |
1da177e4 LT |
517 | void *ret; |
518 | int order = get_order(size); | |
1e74f300 FT |
519 | u64 dma_mask = DMA_32BIT_MASK; |
520 | ||
521 | if (hwdev && hwdev->coherent_dma_mask) | |
522 | dma_mask = hwdev->coherent_dma_mask; | |
1da177e4 | 523 | |
25667d67 | 524 | ret = (void *)__get_free_pages(flags, order); |
70a7d3cc JF |
525 | if (ret && |
526 | !is_buffer_dma_capable(dma_mask, swiotlb_virt_to_bus(hwdev, ret), | |
527 | size)) { | |
1da177e4 LT |
528 | /* |
529 | * The allocated memory isn't reachable by the device. | |
530 | * Fall back on swiotlb_map_single(). | |
531 | */ | |
532 | free_pages((unsigned long) ret, order); | |
533 | ret = NULL; | |
534 | } | |
535 | if (!ret) { | |
536 | /* | |
537 | * We are either out of memory or the device can't DMA | |
538 | * to GFP_DMA memory; fall back on | |
539 | * swiotlb_map_single(), which will grab memory from | |
540 | * the lowest available address range. | |
541 | */ | |
bc40ac66 | 542 | ret = map_single(hwdev, 0, size, DMA_FROM_DEVICE); |
9dfda12b | 543 | if (!ret) |
1da177e4 | 544 | return NULL; |
1da177e4 LT |
545 | } |
546 | ||
547 | memset(ret, 0, size); | |
70a7d3cc | 548 | dev_addr = swiotlb_virt_to_bus(hwdev, ret); |
1da177e4 LT |
549 | |
550 | /* Confirm address can be DMA'd by device */ | |
1e74f300 | 551 | if (!is_buffer_dma_capable(dma_mask, dev_addr, size)) { |
563aaf06 | 552 | printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", |
1e74f300 | 553 | (unsigned long long)dma_mask, |
563aaf06 | 554 | (unsigned long long)dev_addr); |
a2b89b59 FT |
555 | |
556 | /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ | |
557 | unmap_single(hwdev, ret, size, DMA_TO_DEVICE); | |
558 | return NULL; | |
1da177e4 LT |
559 | } |
560 | *dma_handle = dev_addr; | |
561 | return ret; | |
562 | } | |
563 | ||
564 | void | |
565 | swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, | |
566 | dma_addr_t dma_handle) | |
567 | { | |
aa24886e | 568 | WARN_ON(irqs_disabled()); |
640aebfe | 569 | if (!is_swiotlb_buffer(vaddr)) |
1da177e4 LT |
570 | free_pages((unsigned long) vaddr, get_order(size)); |
571 | else | |
572 | /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ | |
21f6c4de | 573 | unmap_single(hwdev, vaddr, size, DMA_TO_DEVICE); |
1da177e4 LT |
574 | } |
575 | ||
576 | static void | |
577 | swiotlb_full(struct device *dev, size_t size, int dir, int do_panic) | |
578 | { | |
579 | /* | |
580 | * Ran out of IOMMU space for this operation. This is very bad. | |
581 | * Unfortunately the drivers cannot handle this operation properly. | |
17e5ad6c | 582 | * unless they check for dma_mapping_error (most don't) |
1da177e4 LT |
583 | * When the mapping is small enough return a static buffer to limit |
584 | * the damage, or panic when the transfer is too big. | |
585 | */ | |
563aaf06 | 586 | printk(KERN_ERR "DMA: Out of SW-IOMMU space for %zu bytes at " |
1da177e4 LT |
587 | "device %s\n", size, dev ? dev->bus_id : "?"); |
588 | ||
589 | if (size > io_tlb_overflow && do_panic) { | |
17e5ad6c TL |
590 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
591 | panic("DMA: Memory would be corrupted\n"); | |
592 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) | |
593 | panic("DMA: Random memory would be DMAed\n"); | |
1da177e4 LT |
594 | } |
595 | } | |
596 | ||
597 | /* | |
598 | * Map a single buffer of the indicated size for DMA in streaming mode. The | |
17e5ad6c | 599 | * physical address to use is returned. |
1da177e4 LT |
600 | * |
601 | * Once the device is given the dma address, the device owns this memory until | |
602 | * either swiotlb_unmap_single or swiotlb_dma_sync_single is performed. | |
603 | */ | |
604 | dma_addr_t | |
309df0c5 AK |
605 | swiotlb_map_single_attrs(struct device *hwdev, void *ptr, size_t size, |
606 | int dir, struct dma_attrs *attrs) | |
1da177e4 | 607 | { |
70a7d3cc | 608 | dma_addr_t dev_addr = swiotlb_virt_to_bus(hwdev, ptr); |
1da177e4 LT |
609 | void *map; |
610 | ||
34814545 | 611 | BUG_ON(dir == DMA_NONE); |
1da177e4 LT |
612 | /* |
613 | * If the pointer passed in happens to be in the device's DMA window, | |
614 | * we can safely return the device addr and not worry about bounce | |
615 | * buffering it. | |
616 | */ | |
b81ea27b IC |
617 | if (!address_needs_mapping(hwdev, dev_addr, size) && |
618 | !range_needs_mapping(ptr, size)) | |
1da177e4 LT |
619 | return dev_addr; |
620 | ||
621 | /* | |
622 | * Oh well, have to allocate and map a bounce buffer. | |
623 | */ | |
bc40ac66 | 624 | map = map_single(hwdev, virt_to_phys(ptr), size, dir); |
1da177e4 LT |
625 | if (!map) { |
626 | swiotlb_full(hwdev, size, dir, 1); | |
627 | map = io_tlb_overflow_buffer; | |
628 | } | |
629 | ||
70a7d3cc | 630 | dev_addr = swiotlb_virt_to_bus(hwdev, map); |
1da177e4 LT |
631 | |
632 | /* | |
633 | * Ensure that the address returned is DMA'ble | |
634 | */ | |
2797982e | 635 | if (address_needs_mapping(hwdev, dev_addr, size)) |
1da177e4 LT |
636 | panic("map_single: bounce buffer is not DMA'ble"); |
637 | ||
638 | return dev_addr; | |
639 | } | |
309df0c5 AK |
640 | EXPORT_SYMBOL(swiotlb_map_single_attrs); |
641 | ||
642 | dma_addr_t | |
643 | swiotlb_map_single(struct device *hwdev, void *ptr, size_t size, int dir) | |
644 | { | |
645 | return swiotlb_map_single_attrs(hwdev, ptr, size, dir, NULL); | |
646 | } | |
1da177e4 | 647 | |
1da177e4 LT |
648 | /* |
649 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | |
650 | * match what was provided for in a previous swiotlb_map_single call. All | |
651 | * other usages are undefined. | |
652 | * | |
653 | * After this call, reads by the cpu to the buffer are guaranteed to see | |
654 | * whatever the device wrote there. | |
655 | */ | |
656 | void | |
309df0c5 AK |
657 | swiotlb_unmap_single_attrs(struct device *hwdev, dma_addr_t dev_addr, |
658 | size_t size, int dir, struct dma_attrs *attrs) | |
1da177e4 | 659 | { |
e08e1f7a | 660 | char *dma_addr = swiotlb_bus_to_virt(dev_addr); |
1da177e4 | 661 | |
34814545 | 662 | BUG_ON(dir == DMA_NONE); |
640aebfe | 663 | if (is_swiotlb_buffer(dma_addr)) |
1da177e4 LT |
664 | unmap_single(hwdev, dma_addr, size, dir); |
665 | else if (dir == DMA_FROM_DEVICE) | |
cde14bbf | 666 | dma_mark_clean(dma_addr, size); |
1da177e4 | 667 | } |
309df0c5 | 668 | EXPORT_SYMBOL(swiotlb_unmap_single_attrs); |
1da177e4 | 669 | |
309df0c5 AK |
670 | void |
671 | swiotlb_unmap_single(struct device *hwdev, dma_addr_t dev_addr, size_t size, | |
672 | int dir) | |
673 | { | |
674 | return swiotlb_unmap_single_attrs(hwdev, dev_addr, size, dir, NULL); | |
675 | } | |
1da177e4 LT |
676 | /* |
677 | * Make physical memory consistent for a single streaming mode DMA translation | |
678 | * after a transfer. | |
679 | * | |
680 | * If you perform a swiotlb_map_single() but wish to interrogate the buffer | |
17e5ad6c TL |
681 | * using the cpu, yet do not wish to teardown the dma mapping, you must |
682 | * call this function before doing so. At the next point you give the dma | |
1da177e4 LT |
683 | * address back to the card, you must first perform a |
684 | * swiotlb_dma_sync_for_device, and then the device again owns the buffer | |
685 | */ | |
be6b0267 | 686 | static void |
8270f3f1 | 687 | swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr, |
de69e0f0 | 688 | size_t size, int dir, int target) |
1da177e4 | 689 | { |
e08e1f7a | 690 | char *dma_addr = swiotlb_bus_to_virt(dev_addr); |
1da177e4 | 691 | |
34814545 | 692 | BUG_ON(dir == DMA_NONE); |
640aebfe | 693 | if (is_swiotlb_buffer(dma_addr)) |
de69e0f0 | 694 | sync_single(hwdev, dma_addr, size, dir, target); |
1da177e4 | 695 | else if (dir == DMA_FROM_DEVICE) |
cde14bbf | 696 | dma_mark_clean(dma_addr, size); |
1da177e4 LT |
697 | } |
698 | ||
8270f3f1 JL |
699 | void |
700 | swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
701 | size_t size, int dir) | |
702 | { | |
de69e0f0 | 703 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU); |
8270f3f1 JL |
704 | } |
705 | ||
1da177e4 LT |
706 | void |
707 | swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
708 | size_t size, int dir) | |
709 | { | |
de69e0f0 | 710 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE); |
1da177e4 LT |
711 | } |
712 | ||
878a97cf JL |
713 | /* |
714 | * Same as above, but for a sub-range of the mapping. | |
715 | */ | |
be6b0267 | 716 | static void |
878a97cf | 717 | swiotlb_sync_single_range(struct device *hwdev, dma_addr_t dev_addr, |
de69e0f0 JL |
718 | unsigned long offset, size_t size, |
719 | int dir, int target) | |
878a97cf | 720 | { |
e08e1f7a | 721 | char *dma_addr = swiotlb_bus_to_virt(dev_addr) + offset; |
878a97cf | 722 | |
34814545 | 723 | BUG_ON(dir == DMA_NONE); |
640aebfe | 724 | if (is_swiotlb_buffer(dma_addr)) |
de69e0f0 | 725 | sync_single(hwdev, dma_addr, size, dir, target); |
878a97cf | 726 | else if (dir == DMA_FROM_DEVICE) |
cde14bbf | 727 | dma_mark_clean(dma_addr, size); |
878a97cf JL |
728 | } |
729 | ||
730 | void | |
731 | swiotlb_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
732 | unsigned long offset, size_t size, int dir) | |
733 | { | |
de69e0f0 JL |
734 | swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir, |
735 | SYNC_FOR_CPU); | |
878a97cf JL |
736 | } |
737 | ||
738 | void | |
739 | swiotlb_sync_single_range_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
740 | unsigned long offset, size_t size, int dir) | |
741 | { | |
de69e0f0 JL |
742 | swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir, |
743 | SYNC_FOR_DEVICE); | |
878a97cf JL |
744 | } |
745 | ||
309df0c5 AK |
746 | void swiotlb_unmap_sg_attrs(struct device *, struct scatterlist *, int, int, |
747 | struct dma_attrs *); | |
1da177e4 LT |
748 | /* |
749 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
750 | * This is the scatter-gather version of the above swiotlb_map_single | |
751 | * interface. Here the scatter gather list elements are each tagged with the | |
752 | * appropriate dma address and length. They are obtained via | |
753 | * sg_dma_{address,length}(SG). | |
754 | * | |
755 | * NOTE: An implementation may be able to use a smaller number of | |
756 | * DMA address/length pairs than there are SG table elements. | |
757 | * (for example via virtual mapping capabilities) | |
758 | * The routine returns the number of addr/length pairs actually | |
759 | * used, at most nents. | |
760 | * | |
761 | * Device ownership issues as mentioned above for swiotlb_map_single are the | |
762 | * same here. | |
763 | */ | |
764 | int | |
309df0c5 AK |
765 | swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, |
766 | int dir, struct dma_attrs *attrs) | |
1da177e4 | 767 | { |
dbfd49fe | 768 | struct scatterlist *sg; |
1da177e4 LT |
769 | int i; |
770 | ||
34814545 | 771 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 772 | |
dbfd49fe | 773 | for_each_sg(sgl, sg, nelems, i) { |
bc40ac66 BB |
774 | void *addr = sg_virt(sg); |
775 | dma_addr_t dev_addr = swiotlb_virt_to_bus(hwdev, addr); | |
776 | ||
777 | if (range_needs_mapping(addr, sg->length) || | |
2797982e | 778 | address_needs_mapping(hwdev, dev_addr, sg->length)) { |
bc40ac66 BB |
779 | void *map = map_single(hwdev, sg_phys(sg), |
780 | sg->length, dir); | |
7e870233 | 781 | if (!map) { |
1da177e4 LT |
782 | /* Don't panic here, we expect map_sg users |
783 | to do proper error handling. */ | |
784 | swiotlb_full(hwdev, sg->length, dir, 0); | |
309df0c5 AK |
785 | swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir, |
786 | attrs); | |
dbfd49fe | 787 | sgl[0].dma_length = 0; |
1da177e4 LT |
788 | return 0; |
789 | } | |
70a7d3cc | 790 | sg->dma_address = swiotlb_virt_to_bus(hwdev, map); |
1da177e4 LT |
791 | } else |
792 | sg->dma_address = dev_addr; | |
793 | sg->dma_length = sg->length; | |
794 | } | |
795 | return nelems; | |
796 | } | |
309df0c5 AK |
797 | EXPORT_SYMBOL(swiotlb_map_sg_attrs); |
798 | ||
799 | int | |
800 | swiotlb_map_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
801 | int dir) | |
802 | { | |
803 | return swiotlb_map_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
804 | } | |
1da177e4 LT |
805 | |
806 | /* | |
807 | * Unmap a set of streaming mode DMA translations. Again, cpu read rules | |
808 | * concerning calls here are the same as for swiotlb_unmap_single() above. | |
809 | */ | |
810 | void | |
309df0c5 AK |
811 | swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl, |
812 | int nelems, int dir, struct dma_attrs *attrs) | |
1da177e4 | 813 | { |
dbfd49fe | 814 | struct scatterlist *sg; |
1da177e4 LT |
815 | int i; |
816 | ||
34814545 | 817 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 818 | |
dbfd49fe | 819 | for_each_sg(sgl, sg, nelems, i) { |
70a7d3cc | 820 | if (sg->dma_address != swiotlb_sg_to_bus(hwdev, sg)) |
e08e1f7a | 821 | unmap_single(hwdev, swiotlb_bus_to_virt(sg->dma_address), |
93fbff63 | 822 | sg->dma_length, dir); |
1da177e4 | 823 | else if (dir == DMA_FROM_DEVICE) |
ef9b1893 | 824 | dma_mark_clean(swiotlb_bus_to_virt(sg->dma_address), sg->dma_length); |
dbfd49fe | 825 | } |
1da177e4 | 826 | } |
309df0c5 AK |
827 | EXPORT_SYMBOL(swiotlb_unmap_sg_attrs); |
828 | ||
829 | void | |
830 | swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
831 | int dir) | |
832 | { | |
833 | return swiotlb_unmap_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
834 | } | |
1da177e4 LT |
835 | |
836 | /* | |
837 | * Make physical memory consistent for a set of streaming mode DMA translations | |
838 | * after a transfer. | |
839 | * | |
840 | * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules | |
841 | * and usage. | |
842 | */ | |
be6b0267 | 843 | static void |
dbfd49fe | 844 | swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl, |
de69e0f0 | 845 | int nelems, int dir, int target) |
1da177e4 | 846 | { |
dbfd49fe | 847 | struct scatterlist *sg; |
1da177e4 LT |
848 | int i; |
849 | ||
34814545 | 850 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 851 | |
dbfd49fe | 852 | for_each_sg(sgl, sg, nelems, i) { |
70a7d3cc | 853 | if (sg->dma_address != swiotlb_sg_to_bus(hwdev, sg)) |
e08e1f7a | 854 | sync_single(hwdev, swiotlb_bus_to_virt(sg->dma_address), |
de69e0f0 | 855 | sg->dma_length, dir, target); |
cde14bbf | 856 | else if (dir == DMA_FROM_DEVICE) |
ef9b1893 | 857 | dma_mark_clean(swiotlb_bus_to_virt(sg->dma_address), sg->dma_length); |
dbfd49fe | 858 | } |
1da177e4 LT |
859 | } |
860 | ||
8270f3f1 JL |
861 | void |
862 | swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, | |
863 | int nelems, int dir) | |
864 | { | |
de69e0f0 | 865 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU); |
8270f3f1 JL |
866 | } |
867 | ||
1da177e4 LT |
868 | void |
869 | swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, | |
870 | int nelems, int dir) | |
871 | { | |
de69e0f0 | 872 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE); |
1da177e4 LT |
873 | } |
874 | ||
875 | int | |
8d8bb39b | 876 | swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) |
1da177e4 | 877 | { |
70a7d3cc | 878 | return (dma_addr == swiotlb_virt_to_bus(hwdev, io_tlb_overflow_buffer)); |
1da177e4 LT |
879 | } |
880 | ||
881 | /* | |
17e5ad6c | 882 | * Return whether the given device DMA address mask can be supported |
1da177e4 | 883 | * properly. For example, if your device can only drive the low 24-bits |
17e5ad6c | 884 | * during bus mastering, then you would pass 0x00ffffff as the mask to |
1da177e4 LT |
885 | * this function. |
886 | */ | |
887 | int | |
563aaf06 | 888 | swiotlb_dma_supported(struct device *hwdev, u64 mask) |
1da177e4 | 889 | { |
70a7d3cc | 890 | return swiotlb_virt_to_bus(hwdev, io_tlb_end - 1) <= mask; |
1da177e4 LT |
891 | } |
892 | ||
1da177e4 LT |
893 | EXPORT_SYMBOL(swiotlb_map_single); |
894 | EXPORT_SYMBOL(swiotlb_unmap_single); | |
895 | EXPORT_SYMBOL(swiotlb_map_sg); | |
896 | EXPORT_SYMBOL(swiotlb_unmap_sg); | |
897 | EXPORT_SYMBOL(swiotlb_sync_single_for_cpu); | |
898 | EXPORT_SYMBOL(swiotlb_sync_single_for_device); | |
878a97cf JL |
899 | EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_cpu); |
900 | EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_device); | |
1da177e4 LT |
901 | EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu); |
902 | EXPORT_SYMBOL(swiotlb_sync_sg_for_device); | |
903 | EXPORT_SYMBOL(swiotlb_dma_mapping_error); | |
25667d67 TL |
904 | EXPORT_SYMBOL(swiotlb_alloc_coherent); |
905 | EXPORT_SYMBOL(swiotlb_free_coherent); | |
1da177e4 | 906 | EXPORT_SYMBOL(swiotlb_dma_supported); |