Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
7 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
fb05a379 | 17 | * 08/12/11 beckyb Add highmem support |
1da177e4 LT |
18 | */ |
19 | ||
20 | #include <linux/cache.h> | |
17e5ad6c | 21 | #include <linux/dma-mapping.h> |
1da177e4 | 22 | #include <linux/mm.h> |
8bc3bcc9 | 23 | #include <linux/export.h> |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/string.h> | |
0016fdee | 26 | #include <linux/swiotlb.h> |
fb05a379 | 27 | #include <linux/pfn.h> |
1da177e4 LT |
28 | #include <linux/types.h> |
29 | #include <linux/ctype.h> | |
ef9b1893 | 30 | #include <linux/highmem.h> |
5a0e3ad6 | 31 | #include <linux/gfp.h> |
84be456f | 32 | #include <linux/scatterlist.h> |
c7753208 | 33 | #include <linux/mem_encrypt.h> |
1da177e4 LT |
34 | |
35 | #include <asm/io.h> | |
1da177e4 LT |
36 | #include <asm/dma.h> |
37 | ||
38 | #include <linux/init.h> | |
39 | #include <linux/bootmem.h> | |
a8522509 | 40 | #include <linux/iommu-helper.h> |
1da177e4 | 41 | |
ce5be5a1 | 42 | #define CREATE_TRACE_POINTS |
2b2b614d ZK |
43 | #include <trace/events/swiotlb.h> |
44 | ||
1da177e4 LT |
45 | #define OFFSET(val,align) ((unsigned long) \ |
46 | ( (val) & ( (align) - 1))) | |
47 | ||
0b9afede AW |
48 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
49 | ||
50 | /* | |
51 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
52 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
53 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
54 | */ | |
55 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
56 | ||
ae7871be | 57 | enum swiotlb_force swiotlb_force; |
1da177e4 LT |
58 | |
59 | /* | |
bfc5501f KRW |
60 | * Used to do a quick range check in swiotlb_tbl_unmap_single and |
61 | * swiotlb_tbl_sync_single_*, to see if the memory was in fact allocated by this | |
1da177e4 LT |
62 | * API. |
63 | */ | |
ff7204a7 | 64 | static phys_addr_t io_tlb_start, io_tlb_end; |
1da177e4 LT |
65 | |
66 | /* | |
b595076a | 67 | * The number of IO TLB blocks (in groups of 64) between io_tlb_start and |
1da177e4 LT |
68 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. |
69 | */ | |
70 | static unsigned long io_tlb_nslabs; | |
71 | ||
72 | /* | |
73 | * When the IOMMU overflows we return a fallback buffer. This sets the size. | |
74 | */ | |
75 | static unsigned long io_tlb_overflow = 32*1024; | |
76 | ||
ee3f6ba8 | 77 | static phys_addr_t io_tlb_overflow_buffer; |
1da177e4 LT |
78 | |
79 | /* | |
80 | * This is a free list describing the number of free entries available from | |
81 | * each index | |
82 | */ | |
83 | static unsigned int *io_tlb_list; | |
84 | static unsigned int io_tlb_index; | |
85 | ||
7453c549 KRW |
86 | /* |
87 | * Max segment that we can provide which (if pages are contingous) will | |
88 | * not be bounced (unless SWIOTLB_FORCE is set). | |
89 | */ | |
90 | unsigned int max_segment; | |
91 | ||
1da177e4 LT |
92 | /* |
93 | * We need to save away the original address corresponding to a mapped entry | |
94 | * for the sync operations. | |
95 | */ | |
8e0629c1 | 96 | #define INVALID_PHYS_ADDR (~(phys_addr_t)0) |
bc40ac66 | 97 | static phys_addr_t *io_tlb_orig_addr; |
1da177e4 LT |
98 | |
99 | /* | |
100 | * Protect the above data structures in the map and unmap calls | |
101 | */ | |
102 | static DEFINE_SPINLOCK(io_tlb_lock); | |
103 | ||
5740afdb FT |
104 | static int late_alloc; |
105 | ||
1da177e4 LT |
106 | static int __init |
107 | setup_io_tlb_npages(char *str) | |
108 | { | |
109 | if (isdigit(*str)) { | |
e8579e72 | 110 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
111 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
112 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
113 | } | |
114 | if (*str == ',') | |
115 | ++str; | |
fff5d992 | 116 | if (!strcmp(str, "force")) { |
ae7871be | 117 | swiotlb_force = SWIOTLB_FORCE; |
fff5d992 GU |
118 | } else if (!strcmp(str, "noforce")) { |
119 | swiotlb_force = SWIOTLB_NO_FORCE; | |
120 | io_tlb_nslabs = 1; | |
121 | } | |
b18485e7 | 122 | |
c729de8f | 123 | return 0; |
1da177e4 | 124 | } |
c729de8f | 125 | early_param("swiotlb", setup_io_tlb_npages); |
1da177e4 LT |
126 | /* make io_tlb_overflow tunable too? */ |
127 | ||
f21ffe9f | 128 | unsigned long swiotlb_nr_tbl(void) |
5f98ecdb FT |
129 | { |
130 | return io_tlb_nslabs; | |
131 | } | |
f21ffe9f | 132 | EXPORT_SYMBOL_GPL(swiotlb_nr_tbl); |
c729de8f | 133 | |
7453c549 KRW |
134 | unsigned int swiotlb_max_segment(void) |
135 | { | |
136 | return max_segment; | |
137 | } | |
138 | EXPORT_SYMBOL_GPL(swiotlb_max_segment); | |
139 | ||
140 | void swiotlb_set_max_segment(unsigned int val) | |
141 | { | |
142 | if (swiotlb_force == SWIOTLB_FORCE) | |
143 | max_segment = 1; | |
144 | else | |
145 | max_segment = rounddown(val, PAGE_SIZE); | |
146 | } | |
147 | ||
c729de8f YL |
148 | /* default to 64MB */ |
149 | #define IO_TLB_DEFAULT_SIZE (64UL<<20) | |
150 | unsigned long swiotlb_size_or_default(void) | |
151 | { | |
152 | unsigned long size; | |
153 | ||
154 | size = io_tlb_nslabs << IO_TLB_SHIFT; | |
155 | ||
156 | return size ? size : (IO_TLB_DEFAULT_SIZE); | |
157 | } | |
158 | ||
c7753208 TL |
159 | void __weak swiotlb_set_mem_attributes(void *vaddr, unsigned long size) { } |
160 | ||
161 | /* For swiotlb, clear memory encryption mask from dma addresses */ | |
162 | static dma_addr_t swiotlb_phys_to_dma(struct device *hwdev, | |
163 | phys_addr_t address) | |
164 | { | |
165 | return __sme_clr(phys_to_dma(hwdev, address)); | |
166 | } | |
167 | ||
02ca646e | 168 | /* Note that this doesn't work with highmem page */ |
70a7d3cc JF |
169 | static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev, |
170 | volatile void *address) | |
e08e1f7a | 171 | { |
862d196b | 172 | return phys_to_dma(hwdev, virt_to_phys(address)); |
e08e1f7a IC |
173 | } |
174 | ||
ac2cbab2 YL |
175 | static bool no_iotlb_memory; |
176 | ||
ad32e8cb | 177 | void swiotlb_print_info(void) |
2e5b2b86 | 178 | { |
ad32e8cb | 179 | unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
ff7204a7 | 180 | unsigned char *vstart, *vend; |
2e5b2b86 | 181 | |
ac2cbab2 YL |
182 | if (no_iotlb_memory) { |
183 | pr_warn("software IO TLB: No low mem\n"); | |
184 | return; | |
185 | } | |
186 | ||
ff7204a7 | 187 | vstart = phys_to_virt(io_tlb_start); |
c40dba06 | 188 | vend = phys_to_virt(io_tlb_end); |
2e5b2b86 | 189 | |
3af684c7 | 190 | printk(KERN_INFO "software IO TLB [mem %#010llx-%#010llx] (%luMB) mapped at [%p-%p]\n", |
ff7204a7 | 191 | (unsigned long long)io_tlb_start, |
c40dba06 | 192 | (unsigned long long)io_tlb_end, |
ff7204a7 | 193 | bytes >> 20, vstart, vend - 1); |
2e5b2b86 IC |
194 | } |
195 | ||
c7753208 TL |
196 | /* |
197 | * Early SWIOTLB allocation may be too early to allow an architecture to | |
198 | * perform the desired operations. This function allows the architecture to | |
199 | * call SWIOTLB when the operations are possible. It needs to be called | |
200 | * before the SWIOTLB memory is used. | |
201 | */ | |
202 | void __init swiotlb_update_mem_attributes(void) | |
203 | { | |
204 | void *vaddr; | |
205 | unsigned long bytes; | |
206 | ||
207 | if (no_iotlb_memory || late_alloc) | |
208 | return; | |
209 | ||
210 | vaddr = phys_to_virt(io_tlb_start); | |
211 | bytes = PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT); | |
212 | swiotlb_set_mem_attributes(vaddr, bytes); | |
213 | memset(vaddr, 0, bytes); | |
214 | ||
215 | vaddr = phys_to_virt(io_tlb_overflow_buffer); | |
216 | bytes = PAGE_ALIGN(io_tlb_overflow); | |
217 | swiotlb_set_mem_attributes(vaddr, bytes); | |
218 | memset(vaddr, 0, bytes); | |
219 | } | |
220 | ||
ac2cbab2 | 221 | int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose) |
1da177e4 | 222 | { |
ee3f6ba8 | 223 | void *v_overflow_buffer; |
563aaf06 | 224 | unsigned long i, bytes; |
1da177e4 | 225 | |
abbceff7 | 226 | bytes = nslabs << IO_TLB_SHIFT; |
1da177e4 | 227 | |
abbceff7 | 228 | io_tlb_nslabs = nslabs; |
ff7204a7 AD |
229 | io_tlb_start = __pa(tlb); |
230 | io_tlb_end = io_tlb_start + bytes; | |
1da177e4 | 231 | |
ee3f6ba8 AD |
232 | /* |
233 | * Get the overflow emergency buffer | |
234 | */ | |
ad6492b8 | 235 | v_overflow_buffer = memblock_virt_alloc_low_nopanic( |
457ff1de SS |
236 | PAGE_ALIGN(io_tlb_overflow), |
237 | PAGE_SIZE); | |
ee3f6ba8 | 238 | if (!v_overflow_buffer) |
ac2cbab2 | 239 | return -ENOMEM; |
ee3f6ba8 AD |
240 | |
241 | io_tlb_overflow_buffer = __pa(v_overflow_buffer); | |
242 | ||
1da177e4 LT |
243 | /* |
244 | * Allocate and initialize the free list array. This array is used | |
245 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
246 | * between io_tlb_start and io_tlb_end. | |
247 | */ | |
457ff1de SS |
248 | io_tlb_list = memblock_virt_alloc( |
249 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int)), | |
250 | PAGE_SIZE); | |
457ff1de SS |
251 | io_tlb_orig_addr = memblock_virt_alloc( |
252 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t)), | |
253 | PAGE_SIZE); | |
8e0629c1 JB |
254 | for (i = 0; i < io_tlb_nslabs; i++) { |
255 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
256 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
257 | } | |
258 | io_tlb_index = 0; | |
1da177e4 | 259 | |
ad32e8cb FT |
260 | if (verbose) |
261 | swiotlb_print_info(); | |
ac2cbab2 | 262 | |
7453c549 | 263 | swiotlb_set_max_segment(io_tlb_nslabs << IO_TLB_SHIFT); |
ac2cbab2 | 264 | return 0; |
1da177e4 LT |
265 | } |
266 | ||
abbceff7 FT |
267 | /* |
268 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
269 | * structures for the software IO TLB used to implement the DMA API. | |
270 | */ | |
ac2cbab2 YL |
271 | void __init |
272 | swiotlb_init(int verbose) | |
abbceff7 | 273 | { |
c729de8f | 274 | size_t default_size = IO_TLB_DEFAULT_SIZE; |
ff7204a7 | 275 | unsigned char *vstart; |
abbceff7 FT |
276 | unsigned long bytes; |
277 | ||
278 | if (!io_tlb_nslabs) { | |
279 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
280 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
281 | } | |
282 | ||
283 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; | |
284 | ||
ac2cbab2 | 285 | /* Get IO TLB memory from the low pages */ |
ad6492b8 | 286 | vstart = memblock_virt_alloc_low_nopanic(PAGE_ALIGN(bytes), PAGE_SIZE); |
ac2cbab2 YL |
287 | if (vstart && !swiotlb_init_with_tbl(vstart, io_tlb_nslabs, verbose)) |
288 | return; | |
abbceff7 | 289 | |
ac2cbab2 | 290 | if (io_tlb_start) |
457ff1de SS |
291 | memblock_free_early(io_tlb_start, |
292 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
ac2cbab2 YL |
293 | pr_warn("Cannot allocate SWIOTLB buffer"); |
294 | no_iotlb_memory = true; | |
1da177e4 LT |
295 | } |
296 | ||
0b9afede AW |
297 | /* |
298 | * Systems with larger DMA zones (those that don't support ISA) can | |
299 | * initialize the swiotlb later using the slab allocator if needed. | |
300 | * This should be just like above, but with some error catching. | |
301 | */ | |
302 | int | |
563aaf06 | 303 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 304 | { |
74838b75 | 305 | unsigned long bytes, req_nslabs = io_tlb_nslabs; |
ff7204a7 | 306 | unsigned char *vstart = NULL; |
0b9afede | 307 | unsigned int order; |
74838b75 | 308 | int rc = 0; |
0b9afede AW |
309 | |
310 | if (!io_tlb_nslabs) { | |
311 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
312 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
313 | } | |
314 | ||
315 | /* | |
316 | * Get IO TLB memory from the low pages | |
317 | */ | |
563aaf06 | 318 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 319 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 320 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
321 | |
322 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
ff7204a7 AD |
323 | vstart = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
324 | order); | |
325 | if (vstart) | |
0b9afede AW |
326 | break; |
327 | order--; | |
328 | } | |
329 | ||
ff7204a7 | 330 | if (!vstart) { |
74838b75 KRW |
331 | io_tlb_nslabs = req_nslabs; |
332 | return -ENOMEM; | |
333 | } | |
563aaf06 | 334 | if (order != get_order(bytes)) { |
0b9afede AW |
335 | printk(KERN_WARNING "Warning: only able to allocate %ld MB " |
336 | "for software IO TLB\n", (PAGE_SIZE << order) >> 20); | |
337 | io_tlb_nslabs = SLABS_PER_PAGE << order; | |
338 | } | |
ff7204a7 | 339 | rc = swiotlb_late_init_with_tbl(vstart, io_tlb_nslabs); |
74838b75 | 340 | if (rc) |
ff7204a7 | 341 | free_pages((unsigned long)vstart, order); |
7453c549 | 342 | |
74838b75 KRW |
343 | return rc; |
344 | } | |
345 | ||
346 | int | |
347 | swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs) | |
348 | { | |
349 | unsigned long i, bytes; | |
ee3f6ba8 | 350 | unsigned char *v_overflow_buffer; |
74838b75 KRW |
351 | |
352 | bytes = nslabs << IO_TLB_SHIFT; | |
353 | ||
354 | io_tlb_nslabs = nslabs; | |
ff7204a7 AD |
355 | io_tlb_start = virt_to_phys(tlb); |
356 | io_tlb_end = io_tlb_start + bytes; | |
74838b75 | 357 | |
c7753208 | 358 | swiotlb_set_mem_attributes(tlb, bytes); |
ff7204a7 | 359 | memset(tlb, 0, bytes); |
0b9afede | 360 | |
ee3f6ba8 AD |
361 | /* |
362 | * Get the overflow emergency buffer | |
363 | */ | |
364 | v_overflow_buffer = (void *)__get_free_pages(GFP_DMA, | |
365 | get_order(io_tlb_overflow)); | |
366 | if (!v_overflow_buffer) | |
367 | goto cleanup2; | |
368 | ||
c7753208 TL |
369 | swiotlb_set_mem_attributes(v_overflow_buffer, io_tlb_overflow); |
370 | memset(v_overflow_buffer, 0, io_tlb_overflow); | |
ee3f6ba8 AD |
371 | io_tlb_overflow_buffer = virt_to_phys(v_overflow_buffer); |
372 | ||
0b9afede AW |
373 | /* |
374 | * Allocate and initialize the free list array. This array is used | |
375 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
376 | * between io_tlb_start and io_tlb_end. | |
377 | */ | |
378 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
379 | get_order(io_tlb_nslabs * sizeof(int))); | |
380 | if (!io_tlb_list) | |
ee3f6ba8 | 381 | goto cleanup3; |
0b9afede | 382 | |
bc40ac66 BB |
383 | io_tlb_orig_addr = (phys_addr_t *) |
384 | __get_free_pages(GFP_KERNEL, | |
385 | get_order(io_tlb_nslabs * | |
386 | sizeof(phys_addr_t))); | |
0b9afede | 387 | if (!io_tlb_orig_addr) |
ee3f6ba8 | 388 | goto cleanup4; |
0b9afede | 389 | |
8e0629c1 JB |
390 | for (i = 0; i < io_tlb_nslabs; i++) { |
391 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
392 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
393 | } | |
394 | io_tlb_index = 0; | |
0b9afede | 395 | |
ad32e8cb | 396 | swiotlb_print_info(); |
0b9afede | 397 | |
5740afdb FT |
398 | late_alloc = 1; |
399 | ||
7453c549 KRW |
400 | swiotlb_set_max_segment(io_tlb_nslabs << IO_TLB_SHIFT); |
401 | ||
0b9afede AW |
402 | return 0; |
403 | ||
404 | cleanup4: | |
25667d67 TL |
405 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
406 | sizeof(int))); | |
0b9afede | 407 | io_tlb_list = NULL; |
ee3f6ba8 AD |
408 | cleanup3: |
409 | free_pages((unsigned long)v_overflow_buffer, | |
410 | get_order(io_tlb_overflow)); | |
411 | io_tlb_overflow_buffer = 0; | |
0b9afede | 412 | cleanup2: |
c40dba06 | 413 | io_tlb_end = 0; |
ff7204a7 | 414 | io_tlb_start = 0; |
74838b75 | 415 | io_tlb_nslabs = 0; |
7453c549 | 416 | max_segment = 0; |
0b9afede AW |
417 | return -ENOMEM; |
418 | } | |
419 | ||
5740afdb FT |
420 | void __init swiotlb_free(void) |
421 | { | |
ee3f6ba8 | 422 | if (!io_tlb_orig_addr) |
5740afdb FT |
423 | return; |
424 | ||
425 | if (late_alloc) { | |
ee3f6ba8 | 426 | free_pages((unsigned long)phys_to_virt(io_tlb_overflow_buffer), |
5740afdb FT |
427 | get_order(io_tlb_overflow)); |
428 | free_pages((unsigned long)io_tlb_orig_addr, | |
429 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
430 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * | |
431 | sizeof(int))); | |
ff7204a7 | 432 | free_pages((unsigned long)phys_to_virt(io_tlb_start), |
5740afdb FT |
433 | get_order(io_tlb_nslabs << IO_TLB_SHIFT)); |
434 | } else { | |
457ff1de SS |
435 | memblock_free_late(io_tlb_overflow_buffer, |
436 | PAGE_ALIGN(io_tlb_overflow)); | |
437 | memblock_free_late(__pa(io_tlb_orig_addr), | |
438 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t))); | |
439 | memblock_free_late(__pa(io_tlb_list), | |
440 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int))); | |
441 | memblock_free_late(io_tlb_start, | |
442 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
5740afdb | 443 | } |
f21ffe9f | 444 | io_tlb_nslabs = 0; |
7453c549 | 445 | max_segment = 0; |
5740afdb FT |
446 | } |
447 | ||
9c5a3621 | 448 | int is_swiotlb_buffer(phys_addr_t paddr) |
640aebfe | 449 | { |
ff7204a7 | 450 | return paddr >= io_tlb_start && paddr < io_tlb_end; |
640aebfe FT |
451 | } |
452 | ||
fb05a379 BB |
453 | /* |
454 | * Bounce: copy the swiotlb buffer back to the original dma location | |
455 | */ | |
af51a9f1 AD |
456 | static void swiotlb_bounce(phys_addr_t orig_addr, phys_addr_t tlb_addr, |
457 | size_t size, enum dma_data_direction dir) | |
fb05a379 | 458 | { |
af51a9f1 AD |
459 | unsigned long pfn = PFN_DOWN(orig_addr); |
460 | unsigned char *vaddr = phys_to_virt(tlb_addr); | |
fb05a379 BB |
461 | |
462 | if (PageHighMem(pfn_to_page(pfn))) { | |
463 | /* The buffer does not have a mapping. Map it in and copy */ | |
af51a9f1 | 464 | unsigned int offset = orig_addr & ~PAGE_MASK; |
fb05a379 BB |
465 | char *buffer; |
466 | unsigned int sz = 0; | |
467 | unsigned long flags; | |
468 | ||
469 | while (size) { | |
67131ad0 | 470 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
fb05a379 BB |
471 | |
472 | local_irq_save(flags); | |
c3eede8e | 473 | buffer = kmap_atomic(pfn_to_page(pfn)); |
fb05a379 | 474 | if (dir == DMA_TO_DEVICE) |
af51a9f1 | 475 | memcpy(vaddr, buffer + offset, sz); |
ef9b1893 | 476 | else |
af51a9f1 | 477 | memcpy(buffer + offset, vaddr, sz); |
c3eede8e | 478 | kunmap_atomic(buffer); |
ef9b1893 | 479 | local_irq_restore(flags); |
fb05a379 BB |
480 | |
481 | size -= sz; | |
482 | pfn++; | |
af51a9f1 | 483 | vaddr += sz; |
fb05a379 | 484 | offset = 0; |
ef9b1893 | 485 | } |
af51a9f1 AD |
486 | } else if (dir == DMA_TO_DEVICE) { |
487 | memcpy(vaddr, phys_to_virt(orig_addr), size); | |
ef9b1893 | 488 | } else { |
af51a9f1 | 489 | memcpy(phys_to_virt(orig_addr), vaddr, size); |
ef9b1893 | 490 | } |
1b548f66 JF |
491 | } |
492 | ||
e05ed4d1 AD |
493 | phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, |
494 | dma_addr_t tbl_dma_addr, | |
495 | phys_addr_t orig_addr, size_t size, | |
0443fa00 AD |
496 | enum dma_data_direction dir, |
497 | unsigned long attrs) | |
1da177e4 LT |
498 | { |
499 | unsigned long flags; | |
e05ed4d1 | 500 | phys_addr_t tlb_addr; |
1da177e4 LT |
501 | unsigned int nslots, stride, index, wrap; |
502 | int i; | |
681cc5cd FT |
503 | unsigned long mask; |
504 | unsigned long offset_slots; | |
505 | unsigned long max_slots; | |
506 | ||
ac2cbab2 YL |
507 | if (no_iotlb_memory) |
508 | panic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer"); | |
509 | ||
648babb7 TL |
510 | if (sme_active()) |
511 | pr_warn_once("SME is active and system is using DMA bounce buffers\n"); | |
512 | ||
681cc5cd | 513 | mask = dma_get_seg_boundary(hwdev); |
681cc5cd | 514 | |
eb605a57 FT |
515 | tbl_dma_addr &= mask; |
516 | ||
517 | offset_slots = ALIGN(tbl_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
a5ddde4a IC |
518 | |
519 | /* | |
520 | * Carefully handle integer overflow which can occur when mask == ~0UL. | |
521 | */ | |
b15a3891 JB |
522 | max_slots = mask + 1 |
523 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
524 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
525 | |
526 | /* | |
602d9858 NY |
527 | * For mappings greater than or equal to a page, we limit the stride |
528 | * (and hence alignment) to a page size. | |
1da177e4 LT |
529 | */ |
530 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
602d9858 | 531 | if (size >= PAGE_SIZE) |
1da177e4 LT |
532 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); |
533 | else | |
534 | stride = 1; | |
535 | ||
34814545 | 536 | BUG_ON(!nslots); |
1da177e4 LT |
537 | |
538 | /* | |
539 | * Find suitable number of IO TLB entries size that will fit this | |
540 | * request and allocate a buffer from that IO TLB pool. | |
541 | */ | |
542 | spin_lock_irqsave(&io_tlb_lock, flags); | |
a7133a15 AM |
543 | index = ALIGN(io_tlb_index, stride); |
544 | if (index >= io_tlb_nslabs) | |
545 | index = 0; | |
546 | wrap = index; | |
547 | ||
548 | do { | |
a8522509 FT |
549 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
550 | max_slots)) { | |
b15a3891 JB |
551 | index += stride; |
552 | if (index >= io_tlb_nslabs) | |
553 | index = 0; | |
a7133a15 AM |
554 | if (index == wrap) |
555 | goto not_found; | |
556 | } | |
557 | ||
558 | /* | |
559 | * If we find a slot that indicates we have 'nslots' number of | |
560 | * contiguous buffers, we allocate the buffers from that slot | |
561 | * and mark the entries as '0' indicating unavailable. | |
562 | */ | |
563 | if (io_tlb_list[index] >= nslots) { | |
564 | int count = 0; | |
565 | ||
566 | for (i = index; i < (int) (index + nslots); i++) | |
567 | io_tlb_list[i] = 0; | |
568 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
569 | io_tlb_list[i] = ++count; | |
e05ed4d1 | 570 | tlb_addr = io_tlb_start + (index << IO_TLB_SHIFT); |
1da177e4 | 571 | |
a7133a15 AM |
572 | /* |
573 | * Update the indices to avoid searching in the next | |
574 | * round. | |
575 | */ | |
576 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
577 | ? (index + nslots) : 0); | |
578 | ||
579 | goto found; | |
580 | } | |
581 | index += stride; | |
582 | if (index >= io_tlb_nslabs) | |
583 | index = 0; | |
584 | } while (index != wrap); | |
585 | ||
586 | not_found: | |
587 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
0cb637bf KRW |
588 | if (printk_ratelimit()) |
589 | dev_warn(hwdev, "swiotlb buffer is full (sz: %zd bytes)\n", size); | |
e05ed4d1 | 590 | return SWIOTLB_MAP_ERROR; |
a7133a15 | 591 | found: |
1da177e4 LT |
592 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
593 | ||
594 | /* | |
595 | * Save away the mapping from the original address to the DMA address. | |
596 | * This is needed when we sync the memory. Then we sync the buffer if | |
597 | * needed. | |
598 | */ | |
bc40ac66 | 599 | for (i = 0; i < nslots; i++) |
e05ed4d1 | 600 | io_tlb_orig_addr[index+i] = orig_addr + (i << IO_TLB_SHIFT); |
0443fa00 AD |
601 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
602 | (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 603 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_TO_DEVICE); |
1da177e4 | 604 | |
e05ed4d1 | 605 | return tlb_addr; |
1da177e4 | 606 | } |
d7ef1533 | 607 | EXPORT_SYMBOL_GPL(swiotlb_tbl_map_single); |
1da177e4 | 608 | |
eb605a57 FT |
609 | /* |
610 | * Allocates bounce buffer and returns its kernel virtual address. | |
611 | */ | |
612 | ||
023600f1 AC |
613 | static phys_addr_t |
614 | map_single(struct device *hwdev, phys_addr_t phys, size_t size, | |
0443fa00 | 615 | enum dma_data_direction dir, unsigned long attrs) |
eb605a57 | 616 | { |
fff5d992 GU |
617 | dma_addr_t start_dma_addr; |
618 | ||
619 | if (swiotlb_force == SWIOTLB_NO_FORCE) { | |
620 | dev_warn_ratelimited(hwdev, "Cannot do DMA to address %pa\n", | |
621 | &phys); | |
622 | return SWIOTLB_MAP_ERROR; | |
623 | } | |
eb605a57 | 624 | |
c7753208 | 625 | start_dma_addr = swiotlb_phys_to_dma(hwdev, io_tlb_start); |
0443fa00 AD |
626 | return swiotlb_tbl_map_single(hwdev, start_dma_addr, phys, size, |
627 | dir, attrs); | |
eb605a57 FT |
628 | } |
629 | ||
1da177e4 LT |
630 | /* |
631 | * dma_addr is the kernel virtual address of the bounce buffer to unmap. | |
632 | */ | |
61ca08c3 | 633 | void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr, |
0443fa00 AD |
634 | size_t size, enum dma_data_direction dir, |
635 | unsigned long attrs) | |
1da177e4 LT |
636 | { |
637 | unsigned long flags; | |
638 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
61ca08c3 AD |
639 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
640 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
1da177e4 LT |
641 | |
642 | /* | |
643 | * First, sync the memory before unmapping the entry | |
644 | */ | |
8e0629c1 | 645 | if (orig_addr != INVALID_PHYS_ADDR && |
0443fa00 | 646 | !(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
8e0629c1 | 647 | ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
af51a9f1 | 648 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_FROM_DEVICE); |
1da177e4 LT |
649 | |
650 | /* | |
651 | * Return the buffer to the free list by setting the corresponding | |
af901ca1 | 652 | * entries to indicate the number of contiguous entries available. |
1da177e4 LT |
653 | * While returning the entries to the free list, we merge the entries |
654 | * with slots below and above the pool being returned. | |
655 | */ | |
656 | spin_lock_irqsave(&io_tlb_lock, flags); | |
657 | { | |
658 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
659 | io_tlb_list[index + nslots] : 0); | |
660 | /* | |
661 | * Step 1: return the slots to the free list, merging the | |
662 | * slots with superceeding slots | |
663 | */ | |
8e0629c1 | 664 | for (i = index + nslots - 1; i >= index; i--) { |
1da177e4 | 665 | io_tlb_list[i] = ++count; |
8e0629c1 JB |
666 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; |
667 | } | |
1da177e4 LT |
668 | /* |
669 | * Step 2: merge the returned slots with the preceding slots, | |
670 | * if available (non zero) | |
671 | */ | |
672 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
673 | io_tlb_list[i] = ++count; | |
674 | } | |
675 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
676 | } | |
d7ef1533 | 677 | EXPORT_SYMBOL_GPL(swiotlb_tbl_unmap_single); |
1da177e4 | 678 | |
fbfda893 AD |
679 | void swiotlb_tbl_sync_single(struct device *hwdev, phys_addr_t tlb_addr, |
680 | size_t size, enum dma_data_direction dir, | |
681 | enum dma_sync_target target) | |
1da177e4 | 682 | { |
fbfda893 AD |
683 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
684 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
bc40ac66 | 685 | |
8e0629c1 JB |
686 | if (orig_addr == INVALID_PHYS_ADDR) |
687 | return; | |
fbfda893 | 688 | orig_addr += (unsigned long)tlb_addr & ((1 << IO_TLB_SHIFT) - 1); |
df336d1c | 689 | |
de69e0f0 JL |
690 | switch (target) { |
691 | case SYNC_FOR_CPU: | |
692 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 693 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 694 | size, DMA_FROM_DEVICE); |
34814545 ES |
695 | else |
696 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
697 | break; |
698 | case SYNC_FOR_DEVICE: | |
699 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 700 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 701 | size, DMA_TO_DEVICE); |
34814545 ES |
702 | else |
703 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
704 | break; |
705 | default: | |
1da177e4 | 706 | BUG(); |
de69e0f0 | 707 | } |
1da177e4 | 708 | } |
d7ef1533 | 709 | EXPORT_SYMBOL_GPL(swiotlb_tbl_sync_single); |
1da177e4 LT |
710 | |
711 | void * | |
712 | swiotlb_alloc_coherent(struct device *hwdev, size_t size, | |
06a54497 | 713 | dma_addr_t *dma_handle, gfp_t flags) |
1da177e4 | 714 | { |
563aaf06 | 715 | dma_addr_t dev_addr; |
1da177e4 LT |
716 | void *ret; |
717 | int order = get_order(size); | |
284901a9 | 718 | u64 dma_mask = DMA_BIT_MASK(32); |
1e74f300 FT |
719 | |
720 | if (hwdev && hwdev->coherent_dma_mask) | |
721 | dma_mask = hwdev->coherent_dma_mask; | |
1da177e4 | 722 | |
25667d67 | 723 | ret = (void *)__get_free_pages(flags, order); |
e05ed4d1 AD |
724 | if (ret) { |
725 | dev_addr = swiotlb_virt_to_bus(hwdev, ret); | |
726 | if (dev_addr + size - 1 > dma_mask) { | |
727 | /* | |
728 | * The allocated memory isn't reachable by the device. | |
729 | */ | |
730 | free_pages((unsigned long) ret, order); | |
731 | ret = NULL; | |
732 | } | |
1da177e4 LT |
733 | } |
734 | if (!ret) { | |
735 | /* | |
bfc5501f KRW |
736 | * We are either out of memory or the device can't DMA to |
737 | * GFP_DMA memory; fall back on map_single(), which | |
ceb5ac32 | 738 | * will grab memory from the lowest available address range. |
1da177e4 | 739 | */ |
0443fa00 AD |
740 | phys_addr_t paddr = map_single(hwdev, 0, size, |
741 | DMA_FROM_DEVICE, 0); | |
e05ed4d1 | 742 | if (paddr == SWIOTLB_MAP_ERROR) |
94cc81f9 | 743 | goto err_warn; |
1da177e4 | 744 | |
e05ed4d1 | 745 | ret = phys_to_virt(paddr); |
c7753208 | 746 | dev_addr = swiotlb_phys_to_dma(hwdev, paddr); |
1da177e4 | 747 | |
61ca08c3 AD |
748 | /* Confirm address can be DMA'd by device */ |
749 | if (dev_addr + size - 1 > dma_mask) { | |
750 | printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", | |
751 | (unsigned long long)dma_mask, | |
752 | (unsigned long long)dev_addr); | |
a2b89b59 | 753 | |
0443fa00 AD |
754 | /* |
755 | * DMA_TO_DEVICE to avoid memcpy in unmap_single. | |
756 | * The DMA_ATTR_SKIP_CPU_SYNC is optional. | |
757 | */ | |
61ca08c3 | 758 | swiotlb_tbl_unmap_single(hwdev, paddr, |
0443fa00 AD |
759 | size, DMA_TO_DEVICE, |
760 | DMA_ATTR_SKIP_CPU_SYNC); | |
94cc81f9 | 761 | goto err_warn; |
61ca08c3 | 762 | } |
1da177e4 | 763 | } |
e05ed4d1 | 764 | |
1da177e4 | 765 | *dma_handle = dev_addr; |
e05ed4d1 AD |
766 | memset(ret, 0, size); |
767 | ||
1da177e4 | 768 | return ret; |
94cc81f9 JR |
769 | |
770 | err_warn: | |
771 | pr_warn("swiotlb: coherent allocation failed for device %s size=%zu\n", | |
772 | dev_name(hwdev), size); | |
773 | dump_stack(); | |
774 | ||
775 | return NULL; | |
1da177e4 | 776 | } |
874d6a95 | 777 | EXPORT_SYMBOL(swiotlb_alloc_coherent); |
1da177e4 LT |
778 | |
779 | void | |
780 | swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, | |
02ca646e | 781 | dma_addr_t dev_addr) |
1da177e4 | 782 | { |
862d196b | 783 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
02ca646e | 784 | |
aa24886e | 785 | WARN_ON(irqs_disabled()); |
02ca646e FT |
786 | if (!is_swiotlb_buffer(paddr)) |
787 | free_pages((unsigned long)vaddr, get_order(size)); | |
1da177e4 | 788 | else |
0443fa00 AD |
789 | /* |
790 | * DMA_TO_DEVICE to avoid memcpy in swiotlb_tbl_unmap_single. | |
791 | * DMA_ATTR_SKIP_CPU_SYNC is optional. | |
792 | */ | |
793 | swiotlb_tbl_unmap_single(hwdev, paddr, size, DMA_TO_DEVICE, | |
794 | DMA_ATTR_SKIP_CPU_SYNC); | |
1da177e4 | 795 | } |
874d6a95 | 796 | EXPORT_SYMBOL(swiotlb_free_coherent); |
1da177e4 LT |
797 | |
798 | static void | |
22d48269 KRW |
799 | swiotlb_full(struct device *dev, size_t size, enum dma_data_direction dir, |
800 | int do_panic) | |
1da177e4 | 801 | { |
fff5d992 GU |
802 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
803 | return; | |
804 | ||
1da177e4 LT |
805 | /* |
806 | * Ran out of IOMMU space for this operation. This is very bad. | |
807 | * Unfortunately the drivers cannot handle this operation properly. | |
17e5ad6c | 808 | * unless they check for dma_mapping_error (most don't) |
1da177e4 LT |
809 | * When the mapping is small enough return a static buffer to limit |
810 | * the damage, or panic when the transfer is too big. | |
811 | */ | |
0d2e1898 GU |
812 | dev_err_ratelimited(dev, "DMA: Out of SW-IOMMU space for %zu bytes\n", |
813 | size); | |
1da177e4 | 814 | |
c7084b35 CD |
815 | if (size <= io_tlb_overflow || !do_panic) |
816 | return; | |
817 | ||
818 | if (dir == DMA_BIDIRECTIONAL) | |
819 | panic("DMA: Random memory could be DMA accessed\n"); | |
820 | if (dir == DMA_FROM_DEVICE) | |
821 | panic("DMA: Random memory could be DMA written\n"); | |
822 | if (dir == DMA_TO_DEVICE) | |
823 | panic("DMA: Random memory could be DMA read\n"); | |
1da177e4 LT |
824 | } |
825 | ||
826 | /* | |
827 | * Map a single buffer of the indicated size for DMA in streaming mode. The | |
17e5ad6c | 828 | * physical address to use is returned. |
1da177e4 LT |
829 | * |
830 | * Once the device is given the dma address, the device owns this memory until | |
ceb5ac32 | 831 | * either swiotlb_unmap_page or swiotlb_dma_sync_single is performed. |
1da177e4 | 832 | */ |
f98eee8e FT |
833 | dma_addr_t swiotlb_map_page(struct device *dev, struct page *page, |
834 | unsigned long offset, size_t size, | |
835 | enum dma_data_direction dir, | |
00085f1e | 836 | unsigned long attrs) |
1da177e4 | 837 | { |
e05ed4d1 | 838 | phys_addr_t map, phys = page_to_phys(page) + offset; |
862d196b | 839 | dma_addr_t dev_addr = phys_to_dma(dev, phys); |
1da177e4 | 840 | |
34814545 | 841 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 842 | /* |
ceb5ac32 | 843 | * If the address happens to be in the device's DMA window, |
1da177e4 LT |
844 | * we can safely return the device addr and not worry about bounce |
845 | * buffering it. | |
846 | */ | |
ae7871be | 847 | if (dma_capable(dev, dev_addr, size) && swiotlb_force != SWIOTLB_FORCE) |
1da177e4 LT |
848 | return dev_addr; |
849 | ||
2b2b614d ZK |
850 | trace_swiotlb_bounced(dev, dev_addr, size, swiotlb_force); |
851 | ||
e05ed4d1 | 852 | /* Oh well, have to allocate and map a bounce buffer. */ |
0443fa00 | 853 | map = map_single(dev, phys, size, dir, attrs); |
e05ed4d1 | 854 | if (map == SWIOTLB_MAP_ERROR) { |
f98eee8e | 855 | swiotlb_full(dev, size, dir, 1); |
c7753208 | 856 | return swiotlb_phys_to_dma(dev, io_tlb_overflow_buffer); |
1da177e4 LT |
857 | } |
858 | ||
c7753208 | 859 | dev_addr = swiotlb_phys_to_dma(dev, map); |
1da177e4 | 860 | |
e05ed4d1 | 861 | /* Ensure that the address returned is DMA'ble */ |
0443fa00 AD |
862 | if (dma_capable(dev, dev_addr, size)) |
863 | return dev_addr; | |
864 | ||
d29fa0cb AD |
865 | attrs |= DMA_ATTR_SKIP_CPU_SYNC; |
866 | swiotlb_tbl_unmap_single(dev, map, size, dir, attrs); | |
1da177e4 | 867 | |
c7753208 | 868 | return swiotlb_phys_to_dma(dev, io_tlb_overflow_buffer); |
1da177e4 | 869 | } |
f98eee8e | 870 | EXPORT_SYMBOL_GPL(swiotlb_map_page); |
1da177e4 | 871 | |
1da177e4 LT |
872 | /* |
873 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | |
ceb5ac32 | 874 | * match what was provided for in a previous swiotlb_map_page call. All |
1da177e4 LT |
875 | * other usages are undefined. |
876 | * | |
877 | * After this call, reads by the cpu to the buffer are guaranteed to see | |
878 | * whatever the device wrote there. | |
879 | */ | |
7fcebbd2 | 880 | static void unmap_single(struct device *hwdev, dma_addr_t dev_addr, |
0443fa00 AD |
881 | size_t size, enum dma_data_direction dir, |
882 | unsigned long attrs) | |
1da177e4 | 883 | { |
862d196b | 884 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 885 | |
34814545 | 886 | BUG_ON(dir == DMA_NONE); |
7fcebbd2 | 887 | |
02ca646e | 888 | if (is_swiotlb_buffer(paddr)) { |
0443fa00 | 889 | swiotlb_tbl_unmap_single(hwdev, paddr, size, dir, attrs); |
7fcebbd2 BB |
890 | return; |
891 | } | |
892 | ||
893 | if (dir != DMA_FROM_DEVICE) | |
894 | return; | |
895 | ||
02ca646e FT |
896 | /* |
897 | * phys_to_virt doesn't work with hihgmem page but we could | |
898 | * call dma_mark_clean() with hihgmem page here. However, we | |
899 | * are fine since dma_mark_clean() is null on POWERPC. We can | |
900 | * make dma_mark_clean() take a physical address if necessary. | |
901 | */ | |
902 | dma_mark_clean(phys_to_virt(paddr), size); | |
7fcebbd2 BB |
903 | } |
904 | ||
905 | void swiotlb_unmap_page(struct device *hwdev, dma_addr_t dev_addr, | |
906 | size_t size, enum dma_data_direction dir, | |
00085f1e | 907 | unsigned long attrs) |
7fcebbd2 | 908 | { |
0443fa00 | 909 | unmap_single(hwdev, dev_addr, size, dir, attrs); |
1da177e4 | 910 | } |
f98eee8e | 911 | EXPORT_SYMBOL_GPL(swiotlb_unmap_page); |
874d6a95 | 912 | |
1da177e4 LT |
913 | /* |
914 | * Make physical memory consistent for a single streaming mode DMA translation | |
915 | * after a transfer. | |
916 | * | |
ceb5ac32 | 917 | * If you perform a swiotlb_map_page() but wish to interrogate the buffer |
17e5ad6c TL |
918 | * using the cpu, yet do not wish to teardown the dma mapping, you must |
919 | * call this function before doing so. At the next point you give the dma | |
1da177e4 LT |
920 | * address back to the card, you must first perform a |
921 | * swiotlb_dma_sync_for_device, and then the device again owns the buffer | |
922 | */ | |
be6b0267 | 923 | static void |
8270f3f1 | 924 | swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr, |
d7ef1533 KRW |
925 | size_t size, enum dma_data_direction dir, |
926 | enum dma_sync_target target) | |
1da177e4 | 927 | { |
862d196b | 928 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 929 | |
34814545 | 930 | BUG_ON(dir == DMA_NONE); |
380d6878 | 931 | |
02ca646e | 932 | if (is_swiotlb_buffer(paddr)) { |
fbfda893 | 933 | swiotlb_tbl_sync_single(hwdev, paddr, size, dir, target); |
380d6878 BB |
934 | return; |
935 | } | |
936 | ||
937 | if (dir != DMA_FROM_DEVICE) | |
938 | return; | |
939 | ||
02ca646e | 940 | dma_mark_clean(phys_to_virt(paddr), size); |
1da177e4 LT |
941 | } |
942 | ||
8270f3f1 JL |
943 | void |
944 | swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 945 | size_t size, enum dma_data_direction dir) |
8270f3f1 | 946 | { |
de69e0f0 | 947 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU); |
8270f3f1 | 948 | } |
874d6a95 | 949 | EXPORT_SYMBOL(swiotlb_sync_single_for_cpu); |
8270f3f1 | 950 | |
1da177e4 LT |
951 | void |
952 | swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 953 | size_t size, enum dma_data_direction dir) |
1da177e4 | 954 | { |
de69e0f0 | 955 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE); |
1da177e4 | 956 | } |
874d6a95 | 957 | EXPORT_SYMBOL(swiotlb_sync_single_for_device); |
1da177e4 LT |
958 | |
959 | /* | |
960 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
ceb5ac32 | 961 | * This is the scatter-gather version of the above swiotlb_map_page |
1da177e4 LT |
962 | * interface. Here the scatter gather list elements are each tagged with the |
963 | * appropriate dma address and length. They are obtained via | |
964 | * sg_dma_{address,length}(SG). | |
965 | * | |
966 | * NOTE: An implementation may be able to use a smaller number of | |
967 | * DMA address/length pairs than there are SG table elements. | |
968 | * (for example via virtual mapping capabilities) | |
969 | * The routine returns the number of addr/length pairs actually | |
970 | * used, at most nents. | |
971 | * | |
ceb5ac32 | 972 | * Device ownership issues as mentioned above for swiotlb_map_page are the |
1da177e4 LT |
973 | * same here. |
974 | */ | |
975 | int | |
309df0c5 | 976 | swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, |
00085f1e | 977 | enum dma_data_direction dir, unsigned long attrs) |
1da177e4 | 978 | { |
dbfd49fe | 979 | struct scatterlist *sg; |
1da177e4 LT |
980 | int i; |
981 | ||
34814545 | 982 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 983 | |
dbfd49fe | 984 | for_each_sg(sgl, sg, nelems, i) { |
961d7d0e | 985 | phys_addr_t paddr = sg_phys(sg); |
862d196b | 986 | dma_addr_t dev_addr = phys_to_dma(hwdev, paddr); |
bc40ac66 | 987 | |
ae7871be | 988 | if (swiotlb_force == SWIOTLB_FORCE || |
b9394647 | 989 | !dma_capable(hwdev, dev_addr, sg->length)) { |
e05ed4d1 | 990 | phys_addr_t map = map_single(hwdev, sg_phys(sg), |
0443fa00 | 991 | sg->length, dir, attrs); |
e05ed4d1 | 992 | if (map == SWIOTLB_MAP_ERROR) { |
1da177e4 LT |
993 | /* Don't panic here, we expect map_sg users |
994 | to do proper error handling. */ | |
995 | swiotlb_full(hwdev, sg->length, dir, 0); | |
d29fa0cb | 996 | attrs |= DMA_ATTR_SKIP_CPU_SYNC; |
309df0c5 AK |
997 | swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir, |
998 | attrs); | |
4d86ec7a | 999 | sg_dma_len(sgl) = 0; |
1da177e4 LT |
1000 | return 0; |
1001 | } | |
c7753208 | 1002 | sg->dma_address = swiotlb_phys_to_dma(hwdev, map); |
1da177e4 LT |
1003 | } else |
1004 | sg->dma_address = dev_addr; | |
4d86ec7a | 1005 | sg_dma_len(sg) = sg->length; |
1da177e4 LT |
1006 | } |
1007 | return nelems; | |
1008 | } | |
309df0c5 AK |
1009 | EXPORT_SYMBOL(swiotlb_map_sg_attrs); |
1010 | ||
1da177e4 LT |
1011 | /* |
1012 | * Unmap a set of streaming mode DMA translations. Again, cpu read rules | |
ceb5ac32 | 1013 | * concerning calls here are the same as for swiotlb_unmap_page() above. |
1da177e4 LT |
1014 | */ |
1015 | void | |
309df0c5 | 1016 | swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl, |
00085f1e KK |
1017 | int nelems, enum dma_data_direction dir, |
1018 | unsigned long attrs) | |
1da177e4 | 1019 | { |
dbfd49fe | 1020 | struct scatterlist *sg; |
1da177e4 LT |
1021 | int i; |
1022 | ||
34814545 | 1023 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 1024 | |
7fcebbd2 | 1025 | for_each_sg(sgl, sg, nelems, i) |
0443fa00 AD |
1026 | unmap_single(hwdev, sg->dma_address, sg_dma_len(sg), dir, |
1027 | attrs); | |
1da177e4 | 1028 | } |
309df0c5 AK |
1029 | EXPORT_SYMBOL(swiotlb_unmap_sg_attrs); |
1030 | ||
1da177e4 LT |
1031 | /* |
1032 | * Make physical memory consistent for a set of streaming mode DMA translations | |
1033 | * after a transfer. | |
1034 | * | |
1035 | * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules | |
1036 | * and usage. | |
1037 | */ | |
be6b0267 | 1038 | static void |
dbfd49fe | 1039 | swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl, |
d7ef1533 KRW |
1040 | int nelems, enum dma_data_direction dir, |
1041 | enum dma_sync_target target) | |
1da177e4 | 1042 | { |
dbfd49fe | 1043 | struct scatterlist *sg; |
1da177e4 LT |
1044 | int i; |
1045 | ||
380d6878 BB |
1046 | for_each_sg(sgl, sg, nelems, i) |
1047 | swiotlb_sync_single(hwdev, sg->dma_address, | |
4d86ec7a | 1048 | sg_dma_len(sg), dir, target); |
1da177e4 LT |
1049 | } |
1050 | ||
8270f3f1 JL |
1051 | void |
1052 | swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 1053 | int nelems, enum dma_data_direction dir) |
8270f3f1 | 1054 | { |
de69e0f0 | 1055 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU); |
8270f3f1 | 1056 | } |
874d6a95 | 1057 | EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu); |
8270f3f1 | 1058 | |
1da177e4 LT |
1059 | void |
1060 | swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 1061 | int nelems, enum dma_data_direction dir) |
1da177e4 | 1062 | { |
de69e0f0 | 1063 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE); |
1da177e4 | 1064 | } |
874d6a95 | 1065 | EXPORT_SYMBOL(swiotlb_sync_sg_for_device); |
1da177e4 LT |
1066 | |
1067 | int | |
8d8bb39b | 1068 | swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) |
1da177e4 | 1069 | { |
c7753208 | 1070 | return (dma_addr == swiotlb_phys_to_dma(hwdev, io_tlb_overflow_buffer)); |
1da177e4 | 1071 | } |
874d6a95 | 1072 | EXPORT_SYMBOL(swiotlb_dma_mapping_error); |
1da177e4 LT |
1073 | |
1074 | /* | |
17e5ad6c | 1075 | * Return whether the given device DMA address mask can be supported |
1da177e4 | 1076 | * properly. For example, if your device can only drive the low 24-bits |
17e5ad6c | 1077 | * during bus mastering, then you would pass 0x00ffffff as the mask to |
1da177e4 LT |
1078 | * this function. |
1079 | */ | |
1080 | int | |
563aaf06 | 1081 | swiotlb_dma_supported(struct device *hwdev, u64 mask) |
1da177e4 | 1082 | { |
c7753208 | 1083 | return swiotlb_phys_to_dma(hwdev, io_tlb_end - 1) <= mask; |
1da177e4 | 1084 | } |
1da177e4 | 1085 | EXPORT_SYMBOL(swiotlb_dma_supported); |