[linux-2.6-block.git] / lib / dma-direct.c

// SPDX-License-Identifier: GPL-2.0
/*
 * DMA operations that map physical memory directly without using an IOMMU or
 * flushing caches.
 */
#include <linux/export.h>
#include <linux/mm.h>
#include <linux/dma-direct.h>
#include <linux/scatterlist.h>
#include <linux/dma-contiguous.h>
#include <linux/pfn.h>
#include <linux/set_memory.h>

#define DIRECT_MAPPING_ERROR		0

/*
 * Most architectures use ZONE_DMA for the first 16 Megabytes, but
 * some use it for entirely different regions:
 */
#ifndef ARCH_ZONE_DMA_BITS
#define ARCH_ZONE_DMA_BITS 24
#endif

/*
 * For AMD SEV all DMA must be to unencrypted addresses.
 */
static inline bool force_dma_unencrypted(void)
{
	return sev_active();
}

static bool
check_addr(struct device *dev, dma_addr_t dma_addr, size_t size,
		const char *caller)
{
	if (unlikely(dev && !dma_capable(dev, dma_addr, size))) {
		if (*dev->dma_mask >= DMA_BIT_MASK(32)) {
			dev_err(dev,
				"%s: overflow %pad+%zu of device mask %llx\n",
				caller, &dma_addr, size, *dev->dma_mask);
		}
		return false;
	}
	return true;
}

static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
{
	dma_addr_t addr = force_dma_unencrypted() ?
		__phys_to_dma(dev, phys) : phys_to_dma(dev, phys);
	return addr + size - 1 <= dev->coherent_dma_mask;
}

void *dma_direct_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
		gfp_t gfp, unsigned long attrs)
{
	unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
	int page_order = get_order(size);
	struct page *page = NULL;
	void *ret;

	/* we always manually zero the memory once we are done: */
	gfp &= ~__GFP_ZERO;

	/* GFP_DMA32 and GFP_DMA are no ops without the corresponding zones: */
	if (dev->coherent_dma_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
		gfp |= GFP_DMA;
	if (dev->coherent_dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
		gfp |= GFP_DMA32;

again:
	/* CMA can be used only in the context which permits sleeping */
	if (gfpflags_allow_blocking(gfp)) {
		page = dma_alloc_from_contiguous(dev, count, page_order, gfp);
		if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
			dma_release_from_contiguous(dev, page, count);
			page = NULL;
		}
	}
	if (!page)
		page = alloc_pages_node(dev_to_node(dev), gfp, page_order);

	if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
		__free_pages(page, page_order);
		page = NULL;

		if (IS_ENABLED(CONFIG_ZONE_DMA) &&
		    dev->coherent_dma_mask < DMA_BIT_MASK(32) &&
		    !(gfp & GFP_DMA)) {
			gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
			goto again;
		}
	}

	if (!page)
		return NULL;
	ret = page_address(page);
	if (force_dma_unencrypted()) {
		set_memory_decrypted((unsigned long)ret, 1 << page_order);
		*dma_handle = __phys_to_dma(dev, page_to_phys(page));
	} else {
		*dma_handle = phys_to_dma(dev, page_to_phys(page));
	}
	memset(ret, 0, size);
	return ret;
}

/*
 * NOTE: this function must never look at the dma_addr argument, because we want
 * to be able to use it as a helper for iommu implementations as well.
 */
void dma_direct_free(struct device *dev, size_t size, void *cpu_addr,
		dma_addr_t dma_addr, unsigned long attrs)
{
	unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
	unsigned int page_order = get_order(size);

	if (force_dma_unencrypted())
		set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
	if (!dma_release_from_contiguous(dev, virt_to_page(cpu_addr), count))
		free_pages((unsigned long)cpu_addr, page_order);
}

static dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
		unsigned long offset, size_t size, enum dma_data_direction dir,
		unsigned long attrs)
{
	dma_addr_t dma_addr = phys_to_dma(dev, page_to_phys(page)) + offset;

	if (!check_addr(dev, dma_addr, size, __func__))
		return DIRECT_MAPPING_ERROR;
	return dma_addr;
}

static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
		int nents, enum dma_data_direction dir, unsigned long attrs)
{
	int i;
	struct scatterlist *sg;

	for_each_sg(sgl, sg, nents, i) {
		BUG_ON(!sg_page(sg));

		sg_dma_address(sg) = phys_to_dma(dev, sg_phys(sg));
		if (!check_addr(dev, sg_dma_address(sg), sg->length, __func__))
			return 0;
		sg_dma_len(sg) = sg->length;
	}

	return nents;
}

int dma_direct_supported(struct device *dev, u64 mask)
{
#ifdef CONFIG_ZONE_DMA
	if (mask < DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
		return 0;
#else
	/*
	 * Because 32-bit DMA masks are so common we expect every architecture
	 * to be able to satisfy them - either by not supporting more physical
	 * memory, or by providing a ZONE_DMA32.  If neither is the case, the
	 * architecture needs to use an IOMMU instead of the direct mapping.
	 */
	if (mask < DMA_BIT_MASK(32))
		return 0;
#endif
	return 1;
}

static int dma_direct_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
	return dma_addr == DIRECT_MAPPING_ERROR;
}

const struct dma_map_ops dma_direct_ops = {
	.alloc			= dma_direct_alloc,
	.free			= dma_direct_free,
	.map_page		= dma_direct_map_page,
	.map_sg			= dma_direct_map_sg,
	.dma_supported		= dma_direct_supported,
	.mapping_error		= dma_direct_mapping_error,
	.is_phys		= 1,
};
EXPORT_SYMBOL(dma_direct_ops);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
a8463d4b	2	/*
2e86a047 CH	3	* DMA operations that map physical memory directly without using an IOMMU or
2e86a047 CH	4	* flushing caches.
a8463d4b CB	5	*/
	6	#include <linux/export.h>
	7	#include <linux/mm.h>
2e86a047	8	#include <linux/dma-direct.h>
a8463d4b	9	#include <linux/scatterlist.h>
080321d3	10	#include <linux/dma-contiguous.h>
25f1e188	11	#include <linux/pfn.h>
c10f07aa	12	#include <linux/set_memory.h>
a8463d4b	13
27975969 CH	14	#define DIRECT_MAPPING_ERROR 0
27975969 CH	15
c61e9637 CH	16	/*
	17	* Most architectures use ZONE_DMA for the first 16 Megabytes, but
	18	* some use it for entirely different regions:
	19	*/
	20	#ifndef ARCH_ZONE_DMA_BITS
	21	#define ARCH_ZONE_DMA_BITS 24
	22	#endif
	23
c10f07aa CH	24	/*
	25	* For AMD SEV all DMA must be to unencrypted addresses.
	26	*/
	27	static inline bool force_dma_unencrypted(void)
	28	{
	29	return sev_active();
	30	}
	31
27975969 CH	32	static bool
	33	check_addr(struct device *dev, dma_addr_t dma_addr, size_t size,
	34	const char *caller)
	35	{
	36	if (unlikely(dev && !dma_capable(dev, dma_addr, size))) {
	37	if (*dev->dma_mask >= DMA_BIT_MASK(32)) {
	38	dev_err(dev,
	39	"%s: overflow %pad+%zu of device mask %llx\n",
	40	caller, &dma_addr, size, *dev->dma_mask);
	41	}
	42	return false;
	43	}
	44	return true;
	45	}
	46
95f18391 CH	47	static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
95f18391 CH	48	{
c10f07aa CH	49	dma_addr_t addr = force_dma_unencrypted() ?
	50	__phys_to_dma(dev, phys) : phys_to_dma(dev, phys);
	51	return addr + size - 1 <= dev->coherent_dma_mask;
95f18391 CH	52	}
95f18391 CH	53
19dca8c0 CH	54	void dma_direct_alloc(struct device dev, size_t size, dma_addr_t *dma_handle,
19dca8c0 CH	55	gfp_t gfp, unsigned long attrs)
a8463d4b	56	{
080321d3 CH	57	unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
	58	int page_order = get_order(size);
	59	struct page *page = NULL;
c10f07aa	60	void *ret;
a8463d4b	61
e89f5b37 CH	62	/* we always manually zero the memory once we are done: */
	63	gfp &= ~__GFP_ZERO;
	64
c61e9637 CH	65	/* GFP_DMA32 and GFP_DMA are no ops without the corresponding zones: */
	66	if (dev->coherent_dma_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
	67	gfp \|= GFP_DMA;
	68	if (dev->coherent_dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
	69	gfp \|= GFP_DMA32;
	70
95f18391	71	again:
080321d3	72	/* CMA can be used only in the context which permits sleeping */
95f18391	73	if (gfpflags_allow_blocking(gfp)) {
080321d3	74	page = dma_alloc_from_contiguous(dev, count, page_order, gfp);
95f18391 CH	75	if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
	76	dma_release_from_contiguous(dev, page, count);
	77	page = NULL;
	78	}
	79	}
080321d3	80	if (!page)
21f237e4	81	page = alloc_pages_node(dev_to_node(dev), gfp, page_order);
95f18391 CH	82
	83	if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
	84	__free_pages(page, page_order);
	85	page = NULL;
	86
504a918e TI	87	if (IS_ENABLED(CONFIG_ZONE_DMA) &&
504a918e TI	88	dev->coherent_dma_mask < DMA_BIT_MASK(32) &&
95f18391 CH	89	!(gfp & GFP_DMA)) {
	90	gfp = (gfp & ~GFP_DMA32) \| GFP_DMA;
	91	goto again;
	92	}
	93	}
	94
080321d3 CH	95	if (!page)
080321d3 CH	96	return NULL;
c10f07aa CH	97	ret = page_address(page);
	98	if (force_dma_unencrypted()) {
	99	set_memory_decrypted((unsigned long)ret, 1 << page_order);
	100	*dma_handle = __phys_to_dma(dev, page_to_phys(page));
	101	} else {
	102	*dma_handle = phys_to_dma(dev, page_to_phys(page));
	103	}
	104	memset(ret, 0, size);
	105	return ret;
a8463d4b CB	106	}
a8463d4b CB	107
42ed6452 CH	108	/*
	109	* NOTE: this function must never look at the dma_addr argument, because we want
	110	* to be able to use it as a helper for iommu implementations as well.
	111	*/
19dca8c0	112	void dma_direct_free(struct device dev, size_t size, void cpu_addr,
002e6745	113	dma_addr_t dma_addr, unsigned long attrs)
a8463d4b	114	{
080321d3	115	unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
c10f07aa	116	unsigned int page_order = get_order(size);
080321d3	117
c10f07aa CH	118	if (force_dma_unencrypted())
c10f07aa CH	119	set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
080321d3	120	if (!dma_release_from_contiguous(dev, virt_to_page(cpu_addr), count))
c10f07aa	121	free_pages((unsigned long)cpu_addr, page_order);
a8463d4b CB	122	}
a8463d4b CB	123
002e6745 CH	124	static dma_addr_t dma_direct_map_page(struct device dev, struct page page,
	125	unsigned long offset, size_t size, enum dma_data_direction dir,
	126	unsigned long attrs)
a8463d4b	127	{
27975969 CH	128	dma_addr_t dma_addr = phys_to_dma(dev, page_to_phys(page)) + offset;
	129
	130	if (!check_addr(dev, dma_addr, size, __func__))
	131	return DIRECT_MAPPING_ERROR;
	132	return dma_addr;
a8463d4b CB	133	}
a8463d4b CB	134
002e6745 CH	135	static int dma_direct_map_sg(struct device dev, struct scatterlist sgl,
002e6745 CH	136	int nents, enum dma_data_direction dir, unsigned long attrs)
a8463d4b CB	137	{
	138	int i;
	139	struct scatterlist *sg;
	140
	141	for_each_sg(sgl, sg, nents, i) {
a8463d4b	142	BUG_ON(!sg_page(sg));
2e86a047 CH	143
2e86a047 CH	144	sg_dma_address(sg) = phys_to_dma(dev, sg_phys(sg));
27975969 CH	145	if (!check_addr(dev, sg_dma_address(sg), sg->length, __func__))
27975969 CH	146	return 0;
a8463d4b CB	147	sg_dma_len(sg) = sg->length;
	148	}
	149
	150	return nents;
	151	}
	152
1a9777a8 CH	153	int dma_direct_supported(struct device *dev, u64 mask)
	154	{
	155	#ifdef CONFIG_ZONE_DMA
	156	if (mask < DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
	157	return 0;
	158	#else
	159	/*
	160	* Because 32-bit DMA masks are so common we expect every architecture
	161	* to be able to satisfy them - either by not supporting more physical
	162	* memory, or by providing a ZONE_DMA32. If neither is the case, the
	163	* architecture needs to use an IOMMU instead of the direct mapping.
	164	*/
	165	if (mask < DMA_BIT_MASK(32))
	166	return 0;
	167	#endif
	168	return 1;
	169	}
	170
27975969 CH	171	static int dma_direct_mapping_error(struct device *dev, dma_addr_t dma_addr)
	172	{
	173	return dma_addr == DIRECT_MAPPING_ERROR;
	174	}
	175
002e6745 CH	176	const struct dma_map_ops dma_direct_ops = {
	177	.alloc = dma_direct_alloc,
	178	.free = dma_direct_free,
	179	.map_page = dma_direct_map_page,
	180	.map_sg = dma_direct_map_sg,
1a9777a8	181	.dma_supported = dma_direct_supported,
27975969	182	.mapping_error = dma_direct_mapping_error,
f25e6f6b	183	.is_phys = 1,
a8463d4b	184	};
002e6745	185	EXPORT_SYMBOL(dma_direct_ops);