ALSA: pcm: Fix missing check of the new non-cached buffer type
[linux-2.6-block.git] / kernel / sched / cpupri.c
CommitLineData
b886d83c 1// SPDX-License-Identifier: GPL-2.0-only
6e0534f2 2/*
391e43da 3 * kernel/sched/cpupri.c
6e0534f2
GH
4 *
5 * CPU priority management
6 *
7 * Copyright (C) 2007-2008 Novell
8 *
9 * Author: Gregory Haskins <ghaskins@novell.com>
10 *
11 * This code tracks the priority of each CPU so that global migration
12 * decisions are easy to calculate. Each CPU can be in a state as follows:
13 *
14 * (INVALID), IDLE, NORMAL, RT1, ... RT99
15 *
16 * going from the lowest priority to the highest. CPUs in the INVALID state
17 * are not eligible for routing. The system maintains this state with
97fb7a0a 18 * a 2 dimensional bitmap (the first for priority class, the second for CPUs
6e0534f2
GH
19 * in that class). Therefore a typical application without affinity
20 * restrictions can find a suitable CPU with O(1) complexity (e.g. two bit
21 * searches). For tasks with affinity restrictions, the algorithm has a
22 * worst case complexity of O(min(102, nr_domcpus)), though the scenario that
23 * yields the worst case search is fairly contrived.
6e0534f2 24 */
325ea10c 25#include "sched.h"
6e0534f2
GH
26
27/* Convert between a 140 based task->prio, and our 102 based cpupri */
28static int convert_prio(int prio)
29{
30 int cpupri;
31
32 if (prio == CPUPRI_INVALID)
33 cpupri = CPUPRI_INVALID;
34 else if (prio == MAX_PRIO)
35 cpupri = CPUPRI_IDLE;
36 else if (prio >= MAX_RT_PRIO)
37 cpupri = CPUPRI_NORMAL;
38 else
39 cpupri = MAX_RT_PRIO - prio + 1;
40
41 return cpupri;
42}
43
6e0534f2
GH
44/**
45 * cpupri_find - find the best (lowest-pri) CPU in the system
46 * @cp: The cpupri context
47 * @p: The task
13b8bd0a 48 * @lowest_mask: A mask to fill in with selected CPUs (or NULL)
6e0534f2
GH
49 *
50 * Note: This function returns the recommended CPUs as calculated during the
2a61aa40 51 * current invocation. By the time the call returns, the CPUs may have in
6e0534f2
GH
52 * fact changed priorities any number of times. While not ideal, it is not
53 * an issue of correctness since the normal rebalancer logic will correct
54 * any discrepancies created by racing against the uncertainty of the current
55 * priority configuration.
56 *
e69f6186 57 * Return: (int)bool - CPUs were found
6e0534f2
GH
58 */
59int cpupri_find(struct cpupri *cp, struct task_struct *p,
68e74568 60 struct cpumask *lowest_mask)
6e0534f2 61{
014acbf0
YX
62 int idx = 0;
63 int task_pri = convert_prio(p->prio);
6e0534f2 64
6227cb00 65 BUG_ON(task_pri >= CPUPRI_NR_PRIORITIES);
c92211d9
SR
66
67 for (idx = 0; idx < task_pri; idx++) {
6e0534f2 68 struct cpupri_vec *vec = &cp->pri_to_cpu[idx];
d473750b 69 int skip = 0;
6e0534f2 70
c92211d9 71 if (!atomic_read(&(vec)->count))
d473750b 72 skip = 1;
c92211d9
SR
73 /*
74 * When looking at the vector, we need to read the counter,
75 * do a memory barrier, then read the mask.
76 *
77 * Note: This is still all racey, but we can deal with it.
78 * Ideally, we only want to look at masks that are set.
79 *
80 * If a mask is not set, then the only thing wrong is that we
81 * did a little more work than necessary.
82 *
83 * If we read a zero count but the mask is set, because of the
84 * memory barriers, that can only happen when the highest prio
85 * task for a run queue has left the run queue, in which case,
86 * it will be followed by a pull. If the task we are processing
87 * fails to find a proper place to go, that pull request will
88 * pull this task if the run queue is running at a lower
89 * priority.
90 */
91 smp_rmb();
6e0534f2 92
d473750b
SR
93 /* Need to do the rmb for every iteration */
94 if (skip)
95 continue;
96
3bd37062 97 if (cpumask_any_and(p->cpus_ptr, vec->mask) >= nr_cpu_ids)
6e0534f2
GH
98 continue;
99
07903af1 100 if (lowest_mask) {
3bd37062 101 cpumask_and(lowest_mask, p->cpus_ptr, vec->mask);
07903af1
GH
102
103 /*
104 * We have to ensure that we have at least one bit
105 * still set in the array, since the map could have
106 * been concurrently emptied between the first and
107 * second reads of vec->mask. If we hit this
108 * condition, simply act as though we never hit this
109 * priority level and continue on.
110 */
111 if (cpumask_any(lowest_mask) >= nr_cpu_ids)
112 continue;
113 }
114
6e0534f2
GH
115 return 1;
116 }
117
118 return 0;
119}
120
121/**
97fb7a0a 122 * cpupri_set - update the CPU priority setting
6e0534f2 123 * @cp: The cpupri context
97fb7a0a 124 * @cpu: The target CPU
fa757281 125 * @newpri: The priority (INVALID-RT99) to assign to this CPU
6e0534f2
GH
126 *
127 * Note: Assumes cpu_rq(cpu)->lock is locked
128 *
129 * Returns: (void)
130 */
131void cpupri_set(struct cpupri *cp, int cpu, int newpri)
132{
014acbf0
YX
133 int *currpri = &cp->cpu_to_pri[cpu];
134 int oldpri = *currpri;
135 int do_mb = 0;
6e0534f2
GH
136
137 newpri = convert_prio(newpri);
138
139 BUG_ON(newpri >= CPUPRI_NR_PRIORITIES);
140
141 if (newpri == oldpri)
142 return;
143
144 /*
97fb7a0a 145 * If the CPU was currently mapped to a different value, we
c3a2ae3d
SR
146 * need to map it to the new value then remove the old value.
147 * Note, we must add the new value first, otherwise we risk the
5710f15b 148 * cpu being missed by the priority loop in cpupri_find.
6e0534f2 149 */
6e0534f2
GH
150 if (likely(newpri != CPUPRI_INVALID)) {
151 struct cpupri_vec *vec = &cp->pri_to_cpu[newpri];
152
68e74568 153 cpumask_set_cpu(cpu, vec->mask);
c92211d9
SR
154 /*
155 * When adding a new vector, we update the mask first,
156 * do a write memory barrier, and then update the count, to
157 * make sure the vector is visible when count is set.
158 */
4e857c58 159 smp_mb__before_atomic();
c92211d9 160 atomic_inc(&(vec)->count);
d473750b 161 do_mb = 1;
6e0534f2 162 }
c3a2ae3d
SR
163 if (likely(oldpri != CPUPRI_INVALID)) {
164 struct cpupri_vec *vec = &cp->pri_to_cpu[oldpri];
165
d473750b
SR
166 /*
167 * Because the order of modification of the vec->count
168 * is important, we must make sure that the update
169 * of the new prio is seen before we decrement the
170 * old prio. This makes sure that the loop sees
171 * one or the other when we raise the priority of
172 * the run queue. We don't care about when we lower the
173 * priority, as that will trigger an rt pull anyway.
174 *
175 * We only need to do a memory barrier if we updated
176 * the new priority vec.
177 */
178 if (do_mb)
4e857c58 179 smp_mb__after_atomic();
d473750b 180
c92211d9
SR
181 /*
182 * When removing from the vector, we decrement the counter first
183 * do a memory barrier and then clear the mask.
184 */
185 atomic_dec(&(vec)->count);
4e857c58 186 smp_mb__after_atomic();
c3a2ae3d 187 cpumask_clear_cpu(cpu, vec->mask);
c3a2ae3d 188 }
6e0534f2
GH
189
190 *currpri = newpri;
191}
192
193/**
194 * cpupri_init - initialize the cpupri structure
195 * @cp: The cpupri context
196 *
e69f6186 197 * Return: -ENOMEM on memory allocation failure.
6e0534f2 198 */
68c38fc3 199int cpupri_init(struct cpupri *cp)
6e0534f2
GH
200{
201 int i;
202
6e0534f2
GH
203 for (i = 0; i < CPUPRI_NR_PRIORITIES; i++) {
204 struct cpupri_vec *vec = &cp->pri_to_cpu[i];
205
c92211d9 206 atomic_set(&vec->count, 0);
68c38fc3 207 if (!zalloc_cpumask_var(&vec->mask, GFP_KERNEL))
68e74568 208 goto cleanup;
6e0534f2
GH
209 }
210
4dac0b63
PZ
211 cp->cpu_to_pri = kcalloc(nr_cpu_ids, sizeof(int), GFP_KERNEL);
212 if (!cp->cpu_to_pri)
213 goto cleanup;
214
6e0534f2
GH
215 for_each_possible_cpu(i)
216 cp->cpu_to_pri[i] = CPUPRI_INVALID;
4dac0b63 217
68e74568
RR
218 return 0;
219
220cleanup:
221 for (i--; i >= 0; i--)
222 free_cpumask_var(cp->pri_to_cpu[i].mask);
223 return -ENOMEM;
6e0534f2
GH
224}
225
68e74568
RR
226/**
227 * cpupri_cleanup - clean up the cpupri structure
228 * @cp: The cpupri context
229 */
230void cpupri_cleanup(struct cpupri *cp)
231{
232 int i;
6e0534f2 233
4dac0b63 234 kfree(cp->cpu_to_pri);
68e74568
RR
235 for (i = 0; i < CPUPRI_NR_PRIORITIES; i++)
236 free_cpumask_var(cp->pri_to_cpu[i].mask);
237}