Commit | Line | Data |
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a23db284 WL |
1 | #ifndef _GEN_PV_LOCK_SLOWPATH |
2 | #error "do not include this file" | |
3 | #endif | |
4 | ||
5 | #include <linux/hash.h> | |
6 | #include <linux/bootmem.h> | |
cba77f03 | 7 | #include <linux/debug_locks.h> |
a23db284 WL |
8 | |
9 | /* | |
10 | * Implement paravirt qspinlocks; the general idea is to halt the vcpus instead | |
11 | * of spinning them. | |
12 | * | |
13 | * This relies on the architecture to provide two paravirt hypercalls: | |
14 | * | |
15 | * pv_wait(u8 *ptr, u8 val) -- suspends the vcpu if *ptr == val | |
16 | * pv_kick(cpu) -- wakes a suspended vcpu | |
17 | * | |
18 | * Using these we implement __pv_queued_spin_lock_slowpath() and | |
19 | * __pv_queued_spin_unlock() to replace native_queued_spin_lock_slowpath() and | |
20 | * native_queued_spin_unlock(). | |
21 | */ | |
22 | ||
23 | #define _Q_SLOW_VAL (3U << _Q_LOCKED_OFFSET) | |
24 | ||
cd0272fa WL |
25 | /* |
26 | * Queue Node Adaptive Spinning | |
27 | * | |
28 | * A queue node vCPU will stop spinning if the vCPU in the previous node is | |
29 | * not running. The one lock stealing attempt allowed at slowpath entry | |
30 | * mitigates the slight slowdown for non-overcommitted guest with this | |
31 | * aggressive wait-early mechanism. | |
32 | * | |
33 | * The status of the previous node will be checked at fixed interval | |
34 | * controlled by PV_PREV_CHECK_MASK. This is to ensure that we won't | |
35 | * pound on the cacheline of the previous node too heavily. | |
36 | */ | |
37 | #define PV_PREV_CHECK_MASK 0xff | |
38 | ||
75d22702 WL |
39 | /* |
40 | * Queue node uses: vcpu_running & vcpu_halted. | |
41 | * Queue head uses: vcpu_running & vcpu_hashed. | |
42 | */ | |
a23db284 WL |
43 | enum vcpu_state { |
44 | vcpu_running = 0, | |
75d22702 WL |
45 | vcpu_halted, /* Used only in pv_wait_node */ |
46 | vcpu_hashed, /* = pv_hash'ed + vcpu_halted */ | |
a23db284 WL |
47 | }; |
48 | ||
49 | struct pv_node { | |
50 | struct mcs_spinlock mcs; | |
51 | struct mcs_spinlock __res[3]; | |
52 | ||
53 | int cpu; | |
54 | u8 state; | |
55 | }; | |
56 | ||
eaff0e70 WL |
57 | /* |
58 | * Include queued spinlock statistics code | |
59 | */ | |
60 | #include "qspinlock_stat.h" | |
61 | ||
1c4941fd WL |
62 | /* |
63 | * By replacing the regular queued_spin_trylock() with the function below, | |
64 | * it will be called once when a lock waiter enter the PV slowpath before | |
65 | * being queued. By allowing one lock stealing attempt here when the pending | |
66 | * bit is off, it helps to reduce the performance impact of lock waiter | |
67 | * preemption without the drawback of lock starvation. | |
68 | */ | |
69 | #define queued_spin_trylock(l) pv_queued_spin_steal_lock(l) | |
70 | static inline bool pv_queued_spin_steal_lock(struct qspinlock *lock) | |
71 | { | |
72 | struct __qspinlock *l = (void *)lock; | |
73 | ||
64a5e3cb | 74 | if (!(atomic_read(&lock->val) & _Q_LOCKED_PENDING_MASK) && |
34d54f3d | 75 | (cmpxchg_acquire(&l->locked, 0, _Q_LOCKED_VAL) == 0)) { |
64a5e3cb PZ |
76 | qstat_inc(qstat_pv_lock_stealing, true); |
77 | return true; | |
78 | } | |
79 | ||
80 | return false; | |
1c4941fd WL |
81 | } |
82 | ||
83 | /* | |
84 | * The pending bit is used by the queue head vCPU to indicate that it | |
85 | * is actively spinning on the lock and no lock stealing is allowed. | |
86 | */ | |
87 | #if _Q_PENDING_BITS == 8 | |
88 | static __always_inline void set_pending(struct qspinlock *lock) | |
89 | { | |
90 | struct __qspinlock *l = (void *)lock; | |
91 | ||
92 | WRITE_ONCE(l->pending, 1); | |
93 | } | |
94 | ||
95 | static __always_inline void clear_pending(struct qspinlock *lock) | |
96 | { | |
97 | struct __qspinlock *l = (void *)lock; | |
98 | ||
99 | WRITE_ONCE(l->pending, 0); | |
100 | } | |
101 | ||
102 | /* | |
103 | * The pending bit check in pv_queued_spin_steal_lock() isn't a memory | |
34d54f3d WL |
104 | * barrier. Therefore, an atomic cmpxchg_acquire() is used to acquire the |
105 | * lock just to be sure that it will get it. | |
1c4941fd WL |
106 | */ |
107 | static __always_inline int trylock_clear_pending(struct qspinlock *lock) | |
108 | { | |
109 | struct __qspinlock *l = (void *)lock; | |
110 | ||
111 | return !READ_ONCE(l->locked) && | |
34d54f3d WL |
112 | (cmpxchg_acquire(&l->locked_pending, _Q_PENDING_VAL, |
113 | _Q_LOCKED_VAL) == _Q_PENDING_VAL); | |
1c4941fd WL |
114 | } |
115 | #else /* _Q_PENDING_BITS == 8 */ | |
116 | static __always_inline void set_pending(struct qspinlock *lock) | |
117 | { | |
e37837fb | 118 | atomic_or(_Q_PENDING_VAL, &lock->val); |
1c4941fd WL |
119 | } |
120 | ||
121 | static __always_inline void clear_pending(struct qspinlock *lock) | |
122 | { | |
e37837fb | 123 | atomic_andnot(_Q_PENDING_VAL, &lock->val); |
1c4941fd WL |
124 | } |
125 | ||
126 | static __always_inline int trylock_clear_pending(struct qspinlock *lock) | |
127 | { | |
128 | int val = atomic_read(&lock->val); | |
129 | ||
130 | for (;;) { | |
131 | int old, new; | |
132 | ||
133 | if (val & _Q_LOCKED_MASK) | |
134 | break; | |
135 | ||
136 | /* | |
137 | * Try to clear pending bit & set locked bit | |
138 | */ | |
139 | old = val; | |
140 | new = (val & ~_Q_PENDING_MASK) | _Q_LOCKED_VAL; | |
34d54f3d | 141 | val = atomic_cmpxchg_acquire(&lock->val, old, new); |
1c4941fd WL |
142 | |
143 | if (val == old) | |
144 | return 1; | |
145 | } | |
146 | return 0; | |
147 | } | |
148 | #endif /* _Q_PENDING_BITS == 8 */ | |
149 | ||
a23db284 WL |
150 | /* |
151 | * Lock and MCS node addresses hash table for fast lookup | |
152 | * | |
153 | * Hashing is done on a per-cacheline basis to minimize the need to access | |
154 | * more than one cacheline. | |
155 | * | |
156 | * Dynamically allocate a hash table big enough to hold at least 4X the | |
157 | * number of possible cpus in the system. Allocation is done on page | |
158 | * granularity. So the minimum number of hash buckets should be at least | |
159 | * 256 (64-bit) or 512 (32-bit) to fully utilize a 4k page. | |
160 | * | |
161 | * Since we should not be holding locks from NMI context (very rare indeed) the | |
162 | * max load factor is 0.75, which is around the point where open addressing | |
163 | * breaks down. | |
164 | * | |
165 | */ | |
166 | struct pv_hash_entry { | |
167 | struct qspinlock *lock; | |
168 | struct pv_node *node; | |
169 | }; | |
170 | ||
171 | #define PV_HE_PER_LINE (SMP_CACHE_BYTES / sizeof(struct pv_hash_entry)) | |
172 | #define PV_HE_MIN (PAGE_SIZE / sizeof(struct pv_hash_entry)) | |
173 | ||
174 | static struct pv_hash_entry *pv_lock_hash; | |
175 | static unsigned int pv_lock_hash_bits __read_mostly; | |
176 | ||
177 | /* | |
178 | * Allocate memory for the PV qspinlock hash buckets | |
179 | * | |
180 | * This function should be called from the paravirt spinlock initialization | |
181 | * routine. | |
182 | */ | |
183 | void __init __pv_init_lock_hash(void) | |
184 | { | |
185 | int pv_hash_size = ALIGN(4 * num_possible_cpus(), PV_HE_PER_LINE); | |
186 | ||
187 | if (pv_hash_size < PV_HE_MIN) | |
188 | pv_hash_size = PV_HE_MIN; | |
189 | ||
190 | /* | |
191 | * Allocate space from bootmem which should be page-size aligned | |
192 | * and hence cacheline aligned. | |
193 | */ | |
194 | pv_lock_hash = alloc_large_system_hash("PV qspinlock", | |
195 | sizeof(struct pv_hash_entry), | |
3d375d78 PT |
196 | pv_hash_size, 0, |
197 | HASH_EARLY | HASH_ZERO, | |
a23db284 WL |
198 | &pv_lock_hash_bits, NULL, |
199 | pv_hash_size, pv_hash_size); | |
200 | } | |
201 | ||
202 | #define for_each_hash_entry(he, offset, hash) \ | |
203 | for (hash &= ~(PV_HE_PER_LINE - 1), he = &pv_lock_hash[hash], offset = 0; \ | |
204 | offset < (1 << pv_lock_hash_bits); \ | |
205 | offset++, he = &pv_lock_hash[(hash + offset) & ((1 << pv_lock_hash_bits) - 1)]) | |
206 | ||
207 | static struct qspinlock **pv_hash(struct qspinlock *lock, struct pv_node *node) | |
208 | { | |
209 | unsigned long offset, hash = hash_ptr(lock, pv_lock_hash_bits); | |
210 | struct pv_hash_entry *he; | |
45e898b7 | 211 | int hopcnt = 0; |
a23db284 WL |
212 | |
213 | for_each_hash_entry(he, offset, hash) { | |
45e898b7 | 214 | hopcnt++; |
a23db284 WL |
215 | if (!cmpxchg(&he->lock, NULL, lock)) { |
216 | WRITE_ONCE(he->node, node); | |
45e898b7 | 217 | qstat_hop(hopcnt); |
a23db284 WL |
218 | return &he->lock; |
219 | } | |
220 | } | |
221 | /* | |
222 | * Hard assume there is a free entry for us. | |
223 | * | |
224 | * This is guaranteed by ensuring every blocked lock only ever consumes | |
225 | * a single entry, and since we only have 4 nesting levels per CPU | |
226 | * and allocated 4*nr_possible_cpus(), this must be so. | |
227 | * | |
228 | * The single entry is guaranteed by having the lock owner unhash | |
229 | * before it releases. | |
230 | */ | |
231 | BUG(); | |
232 | } | |
233 | ||
234 | static struct pv_node *pv_unhash(struct qspinlock *lock) | |
235 | { | |
236 | unsigned long offset, hash = hash_ptr(lock, pv_lock_hash_bits); | |
237 | struct pv_hash_entry *he; | |
238 | struct pv_node *node; | |
239 | ||
240 | for_each_hash_entry(he, offset, hash) { | |
241 | if (READ_ONCE(he->lock) == lock) { | |
242 | node = READ_ONCE(he->node); | |
243 | WRITE_ONCE(he->lock, NULL); | |
244 | return node; | |
245 | } | |
246 | } | |
247 | /* | |
248 | * Hard assume we'll find an entry. | |
249 | * | |
250 | * This guarantees a limited lookup time and is itself guaranteed by | |
251 | * having the lock owner do the unhash -- IFF the unlock sees the | |
252 | * SLOW flag, there MUST be a hash entry. | |
253 | */ | |
254 | BUG(); | |
255 | } | |
256 | ||
cd0272fa WL |
257 | /* |
258 | * Return true if when it is time to check the previous node which is not | |
259 | * in a running state. | |
260 | */ | |
261 | static inline bool | |
262 | pv_wait_early(struct pv_node *prev, int loop) | |
263 | { | |
cd0272fa WL |
264 | if ((loop & PV_PREV_CHECK_MASK) != 0) |
265 | return false; | |
266 | ||
75437bb3 | 267 | return READ_ONCE(prev->state) != vcpu_running || vcpu_is_preempted(prev->cpu); |
cd0272fa WL |
268 | } |
269 | ||
a23db284 WL |
270 | /* |
271 | * Initialize the PV part of the mcs_spinlock node. | |
272 | */ | |
273 | static void pv_init_node(struct mcs_spinlock *node) | |
274 | { | |
275 | struct pv_node *pn = (struct pv_node *)node; | |
276 | ||
277 | BUILD_BUG_ON(sizeof(struct pv_node) > 5*sizeof(struct mcs_spinlock)); | |
278 | ||
279 | pn->cpu = smp_processor_id(); | |
280 | pn->state = vcpu_running; | |
281 | } | |
282 | ||
283 | /* | |
284 | * Wait for node->locked to become true, halt the vcpu after a short spin. | |
75d22702 WL |
285 | * pv_kick_node() is used to set _Q_SLOW_VAL and fill in hash table on its |
286 | * behalf. | |
a23db284 | 287 | */ |
cd0272fa | 288 | static void pv_wait_node(struct mcs_spinlock *node, struct mcs_spinlock *prev) |
a23db284 WL |
289 | { |
290 | struct pv_node *pn = (struct pv_node *)node; | |
cd0272fa | 291 | struct pv_node *pp = (struct pv_node *)prev; |
a23db284 | 292 | int loop; |
cd0272fa | 293 | bool wait_early; |
a23db284 | 294 | |
08be8f63 | 295 | for (;;) { |
cd0272fa | 296 | for (wait_early = false, loop = SPIN_THRESHOLD; loop; loop--) { |
a23db284 WL |
297 | if (READ_ONCE(node->locked)) |
298 | return; | |
cd0272fa WL |
299 | if (pv_wait_early(pp, loop)) { |
300 | wait_early = true; | |
301 | break; | |
302 | } | |
a23db284 WL |
303 | cpu_relax(); |
304 | } | |
305 | ||
306 | /* | |
307 | * Order pn->state vs pn->locked thusly: | |
308 | * | |
309 | * [S] pn->state = vcpu_halted [S] next->locked = 1 | |
310 | * MB MB | |
75d22702 | 311 | * [L] pn->locked [RmW] pn->state = vcpu_hashed |
a23db284 | 312 | * |
75d22702 | 313 | * Matches the cmpxchg() from pv_kick_node(). |
a23db284 | 314 | */ |
b92b8b35 | 315 | smp_store_mb(pn->state, vcpu_halted); |
a23db284 | 316 | |
45e898b7 WL |
317 | if (!READ_ONCE(node->locked)) { |
318 | qstat_inc(qstat_pv_wait_node, true); | |
cd0272fa | 319 | qstat_inc(qstat_pv_wait_early, wait_early); |
a23db284 | 320 | pv_wait(&pn->state, vcpu_halted); |
45e898b7 | 321 | } |
a23db284 WL |
322 | |
323 | /* | |
45e898b7 | 324 | * If pv_kick_node() changed us to vcpu_hashed, retain that |
1c4941fd WL |
325 | * value so that pv_wait_head_or_lock() knows to not also try |
326 | * to hash this lock. | |
a23db284 | 327 | */ |
75d22702 | 328 | cmpxchg(&pn->state, vcpu_halted, vcpu_running); |
a23db284 WL |
329 | |
330 | /* | |
331 | * If the locked flag is still not set after wakeup, it is a | |
332 | * spurious wakeup and the vCPU should wait again. However, | |
333 | * there is a pretty high overhead for CPU halting and kicking. | |
334 | * So it is better to spin for a while in the hope that the | |
335 | * MCS lock will be released soon. | |
336 | */ | |
45e898b7 | 337 | qstat_inc(qstat_pv_spurious_wakeup, !READ_ONCE(node->locked)); |
a23db284 | 338 | } |
75d22702 | 339 | |
a23db284 WL |
340 | /* |
341 | * By now our node->locked should be 1 and our caller will not actually | |
342 | * spin-wait for it. We do however rely on our caller to do a | |
343 | * load-acquire for us. | |
344 | */ | |
345 | } | |
346 | ||
347 | /* | |
75d22702 WL |
348 | * Called after setting next->locked = 1 when we're the lock owner. |
349 | * | |
1c4941fd WL |
350 | * Instead of waking the waiters stuck in pv_wait_node() advance their state |
351 | * such that they're waiting in pv_wait_head_or_lock(), this avoids a | |
352 | * wake/sleep cycle. | |
a23db284 | 353 | */ |
75d22702 | 354 | static void pv_kick_node(struct qspinlock *lock, struct mcs_spinlock *node) |
a23db284 WL |
355 | { |
356 | struct pv_node *pn = (struct pv_node *)node; | |
75d22702 | 357 | struct __qspinlock *l = (void *)lock; |
a23db284 WL |
358 | |
359 | /* | |
75d22702 WL |
360 | * If the vCPU is indeed halted, advance its state to match that of |
361 | * pv_wait_node(). If OTOH this fails, the vCPU was running and will | |
362 | * observe its next->locked value and advance itself. | |
a23db284 | 363 | * |
75d22702 | 364 | * Matches with smp_store_mb() and cmpxchg() in pv_wait_node() |
34d54f3d WL |
365 | * |
366 | * The write to next->locked in arch_mcs_spin_unlock_contended() | |
367 | * must be ordered before the read of pn->state in the cmpxchg() | |
368 | * below for the code to work correctly. To guarantee full ordering | |
369 | * irrespective of the success or failure of the cmpxchg(), | |
370 | * a relaxed version with explicit barrier is used. The control | |
371 | * dependency will order the reading of pn->state before any | |
372 | * subsequent writes. | |
75d22702 | 373 | */ |
34d54f3d WL |
374 | smp_mb__before_atomic(); |
375 | if (cmpxchg_relaxed(&pn->state, vcpu_halted, vcpu_hashed) | |
376 | != vcpu_halted) | |
75d22702 WL |
377 | return; |
378 | ||
379 | /* | |
380 | * Put the lock into the hash table and set the _Q_SLOW_VAL. | |
a23db284 | 381 | * |
75d22702 WL |
382 | * As this is the same vCPU that will check the _Q_SLOW_VAL value and |
383 | * the hash table later on at unlock time, no atomic instruction is | |
384 | * needed. | |
a23db284 | 385 | */ |
75d22702 WL |
386 | WRITE_ONCE(l->locked, _Q_SLOW_VAL); |
387 | (void)pv_hash(lock, pn); | |
a23db284 WL |
388 | } |
389 | ||
390 | /* | |
1c4941fd WL |
391 | * Wait for l->locked to become clear and acquire the lock; |
392 | * halt the vcpu after a short spin. | |
a23db284 | 393 | * __pv_queued_spin_unlock() will wake us. |
1c4941fd WL |
394 | * |
395 | * The current value of the lock will be returned for additional processing. | |
a23db284 | 396 | */ |
1c4941fd WL |
397 | static u32 |
398 | pv_wait_head_or_lock(struct qspinlock *lock, struct mcs_spinlock *node) | |
a23db284 WL |
399 | { |
400 | struct pv_node *pn = (struct pv_node *)node; | |
401 | struct __qspinlock *l = (void *)lock; | |
402 | struct qspinlock **lp = NULL; | |
45e898b7 | 403 | int waitcnt = 0; |
a23db284 WL |
404 | int loop; |
405 | ||
75d22702 WL |
406 | /* |
407 | * If pv_kick_node() already advanced our state, we don't need to | |
408 | * insert ourselves into the hash table anymore. | |
409 | */ | |
410 | if (READ_ONCE(pn->state) == vcpu_hashed) | |
411 | lp = (struct qspinlock **)1; | |
412 | ||
32d62510 WL |
413 | /* |
414 | * Tracking # of slowpath locking operations | |
415 | */ | |
416 | qstat_inc(qstat_pv_lock_slowpath, true); | |
417 | ||
45e898b7 | 418 | for (;; waitcnt++) { |
cd0272fa WL |
419 | /* |
420 | * Set correct vCPU state to be used by queue node wait-early | |
421 | * mechanism. | |
422 | */ | |
423 | WRITE_ONCE(pn->state, vcpu_running); | |
424 | ||
1c4941fd WL |
425 | /* |
426 | * Set the pending bit in the active lock spinning loop to | |
427 | * disable lock stealing before attempting to acquire the lock. | |
428 | */ | |
429 | set_pending(lock); | |
a23db284 | 430 | for (loop = SPIN_THRESHOLD; loop; loop--) { |
1c4941fd WL |
431 | if (trylock_clear_pending(lock)) |
432 | goto gotlock; | |
a23db284 WL |
433 | cpu_relax(); |
434 | } | |
1c4941fd WL |
435 | clear_pending(lock); |
436 | ||
a23db284 | 437 | |
a23db284 WL |
438 | if (!lp) { /* ONCE */ |
439 | lp = pv_hash(lock, pn); | |
75d22702 | 440 | |
a23db284 | 441 | /* |
3b3fdf10 WD |
442 | * We must hash before setting _Q_SLOW_VAL, such that |
443 | * when we observe _Q_SLOW_VAL in __pv_queued_spin_unlock() | |
444 | * we'll be sure to be able to observe our hash entry. | |
a23db284 | 445 | * |
3b3fdf10 WD |
446 | * [S] <hash> [Rmw] l->locked == _Q_SLOW_VAL |
447 | * MB RMB | |
448 | * [RmW] l->locked = _Q_SLOW_VAL [L] <unhash> | |
a23db284 | 449 | * |
3b3fdf10 | 450 | * Matches the smp_rmb() in __pv_queued_spin_unlock(). |
a23db284 | 451 | */ |
1c4941fd | 452 | if (xchg(&l->locked, _Q_SLOW_VAL) == 0) { |
a23db284 | 453 | /* |
1c4941fd WL |
454 | * The lock was free and now we own the lock. |
455 | * Change the lock value back to _Q_LOCKED_VAL | |
456 | * and unhash the table. | |
a23db284 | 457 | */ |
1c4941fd | 458 | WRITE_ONCE(l->locked, _Q_LOCKED_VAL); |
a23db284 | 459 | WRITE_ONCE(*lp, NULL); |
1c4941fd | 460 | goto gotlock; |
a23db284 WL |
461 | } |
462 | } | |
229ce631 | 463 | WRITE_ONCE(pn->state, vcpu_hashed); |
45e898b7 WL |
464 | qstat_inc(qstat_pv_wait_head, true); |
465 | qstat_inc(qstat_pv_wait_again, waitcnt); | |
a23db284 WL |
466 | pv_wait(&l->locked, _Q_SLOW_VAL); |
467 | ||
468 | /* | |
08be8f63 WL |
469 | * Because of lock stealing, the queue head vCPU may not be |
470 | * able to acquire the lock before it has to wait again. | |
a23db284 WL |
471 | */ |
472 | } | |
473 | ||
474 | /* | |
1c4941fd WL |
475 | * The cmpxchg() or xchg() call before coming here provides the |
476 | * acquire semantics for locking. The dummy ORing of _Q_LOCKED_VAL | |
477 | * here is to indicate to the compiler that the value will always | |
478 | * be nozero to enable better code optimization. | |
a23db284 | 479 | */ |
1c4941fd WL |
480 | gotlock: |
481 | return (u32)(atomic_read(&lock->val) | _Q_LOCKED_VAL); | |
a23db284 WL |
482 | } |
483 | ||
484 | /* | |
d7804530 WL |
485 | * PV versions of the unlock fastpath and slowpath functions to be used |
486 | * instead of queued_spin_unlock(). | |
a23db284 | 487 | */ |
d7804530 WL |
488 | __visible void |
489 | __pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 locked) | |
a23db284 WL |
490 | { |
491 | struct __qspinlock *l = (void *)lock; | |
492 | struct pv_node *node; | |
a23db284 | 493 | |
0b792bf5 PZ |
494 | if (unlikely(locked != _Q_SLOW_VAL)) { |
495 | WARN(!debug_locks_silent, | |
496 | "pvqspinlock: lock 0x%lx has corrupted value 0x%x!\n", | |
497 | (unsigned long)lock, atomic_read(&lock->val)); | |
cba77f03 WL |
498 | return; |
499 | } | |
500 | ||
3b3fdf10 WD |
501 | /* |
502 | * A failed cmpxchg doesn't provide any memory-ordering guarantees, | |
503 | * so we need a barrier to order the read of the node data in | |
504 | * pv_unhash *after* we've read the lock being _Q_SLOW_VAL. | |
505 | * | |
1c4941fd | 506 | * Matches the cmpxchg() in pv_wait_head_or_lock() setting _Q_SLOW_VAL. |
3b3fdf10 WD |
507 | */ |
508 | smp_rmb(); | |
509 | ||
a23db284 WL |
510 | /* |
511 | * Since the above failed to release, this must be the SLOW path. | |
512 | * Therefore start by looking up the blocked node and unhashing it. | |
513 | */ | |
514 | node = pv_unhash(lock); | |
515 | ||
516 | /* | |
517 | * Now that we have a reference to the (likely) blocked pv_node, | |
518 | * release the lock. | |
519 | */ | |
520 | smp_store_release(&l->locked, 0); | |
521 | ||
522 | /* | |
523 | * At this point the memory pointed at by lock can be freed/reused, | |
524 | * however we can still use the pv_node to kick the CPU. | |
75d22702 WL |
525 | * The other vCPU may not really be halted, but kicking an active |
526 | * vCPU is harmless other than the additional latency in completing | |
527 | * the unlock. | |
a23db284 | 528 | */ |
45e898b7 | 529 | qstat_inc(qstat_pv_kick_unlock, true); |
93edc8bd | 530 | pv_kick(node->cpu); |
a23db284 | 531 | } |
d7804530 | 532 | |
a23db284 WL |
533 | /* |
534 | * Include the architecture specific callee-save thunk of the | |
535 | * __pv_queued_spin_unlock(). This thunk is put together with | |
d7804530 WL |
536 | * __pv_queued_spin_unlock() to make the callee-save thunk and the real unlock |
537 | * function close to each other sharing consecutive instruction cachelines. | |
538 | * Alternatively, architecture specific version of __pv_queued_spin_unlock() | |
539 | * can be defined. | |
a23db284 WL |
540 | */ |
541 | #include <asm/qspinlock_paravirt.h> | |
542 | ||
d7804530 WL |
543 | #ifndef __pv_queued_spin_unlock |
544 | __visible void __pv_queued_spin_unlock(struct qspinlock *lock) | |
545 | { | |
546 | struct __qspinlock *l = (void *)lock; | |
547 | u8 locked; | |
548 | ||
549 | /* | |
550 | * We must not unlock if SLOW, because in that case we must first | |
551 | * unhash. Otherwise it would be possible to have multiple @lock | |
552 | * entries, which would be BAD. | |
553 | */ | |
b1930493 | 554 | locked = cmpxchg_release(&l->locked, _Q_LOCKED_VAL, 0); |
d7804530 WL |
555 | if (likely(locked == _Q_LOCKED_VAL)) |
556 | return; | |
557 | ||
558 | __pv_queued_spin_unlock_slowpath(lock, locked); | |
559 | } | |
560 | #endif /* __pv_queued_spin_unlock */ |