Commit | Line | Data |
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a33fda35 WL |
1 | /* |
2 | * Queued spinlock | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P. | |
81d3dc9a | 15 | * (C) Copyright 2013-2014,2018 Red Hat, Inc. |
a33fda35 | 16 | * (C) Copyright 2015 Intel Corp. |
64d816cb | 17 | * (C) Copyright 2015 Hewlett-Packard Enterprise Development LP |
a33fda35 | 18 | * |
81d3dc9a | 19 | * Authors: Waiman Long <longman@redhat.com> |
a33fda35 WL |
20 | * Peter Zijlstra <peterz@infradead.org> |
21 | */ | |
a23db284 WL |
22 | |
23 | #ifndef _GEN_PV_LOCK_SLOWPATH | |
24 | ||
a33fda35 WL |
25 | #include <linux/smp.h> |
26 | #include <linux/bug.h> | |
27 | #include <linux/cpumask.h> | |
28 | #include <linux/percpu.h> | |
29 | #include <linux/hardirq.h> | |
30 | #include <linux/mutex.h> | |
5671360f | 31 | #include <linux/prefetch.h> |
69f9cae9 | 32 | #include <asm/byteorder.h> |
a33fda35 WL |
33 | #include <asm/qspinlock.h> |
34 | ||
81d3dc9a WL |
35 | /* |
36 | * Include queued spinlock statistics code | |
37 | */ | |
38 | #include "qspinlock_stat.h" | |
39 | ||
a33fda35 WL |
40 | /* |
41 | * The basic principle of a queue-based spinlock can best be understood | |
42 | * by studying a classic queue-based spinlock implementation called the | |
43 | * MCS lock. The paper below provides a good description for this kind | |
44 | * of lock. | |
45 | * | |
46 | * http://www.cise.ufl.edu/tr/DOC/REP-1992-71.pdf | |
47 | * | |
48 | * This queued spinlock implementation is based on the MCS lock, however to make | |
49 | * it fit the 4 bytes we assume spinlock_t to be, and preserve its existing | |
50 | * API, we must modify it somehow. | |
51 | * | |
52 | * In particular; where the traditional MCS lock consists of a tail pointer | |
53 | * (8 bytes) and needs the next pointer (another 8 bytes) of its own node to | |
54 | * unlock the next pending (next->locked), we compress both these: {tail, | |
55 | * next->locked} into a single u32 value. | |
56 | * | |
57 | * Since a spinlock disables recursion of its own context and there is a limit | |
58 | * to the contexts that can nest; namely: task, softirq, hardirq, nmi. As there | |
59 | * are at most 4 nesting levels, it can be encoded by a 2-bit number. Now | |
60 | * we can encode the tail by combining the 2-bit nesting level with the cpu | |
61 | * number. With one byte for the lock value and 3 bytes for the tail, only a | |
62 | * 32-bit word is now needed. Even though we only need 1 bit for the lock, | |
63 | * we extend it to a full byte to achieve better performance for architectures | |
64 | * that support atomic byte write. | |
65 | * | |
66 | * We also change the first spinner to spin on the lock bit instead of its | |
67 | * node; whereby avoiding the need to carry a node from lock to unlock, and | |
68 | * preserving existing lock API. This also makes the unlock code simpler and | |
69 | * faster. | |
69f9cae9 PZI |
70 | * |
71 | * N.B. The current implementation only supports architectures that allow | |
72 | * atomic operations on smaller 8-bit and 16-bit data types. | |
73 | * | |
a33fda35 WL |
74 | */ |
75 | ||
76 | #include "mcs_spinlock.h" | |
77 | ||
a23db284 WL |
78 | #ifdef CONFIG_PARAVIRT_SPINLOCKS |
79 | #define MAX_NODES 8 | |
80 | #else | |
81 | #define MAX_NODES 4 | |
82 | #endif | |
83 | ||
6512276d WD |
84 | /* |
85 | * The pending bit spinning loop count. | |
86 | * This heuristic is used to limit the number of lockword accesses | |
87 | * made by atomic_cond_read_relaxed when waiting for the lock to | |
88 | * transition out of the "== _Q_PENDING_VAL" state. We don't spin | |
89 | * indefinitely because there's no guarantee that we'll make forward | |
90 | * progress. | |
91 | */ | |
92 | #ifndef _Q_PENDING_LOOPS | |
93 | #define _Q_PENDING_LOOPS 1 | |
94 | #endif | |
95 | ||
a33fda35 WL |
96 | /* |
97 | * Per-CPU queue node structures; we can never have more than 4 nested | |
98 | * contexts: task, softirq, hardirq, nmi. | |
99 | * | |
100 | * Exactly fits one 64-byte cacheline on a 64-bit architecture. | |
a23db284 WL |
101 | * |
102 | * PV doubles the storage and uses the second cacheline for PV state. | |
a33fda35 | 103 | */ |
a23db284 | 104 | static DEFINE_PER_CPU_ALIGNED(struct mcs_spinlock, mcs_nodes[MAX_NODES]); |
a33fda35 WL |
105 | |
106 | /* | |
107 | * We must be able to distinguish between no-tail and the tail at 0:0, | |
108 | * therefore increment the cpu number by one. | |
109 | */ | |
110 | ||
8d53fa19 | 111 | static inline __pure u32 encode_tail(int cpu, int idx) |
a33fda35 WL |
112 | { |
113 | u32 tail; | |
114 | ||
115 | #ifdef CONFIG_DEBUG_SPINLOCK | |
116 | BUG_ON(idx > 3); | |
117 | #endif | |
118 | tail = (cpu + 1) << _Q_TAIL_CPU_OFFSET; | |
119 | tail |= idx << _Q_TAIL_IDX_OFFSET; /* assume < 4 */ | |
120 | ||
121 | return tail; | |
122 | } | |
123 | ||
8d53fa19 | 124 | static inline __pure struct mcs_spinlock *decode_tail(u32 tail) |
a33fda35 WL |
125 | { |
126 | int cpu = (tail >> _Q_TAIL_CPU_OFFSET) - 1; | |
127 | int idx = (tail & _Q_TAIL_IDX_MASK) >> _Q_TAIL_IDX_OFFSET; | |
128 | ||
129 | return per_cpu_ptr(&mcs_nodes[idx], cpu); | |
130 | } | |
131 | ||
c1fb159d PZI |
132 | #define _Q_LOCKED_PENDING_MASK (_Q_LOCKED_MASK | _Q_PENDING_MASK) |
133 | ||
2c83e8e9 | 134 | #if _Q_PENDING_BITS == 8 |
59fb586b WD |
135 | /** |
136 | * clear_pending - clear the pending bit. | |
137 | * @lock: Pointer to queued spinlock structure | |
138 | * | |
139 | * *,1,* -> *,0,* | |
140 | */ | |
141 | static __always_inline void clear_pending(struct qspinlock *lock) | |
142 | { | |
143 | WRITE_ONCE(lock->pending, 0); | |
144 | } | |
145 | ||
69f9cae9 PZI |
146 | /** |
147 | * clear_pending_set_locked - take ownership and clear the pending bit. | |
148 | * @lock: Pointer to queued spinlock structure | |
149 | * | |
150 | * *,1,0 -> *,0,1 | |
151 | * | |
152 | * Lock stealing is not allowed if this function is used. | |
153 | */ | |
154 | static __always_inline void clear_pending_set_locked(struct qspinlock *lock) | |
155 | { | |
625e88be | 156 | WRITE_ONCE(lock->locked_pending, _Q_LOCKED_VAL); |
69f9cae9 PZI |
157 | } |
158 | ||
159 | /* | |
160 | * xchg_tail - Put in the new queue tail code word & retrieve previous one | |
161 | * @lock : Pointer to queued spinlock structure | |
162 | * @tail : The new queue tail code word | |
163 | * Return: The previous queue tail code word | |
164 | * | |
548095de | 165 | * xchg(lock, tail), which heads an address dependency |
69f9cae9 PZI |
166 | * |
167 | * p,*,* -> n,*,* ; prev = xchg(lock, node) | |
168 | */ | |
169 | static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) | |
170 | { | |
64d816cb | 171 | /* |
9d4646d1 WD |
172 | * We can use relaxed semantics since the caller ensures that the |
173 | * MCS node is properly initialized before updating the tail. | |
64d816cb | 174 | */ |
9d4646d1 | 175 | return (u32)xchg_relaxed(&lock->tail, |
64d816cb | 176 | tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET; |
69f9cae9 PZI |
177 | } |
178 | ||
179 | #else /* _Q_PENDING_BITS == 8 */ | |
180 | ||
59fb586b WD |
181 | /** |
182 | * clear_pending - clear the pending bit. | |
183 | * @lock: Pointer to queued spinlock structure | |
184 | * | |
185 | * *,1,* -> *,0,* | |
186 | */ | |
187 | static __always_inline void clear_pending(struct qspinlock *lock) | |
188 | { | |
189 | atomic_andnot(_Q_PENDING_VAL, &lock->val); | |
190 | } | |
191 | ||
6403bd7d WL |
192 | /** |
193 | * clear_pending_set_locked - take ownership and clear the pending bit. | |
194 | * @lock: Pointer to queued spinlock structure | |
195 | * | |
196 | * *,1,0 -> *,0,1 | |
197 | */ | |
198 | static __always_inline void clear_pending_set_locked(struct qspinlock *lock) | |
199 | { | |
200 | atomic_add(-_Q_PENDING_VAL + _Q_LOCKED_VAL, &lock->val); | |
201 | } | |
202 | ||
203 | /** | |
204 | * xchg_tail - Put in the new queue tail code word & retrieve previous one | |
205 | * @lock : Pointer to queued spinlock structure | |
206 | * @tail : The new queue tail code word | |
207 | * Return: The previous queue tail code word | |
208 | * | |
209 | * xchg(lock, tail) | |
210 | * | |
211 | * p,*,* -> n,*,* ; prev = xchg(lock, node) | |
212 | */ | |
213 | static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) | |
214 | { | |
215 | u32 old, new, val = atomic_read(&lock->val); | |
216 | ||
217 | for (;;) { | |
218 | new = (val & _Q_LOCKED_PENDING_MASK) | tail; | |
64d816cb | 219 | /* |
9d4646d1 WD |
220 | * We can use relaxed semantics since the caller ensures that |
221 | * the MCS node is properly initialized before updating the | |
222 | * tail. | |
64d816cb | 223 | */ |
9d4646d1 | 224 | old = atomic_cmpxchg_relaxed(&lock->val, val, new); |
6403bd7d WL |
225 | if (old == val) |
226 | break; | |
227 | ||
228 | val = old; | |
229 | } | |
230 | return old; | |
231 | } | |
69f9cae9 | 232 | #endif /* _Q_PENDING_BITS == 8 */ |
6403bd7d | 233 | |
7aa54be2 PZ |
234 | /** |
235 | * queued_fetch_set_pending_acquire - fetch the whole lock value and set pending | |
236 | * @lock : Pointer to queued spinlock structure | |
237 | * Return: The previous lock value | |
238 | * | |
239 | * *,*,* -> *,1,* | |
240 | */ | |
241 | #ifndef queued_fetch_set_pending_acquire | |
242 | static __always_inline u32 queued_fetch_set_pending_acquire(struct qspinlock *lock) | |
243 | { | |
244 | return atomic_fetch_or_acquire(_Q_PENDING_VAL, &lock->val); | |
245 | } | |
246 | #endif | |
247 | ||
2c83e8e9 WL |
248 | /** |
249 | * set_locked - Set the lock bit and own the lock | |
250 | * @lock: Pointer to queued spinlock structure | |
251 | * | |
252 | * *,*,0 -> *,0,1 | |
253 | */ | |
254 | static __always_inline void set_locked(struct qspinlock *lock) | |
255 | { | |
625e88be | 256 | WRITE_ONCE(lock->locked, _Q_LOCKED_VAL); |
2c83e8e9 WL |
257 | } |
258 | ||
a23db284 WL |
259 | |
260 | /* | |
261 | * Generate the native code for queued_spin_unlock_slowpath(); provide NOPs for | |
262 | * all the PV callbacks. | |
263 | */ | |
264 | ||
265 | static __always_inline void __pv_init_node(struct mcs_spinlock *node) { } | |
cd0272fa WL |
266 | static __always_inline void __pv_wait_node(struct mcs_spinlock *node, |
267 | struct mcs_spinlock *prev) { } | |
75d22702 WL |
268 | static __always_inline void __pv_kick_node(struct qspinlock *lock, |
269 | struct mcs_spinlock *node) { } | |
1c4941fd WL |
270 | static __always_inline u32 __pv_wait_head_or_lock(struct qspinlock *lock, |
271 | struct mcs_spinlock *node) | |
272 | { return 0; } | |
a23db284 WL |
273 | |
274 | #define pv_enabled() false | |
275 | ||
276 | #define pv_init_node __pv_init_node | |
277 | #define pv_wait_node __pv_wait_node | |
278 | #define pv_kick_node __pv_kick_node | |
1c4941fd | 279 | #define pv_wait_head_or_lock __pv_wait_head_or_lock |
a23db284 WL |
280 | |
281 | #ifdef CONFIG_PARAVIRT_SPINLOCKS | |
282 | #define queued_spin_lock_slowpath native_queued_spin_lock_slowpath | |
283 | #endif | |
284 | ||
285 | #endif /* _GEN_PV_LOCK_SLOWPATH */ | |
286 | ||
a33fda35 WL |
287 | /** |
288 | * queued_spin_lock_slowpath - acquire the queued spinlock | |
289 | * @lock: Pointer to queued spinlock structure | |
290 | * @val: Current value of the queued spinlock 32-bit word | |
291 | * | |
c1fb159d | 292 | * (queue tail, pending bit, lock value) |
a33fda35 | 293 | * |
c1fb159d PZI |
294 | * fast : slow : unlock |
295 | * : : | |
296 | * uncontended (0,0,0) -:--> (0,0,1) ------------------------------:--> (*,*,0) | |
297 | * : | ^--------.------. / : | |
298 | * : v \ \ | : | |
299 | * pending : (0,1,1) +--> (0,1,0) \ | : | |
300 | * : | ^--' | | : | |
301 | * : v | | : | |
302 | * uncontended : (n,x,y) +--> (n,0,0) --' | : | |
303 | * queue : | ^--' | : | |
304 | * : v | : | |
305 | * contended : (*,x,y) +--> (*,0,0) ---> (*,0,1) -' : | |
306 | * queue : ^--' : | |
a33fda35 WL |
307 | */ |
308 | void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) | |
309 | { | |
310 | struct mcs_spinlock *prev, *next, *node; | |
59fb586b | 311 | u32 old, tail; |
a33fda35 WL |
312 | int idx; |
313 | ||
314 | BUILD_BUG_ON(CONFIG_NR_CPUS >= (1U << _Q_TAIL_CPU_BITS)); | |
315 | ||
a23db284 | 316 | if (pv_enabled()) |
81d3dc9a | 317 | goto pv_queue; |
a23db284 | 318 | |
43b3f028 | 319 | if (virt_spin_lock(lock)) |
2aa79af6 PZI |
320 | return; |
321 | ||
c1fb159d | 322 | /* |
6512276d WD |
323 | * Wait for in-progress pending->locked hand-overs with a bounded |
324 | * number of spins so that we guarantee forward progress. | |
c1fb159d PZI |
325 | * |
326 | * 0,1,0 -> 0,0,1 | |
327 | */ | |
328 | if (val == _Q_PENDING_VAL) { | |
6512276d WD |
329 | int cnt = _Q_PENDING_LOOPS; |
330 | val = atomic_cond_read_relaxed(&lock->val, | |
331 | (VAL != _Q_PENDING_VAL) || !cnt--); | |
c1fb159d PZI |
332 | } |
333 | ||
59fb586b WD |
334 | /* |
335 | * If we observe any contention; queue. | |
336 | */ | |
337 | if (val & ~_Q_LOCKED_MASK) | |
338 | goto queue; | |
339 | ||
c1fb159d PZI |
340 | /* |
341 | * trylock || pending | |
342 | * | |
756b1df4 | 343 | * 0,0,* -> 0,1,* -> 0,0,1 pending, trylock |
c1fb159d | 344 | */ |
7aa54be2 | 345 | val = queued_fetch_set_pending_acquire(lock); |
756b1df4 | 346 | |
53bf57fa | 347 | /* |
756b1df4 PZ |
348 | * If we observe contention, there is a concurrent locker. |
349 | * | |
350 | * Undo and queue; our setting of PENDING might have made the | |
351 | * n,0,0 -> 0,0,0 transition fail and it will now be waiting | |
352 | * on @next to become !NULL. | |
53bf57fa PZ |
353 | */ |
354 | if (unlikely(val & ~_Q_LOCKED_MASK)) { | |
756b1df4 PZ |
355 | |
356 | /* Undo PENDING if we set it. */ | |
53bf57fa PZ |
357 | if (!(val & _Q_PENDING_MASK)) |
358 | clear_pending(lock); | |
756b1df4 | 359 | |
53bf57fa | 360 | goto queue; |
59fb586b | 361 | } |
c1fb159d PZI |
362 | |
363 | /* | |
53bf57fa PZ |
364 | * We're pending, wait for the owner to go away. |
365 | * | |
366 | * 0,1,1 -> 0,1,0 | |
367 | * | |
368 | * this wait loop must be a load-acquire such that we match the | |
369 | * store-release that clears the locked bit and create lock | |
370 | * sequentiality; this is because not all | |
371 | * clear_pending_set_locked() implementations imply full | |
372 | * barriers. | |
373 | */ | |
374 | if (val & _Q_LOCKED_MASK) | |
375 | atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_MASK)); | |
376 | ||
377 | /* | |
378 | * take ownership and clear the pending bit. | |
379 | * | |
380 | * 0,1,0 -> 0,0,1 | |
c1fb159d | 381 | */ |
53bf57fa PZ |
382 | clear_pending_set_locked(lock); |
383 | qstat_inc(qstat_lock_pending, true); | |
384 | return; | |
c1fb159d PZI |
385 | |
386 | /* | |
387 | * End of pending bit optimistic spinning and beginning of MCS | |
388 | * queuing. | |
389 | */ | |
390 | queue: | |
81d3dc9a WL |
391 | qstat_inc(qstat_lock_slowpath, true); |
392 | pv_queue: | |
a33fda35 WL |
393 | node = this_cpu_ptr(&mcs_nodes[0]); |
394 | idx = node->count++; | |
395 | tail = encode_tail(smp_processor_id(), idx); | |
396 | ||
397 | node += idx; | |
11dc1322 WD |
398 | |
399 | /* | |
400 | * Ensure that we increment the head node->count before initialising | |
401 | * the actual node. If the compiler is kind enough to reorder these | |
402 | * stores, then an IRQ could overwrite our assignments. | |
403 | */ | |
404 | barrier(); | |
405 | ||
a33fda35 WL |
406 | node->locked = 0; |
407 | node->next = NULL; | |
a23db284 | 408 | pv_init_node(node); |
a33fda35 WL |
409 | |
410 | /* | |
6403bd7d WL |
411 | * We touched a (possibly) cold cacheline in the per-cpu queue node; |
412 | * attempt the trylock once more in the hope someone let go while we | |
413 | * weren't watching. | |
a33fda35 | 414 | */ |
6403bd7d WL |
415 | if (queued_spin_trylock(lock)) |
416 | goto release; | |
a33fda35 WL |
417 | |
418 | /* | |
9d4646d1 WD |
419 | * Ensure that the initialisation of @node is complete before we |
420 | * publish the updated tail via xchg_tail() and potentially link | |
421 | * @node into the waitqueue via WRITE_ONCE(prev->next, node) below. | |
422 | */ | |
423 | smp_wmb(); | |
424 | ||
425 | /* | |
426 | * Publish the updated tail. | |
6403bd7d WL |
427 | * We have already touched the queueing cacheline; don't bother with |
428 | * pending stuff. | |
429 | * | |
430 | * p,*,* -> n,*,* | |
a33fda35 | 431 | */ |
6403bd7d | 432 | old = xchg_tail(lock, tail); |
aa68744f | 433 | next = NULL; |
a33fda35 WL |
434 | |
435 | /* | |
436 | * if there was a previous node; link it and wait until reaching the | |
437 | * head of the waitqueue. | |
438 | */ | |
6403bd7d | 439 | if (old & _Q_TAIL_MASK) { |
a33fda35 | 440 | prev = decode_tail(old); |
95bcade3 | 441 | |
9d4646d1 WD |
442 | /* Link @node into the waitqueue. */ |
443 | WRITE_ONCE(prev->next, node); | |
a33fda35 | 444 | |
cd0272fa | 445 | pv_wait_node(node, prev); |
a33fda35 | 446 | arch_mcs_spin_lock_contended(&node->locked); |
81b55986 WL |
447 | |
448 | /* | |
449 | * While waiting for the MCS lock, the next pointer may have | |
450 | * been set by another lock waiter. We optimistically load | |
451 | * the next pointer & prefetch the cacheline for writing | |
452 | * to reduce latency in the upcoming MCS unlock operation. | |
453 | */ | |
454 | next = READ_ONCE(node->next); | |
455 | if (next) | |
456 | prefetchw(next); | |
a33fda35 WL |
457 | } |
458 | ||
459 | /* | |
c1fb159d PZI |
460 | * we're at the head of the waitqueue, wait for the owner & pending to |
461 | * go away. | |
a33fda35 | 462 | * |
c1fb159d | 463 | * *,x,y -> *,0,0 |
2c83e8e9 WL |
464 | * |
465 | * this wait loop must use a load-acquire such that we match the | |
466 | * store-release that clears the locked bit and create lock | |
467 | * sequentiality; this is because the set_locked() function below | |
468 | * does not imply a full barrier. | |
469 | * | |
1c4941fd WL |
470 | * The PV pv_wait_head_or_lock function, if active, will acquire |
471 | * the lock and return a non-zero value. So we have to skip the | |
f9c811fa WD |
472 | * atomic_cond_read_acquire() call. As the next PV queue head hasn't |
473 | * been designated yet, there is no way for the locked value to become | |
1c4941fd WL |
474 | * _Q_SLOW_VAL. So both the set_locked() and the |
475 | * atomic_cmpxchg_relaxed() calls will be safe. | |
476 | * | |
477 | * If PV isn't active, 0 will be returned instead. | |
478 | * | |
a33fda35 | 479 | */ |
1c4941fd WL |
480 | if ((val = pv_wait_head_or_lock(lock, node))) |
481 | goto locked; | |
482 | ||
f9c811fa | 483 | val = atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK)); |
a33fda35 | 484 | |
1c4941fd | 485 | locked: |
a33fda35 WL |
486 | /* |
487 | * claim the lock: | |
488 | * | |
c1fb159d | 489 | * n,0,0 -> 0,0,1 : lock, uncontended |
59fb586b | 490 | * *,*,0 -> *,*,1 : lock, contended |
2c83e8e9 | 491 | * |
59fb586b WD |
492 | * If the queue head is the only one in the queue (lock value == tail) |
493 | * and nobody is pending, clear the tail code and grab the lock. | |
494 | * Otherwise, we only need to grab the lock. | |
a33fda35 | 495 | */ |
c61da58d | 496 | |
ae75d908 | 497 | /* |
756b1df4 PZ |
498 | * In the PV case we might already have _Q_LOCKED_VAL set, because |
499 | * of lock stealing; therefore we must also allow: | |
ae75d908 | 500 | * |
756b1df4 PZ |
501 | * n,0,1 -> 0,0,1 |
502 | * | |
503 | * Note: at this point: (val & _Q_PENDING_MASK) == 0, because of the | |
504 | * above wait condition, therefore any concurrent setting of | |
505 | * PENDING will make the uncontended transition fail. | |
ae75d908 | 506 | */ |
756b1df4 PZ |
507 | if ((val & _Q_TAIL_MASK) == tail) { |
508 | if (atomic_try_cmpxchg_relaxed(&lock->val, &val, _Q_LOCKED_VAL)) | |
509 | goto release; /* No contention */ | |
510 | } | |
a33fda35 | 511 | |
756b1df4 PZ |
512 | /* |
513 | * Either somebody is queued behind us or _Q_PENDING_VAL got set | |
514 | * which will then detect the remaining tail and queue behind us | |
515 | * ensuring we'll see a @next. | |
516 | */ | |
c61da58d WD |
517 | set_locked(lock); |
518 | ||
a33fda35 | 519 | /* |
aa68744f | 520 | * contended path; wait for next if not observed yet, release. |
a33fda35 | 521 | */ |
c131a198 WD |
522 | if (!next) |
523 | next = smp_cond_load_relaxed(&node->next, (VAL)); | |
a33fda35 | 524 | |
2c83e8e9 | 525 | arch_mcs_spin_unlock_contended(&next->locked); |
75d22702 | 526 | pv_kick_node(lock, next); |
a33fda35 WL |
527 | |
528 | release: | |
529 | /* | |
530 | * release the node | |
531 | */ | |
0dceeaf5 | 532 | __this_cpu_dec(mcs_nodes[0].count); |
a33fda35 WL |
533 | } |
534 | EXPORT_SYMBOL(queued_spin_lock_slowpath); | |
a23db284 WL |
535 | |
536 | /* | |
537 | * Generate the paravirt code for queued_spin_unlock_slowpath(). | |
538 | */ | |
539 | #if !defined(_GEN_PV_LOCK_SLOWPATH) && defined(CONFIG_PARAVIRT_SPINLOCKS) | |
540 | #define _GEN_PV_LOCK_SLOWPATH | |
541 | ||
542 | #undef pv_enabled | |
543 | #define pv_enabled() true | |
544 | ||
545 | #undef pv_init_node | |
546 | #undef pv_wait_node | |
547 | #undef pv_kick_node | |
1c4941fd | 548 | #undef pv_wait_head_or_lock |
a23db284 WL |
549 | |
550 | #undef queued_spin_lock_slowpath | |
551 | #define queued_spin_lock_slowpath __pv_queued_spin_lock_slowpath | |
552 | ||
553 | #include "qspinlock_paravirt.h" | |
554 | #include "qspinlock.c" | |
555 | ||
556 | #endif |