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52a65ff5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
a34db9b2 IM |
3 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
4 | * Copyright (C) 2005-2006 Thomas Gleixner | |
1da177e4 LT |
5 | * |
6 | * This file contains driver APIs to the irq subsystem. | |
7 | */ | |
8 | ||
97fd75b7 AM |
9 | #define pr_fmt(fmt) "genirq: " fmt |
10 | ||
1da177e4 | 11 | #include <linux/irq.h> |
3aa551c9 | 12 | #include <linux/kthread.h> |
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/random.h> | |
15 | #include <linux/interrupt.h> | |
4001d8e8 | 16 | #include <linux/irqdomain.h> |
1aeb272c | 17 | #include <linux/slab.h> |
3aa551c9 | 18 | #include <linux/sched.h> |
8bd75c77 | 19 | #include <linux/sched/rt.h> |
0881e7bd | 20 | #include <linux/sched/task.h> |
11ea68f5 | 21 | #include <linux/sched/isolation.h> |
ae7e81c0 | 22 | #include <uapi/linux/sched/types.h> |
4d1d61a6 | 23 | #include <linux/task_work.h> |
1da177e4 LT |
24 | |
25 | #include "internals.h" | |
26 | ||
b6a32bbd | 27 | #if defined(CONFIG_IRQ_FORCED_THREADING) && !defined(CONFIG_PREEMPT_RT) |
8d32a307 | 28 | __read_mostly bool force_irqthreads; |
47b82e88 | 29 | EXPORT_SYMBOL_GPL(force_irqthreads); |
8d32a307 TG |
30 | |
31 | static int __init setup_forced_irqthreads(char *arg) | |
32 | { | |
33 | force_irqthreads = true; | |
34 | return 0; | |
35 | } | |
36 | early_param("threadirqs", setup_forced_irqthreads); | |
37 | #endif | |
38 | ||
62e04686 | 39 | static void __synchronize_hardirq(struct irq_desc *desc, bool sync_chip) |
1da177e4 | 40 | { |
62e04686 | 41 | struct irq_data *irqd = irq_desc_get_irq_data(desc); |
32f4125e | 42 | bool inprogress; |
1da177e4 | 43 | |
a98ce5c6 HX |
44 | do { |
45 | unsigned long flags; | |
46 | ||
47 | /* | |
48 | * Wait until we're out of the critical section. This might | |
49 | * give the wrong answer due to the lack of memory barriers. | |
50 | */ | |
32f4125e | 51 | while (irqd_irq_inprogress(&desc->irq_data)) |
a98ce5c6 HX |
52 | cpu_relax(); |
53 | ||
54 | /* Ok, that indicated we're done: double-check carefully. */ | |
239007b8 | 55 | raw_spin_lock_irqsave(&desc->lock, flags); |
32f4125e | 56 | inprogress = irqd_irq_inprogress(&desc->irq_data); |
62e04686 TG |
57 | |
58 | /* | |
59 | * If requested and supported, check at the chip whether it | |
60 | * is in flight at the hardware level, i.e. already pending | |
61 | * in a CPU and waiting for service and acknowledge. | |
62 | */ | |
63 | if (!inprogress && sync_chip) { | |
64 | /* | |
65 | * Ignore the return code. inprogress is only updated | |
66 | * when the chip supports it. | |
67 | */ | |
68 | __irq_get_irqchip_state(irqd, IRQCHIP_STATE_ACTIVE, | |
69 | &inprogress); | |
70 | } | |
239007b8 | 71 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
a98ce5c6 HX |
72 | |
73 | /* Oops, that failed? */ | |
32f4125e | 74 | } while (inprogress); |
18258f72 TG |
75 | } |
76 | ||
77 | /** | |
78 | * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs) | |
79 | * @irq: interrupt number to wait for | |
80 | * | |
81 | * This function waits for any pending hard IRQ handlers for this | |
82 | * interrupt to complete before returning. If you use this | |
83 | * function while holding a resource the IRQ handler may need you | |
84 | * will deadlock. It does not take associated threaded handlers | |
85 | * into account. | |
86 | * | |
87 | * Do not use this for shutdown scenarios where you must be sure | |
88 | * that all parts (hardirq and threaded handler) have completed. | |
89 | * | |
02cea395 PZ |
90 | * Returns: false if a threaded handler is active. |
91 | * | |
18258f72 | 92 | * This function may be called - with care - from IRQ context. |
62e04686 TG |
93 | * |
94 | * It does not check whether there is an interrupt in flight at the | |
95 | * hardware level, but not serviced yet, as this might deadlock when | |
96 | * called with interrupts disabled and the target CPU of the interrupt | |
97 | * is the current CPU. | |
18258f72 | 98 | */ |
02cea395 | 99 | bool synchronize_hardirq(unsigned int irq) |
18258f72 TG |
100 | { |
101 | struct irq_desc *desc = irq_to_desc(irq); | |
3aa551c9 | 102 | |
02cea395 | 103 | if (desc) { |
62e04686 | 104 | __synchronize_hardirq(desc, false); |
02cea395 PZ |
105 | return !atomic_read(&desc->threads_active); |
106 | } | |
107 | ||
108 | return true; | |
18258f72 TG |
109 | } |
110 | EXPORT_SYMBOL(synchronize_hardirq); | |
111 | ||
112 | /** | |
113 | * synchronize_irq - wait for pending IRQ handlers (on other CPUs) | |
114 | * @irq: interrupt number to wait for | |
115 | * | |
116 | * This function waits for any pending IRQ handlers for this interrupt | |
117 | * to complete before returning. If you use this function while | |
118 | * holding a resource the IRQ handler may need you will deadlock. | |
119 | * | |
1d21f2af TG |
120 | * Can only be called from preemptible code as it might sleep when |
121 | * an interrupt thread is associated to @irq. | |
62e04686 TG |
122 | * |
123 | * It optionally makes sure (when the irq chip supports that method) | |
124 | * that the interrupt is not pending in any CPU and waiting for | |
125 | * service. | |
18258f72 TG |
126 | */ |
127 | void synchronize_irq(unsigned int irq) | |
128 | { | |
129 | struct irq_desc *desc = irq_to_desc(irq); | |
130 | ||
131 | if (desc) { | |
62e04686 | 132 | __synchronize_hardirq(desc, true); |
18258f72 TG |
133 | /* |
134 | * We made sure that no hardirq handler is | |
135 | * running. Now verify that no threaded handlers are | |
136 | * active. | |
137 | */ | |
138 | wait_event(desc->wait_for_threads, | |
139 | !atomic_read(&desc->threads_active)); | |
140 | } | |
1da177e4 | 141 | } |
1da177e4 LT |
142 | EXPORT_SYMBOL(synchronize_irq); |
143 | ||
3aa551c9 TG |
144 | #ifdef CONFIG_SMP |
145 | cpumask_var_t irq_default_affinity; | |
146 | ||
9c255583 | 147 | static bool __irq_can_set_affinity(struct irq_desc *desc) |
e019c249 JL |
148 | { |
149 | if (!desc || !irqd_can_balance(&desc->irq_data) || | |
150 | !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity) | |
9c255583 TG |
151 | return false; |
152 | return true; | |
e019c249 JL |
153 | } |
154 | ||
771ee3b0 TG |
155 | /** |
156 | * irq_can_set_affinity - Check if the affinity of a given irq can be set | |
157 | * @irq: Interrupt to check | |
158 | * | |
159 | */ | |
160 | int irq_can_set_affinity(unsigned int irq) | |
161 | { | |
e019c249 | 162 | return __irq_can_set_affinity(irq_to_desc(irq)); |
771ee3b0 TG |
163 | } |
164 | ||
9c255583 TG |
165 | /** |
166 | * irq_can_set_affinity_usr - Check if affinity of a irq can be set from user space | |
167 | * @irq: Interrupt to check | |
168 | * | |
169 | * Like irq_can_set_affinity() above, but additionally checks for the | |
170 | * AFFINITY_MANAGED flag. | |
171 | */ | |
172 | bool irq_can_set_affinity_usr(unsigned int irq) | |
173 | { | |
174 | struct irq_desc *desc = irq_to_desc(irq); | |
175 | ||
176 | return __irq_can_set_affinity(desc) && | |
177 | !irqd_affinity_is_managed(&desc->irq_data); | |
178 | } | |
179 | ||
591d2fb0 TG |
180 | /** |
181 | * irq_set_thread_affinity - Notify irq threads to adjust affinity | |
182 | * @desc: irq descriptor which has affitnity changed | |
183 | * | |
184 | * We just set IRQTF_AFFINITY and delegate the affinity setting | |
185 | * to the interrupt thread itself. We can not call | |
186 | * set_cpus_allowed_ptr() here as we hold desc->lock and this | |
187 | * code can be called from hard interrupt context. | |
188 | */ | |
189 | void irq_set_thread_affinity(struct irq_desc *desc) | |
3aa551c9 | 190 | { |
f944b5a7 | 191 | struct irqaction *action; |
3aa551c9 | 192 | |
f944b5a7 | 193 | for_each_action_of_desc(desc, action) |
3aa551c9 | 194 | if (action->thread) |
591d2fb0 | 195 | set_bit(IRQTF_AFFINITY, &action->thread_flags); |
3aa551c9 TG |
196 | } |
197 | ||
19e1d4e9 TG |
198 | static void irq_validate_effective_affinity(struct irq_data *data) |
199 | { | |
200 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK | |
201 | const struct cpumask *m = irq_data_get_effective_affinity_mask(data); | |
202 | struct irq_chip *chip = irq_data_get_irq_chip(data); | |
203 | ||
204 | if (!cpumask_empty(m)) | |
205 | return; | |
206 | pr_warn_once("irq_chip %s did not update eff. affinity mask of irq %u\n", | |
207 | chip->name, data->irq); | |
208 | #endif | |
209 | } | |
210 | ||
818b0f3b JL |
211 | int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, |
212 | bool force) | |
213 | { | |
214 | struct irq_desc *desc = irq_data_to_desc(data); | |
215 | struct irq_chip *chip = irq_data_get_irq_chip(data); | |
216 | int ret; | |
217 | ||
e43b3b58 TG |
218 | if (!chip || !chip->irq_set_affinity) |
219 | return -EINVAL; | |
220 | ||
11ea68f5 ML |
221 | /* |
222 | * If this is a managed interrupt and housekeeping is enabled on | |
223 | * it check whether the requested affinity mask intersects with | |
224 | * a housekeeping CPU. If so, then remove the isolated CPUs from | |
225 | * the mask and just keep the housekeeping CPU(s). This prevents | |
226 | * the affinity setter from routing the interrupt to an isolated | |
227 | * CPU to avoid that I/O submitted from a housekeeping CPU causes | |
228 | * interrupts on an isolated one. | |
229 | * | |
230 | * If the masks do not intersect or include online CPU(s) then | |
231 | * keep the requested mask. The isolated target CPUs are only | |
232 | * receiving interrupts when the I/O operation was submitted | |
233 | * directly from them. | |
234 | * | |
235 | * If all housekeeping CPUs in the affinity mask are offline, the | |
236 | * interrupt will be migrated by the CPU hotplug code once a | |
237 | * housekeeping CPU which belongs to the affinity mask comes | |
238 | * online. | |
239 | */ | |
240 | if (irqd_affinity_is_managed(data) && | |
241 | housekeeping_enabled(HK_FLAG_MANAGED_IRQ)) { | |
242 | const struct cpumask *hk_mask, *prog_mask; | |
243 | ||
244 | static DEFINE_RAW_SPINLOCK(tmp_mask_lock); | |
245 | static struct cpumask tmp_mask; | |
246 | ||
247 | hk_mask = housekeeping_cpumask(HK_FLAG_MANAGED_IRQ); | |
248 | ||
249 | raw_spin_lock(&tmp_mask_lock); | |
250 | cpumask_and(&tmp_mask, mask, hk_mask); | |
251 | if (!cpumask_intersects(&tmp_mask, cpu_online_mask)) | |
252 | prog_mask = mask; | |
253 | else | |
254 | prog_mask = &tmp_mask; | |
255 | ret = chip->irq_set_affinity(data, prog_mask, force); | |
256 | raw_spin_unlock(&tmp_mask_lock); | |
257 | } else { | |
258 | ret = chip->irq_set_affinity(data, mask, force); | |
259 | } | |
818b0f3b JL |
260 | switch (ret) { |
261 | case IRQ_SET_MASK_OK: | |
2cb62547 | 262 | case IRQ_SET_MASK_OK_DONE: |
9df872fa | 263 | cpumask_copy(desc->irq_common_data.affinity, mask); |
93417a3f | 264 | /* fall through */ |
818b0f3b | 265 | case IRQ_SET_MASK_OK_NOCOPY: |
19e1d4e9 | 266 | irq_validate_effective_affinity(data); |
818b0f3b JL |
267 | irq_set_thread_affinity(desc); |
268 | ret = 0; | |
269 | } | |
270 | ||
271 | return ret; | |
272 | } | |
273 | ||
12f47073 TG |
274 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
275 | static inline int irq_set_affinity_pending(struct irq_data *data, | |
276 | const struct cpumask *dest) | |
277 | { | |
278 | struct irq_desc *desc = irq_data_to_desc(data); | |
279 | ||
280 | irqd_set_move_pending(data); | |
281 | irq_copy_pending(desc, dest); | |
282 | return 0; | |
283 | } | |
284 | #else | |
285 | static inline int irq_set_affinity_pending(struct irq_data *data, | |
286 | const struct cpumask *dest) | |
287 | { | |
288 | return -EBUSY; | |
289 | } | |
290 | #endif | |
291 | ||
292 | static int irq_try_set_affinity(struct irq_data *data, | |
293 | const struct cpumask *dest, bool force) | |
294 | { | |
295 | int ret = irq_do_set_affinity(data, dest, force); | |
296 | ||
297 | /* | |
298 | * In case that the underlying vector management is busy and the | |
299 | * architecture supports the generic pending mechanism then utilize | |
300 | * this to avoid returning an error to user space. | |
301 | */ | |
302 | if (ret == -EBUSY && !force) | |
303 | ret = irq_set_affinity_pending(data, dest); | |
304 | return ret; | |
305 | } | |
306 | ||
01f8fa4f TG |
307 | int irq_set_affinity_locked(struct irq_data *data, const struct cpumask *mask, |
308 | bool force) | |
771ee3b0 | 309 | { |
c2d0c555 DD |
310 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
311 | struct irq_desc *desc = irq_data_to_desc(data); | |
1fa46f1f | 312 | int ret = 0; |
771ee3b0 | 313 | |
c2d0c555 | 314 | if (!chip || !chip->irq_set_affinity) |
771ee3b0 TG |
315 | return -EINVAL; |
316 | ||
12f47073 TG |
317 | if (irq_can_move_pcntxt(data) && !irqd_is_setaffinity_pending(data)) { |
318 | ret = irq_try_set_affinity(data, mask, force); | |
1fa46f1f | 319 | } else { |
c2d0c555 | 320 | irqd_set_move_pending(data); |
1fa46f1f | 321 | irq_copy_pending(desc, mask); |
57b150cc | 322 | } |
1fa46f1f | 323 | |
cd7eab44 BH |
324 | if (desc->affinity_notify) { |
325 | kref_get(&desc->affinity_notify->kref); | |
df81dfcf EC |
326 | if (!schedule_work(&desc->affinity_notify->work)) { |
327 | /* Work was already scheduled, drop our extra ref */ | |
328 | kref_put(&desc->affinity_notify->kref, | |
329 | desc->affinity_notify->release); | |
330 | } | |
cd7eab44 | 331 | } |
c2d0c555 DD |
332 | irqd_set(data, IRQD_AFFINITY_SET); |
333 | ||
334 | return ret; | |
335 | } | |
336 | ||
01f8fa4f | 337 | int __irq_set_affinity(unsigned int irq, const struct cpumask *mask, bool force) |
c2d0c555 DD |
338 | { |
339 | struct irq_desc *desc = irq_to_desc(irq); | |
340 | unsigned long flags; | |
341 | int ret; | |
342 | ||
343 | if (!desc) | |
344 | return -EINVAL; | |
345 | ||
346 | raw_spin_lock_irqsave(&desc->lock, flags); | |
01f8fa4f | 347 | ret = irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask, force); |
239007b8 | 348 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1fa46f1f | 349 | return ret; |
771ee3b0 TG |
350 | } |
351 | ||
e7a297b0 PWJ |
352 | int irq_set_affinity_hint(unsigned int irq, const struct cpumask *m) |
353 | { | |
e7a297b0 | 354 | unsigned long flags; |
31d9d9b6 | 355 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
e7a297b0 PWJ |
356 | |
357 | if (!desc) | |
358 | return -EINVAL; | |
e7a297b0 | 359 | desc->affinity_hint = m; |
02725e74 | 360 | irq_put_desc_unlock(desc, flags); |
e2e64a93 | 361 | /* set the initial affinity to prevent every interrupt being on CPU0 */ |
4fe7ffb7 JB |
362 | if (m) |
363 | __irq_set_affinity(irq, m, false); | |
e7a297b0 PWJ |
364 | return 0; |
365 | } | |
366 | EXPORT_SYMBOL_GPL(irq_set_affinity_hint); | |
367 | ||
cd7eab44 BH |
368 | static void irq_affinity_notify(struct work_struct *work) |
369 | { | |
370 | struct irq_affinity_notify *notify = | |
371 | container_of(work, struct irq_affinity_notify, work); | |
372 | struct irq_desc *desc = irq_to_desc(notify->irq); | |
373 | cpumask_var_t cpumask; | |
374 | unsigned long flags; | |
375 | ||
1fa46f1f | 376 | if (!desc || !alloc_cpumask_var(&cpumask, GFP_KERNEL)) |
cd7eab44 BH |
377 | goto out; |
378 | ||
379 | raw_spin_lock_irqsave(&desc->lock, flags); | |
0ef5ca1e | 380 | if (irq_move_pending(&desc->irq_data)) |
1fa46f1f | 381 | irq_get_pending(cpumask, desc); |
cd7eab44 | 382 | else |
9df872fa | 383 | cpumask_copy(cpumask, desc->irq_common_data.affinity); |
cd7eab44 BH |
384 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
385 | ||
386 | notify->notify(notify, cpumask); | |
387 | ||
388 | free_cpumask_var(cpumask); | |
389 | out: | |
390 | kref_put(¬ify->kref, notify->release); | |
391 | } | |
392 | ||
393 | /** | |
394 | * irq_set_affinity_notifier - control notification of IRQ affinity changes | |
395 | * @irq: Interrupt for which to enable/disable notification | |
396 | * @notify: Context for notification, or %NULL to disable | |
397 | * notification. Function pointers must be initialised; | |
398 | * the other fields will be initialised by this function. | |
399 | * | |
400 | * Must be called in process context. Notification may only be enabled | |
401 | * after the IRQ is allocated and must be disabled before the IRQ is | |
402 | * freed using free_irq(). | |
403 | */ | |
404 | int | |
405 | irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify) | |
406 | { | |
407 | struct irq_desc *desc = irq_to_desc(irq); | |
408 | struct irq_affinity_notify *old_notify; | |
409 | unsigned long flags; | |
410 | ||
411 | /* The release function is promised process context */ | |
412 | might_sleep(); | |
413 | ||
b525903c | 414 | if (!desc || desc->istate & IRQS_NMI) |
cd7eab44 BH |
415 | return -EINVAL; |
416 | ||
417 | /* Complete initialisation of *notify */ | |
418 | if (notify) { | |
419 | notify->irq = irq; | |
420 | kref_init(¬ify->kref); | |
421 | INIT_WORK(¬ify->work, irq_affinity_notify); | |
422 | } | |
423 | ||
424 | raw_spin_lock_irqsave(&desc->lock, flags); | |
425 | old_notify = desc->affinity_notify; | |
426 | desc->affinity_notify = notify; | |
427 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
428 | ||
59c39840 | 429 | if (old_notify) { |
df81dfcf EC |
430 | if (cancel_work_sync(&old_notify->work)) { |
431 | /* Pending work had a ref, put that one too */ | |
432 | kref_put(&old_notify->kref, old_notify->release); | |
433 | } | |
cd7eab44 | 434 | kref_put(&old_notify->kref, old_notify->release); |
59c39840 | 435 | } |
cd7eab44 BH |
436 | |
437 | return 0; | |
438 | } | |
439 | EXPORT_SYMBOL_GPL(irq_set_affinity_notifier); | |
440 | ||
18404756 MK |
441 | #ifndef CONFIG_AUTO_IRQ_AFFINITY |
442 | /* | |
443 | * Generic version of the affinity autoselector. | |
444 | */ | |
43564bd9 | 445 | int irq_setup_affinity(struct irq_desc *desc) |
18404756 | 446 | { |
569bda8d | 447 | struct cpumask *set = irq_default_affinity; |
cba4235e TG |
448 | int ret, node = irq_desc_get_node(desc); |
449 | static DEFINE_RAW_SPINLOCK(mask_lock); | |
450 | static struct cpumask mask; | |
569bda8d | 451 | |
b008207c | 452 | /* Excludes PER_CPU and NO_BALANCE interrupts */ |
e019c249 | 453 | if (!__irq_can_set_affinity(desc)) |
18404756 MK |
454 | return 0; |
455 | ||
cba4235e | 456 | raw_spin_lock(&mask_lock); |
f6d87f4b | 457 | /* |
9332ef9d | 458 | * Preserve the managed affinity setting and a userspace affinity |
06ee6d57 | 459 | * setup, but make sure that one of the targets is online. |
f6d87f4b | 460 | */ |
06ee6d57 TG |
461 | if (irqd_affinity_is_managed(&desc->irq_data) || |
462 | irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) { | |
9df872fa | 463 | if (cpumask_intersects(desc->irq_common_data.affinity, |
569bda8d | 464 | cpu_online_mask)) |
9df872fa | 465 | set = desc->irq_common_data.affinity; |
0c6f8a8b | 466 | else |
2bdd1055 | 467 | irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET); |
f6d87f4b | 468 | } |
18404756 | 469 | |
cba4235e | 470 | cpumask_and(&mask, cpu_online_mask, set); |
bddda606 SR |
471 | if (cpumask_empty(&mask)) |
472 | cpumask_copy(&mask, cpu_online_mask); | |
473 | ||
241fc640 PB |
474 | if (node != NUMA_NO_NODE) { |
475 | const struct cpumask *nodemask = cpumask_of_node(node); | |
476 | ||
477 | /* make sure at least one of the cpus in nodemask is online */ | |
cba4235e TG |
478 | if (cpumask_intersects(&mask, nodemask)) |
479 | cpumask_and(&mask, &mask, nodemask); | |
241fc640 | 480 | } |
cba4235e TG |
481 | ret = irq_do_set_affinity(&desc->irq_data, &mask, false); |
482 | raw_spin_unlock(&mask_lock); | |
483 | return ret; | |
18404756 | 484 | } |
f6d87f4b | 485 | #else |
a8a98eac | 486 | /* Wrapper for ALPHA specific affinity selector magic */ |
cba4235e | 487 | int irq_setup_affinity(struct irq_desc *desc) |
f6d87f4b | 488 | { |
cba4235e | 489 | return irq_select_affinity(irq_desc_get_irq(desc)); |
f6d87f4b | 490 | } |
cba6437a TG |
491 | #endif /* CONFIG_AUTO_IRQ_AFFINITY */ |
492 | #endif /* CONFIG_SMP */ | |
18404756 | 493 | |
1da177e4 | 494 | |
fcf1ae2f FW |
495 | /** |
496 | * irq_set_vcpu_affinity - Set vcpu affinity for the interrupt | |
497 | * @irq: interrupt number to set affinity | |
250a53d6 CD |
498 | * @vcpu_info: vCPU specific data or pointer to a percpu array of vCPU |
499 | * specific data for percpu_devid interrupts | |
fcf1ae2f FW |
500 | * |
501 | * This function uses the vCPU specific data to set the vCPU | |
502 | * affinity for an irq. The vCPU specific data is passed from | |
503 | * outside, such as KVM. One example code path is as below: | |
504 | * KVM -> IOMMU -> irq_set_vcpu_affinity(). | |
505 | */ | |
506 | int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info) | |
507 | { | |
508 | unsigned long flags; | |
509 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
510 | struct irq_data *data; | |
511 | struct irq_chip *chip; | |
512 | int ret = -ENOSYS; | |
513 | ||
514 | if (!desc) | |
515 | return -EINVAL; | |
516 | ||
517 | data = irq_desc_get_irq_data(desc); | |
0abce64a MZ |
518 | do { |
519 | chip = irq_data_get_irq_chip(data); | |
520 | if (chip && chip->irq_set_vcpu_affinity) | |
521 | break; | |
522 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
523 | data = data->parent_data; | |
524 | #else | |
525 | data = NULL; | |
526 | #endif | |
527 | } while (data); | |
528 | ||
529 | if (data) | |
fcf1ae2f FW |
530 | ret = chip->irq_set_vcpu_affinity(data, vcpu_info); |
531 | irq_put_desc_unlock(desc, flags); | |
532 | ||
533 | return ret; | |
534 | } | |
535 | EXPORT_SYMBOL_GPL(irq_set_vcpu_affinity); | |
536 | ||
79ff1cda | 537 | void __disable_irq(struct irq_desc *desc) |
0a0c5168 | 538 | { |
3aae994f | 539 | if (!desc->depth++) |
87923470 | 540 | irq_disable(desc); |
0a0c5168 RW |
541 | } |
542 | ||
02725e74 TG |
543 | static int __disable_irq_nosync(unsigned int irq) |
544 | { | |
545 | unsigned long flags; | |
31d9d9b6 | 546 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 TG |
547 | |
548 | if (!desc) | |
549 | return -EINVAL; | |
79ff1cda | 550 | __disable_irq(desc); |
02725e74 TG |
551 | irq_put_desc_busunlock(desc, flags); |
552 | return 0; | |
553 | } | |
554 | ||
1da177e4 LT |
555 | /** |
556 | * disable_irq_nosync - disable an irq without waiting | |
557 | * @irq: Interrupt to disable | |
558 | * | |
559 | * Disable the selected interrupt line. Disables and Enables are | |
560 | * nested. | |
561 | * Unlike disable_irq(), this function does not ensure existing | |
562 | * instances of the IRQ handler have completed before returning. | |
563 | * | |
564 | * This function may be called from IRQ context. | |
565 | */ | |
566 | void disable_irq_nosync(unsigned int irq) | |
567 | { | |
02725e74 | 568 | __disable_irq_nosync(irq); |
1da177e4 | 569 | } |
1da177e4 LT |
570 | EXPORT_SYMBOL(disable_irq_nosync); |
571 | ||
572 | /** | |
573 | * disable_irq - disable an irq and wait for completion | |
574 | * @irq: Interrupt to disable | |
575 | * | |
576 | * Disable the selected interrupt line. Enables and Disables are | |
577 | * nested. | |
578 | * This function waits for any pending IRQ handlers for this interrupt | |
579 | * to complete before returning. If you use this function while | |
580 | * holding a resource the IRQ handler may need you will deadlock. | |
581 | * | |
582 | * This function may be called - with care - from IRQ context. | |
583 | */ | |
584 | void disable_irq(unsigned int irq) | |
585 | { | |
02725e74 | 586 | if (!__disable_irq_nosync(irq)) |
1da177e4 LT |
587 | synchronize_irq(irq); |
588 | } | |
1da177e4 LT |
589 | EXPORT_SYMBOL(disable_irq); |
590 | ||
02cea395 PZ |
591 | /** |
592 | * disable_hardirq - disables an irq and waits for hardirq completion | |
593 | * @irq: Interrupt to disable | |
594 | * | |
595 | * Disable the selected interrupt line. Enables and Disables are | |
596 | * nested. | |
597 | * This function waits for any pending hard IRQ handlers for this | |
598 | * interrupt to complete before returning. If you use this function while | |
599 | * holding a resource the hard IRQ handler may need you will deadlock. | |
600 | * | |
601 | * When used to optimistically disable an interrupt from atomic context | |
602 | * the return value must be checked. | |
603 | * | |
604 | * Returns: false if a threaded handler is active. | |
605 | * | |
606 | * This function may be called - with care - from IRQ context. | |
607 | */ | |
608 | bool disable_hardirq(unsigned int irq) | |
609 | { | |
610 | if (!__disable_irq_nosync(irq)) | |
611 | return synchronize_hardirq(irq); | |
612 | ||
613 | return false; | |
614 | } | |
615 | EXPORT_SYMBOL_GPL(disable_hardirq); | |
616 | ||
b525903c JT |
617 | /** |
618 | * disable_nmi_nosync - disable an nmi without waiting | |
619 | * @irq: Interrupt to disable | |
620 | * | |
621 | * Disable the selected interrupt line. Disables and enables are | |
622 | * nested. | |
623 | * The interrupt to disable must have been requested through request_nmi. | |
624 | * Unlike disable_nmi(), this function does not ensure existing | |
625 | * instances of the IRQ handler have completed before returning. | |
626 | */ | |
627 | void disable_nmi_nosync(unsigned int irq) | |
628 | { | |
629 | disable_irq_nosync(irq); | |
630 | } | |
631 | ||
79ff1cda | 632 | void __enable_irq(struct irq_desc *desc) |
1adb0850 TG |
633 | { |
634 | switch (desc->depth) { | |
635 | case 0: | |
0a0c5168 | 636 | err_out: |
79ff1cda JL |
637 | WARN(1, KERN_WARNING "Unbalanced enable for IRQ %d\n", |
638 | irq_desc_get_irq(desc)); | |
1adb0850 TG |
639 | break; |
640 | case 1: { | |
c531e836 | 641 | if (desc->istate & IRQS_SUSPENDED) |
0a0c5168 | 642 | goto err_out; |
1adb0850 | 643 | /* Prevent probing on this irq: */ |
1ccb4e61 | 644 | irq_settings_set_noprobe(desc); |
201d7f47 TG |
645 | /* |
646 | * Call irq_startup() not irq_enable() here because the | |
647 | * interrupt might be marked NOAUTOEN. So irq_startup() | |
648 | * needs to be invoked when it gets enabled the first | |
649 | * time. If it was already started up, then irq_startup() | |
650 | * will invoke irq_enable() under the hood. | |
651 | */ | |
c942cee4 | 652 | irq_startup(desc, IRQ_RESEND, IRQ_START_FORCE); |
201d7f47 | 653 | break; |
1adb0850 TG |
654 | } |
655 | default: | |
656 | desc->depth--; | |
657 | } | |
658 | } | |
659 | ||
1da177e4 LT |
660 | /** |
661 | * enable_irq - enable handling of an irq | |
662 | * @irq: Interrupt to enable | |
663 | * | |
664 | * Undoes the effect of one call to disable_irq(). If this | |
665 | * matches the last disable, processing of interrupts on this | |
666 | * IRQ line is re-enabled. | |
667 | * | |
70aedd24 | 668 | * This function may be called from IRQ context only when |
6b8ff312 | 669 | * desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL ! |
1da177e4 LT |
670 | */ |
671 | void enable_irq(unsigned int irq) | |
672 | { | |
1da177e4 | 673 | unsigned long flags; |
31d9d9b6 | 674 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
1da177e4 | 675 | |
7d94f7ca | 676 | if (!desc) |
c2b5a251 | 677 | return; |
50f7c032 TG |
678 | if (WARN(!desc->irq_data.chip, |
679 | KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq)) | |
02725e74 | 680 | goto out; |
2656c366 | 681 | |
79ff1cda | 682 | __enable_irq(desc); |
02725e74 TG |
683 | out: |
684 | irq_put_desc_busunlock(desc, flags); | |
1da177e4 | 685 | } |
1da177e4 LT |
686 | EXPORT_SYMBOL(enable_irq); |
687 | ||
b525903c JT |
688 | /** |
689 | * enable_nmi - enable handling of an nmi | |
690 | * @irq: Interrupt to enable | |
691 | * | |
692 | * The interrupt to enable must have been requested through request_nmi. | |
693 | * Undoes the effect of one call to disable_nmi(). If this | |
694 | * matches the last disable, processing of interrupts on this | |
695 | * IRQ line is re-enabled. | |
696 | */ | |
697 | void enable_nmi(unsigned int irq) | |
698 | { | |
699 | enable_irq(irq); | |
700 | } | |
701 | ||
0c5d1eb7 | 702 | static int set_irq_wake_real(unsigned int irq, unsigned int on) |
2db87321 | 703 | { |
08678b08 | 704 | struct irq_desc *desc = irq_to_desc(irq); |
2db87321 UKK |
705 | int ret = -ENXIO; |
706 | ||
60f96b41 SS |
707 | if (irq_desc_get_chip(desc)->flags & IRQCHIP_SKIP_SET_WAKE) |
708 | return 0; | |
709 | ||
2f7e99bb TG |
710 | if (desc->irq_data.chip->irq_set_wake) |
711 | ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on); | |
2db87321 UKK |
712 | |
713 | return ret; | |
714 | } | |
715 | ||
ba9a2331 | 716 | /** |
a0cd9ca2 | 717 | * irq_set_irq_wake - control irq power management wakeup |
ba9a2331 TG |
718 | * @irq: interrupt to control |
719 | * @on: enable/disable power management wakeup | |
720 | * | |
15a647eb DB |
721 | * Enable/disable power management wakeup mode, which is |
722 | * disabled by default. Enables and disables must match, | |
723 | * just as they match for non-wakeup mode support. | |
724 | * | |
725 | * Wakeup mode lets this IRQ wake the system from sleep | |
726 | * states like "suspend to RAM". | |
f9f21cea SB |
727 | * |
728 | * Note: irq enable/disable state is completely orthogonal | |
729 | * to the enable/disable state of irq wake. An irq can be | |
730 | * disabled with disable_irq() and still wake the system as | |
731 | * long as the irq has wake enabled. If this does not hold, | |
732 | * then the underlying irq chip and the related driver need | |
733 | * to be investigated. | |
ba9a2331 | 734 | */ |
a0cd9ca2 | 735 | int irq_set_irq_wake(unsigned int irq, unsigned int on) |
ba9a2331 | 736 | { |
ba9a2331 | 737 | unsigned long flags; |
31d9d9b6 | 738 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
2db87321 | 739 | int ret = 0; |
ba9a2331 | 740 | |
13863a66 JJ |
741 | if (!desc) |
742 | return -EINVAL; | |
743 | ||
b525903c JT |
744 | /* Don't use NMIs as wake up interrupts please */ |
745 | if (desc->istate & IRQS_NMI) { | |
746 | ret = -EINVAL; | |
747 | goto out_unlock; | |
748 | } | |
749 | ||
15a647eb DB |
750 | /* wakeup-capable irqs can be shared between drivers that |
751 | * don't need to have the same sleep mode behaviors. | |
752 | */ | |
15a647eb | 753 | if (on) { |
2db87321 UKK |
754 | if (desc->wake_depth++ == 0) { |
755 | ret = set_irq_wake_real(irq, on); | |
756 | if (ret) | |
757 | desc->wake_depth = 0; | |
758 | else | |
7f94226f | 759 | irqd_set(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 760 | } |
15a647eb DB |
761 | } else { |
762 | if (desc->wake_depth == 0) { | |
7a2c4770 | 763 | WARN(1, "Unbalanced IRQ %d wake disable\n", irq); |
2db87321 UKK |
764 | } else if (--desc->wake_depth == 0) { |
765 | ret = set_irq_wake_real(irq, on); | |
766 | if (ret) | |
767 | desc->wake_depth = 1; | |
768 | else | |
7f94226f | 769 | irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 770 | } |
15a647eb | 771 | } |
b525903c JT |
772 | |
773 | out_unlock: | |
02725e74 | 774 | irq_put_desc_busunlock(desc, flags); |
ba9a2331 TG |
775 | return ret; |
776 | } | |
a0cd9ca2 | 777 | EXPORT_SYMBOL(irq_set_irq_wake); |
ba9a2331 | 778 | |
1da177e4 LT |
779 | /* |
780 | * Internal function that tells the architecture code whether a | |
781 | * particular irq has been exclusively allocated or is available | |
782 | * for driver use. | |
783 | */ | |
784 | int can_request_irq(unsigned int irq, unsigned long irqflags) | |
785 | { | |
cc8c3b78 | 786 | unsigned long flags; |
31d9d9b6 | 787 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
02725e74 | 788 | int canrequest = 0; |
1da177e4 | 789 | |
7d94f7ca YL |
790 | if (!desc) |
791 | return 0; | |
792 | ||
02725e74 | 793 | if (irq_settings_can_request(desc)) { |
2779db8d BH |
794 | if (!desc->action || |
795 | irqflags & desc->action->flags & IRQF_SHARED) | |
796 | canrequest = 1; | |
02725e74 TG |
797 | } |
798 | irq_put_desc_unlock(desc, flags); | |
799 | return canrequest; | |
1da177e4 LT |
800 | } |
801 | ||
a1ff541a | 802 | int __irq_set_trigger(struct irq_desc *desc, unsigned long flags) |
82736f4d | 803 | { |
6b8ff312 | 804 | struct irq_chip *chip = desc->irq_data.chip; |
d4d5e089 | 805 | int ret, unmask = 0; |
82736f4d | 806 | |
b2ba2c30 | 807 | if (!chip || !chip->irq_set_type) { |
82736f4d UKK |
808 | /* |
809 | * IRQF_TRIGGER_* but the PIC does not support multiple | |
810 | * flow-types? | |
811 | */ | |
a1ff541a JL |
812 | pr_debug("No set_type function for IRQ %d (%s)\n", |
813 | irq_desc_get_irq(desc), | |
f5d89470 | 814 | chip ? (chip->name ? : "unknown") : "unknown"); |
82736f4d UKK |
815 | return 0; |
816 | } | |
817 | ||
d4d5e089 | 818 | if (chip->flags & IRQCHIP_SET_TYPE_MASKED) { |
32f4125e | 819 | if (!irqd_irq_masked(&desc->irq_data)) |
d4d5e089 | 820 | mask_irq(desc); |
32f4125e | 821 | if (!irqd_irq_disabled(&desc->irq_data)) |
d4d5e089 TG |
822 | unmask = 1; |
823 | } | |
824 | ||
00b992de AK |
825 | /* Mask all flags except trigger mode */ |
826 | flags &= IRQ_TYPE_SENSE_MASK; | |
b2ba2c30 | 827 | ret = chip->irq_set_type(&desc->irq_data, flags); |
82736f4d | 828 | |
876dbd4c TG |
829 | switch (ret) { |
830 | case IRQ_SET_MASK_OK: | |
2cb62547 | 831 | case IRQ_SET_MASK_OK_DONE: |
876dbd4c TG |
832 | irqd_clear(&desc->irq_data, IRQD_TRIGGER_MASK); |
833 | irqd_set(&desc->irq_data, flags); | |
44133f7e | 834 | /* fall through */ |
876dbd4c TG |
835 | |
836 | case IRQ_SET_MASK_OK_NOCOPY: | |
837 | flags = irqd_get_trigger_type(&desc->irq_data); | |
838 | irq_settings_set_trigger_mask(desc, flags); | |
839 | irqd_clear(&desc->irq_data, IRQD_LEVEL); | |
840 | irq_settings_clr_level(desc); | |
841 | if (flags & IRQ_TYPE_LEVEL_MASK) { | |
842 | irq_settings_set_level(desc); | |
843 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
844 | } | |
46732475 | 845 | |
d4d5e089 | 846 | ret = 0; |
8fff39e0 | 847 | break; |
876dbd4c | 848 | default: |
d75f773c | 849 | pr_err("Setting trigger mode %lu for irq %u failed (%pS)\n", |
a1ff541a | 850 | flags, irq_desc_get_irq(desc), chip->irq_set_type); |
0c5d1eb7 | 851 | } |
d4d5e089 TG |
852 | if (unmask) |
853 | unmask_irq(desc); | |
82736f4d UKK |
854 | return ret; |
855 | } | |
856 | ||
293a7a0a TG |
857 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
858 | int irq_set_parent(int irq, int parent_irq) | |
859 | { | |
860 | unsigned long flags; | |
861 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
862 | ||
863 | if (!desc) | |
864 | return -EINVAL; | |
865 | ||
866 | desc->parent_irq = parent_irq; | |
867 | ||
868 | irq_put_desc_unlock(desc, flags); | |
869 | return 0; | |
870 | } | |
3118dac5 | 871 | EXPORT_SYMBOL_GPL(irq_set_parent); |
293a7a0a TG |
872 | #endif |
873 | ||
b25c340c TG |
874 | /* |
875 | * Default primary interrupt handler for threaded interrupts. Is | |
876 | * assigned as primary handler when request_threaded_irq is called | |
877 | * with handler == NULL. Useful for oneshot interrupts. | |
878 | */ | |
879 | static irqreturn_t irq_default_primary_handler(int irq, void *dev_id) | |
880 | { | |
881 | return IRQ_WAKE_THREAD; | |
882 | } | |
883 | ||
399b5da2 TG |
884 | /* |
885 | * Primary handler for nested threaded interrupts. Should never be | |
886 | * called. | |
887 | */ | |
888 | static irqreturn_t irq_nested_primary_handler(int irq, void *dev_id) | |
889 | { | |
890 | WARN(1, "Primary handler called for nested irq %d\n", irq); | |
891 | return IRQ_NONE; | |
892 | } | |
893 | ||
2a1d3ab8 TG |
894 | static irqreturn_t irq_forced_secondary_handler(int irq, void *dev_id) |
895 | { | |
896 | WARN(1, "Secondary action handler called for irq %d\n", irq); | |
897 | return IRQ_NONE; | |
898 | } | |
899 | ||
3aa551c9 TG |
900 | static int irq_wait_for_interrupt(struct irqaction *action) |
901 | { | |
519cc865 LW |
902 | for (;;) { |
903 | set_current_state(TASK_INTERRUPTIBLE); | |
550acb19 | 904 | |
519cc865 LW |
905 | if (kthread_should_stop()) { |
906 | /* may need to run one last time */ | |
907 | if (test_and_clear_bit(IRQTF_RUNTHREAD, | |
908 | &action->thread_flags)) { | |
909 | __set_current_state(TASK_RUNNING); | |
910 | return 0; | |
911 | } | |
912 | __set_current_state(TASK_RUNNING); | |
913 | return -1; | |
914 | } | |
f48fe81e TG |
915 | |
916 | if (test_and_clear_bit(IRQTF_RUNTHREAD, | |
917 | &action->thread_flags)) { | |
3aa551c9 TG |
918 | __set_current_state(TASK_RUNNING); |
919 | return 0; | |
f48fe81e TG |
920 | } |
921 | schedule(); | |
3aa551c9 | 922 | } |
3aa551c9 TG |
923 | } |
924 | ||
b25c340c TG |
925 | /* |
926 | * Oneshot interrupts keep the irq line masked until the threaded | |
927 | * handler finished. unmask if the interrupt has not been disabled and | |
928 | * is marked MASKED. | |
929 | */ | |
b5faba21 | 930 | static void irq_finalize_oneshot(struct irq_desc *desc, |
f3f79e38 | 931 | struct irqaction *action) |
b25c340c | 932 | { |
2a1d3ab8 TG |
933 | if (!(desc->istate & IRQS_ONESHOT) || |
934 | action->handler == irq_forced_secondary_handler) | |
b5faba21 | 935 | return; |
0b1adaa0 | 936 | again: |
3876ec9e | 937 | chip_bus_lock(desc); |
239007b8 | 938 | raw_spin_lock_irq(&desc->lock); |
0b1adaa0 TG |
939 | |
940 | /* | |
941 | * Implausible though it may be we need to protect us against | |
942 | * the following scenario: | |
943 | * | |
944 | * The thread is faster done than the hard interrupt handler | |
945 | * on the other CPU. If we unmask the irq line then the | |
946 | * interrupt can come in again and masks the line, leaves due | |
009b4c3b | 947 | * to IRQS_INPROGRESS and the irq line is masked forever. |
b5faba21 TG |
948 | * |
949 | * This also serializes the state of shared oneshot handlers | |
950 | * versus "desc->threads_onehsot |= action->thread_mask;" in | |
951 | * irq_wake_thread(). See the comment there which explains the | |
952 | * serialization. | |
0b1adaa0 | 953 | */ |
32f4125e | 954 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) { |
0b1adaa0 | 955 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 956 | chip_bus_sync_unlock(desc); |
0b1adaa0 TG |
957 | cpu_relax(); |
958 | goto again; | |
959 | } | |
960 | ||
b5faba21 TG |
961 | /* |
962 | * Now check again, whether the thread should run. Otherwise | |
963 | * we would clear the threads_oneshot bit of this thread which | |
964 | * was just set. | |
965 | */ | |
f3f79e38 | 966 | if (test_bit(IRQTF_RUNTHREAD, &action->thread_flags)) |
b5faba21 TG |
967 | goto out_unlock; |
968 | ||
969 | desc->threads_oneshot &= ~action->thread_mask; | |
970 | ||
32f4125e TG |
971 | if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && |
972 | irqd_irq_masked(&desc->irq_data)) | |
328a4978 | 973 | unmask_threaded_irq(desc); |
32f4125e | 974 | |
b5faba21 | 975 | out_unlock: |
239007b8 | 976 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 977 | chip_bus_sync_unlock(desc); |
b25c340c TG |
978 | } |
979 | ||
61f38261 | 980 | #ifdef CONFIG_SMP |
591d2fb0 | 981 | /* |
b04c644e | 982 | * Check whether we need to change the affinity of the interrupt thread. |
591d2fb0 TG |
983 | */ |
984 | static void | |
985 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) | |
986 | { | |
987 | cpumask_var_t mask; | |
04aa530e | 988 | bool valid = true; |
591d2fb0 TG |
989 | |
990 | if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags)) | |
991 | return; | |
992 | ||
993 | /* | |
994 | * In case we are out of memory we set IRQTF_AFFINITY again and | |
995 | * try again next time | |
996 | */ | |
997 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { | |
998 | set_bit(IRQTF_AFFINITY, &action->thread_flags); | |
999 | return; | |
1000 | } | |
1001 | ||
239007b8 | 1002 | raw_spin_lock_irq(&desc->lock); |
04aa530e TG |
1003 | /* |
1004 | * This code is triggered unconditionally. Check the affinity | |
1005 | * mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out. | |
1006 | */ | |
cbf86999 TG |
1007 | if (cpumask_available(desc->irq_common_data.affinity)) { |
1008 | const struct cpumask *m; | |
1009 | ||
1010 | m = irq_data_get_effective_affinity_mask(&desc->irq_data); | |
1011 | cpumask_copy(mask, m); | |
1012 | } else { | |
04aa530e | 1013 | valid = false; |
cbf86999 | 1014 | } |
239007b8 | 1015 | raw_spin_unlock_irq(&desc->lock); |
591d2fb0 | 1016 | |
04aa530e TG |
1017 | if (valid) |
1018 | set_cpus_allowed_ptr(current, mask); | |
591d2fb0 TG |
1019 | free_cpumask_var(mask); |
1020 | } | |
61f38261 BP |
1021 | #else |
1022 | static inline void | |
1023 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { } | |
1024 | #endif | |
591d2fb0 | 1025 | |
8d32a307 | 1026 | /* |
c5f48c0a | 1027 | * Interrupts which are not explicitly requested as threaded |
8d32a307 TG |
1028 | * interrupts rely on the implicit bh/preempt disable of the hard irq |
1029 | * context. So we need to disable bh here to avoid deadlocks and other | |
1030 | * side effects. | |
1031 | */ | |
3a43e05f | 1032 | static irqreturn_t |
8d32a307 TG |
1033 | irq_forced_thread_fn(struct irq_desc *desc, struct irqaction *action) |
1034 | { | |
3a43e05f SAS |
1035 | irqreturn_t ret; |
1036 | ||
8d32a307 | 1037 | local_bh_disable(); |
3a43e05f | 1038 | ret = action->thread_fn(action->irq, action->dev_id); |
746a923b LW |
1039 | if (ret == IRQ_HANDLED) |
1040 | atomic_inc(&desc->threads_handled); | |
1041 | ||
f3f79e38 | 1042 | irq_finalize_oneshot(desc, action); |
8d32a307 | 1043 | local_bh_enable(); |
3a43e05f | 1044 | return ret; |
8d32a307 TG |
1045 | } |
1046 | ||
1047 | /* | |
f788e7bf | 1048 | * Interrupts explicitly requested as threaded interrupts want to be |
8d32a307 TG |
1049 | * preemtible - many of them need to sleep and wait for slow busses to |
1050 | * complete. | |
1051 | */ | |
3a43e05f SAS |
1052 | static irqreturn_t irq_thread_fn(struct irq_desc *desc, |
1053 | struct irqaction *action) | |
8d32a307 | 1054 | { |
3a43e05f SAS |
1055 | irqreturn_t ret; |
1056 | ||
1057 | ret = action->thread_fn(action->irq, action->dev_id); | |
746a923b LW |
1058 | if (ret == IRQ_HANDLED) |
1059 | atomic_inc(&desc->threads_handled); | |
1060 | ||
f3f79e38 | 1061 | irq_finalize_oneshot(desc, action); |
3a43e05f | 1062 | return ret; |
8d32a307 TG |
1063 | } |
1064 | ||
7140ea19 IY |
1065 | static void wake_threads_waitq(struct irq_desc *desc) |
1066 | { | |
c685689f | 1067 | if (atomic_dec_and_test(&desc->threads_active)) |
7140ea19 IY |
1068 | wake_up(&desc->wait_for_threads); |
1069 | } | |
1070 | ||
67d12145 | 1071 | static void irq_thread_dtor(struct callback_head *unused) |
4d1d61a6 ON |
1072 | { |
1073 | struct task_struct *tsk = current; | |
1074 | struct irq_desc *desc; | |
1075 | struct irqaction *action; | |
1076 | ||
1077 | if (WARN_ON_ONCE(!(current->flags & PF_EXITING))) | |
1078 | return; | |
1079 | ||
1080 | action = kthread_data(tsk); | |
1081 | ||
fb21affa | 1082 | pr_err("exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n", |
19af395d | 1083 | tsk->comm, tsk->pid, action->irq); |
4d1d61a6 ON |
1084 | |
1085 | ||
1086 | desc = irq_to_desc(action->irq); | |
1087 | /* | |
1088 | * If IRQTF_RUNTHREAD is set, we need to decrement | |
1089 | * desc->threads_active and wake possible waiters. | |
1090 | */ | |
1091 | if (test_and_clear_bit(IRQTF_RUNTHREAD, &action->thread_flags)) | |
1092 | wake_threads_waitq(desc); | |
1093 | ||
1094 | /* Prevent a stale desc->threads_oneshot */ | |
1095 | irq_finalize_oneshot(desc, action); | |
1096 | } | |
1097 | ||
2a1d3ab8 TG |
1098 | static void irq_wake_secondary(struct irq_desc *desc, struct irqaction *action) |
1099 | { | |
1100 | struct irqaction *secondary = action->secondary; | |
1101 | ||
1102 | if (WARN_ON_ONCE(!secondary)) | |
1103 | return; | |
1104 | ||
1105 | raw_spin_lock_irq(&desc->lock); | |
1106 | __irq_wake_thread(desc, secondary); | |
1107 | raw_spin_unlock_irq(&desc->lock); | |
1108 | } | |
1109 | ||
3aa551c9 TG |
1110 | /* |
1111 | * Interrupt handler thread | |
1112 | */ | |
1113 | static int irq_thread(void *data) | |
1114 | { | |
67d12145 | 1115 | struct callback_head on_exit_work; |
3aa551c9 TG |
1116 | struct irqaction *action = data; |
1117 | struct irq_desc *desc = irq_to_desc(action->irq); | |
3a43e05f SAS |
1118 | irqreturn_t (*handler_fn)(struct irq_desc *desc, |
1119 | struct irqaction *action); | |
3aa551c9 | 1120 | |
540b60e2 | 1121 | if (force_irqthreads && test_bit(IRQTF_FORCED_THREAD, |
8d32a307 TG |
1122 | &action->thread_flags)) |
1123 | handler_fn = irq_forced_thread_fn; | |
1124 | else | |
1125 | handler_fn = irq_thread_fn; | |
1126 | ||
41f9d29f | 1127 | init_task_work(&on_exit_work, irq_thread_dtor); |
4d1d61a6 | 1128 | task_work_add(current, &on_exit_work, false); |
3aa551c9 | 1129 | |
f3de44ed SM |
1130 | irq_thread_check_affinity(desc, action); |
1131 | ||
3aa551c9 | 1132 | while (!irq_wait_for_interrupt(action)) { |
7140ea19 | 1133 | irqreturn_t action_ret; |
3aa551c9 | 1134 | |
591d2fb0 TG |
1135 | irq_thread_check_affinity(desc, action); |
1136 | ||
7140ea19 | 1137 | action_ret = handler_fn(desc, action); |
2a1d3ab8 TG |
1138 | if (action_ret == IRQ_WAKE_THREAD) |
1139 | irq_wake_secondary(desc, action); | |
3aa551c9 | 1140 | |
7140ea19 | 1141 | wake_threads_waitq(desc); |
3aa551c9 TG |
1142 | } |
1143 | ||
7140ea19 IY |
1144 | /* |
1145 | * This is the regular exit path. __free_irq() is stopping the | |
1146 | * thread via kthread_stop() after calling | |
519cc865 | 1147 | * synchronize_hardirq(). So neither IRQTF_RUNTHREAD nor the |
836557bd | 1148 | * oneshot mask bit can be set. |
3aa551c9 | 1149 | */ |
4d1d61a6 | 1150 | task_work_cancel(current, irq_thread_dtor); |
3aa551c9 TG |
1151 | return 0; |
1152 | } | |
1153 | ||
a92444c6 TG |
1154 | /** |
1155 | * irq_wake_thread - wake the irq thread for the action identified by dev_id | |
1156 | * @irq: Interrupt line | |
1157 | * @dev_id: Device identity for which the thread should be woken | |
1158 | * | |
1159 | */ | |
1160 | void irq_wake_thread(unsigned int irq, void *dev_id) | |
1161 | { | |
1162 | struct irq_desc *desc = irq_to_desc(irq); | |
1163 | struct irqaction *action; | |
1164 | unsigned long flags; | |
1165 | ||
1166 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
1167 | return; | |
1168 | ||
1169 | raw_spin_lock_irqsave(&desc->lock, flags); | |
f944b5a7 | 1170 | for_each_action_of_desc(desc, action) { |
a92444c6 TG |
1171 | if (action->dev_id == dev_id) { |
1172 | if (action->thread) | |
1173 | __irq_wake_thread(desc, action); | |
1174 | break; | |
1175 | } | |
1176 | } | |
1177 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1178 | } | |
1179 | EXPORT_SYMBOL_GPL(irq_wake_thread); | |
1180 | ||
2a1d3ab8 | 1181 | static int irq_setup_forced_threading(struct irqaction *new) |
8d32a307 TG |
1182 | { |
1183 | if (!force_irqthreads) | |
2a1d3ab8 | 1184 | return 0; |
8d32a307 | 1185 | if (new->flags & (IRQF_NO_THREAD | IRQF_PERCPU | IRQF_ONESHOT)) |
2a1d3ab8 | 1186 | return 0; |
8d32a307 | 1187 | |
d1f0301b TG |
1188 | /* |
1189 | * No further action required for interrupts which are requested as | |
1190 | * threaded interrupts already | |
1191 | */ | |
1192 | if (new->handler == irq_default_primary_handler) | |
1193 | return 0; | |
1194 | ||
8d32a307 TG |
1195 | new->flags |= IRQF_ONESHOT; |
1196 | ||
2a1d3ab8 TG |
1197 | /* |
1198 | * Handle the case where we have a real primary handler and a | |
1199 | * thread handler. We force thread them as well by creating a | |
1200 | * secondary action. | |
1201 | */ | |
d1f0301b | 1202 | if (new->handler && new->thread_fn) { |
2a1d3ab8 TG |
1203 | /* Allocate the secondary action */ |
1204 | new->secondary = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
1205 | if (!new->secondary) | |
1206 | return -ENOMEM; | |
1207 | new->secondary->handler = irq_forced_secondary_handler; | |
1208 | new->secondary->thread_fn = new->thread_fn; | |
1209 | new->secondary->dev_id = new->dev_id; | |
1210 | new->secondary->irq = new->irq; | |
1211 | new->secondary->name = new->name; | |
8d32a307 | 1212 | } |
2a1d3ab8 TG |
1213 | /* Deal with the primary handler */ |
1214 | set_bit(IRQTF_FORCED_THREAD, &new->thread_flags); | |
1215 | new->thread_fn = new->handler; | |
1216 | new->handler = irq_default_primary_handler; | |
1217 | return 0; | |
8d32a307 TG |
1218 | } |
1219 | ||
c1bacbae TG |
1220 | static int irq_request_resources(struct irq_desc *desc) |
1221 | { | |
1222 | struct irq_data *d = &desc->irq_data; | |
1223 | struct irq_chip *c = d->chip; | |
1224 | ||
1225 | return c->irq_request_resources ? c->irq_request_resources(d) : 0; | |
1226 | } | |
1227 | ||
1228 | static void irq_release_resources(struct irq_desc *desc) | |
1229 | { | |
1230 | struct irq_data *d = &desc->irq_data; | |
1231 | struct irq_chip *c = d->chip; | |
1232 | ||
1233 | if (c->irq_release_resources) | |
1234 | c->irq_release_resources(d); | |
1235 | } | |
1236 | ||
b525903c JT |
1237 | static bool irq_supports_nmi(struct irq_desc *desc) |
1238 | { | |
1239 | struct irq_data *d = irq_desc_get_irq_data(desc); | |
1240 | ||
1241 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
1242 | /* Only IRQs directly managed by the root irqchip can be set as NMI */ | |
1243 | if (d->parent_data) | |
1244 | return false; | |
1245 | #endif | |
1246 | /* Don't support NMIs for chips behind a slow bus */ | |
1247 | if (d->chip->irq_bus_lock || d->chip->irq_bus_sync_unlock) | |
1248 | return false; | |
1249 | ||
1250 | return d->chip->flags & IRQCHIP_SUPPORTS_NMI; | |
1251 | } | |
1252 | ||
1253 | static int irq_nmi_setup(struct irq_desc *desc) | |
1254 | { | |
1255 | struct irq_data *d = irq_desc_get_irq_data(desc); | |
1256 | struct irq_chip *c = d->chip; | |
1257 | ||
1258 | return c->irq_nmi_setup ? c->irq_nmi_setup(d) : -EINVAL; | |
1259 | } | |
1260 | ||
1261 | static void irq_nmi_teardown(struct irq_desc *desc) | |
1262 | { | |
1263 | struct irq_data *d = irq_desc_get_irq_data(desc); | |
1264 | struct irq_chip *c = d->chip; | |
1265 | ||
1266 | if (c->irq_nmi_teardown) | |
1267 | c->irq_nmi_teardown(d); | |
1268 | } | |
1269 | ||
2a1d3ab8 TG |
1270 | static int |
1271 | setup_irq_thread(struct irqaction *new, unsigned int irq, bool secondary) | |
1272 | { | |
1273 | struct task_struct *t; | |
1274 | struct sched_param param = { | |
1275 | .sched_priority = MAX_USER_RT_PRIO/2, | |
1276 | }; | |
1277 | ||
1278 | if (!secondary) { | |
1279 | t = kthread_create(irq_thread, new, "irq/%d-%s", irq, | |
1280 | new->name); | |
1281 | } else { | |
1282 | t = kthread_create(irq_thread, new, "irq/%d-s-%s", irq, | |
1283 | new->name); | |
1284 | param.sched_priority -= 1; | |
1285 | } | |
1286 | ||
1287 | if (IS_ERR(t)) | |
1288 | return PTR_ERR(t); | |
1289 | ||
1290 | sched_setscheduler_nocheck(t, SCHED_FIFO, ¶m); | |
1291 | ||
1292 | /* | |
1293 | * We keep the reference to the task struct even if | |
1294 | * the thread dies to avoid that the interrupt code | |
1295 | * references an already freed task_struct. | |
1296 | */ | |
7b3c92b8 | 1297 | new->thread = get_task_struct(t); |
2a1d3ab8 TG |
1298 | /* |
1299 | * Tell the thread to set its affinity. This is | |
1300 | * important for shared interrupt handlers as we do | |
1301 | * not invoke setup_affinity() for the secondary | |
1302 | * handlers as everything is already set up. Even for | |
1303 | * interrupts marked with IRQF_NO_BALANCE this is | |
1304 | * correct as we want the thread to move to the cpu(s) | |
1305 | * on which the requesting code placed the interrupt. | |
1306 | */ | |
1307 | set_bit(IRQTF_AFFINITY, &new->thread_flags); | |
1308 | return 0; | |
1309 | } | |
1310 | ||
1da177e4 LT |
1311 | /* |
1312 | * Internal function to register an irqaction - typically used to | |
1313 | * allocate special interrupts that are part of the architecture. | |
19d39a38 TG |
1314 | * |
1315 | * Locking rules: | |
1316 | * | |
1317 | * desc->request_mutex Provides serialization against a concurrent free_irq() | |
1318 | * chip_bus_lock Provides serialization for slow bus operations | |
1319 | * desc->lock Provides serialization against hard interrupts | |
1320 | * | |
1321 | * chip_bus_lock and desc->lock are sufficient for all other management and | |
1322 | * interrupt related functions. desc->request_mutex solely serializes | |
1323 | * request/free_irq(). | |
1da177e4 | 1324 | */ |
d3c60047 | 1325 | static int |
327ec569 | 1326 | __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) |
1da177e4 | 1327 | { |
f17c7545 | 1328 | struct irqaction *old, **old_ptr; |
b5faba21 | 1329 | unsigned long flags, thread_mask = 0; |
3b8249e7 | 1330 | int ret, nested, shared = 0; |
1da177e4 | 1331 | |
7d94f7ca | 1332 | if (!desc) |
c2b5a251 MW |
1333 | return -EINVAL; |
1334 | ||
6b8ff312 | 1335 | if (desc->irq_data.chip == &no_irq_chip) |
1da177e4 | 1336 | return -ENOSYS; |
b6873807 SAS |
1337 | if (!try_module_get(desc->owner)) |
1338 | return -ENODEV; | |
1da177e4 | 1339 | |
2a1d3ab8 TG |
1340 | new->irq = irq; |
1341 | ||
4b357dae JH |
1342 | /* |
1343 | * If the trigger type is not specified by the caller, | |
1344 | * then use the default for this interrupt. | |
1345 | */ | |
1346 | if (!(new->flags & IRQF_TRIGGER_MASK)) | |
1347 | new->flags |= irqd_get_trigger_type(&desc->irq_data); | |
1348 | ||
3aa551c9 | 1349 | /* |
399b5da2 TG |
1350 | * Check whether the interrupt nests into another interrupt |
1351 | * thread. | |
1352 | */ | |
1ccb4e61 | 1353 | nested = irq_settings_is_nested_thread(desc); |
399b5da2 | 1354 | if (nested) { |
b6873807 SAS |
1355 | if (!new->thread_fn) { |
1356 | ret = -EINVAL; | |
1357 | goto out_mput; | |
1358 | } | |
399b5da2 TG |
1359 | /* |
1360 | * Replace the primary handler which was provided from | |
1361 | * the driver for non nested interrupt handling by the | |
1362 | * dummy function which warns when called. | |
1363 | */ | |
1364 | new->handler = irq_nested_primary_handler; | |
8d32a307 | 1365 | } else { |
2a1d3ab8 TG |
1366 | if (irq_settings_can_thread(desc)) { |
1367 | ret = irq_setup_forced_threading(new); | |
1368 | if (ret) | |
1369 | goto out_mput; | |
1370 | } | |
399b5da2 TG |
1371 | } |
1372 | ||
3aa551c9 | 1373 | /* |
399b5da2 TG |
1374 | * Create a handler thread when a thread function is supplied |
1375 | * and the interrupt does not nest into another interrupt | |
1376 | * thread. | |
3aa551c9 | 1377 | */ |
399b5da2 | 1378 | if (new->thread_fn && !nested) { |
2a1d3ab8 TG |
1379 | ret = setup_irq_thread(new, irq, false); |
1380 | if (ret) | |
b6873807 | 1381 | goto out_mput; |
2a1d3ab8 TG |
1382 | if (new->secondary) { |
1383 | ret = setup_irq_thread(new->secondary, irq, true); | |
1384 | if (ret) | |
1385 | goto out_thread; | |
b6873807 | 1386 | } |
3aa551c9 TG |
1387 | } |
1388 | ||
dc9b229a TG |
1389 | /* |
1390 | * Drivers are often written to work w/o knowledge about the | |
1391 | * underlying irq chip implementation, so a request for a | |
1392 | * threaded irq without a primary hard irq context handler | |
1393 | * requires the ONESHOT flag to be set. Some irq chips like | |
1394 | * MSI based interrupts are per se one shot safe. Check the | |
1395 | * chip flags, so we can avoid the unmask dance at the end of | |
1396 | * the threaded handler for those. | |
1397 | */ | |
1398 | if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE) | |
1399 | new->flags &= ~IRQF_ONESHOT; | |
1400 | ||
19d39a38 TG |
1401 | /* |
1402 | * Protects against a concurrent __free_irq() call which might wait | |
519cc865 | 1403 | * for synchronize_hardirq() to complete without holding the optional |
836557bd LW |
1404 | * chip bus lock and desc->lock. Also protects against handing out |
1405 | * a recycled oneshot thread_mask bit while it's still in use by | |
1406 | * its previous owner. | |
19d39a38 | 1407 | */ |
9114014c | 1408 | mutex_lock(&desc->request_mutex); |
19d39a38 TG |
1409 | |
1410 | /* | |
1411 | * Acquire bus lock as the irq_request_resources() callback below | |
1412 | * might rely on the serialization or the magic power management | |
1413 | * functions which are abusing the irq_bus_lock() callback, | |
1414 | */ | |
1415 | chip_bus_lock(desc); | |
1416 | ||
1417 | /* First installed action requests resources. */ | |
46e48e25 TG |
1418 | if (!desc->action) { |
1419 | ret = irq_request_resources(desc); | |
1420 | if (ret) { | |
1421 | pr_err("Failed to request resources for %s (irq %d) on irqchip %s\n", | |
1422 | new->name, irq, desc->irq_data.chip->name); | |
19d39a38 | 1423 | goto out_bus_unlock; |
46e48e25 TG |
1424 | } |
1425 | } | |
9114014c | 1426 | |
1da177e4 LT |
1427 | /* |
1428 | * The following block of code has to be executed atomically | |
19d39a38 TG |
1429 | * protected against a concurrent interrupt and any of the other |
1430 | * management calls which are not serialized via | |
1431 | * desc->request_mutex or the optional bus lock. | |
1da177e4 | 1432 | */ |
239007b8 | 1433 | raw_spin_lock_irqsave(&desc->lock, flags); |
f17c7545 IM |
1434 | old_ptr = &desc->action; |
1435 | old = *old_ptr; | |
06fcb0c6 | 1436 | if (old) { |
e76de9f8 TG |
1437 | /* |
1438 | * Can't share interrupts unless both agree to and are | |
1439 | * the same type (level, edge, polarity). So both flag | |
3cca53b0 | 1440 | * fields must have IRQF_SHARED set and the bits which |
9d591edd TG |
1441 | * set the trigger type must match. Also all must |
1442 | * agree on ONESHOT. | |
b525903c | 1443 | * Interrupt lines used for NMIs cannot be shared. |
e76de9f8 | 1444 | */ |
4f8413a3 MZ |
1445 | unsigned int oldtype; |
1446 | ||
b525903c JT |
1447 | if (desc->istate & IRQS_NMI) { |
1448 | pr_err("Invalid attempt to share NMI for %s (irq %d) on irqchip %s.\n", | |
1449 | new->name, irq, desc->irq_data.chip->name); | |
1450 | ret = -EINVAL; | |
1451 | goto out_unlock; | |
1452 | } | |
1453 | ||
4f8413a3 MZ |
1454 | /* |
1455 | * If nobody did set the configuration before, inherit | |
1456 | * the one provided by the requester. | |
1457 | */ | |
1458 | if (irqd_trigger_type_was_set(&desc->irq_data)) { | |
1459 | oldtype = irqd_get_trigger_type(&desc->irq_data); | |
1460 | } else { | |
1461 | oldtype = new->flags & IRQF_TRIGGER_MASK; | |
1462 | irqd_set_trigger_type(&desc->irq_data, oldtype); | |
1463 | } | |
382bd4de | 1464 | |
3cca53b0 | 1465 | if (!((old->flags & new->flags) & IRQF_SHARED) || |
382bd4de | 1466 | (oldtype != (new->flags & IRQF_TRIGGER_MASK)) || |
f5d89470 | 1467 | ((old->flags ^ new->flags) & IRQF_ONESHOT)) |
f5163427 DS |
1468 | goto mismatch; |
1469 | ||
f5163427 | 1470 | /* All handlers must agree on per-cpuness */ |
3cca53b0 TG |
1471 | if ((old->flags & IRQF_PERCPU) != |
1472 | (new->flags & IRQF_PERCPU)) | |
f5163427 | 1473 | goto mismatch; |
1da177e4 LT |
1474 | |
1475 | /* add new interrupt at end of irq queue */ | |
1476 | do { | |
52abb700 TG |
1477 | /* |
1478 | * Or all existing action->thread_mask bits, | |
1479 | * so we can find the next zero bit for this | |
1480 | * new action. | |
1481 | */ | |
b5faba21 | 1482 | thread_mask |= old->thread_mask; |
f17c7545 IM |
1483 | old_ptr = &old->next; |
1484 | old = *old_ptr; | |
1da177e4 LT |
1485 | } while (old); |
1486 | shared = 1; | |
1487 | } | |
1488 | ||
b5faba21 | 1489 | /* |
52abb700 TG |
1490 | * Setup the thread mask for this irqaction for ONESHOT. For |
1491 | * !ONESHOT irqs the thread mask is 0 so we can avoid a | |
1492 | * conditional in irq_wake_thread(). | |
b5faba21 | 1493 | */ |
52abb700 TG |
1494 | if (new->flags & IRQF_ONESHOT) { |
1495 | /* | |
1496 | * Unlikely to have 32 resp 64 irqs sharing one line, | |
1497 | * but who knows. | |
1498 | */ | |
1499 | if (thread_mask == ~0UL) { | |
1500 | ret = -EBUSY; | |
cba4235e | 1501 | goto out_unlock; |
52abb700 TG |
1502 | } |
1503 | /* | |
1504 | * The thread_mask for the action is or'ed to | |
1505 | * desc->thread_active to indicate that the | |
1506 | * IRQF_ONESHOT thread handler has been woken, but not | |
1507 | * yet finished. The bit is cleared when a thread | |
1508 | * completes. When all threads of a shared interrupt | |
1509 | * line have completed desc->threads_active becomes | |
1510 | * zero and the interrupt line is unmasked. See | |
1511 | * handle.c:irq_wake_thread() for further information. | |
1512 | * | |
1513 | * If no thread is woken by primary (hard irq context) | |
1514 | * interrupt handlers, then desc->threads_active is | |
1515 | * also checked for zero to unmask the irq line in the | |
1516 | * affected hard irq flow handlers | |
1517 | * (handle_[fasteoi|level]_irq). | |
1518 | * | |
1519 | * The new action gets the first zero bit of | |
1520 | * thread_mask assigned. See the loop above which or's | |
1521 | * all existing action->thread_mask bits. | |
1522 | */ | |
ffc661c9 | 1523 | new->thread_mask = 1UL << ffz(thread_mask); |
1c6c6952 | 1524 | |
dc9b229a TG |
1525 | } else if (new->handler == irq_default_primary_handler && |
1526 | !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) { | |
1c6c6952 TG |
1527 | /* |
1528 | * The interrupt was requested with handler = NULL, so | |
1529 | * we use the default primary handler for it. But it | |
1530 | * does not have the oneshot flag set. In combination | |
1531 | * with level interrupts this is deadly, because the | |
1532 | * default primary handler just wakes the thread, then | |
1533 | * the irq lines is reenabled, but the device still | |
1534 | * has the level irq asserted. Rinse and repeat.... | |
1535 | * | |
1536 | * While this works for edge type interrupts, we play | |
1537 | * it safe and reject unconditionally because we can't | |
1538 | * say for sure which type this interrupt really | |
1539 | * has. The type flags are unreliable as the | |
1540 | * underlying chip implementation can override them. | |
1541 | */ | |
025af39b LC |
1542 | pr_err("Threaded irq requested with handler=NULL and !ONESHOT for %s (irq %d)\n", |
1543 | new->name, irq); | |
1c6c6952 | 1544 | ret = -EINVAL; |
cba4235e | 1545 | goto out_unlock; |
b5faba21 | 1546 | } |
b5faba21 | 1547 | |
1da177e4 | 1548 | if (!shared) { |
3aa551c9 TG |
1549 | init_waitqueue_head(&desc->wait_for_threads); |
1550 | ||
e76de9f8 | 1551 | /* Setup the type (level, edge polarity) if configured: */ |
3cca53b0 | 1552 | if (new->flags & IRQF_TRIGGER_MASK) { |
a1ff541a JL |
1553 | ret = __irq_set_trigger(desc, |
1554 | new->flags & IRQF_TRIGGER_MASK); | |
82736f4d | 1555 | |
19d39a38 | 1556 | if (ret) |
cba4235e | 1557 | goto out_unlock; |
091738a2 | 1558 | } |
6a6de9ef | 1559 | |
c942cee4 TG |
1560 | /* |
1561 | * Activate the interrupt. That activation must happen | |
1562 | * independently of IRQ_NOAUTOEN. request_irq() can fail | |
1563 | * and the callers are supposed to handle | |
1564 | * that. enable_irq() of an interrupt requested with | |
1565 | * IRQ_NOAUTOEN is not supposed to fail. The activation | |
1566 | * keeps it in shutdown mode, it merily associates | |
1567 | * resources if necessary and if that's not possible it | |
1568 | * fails. Interrupts which are in managed shutdown mode | |
1569 | * will simply ignore that activation request. | |
1570 | */ | |
1571 | ret = irq_activate(desc); | |
1572 | if (ret) | |
1573 | goto out_unlock; | |
1574 | ||
009b4c3b | 1575 | desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \ |
32f4125e TG |
1576 | IRQS_ONESHOT | IRQS_WAITING); |
1577 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
94d39e1f | 1578 | |
a005677b TG |
1579 | if (new->flags & IRQF_PERCPU) { |
1580 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
1581 | irq_settings_set_per_cpu(desc); | |
1582 | } | |
6a58fb3b | 1583 | |
b25c340c | 1584 | if (new->flags & IRQF_ONESHOT) |
3d67baec | 1585 | desc->istate |= IRQS_ONESHOT; |
b25c340c | 1586 | |
2e051552 TG |
1587 | /* Exclude IRQ from balancing if requested */ |
1588 | if (new->flags & IRQF_NOBALANCING) { | |
1589 | irq_settings_set_no_balancing(desc); | |
1590 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
1591 | } | |
1592 | ||
04c848d3 | 1593 | if (irq_settings_can_autoenable(desc)) { |
4cde9c6b | 1594 | irq_startup(desc, IRQ_RESEND, IRQ_START_COND); |
04c848d3 TG |
1595 | } else { |
1596 | /* | |
1597 | * Shared interrupts do not go well with disabling | |
1598 | * auto enable. The sharing interrupt might request | |
1599 | * it while it's still disabled and then wait for | |
1600 | * interrupts forever. | |
1601 | */ | |
1602 | WARN_ON_ONCE(new->flags & IRQF_SHARED); | |
e76de9f8 TG |
1603 | /* Undo nested disables: */ |
1604 | desc->depth = 1; | |
04c848d3 | 1605 | } |
18404756 | 1606 | |
876dbd4c TG |
1607 | } else if (new->flags & IRQF_TRIGGER_MASK) { |
1608 | unsigned int nmsk = new->flags & IRQF_TRIGGER_MASK; | |
7ee7e87d | 1609 | unsigned int omsk = irqd_get_trigger_type(&desc->irq_data); |
876dbd4c TG |
1610 | |
1611 | if (nmsk != omsk) | |
1612 | /* hope the handler works with current trigger mode */ | |
a395d6a7 | 1613 | pr_warn("irq %d uses trigger mode %u; requested %u\n", |
7ee7e87d | 1614 | irq, omsk, nmsk); |
1da177e4 | 1615 | } |
82736f4d | 1616 | |
f17c7545 | 1617 | *old_ptr = new; |
82736f4d | 1618 | |
cab303be TG |
1619 | irq_pm_install_action(desc, new); |
1620 | ||
8528b0f1 LT |
1621 | /* Reset broken irq detection when installing new handler */ |
1622 | desc->irq_count = 0; | |
1623 | desc->irqs_unhandled = 0; | |
1adb0850 TG |
1624 | |
1625 | /* | |
1626 | * Check whether we disabled the irq via the spurious handler | |
1627 | * before. Reenable it and give it another chance. | |
1628 | */ | |
7acdd53e TG |
1629 | if (shared && (desc->istate & IRQS_SPURIOUS_DISABLED)) { |
1630 | desc->istate &= ~IRQS_SPURIOUS_DISABLED; | |
79ff1cda | 1631 | __enable_irq(desc); |
1adb0850 TG |
1632 | } |
1633 | ||
239007b8 | 1634 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3a90795e | 1635 | chip_bus_sync_unlock(desc); |
9114014c | 1636 | mutex_unlock(&desc->request_mutex); |
1da177e4 | 1637 | |
b2d3d61a DL |
1638 | irq_setup_timings(desc, new); |
1639 | ||
69ab8494 TG |
1640 | /* |
1641 | * Strictly no need to wake it up, but hung_task complains | |
1642 | * when no hard interrupt wakes the thread up. | |
1643 | */ | |
1644 | if (new->thread) | |
1645 | wake_up_process(new->thread); | |
2a1d3ab8 TG |
1646 | if (new->secondary) |
1647 | wake_up_process(new->secondary->thread); | |
69ab8494 | 1648 | |
2c6927a3 | 1649 | register_irq_proc(irq, desc); |
1da177e4 LT |
1650 | new->dir = NULL; |
1651 | register_handler_proc(irq, new); | |
1da177e4 | 1652 | return 0; |
f5163427 DS |
1653 | |
1654 | mismatch: | |
3cca53b0 | 1655 | if (!(new->flags & IRQF_PROBE_SHARED)) { |
97fd75b7 | 1656 | pr_err("Flags mismatch irq %d. %08x (%s) vs. %08x (%s)\n", |
f5d89470 TG |
1657 | irq, new->flags, new->name, old->flags, old->name); |
1658 | #ifdef CONFIG_DEBUG_SHIRQ | |
13e87ec6 | 1659 | dump_stack(); |
3f050447 | 1660 | #endif |
f5d89470 | 1661 | } |
3aa551c9 TG |
1662 | ret = -EBUSY; |
1663 | ||
cba4235e | 1664 | out_unlock: |
1c389795 | 1665 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3b8249e7 | 1666 | |
46e48e25 TG |
1667 | if (!desc->action) |
1668 | irq_release_resources(desc); | |
19d39a38 TG |
1669 | out_bus_unlock: |
1670 | chip_bus_sync_unlock(desc); | |
9114014c TG |
1671 | mutex_unlock(&desc->request_mutex); |
1672 | ||
3aa551c9 | 1673 | out_thread: |
3aa551c9 TG |
1674 | if (new->thread) { |
1675 | struct task_struct *t = new->thread; | |
1676 | ||
1677 | new->thread = NULL; | |
05d74efa | 1678 | kthread_stop(t); |
3aa551c9 TG |
1679 | put_task_struct(t); |
1680 | } | |
2a1d3ab8 TG |
1681 | if (new->secondary && new->secondary->thread) { |
1682 | struct task_struct *t = new->secondary->thread; | |
1683 | ||
1684 | new->secondary->thread = NULL; | |
1685 | kthread_stop(t); | |
1686 | put_task_struct(t); | |
1687 | } | |
b6873807 SAS |
1688 | out_mput: |
1689 | module_put(desc->owner); | |
3aa551c9 | 1690 | return ret; |
1da177e4 LT |
1691 | } |
1692 | ||
31d9d9b6 | 1693 | /* |
cbf94f06 MD |
1694 | * Internal function to unregister an irqaction - used to free |
1695 | * regular and special interrupts that are part of the architecture. | |
1da177e4 | 1696 | */ |
83ac4ca9 | 1697 | static struct irqaction *__free_irq(struct irq_desc *desc, void *dev_id) |
1da177e4 | 1698 | { |
83ac4ca9 | 1699 | unsigned irq = desc->irq_data.irq; |
f17c7545 | 1700 | struct irqaction *action, **action_ptr; |
1da177e4 LT |
1701 | unsigned long flags; |
1702 | ||
ae88a23b | 1703 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); |
7d94f7ca | 1704 | |
9114014c | 1705 | mutex_lock(&desc->request_mutex); |
abc7e40c | 1706 | chip_bus_lock(desc); |
239007b8 | 1707 | raw_spin_lock_irqsave(&desc->lock, flags); |
ae88a23b IM |
1708 | |
1709 | /* | |
1710 | * There can be multiple actions per IRQ descriptor, find the right | |
1711 | * one based on the dev_id: | |
1712 | */ | |
f17c7545 | 1713 | action_ptr = &desc->action; |
1da177e4 | 1714 | for (;;) { |
f17c7545 | 1715 | action = *action_ptr; |
1da177e4 | 1716 | |
ae88a23b IM |
1717 | if (!action) { |
1718 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
239007b8 | 1719 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
abc7e40c | 1720 | chip_bus_sync_unlock(desc); |
19d39a38 | 1721 | mutex_unlock(&desc->request_mutex); |
f21cfb25 | 1722 | return NULL; |
ae88a23b | 1723 | } |
1da177e4 | 1724 | |
8316e381 IM |
1725 | if (action->dev_id == dev_id) |
1726 | break; | |
f17c7545 | 1727 | action_ptr = &action->next; |
ae88a23b | 1728 | } |
dbce706e | 1729 | |
ae88a23b | 1730 | /* Found it - now remove it from the list of entries: */ |
f17c7545 | 1731 | *action_ptr = action->next; |
ae88a23b | 1732 | |
cab303be TG |
1733 | irq_pm_remove_action(desc, action); |
1734 | ||
ae88a23b | 1735 | /* If this was the last handler, shut down the IRQ line: */ |
c1bacbae | 1736 | if (!desc->action) { |
e9849777 | 1737 | irq_settings_clr_disable_unlazy(desc); |
4001d8e8 | 1738 | /* Only shutdown. Deactivate after synchronize_hardirq() */ |
46999238 | 1739 | irq_shutdown(desc); |
c1bacbae | 1740 | } |
3aa551c9 | 1741 | |
e7a297b0 PWJ |
1742 | #ifdef CONFIG_SMP |
1743 | /* make sure affinity_hint is cleaned up */ | |
1744 | if (WARN_ON_ONCE(desc->affinity_hint)) | |
1745 | desc->affinity_hint = NULL; | |
1746 | #endif | |
1747 | ||
239007b8 | 1748 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
19d39a38 TG |
1749 | /* |
1750 | * Drop bus_lock here so the changes which were done in the chip | |
1751 | * callbacks above are synced out to the irq chips which hang | |
519cc865 | 1752 | * behind a slow bus (I2C, SPI) before calling synchronize_hardirq(). |
19d39a38 TG |
1753 | * |
1754 | * Aside of that the bus_lock can also be taken from the threaded | |
1755 | * handler in irq_finalize_oneshot() which results in a deadlock | |
519cc865 | 1756 | * because kthread_stop() would wait forever for the thread to |
19d39a38 TG |
1757 | * complete, which is blocked on the bus lock. |
1758 | * | |
1759 | * The still held desc->request_mutex() protects against a | |
1760 | * concurrent request_irq() of this irq so the release of resources | |
1761 | * and timing data is properly serialized. | |
1762 | */ | |
abc7e40c | 1763 | chip_bus_sync_unlock(desc); |
ae88a23b IM |
1764 | |
1765 | unregister_handler_proc(irq, action); | |
1766 | ||
62e04686 TG |
1767 | /* |
1768 | * Make sure it's not being used on another CPU and if the chip | |
1769 | * supports it also make sure that there is no (not yet serviced) | |
1770 | * interrupt in flight at the hardware level. | |
1771 | */ | |
1772 | __synchronize_hardirq(desc, true); | |
1da177e4 | 1773 | |
70edcd77 | 1774 | #ifdef CONFIG_DEBUG_SHIRQ |
ae88a23b IM |
1775 | /* |
1776 | * It's a shared IRQ -- the driver ought to be prepared for an IRQ | |
1777 | * event to happen even now it's being freed, so let's make sure that | |
1778 | * is so by doing an extra call to the handler .... | |
1779 | * | |
1780 | * ( We do this after actually deregistering it, to make sure that a | |
0a13ec0b | 1781 | * 'real' IRQ doesn't run in parallel with our fake. ) |
ae88a23b IM |
1782 | */ |
1783 | if (action->flags & IRQF_SHARED) { | |
1784 | local_irq_save(flags); | |
1785 | action->handler(irq, dev_id); | |
1786 | local_irq_restore(flags); | |
1da177e4 | 1787 | } |
ae88a23b | 1788 | #endif |
2d860ad7 | 1789 | |
519cc865 LW |
1790 | /* |
1791 | * The action has already been removed above, but the thread writes | |
1792 | * its oneshot mask bit when it completes. Though request_mutex is | |
1793 | * held across this which prevents __setup_irq() from handing out | |
1794 | * the same bit to a newly requested action. | |
1795 | */ | |
2d860ad7 | 1796 | if (action->thread) { |
05d74efa | 1797 | kthread_stop(action->thread); |
2d860ad7 | 1798 | put_task_struct(action->thread); |
2a1d3ab8 TG |
1799 | if (action->secondary && action->secondary->thread) { |
1800 | kthread_stop(action->secondary->thread); | |
1801 | put_task_struct(action->secondary->thread); | |
1802 | } | |
2d860ad7 LT |
1803 | } |
1804 | ||
19d39a38 | 1805 | /* Last action releases resources */ |
2343877f | 1806 | if (!desc->action) { |
19d39a38 TG |
1807 | /* |
1808 | * Reaquire bus lock as irq_release_resources() might | |
1809 | * require it to deallocate resources over the slow bus. | |
1810 | */ | |
1811 | chip_bus_lock(desc); | |
4001d8e8 TG |
1812 | /* |
1813 | * There is no interrupt on the fly anymore. Deactivate it | |
1814 | * completely. | |
1815 | */ | |
1816 | raw_spin_lock_irqsave(&desc->lock, flags); | |
1817 | irq_domain_deactivate_irq(&desc->irq_data); | |
1818 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1819 | ||
46e48e25 | 1820 | irq_release_resources(desc); |
19d39a38 | 1821 | chip_bus_sync_unlock(desc); |
2343877f TG |
1822 | irq_remove_timings(desc); |
1823 | } | |
46e48e25 | 1824 | |
9114014c TG |
1825 | mutex_unlock(&desc->request_mutex); |
1826 | ||
be45beb2 | 1827 | irq_chip_pm_put(&desc->irq_data); |
b6873807 | 1828 | module_put(desc->owner); |
2a1d3ab8 | 1829 | kfree(action->secondary); |
f21cfb25 MD |
1830 | return action; |
1831 | } | |
1832 | ||
1833 | /** | |
1834 | * free_irq - free an interrupt allocated with request_irq | |
1835 | * @irq: Interrupt line to free | |
1836 | * @dev_id: Device identity to free | |
1837 | * | |
1838 | * Remove an interrupt handler. The handler is removed and if the | |
1839 | * interrupt line is no longer in use by any driver it is disabled. | |
1840 | * On a shared IRQ the caller must ensure the interrupt is disabled | |
1841 | * on the card it drives before calling this function. The function | |
1842 | * does not return until any executing interrupts for this IRQ | |
1843 | * have completed. | |
1844 | * | |
1845 | * This function must not be called from interrupt context. | |
25ce4be7 CH |
1846 | * |
1847 | * Returns the devname argument passed to request_irq. | |
f21cfb25 | 1848 | */ |
25ce4be7 | 1849 | const void *free_irq(unsigned int irq, void *dev_id) |
f21cfb25 | 1850 | { |
70aedd24 | 1851 | struct irq_desc *desc = irq_to_desc(irq); |
25ce4be7 CH |
1852 | struct irqaction *action; |
1853 | const char *devname; | |
70aedd24 | 1854 | |
31d9d9b6 | 1855 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
25ce4be7 | 1856 | return NULL; |
70aedd24 | 1857 | |
cd7eab44 BH |
1858 | #ifdef CONFIG_SMP |
1859 | if (WARN_ON(desc->affinity_notify)) | |
1860 | desc->affinity_notify = NULL; | |
1861 | #endif | |
1862 | ||
83ac4ca9 | 1863 | action = __free_irq(desc, dev_id); |
2827a418 AM |
1864 | |
1865 | if (!action) | |
1866 | return NULL; | |
1867 | ||
25ce4be7 CH |
1868 | devname = action->name; |
1869 | kfree(action); | |
1870 | return devname; | |
1da177e4 | 1871 | } |
1da177e4 LT |
1872 | EXPORT_SYMBOL(free_irq); |
1873 | ||
b525903c JT |
1874 | /* This function must be called with desc->lock held */ |
1875 | static const void *__cleanup_nmi(unsigned int irq, struct irq_desc *desc) | |
1876 | { | |
1877 | const char *devname = NULL; | |
1878 | ||
1879 | desc->istate &= ~IRQS_NMI; | |
1880 | ||
1881 | if (!WARN_ON(desc->action == NULL)) { | |
1882 | irq_pm_remove_action(desc, desc->action); | |
1883 | devname = desc->action->name; | |
1884 | unregister_handler_proc(irq, desc->action); | |
1885 | ||
1886 | kfree(desc->action); | |
1887 | desc->action = NULL; | |
1888 | } | |
1889 | ||
1890 | irq_settings_clr_disable_unlazy(desc); | |
4001d8e8 | 1891 | irq_shutdown_and_deactivate(desc); |
b525903c JT |
1892 | |
1893 | irq_release_resources(desc); | |
1894 | ||
1895 | irq_chip_pm_put(&desc->irq_data); | |
1896 | module_put(desc->owner); | |
1897 | ||
1898 | return devname; | |
1899 | } | |
1900 | ||
1901 | const void *free_nmi(unsigned int irq, void *dev_id) | |
1902 | { | |
1903 | struct irq_desc *desc = irq_to_desc(irq); | |
1904 | unsigned long flags; | |
1905 | const void *devname; | |
1906 | ||
1907 | if (!desc || WARN_ON(!(desc->istate & IRQS_NMI))) | |
1908 | return NULL; | |
1909 | ||
1910 | if (WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
1911 | return NULL; | |
1912 | ||
1913 | /* NMI still enabled */ | |
1914 | if (WARN_ON(desc->depth == 0)) | |
1915 | disable_nmi_nosync(irq); | |
1916 | ||
1917 | raw_spin_lock_irqsave(&desc->lock, flags); | |
1918 | ||
1919 | irq_nmi_teardown(desc); | |
1920 | devname = __cleanup_nmi(irq, desc); | |
1921 | ||
1922 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1923 | ||
1924 | return devname; | |
1925 | } | |
1926 | ||
1da177e4 | 1927 | /** |
3aa551c9 | 1928 | * request_threaded_irq - allocate an interrupt line |
1da177e4 | 1929 | * @irq: Interrupt line to allocate |
3aa551c9 TG |
1930 | * @handler: Function to be called when the IRQ occurs. |
1931 | * Primary handler for threaded interrupts | |
b25c340c TG |
1932 | * If NULL and thread_fn != NULL the default |
1933 | * primary handler is installed | |
f48fe81e TG |
1934 | * @thread_fn: Function called from the irq handler thread |
1935 | * If NULL, no irq thread is created | |
1da177e4 LT |
1936 | * @irqflags: Interrupt type flags |
1937 | * @devname: An ascii name for the claiming device | |
1938 | * @dev_id: A cookie passed back to the handler function | |
1939 | * | |
1940 | * This call allocates interrupt resources and enables the | |
1941 | * interrupt line and IRQ handling. From the point this | |
1942 | * call is made your handler function may be invoked. Since | |
1943 | * your handler function must clear any interrupt the board | |
1944 | * raises, you must take care both to initialise your hardware | |
1945 | * and to set up the interrupt handler in the right order. | |
1946 | * | |
3aa551c9 | 1947 | * If you want to set up a threaded irq handler for your device |
6d21af4f | 1948 | * then you need to supply @handler and @thread_fn. @handler is |
3aa551c9 TG |
1949 | * still called in hard interrupt context and has to check |
1950 | * whether the interrupt originates from the device. If yes it | |
1951 | * needs to disable the interrupt on the device and return | |
39a2eddb | 1952 | * IRQ_WAKE_THREAD which will wake up the handler thread and run |
3aa551c9 TG |
1953 | * @thread_fn. This split handler design is necessary to support |
1954 | * shared interrupts. | |
1955 | * | |
1da177e4 LT |
1956 | * Dev_id must be globally unique. Normally the address of the |
1957 | * device data structure is used as the cookie. Since the handler | |
1958 | * receives this value it makes sense to use it. | |
1959 | * | |
1960 | * If your interrupt is shared you must pass a non NULL dev_id | |
1961 | * as this is required when freeing the interrupt. | |
1962 | * | |
1963 | * Flags: | |
1964 | * | |
3cca53b0 | 1965 | * IRQF_SHARED Interrupt is shared |
0c5d1eb7 | 1966 | * IRQF_TRIGGER_* Specify active edge(s) or level |
1da177e4 LT |
1967 | * |
1968 | */ | |
3aa551c9 TG |
1969 | int request_threaded_irq(unsigned int irq, irq_handler_t handler, |
1970 | irq_handler_t thread_fn, unsigned long irqflags, | |
1971 | const char *devname, void *dev_id) | |
1da177e4 | 1972 | { |
06fcb0c6 | 1973 | struct irqaction *action; |
08678b08 | 1974 | struct irq_desc *desc; |
d3c60047 | 1975 | int retval; |
1da177e4 | 1976 | |
e237a551 CF |
1977 | if (irq == IRQ_NOTCONNECTED) |
1978 | return -ENOTCONN; | |
1979 | ||
1da177e4 LT |
1980 | /* |
1981 | * Sanity-check: shared interrupts must pass in a real dev-ID, | |
1982 | * otherwise we'll have trouble later trying to figure out | |
1983 | * which interrupt is which (messes up the interrupt freeing | |
1984 | * logic etc). | |
17f48034 RW |
1985 | * |
1986 | * Also IRQF_COND_SUSPEND only makes sense for shared interrupts and | |
1987 | * it cannot be set along with IRQF_NO_SUSPEND. | |
1da177e4 | 1988 | */ |
17f48034 RW |
1989 | if (((irqflags & IRQF_SHARED) && !dev_id) || |
1990 | (!(irqflags & IRQF_SHARED) && (irqflags & IRQF_COND_SUSPEND)) || | |
1991 | ((irqflags & IRQF_NO_SUSPEND) && (irqflags & IRQF_COND_SUSPEND))) | |
1da177e4 | 1992 | return -EINVAL; |
7d94f7ca | 1993 | |
cb5bc832 | 1994 | desc = irq_to_desc(irq); |
7d94f7ca | 1995 | if (!desc) |
1da177e4 | 1996 | return -EINVAL; |
7d94f7ca | 1997 | |
31d9d9b6 MZ |
1998 | if (!irq_settings_can_request(desc) || |
1999 | WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
6550c775 | 2000 | return -EINVAL; |
b25c340c TG |
2001 | |
2002 | if (!handler) { | |
2003 | if (!thread_fn) | |
2004 | return -EINVAL; | |
2005 | handler = irq_default_primary_handler; | |
2006 | } | |
1da177e4 | 2007 | |
45535732 | 2008 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); |
1da177e4 LT |
2009 | if (!action) |
2010 | return -ENOMEM; | |
2011 | ||
2012 | action->handler = handler; | |
3aa551c9 | 2013 | action->thread_fn = thread_fn; |
1da177e4 | 2014 | action->flags = irqflags; |
1da177e4 | 2015 | action->name = devname; |
1da177e4 LT |
2016 | action->dev_id = dev_id; |
2017 | ||
be45beb2 | 2018 | retval = irq_chip_pm_get(&desc->irq_data); |
4396f46c SL |
2019 | if (retval < 0) { |
2020 | kfree(action); | |
be45beb2 | 2021 | return retval; |
4396f46c | 2022 | } |
be45beb2 | 2023 | |
d3c60047 | 2024 | retval = __setup_irq(irq, desc, action); |
70aedd24 | 2025 | |
2a1d3ab8 | 2026 | if (retval) { |
be45beb2 | 2027 | irq_chip_pm_put(&desc->irq_data); |
2a1d3ab8 | 2028 | kfree(action->secondary); |
377bf1e4 | 2029 | kfree(action); |
2a1d3ab8 | 2030 | } |
377bf1e4 | 2031 | |
6d83f94d | 2032 | #ifdef CONFIG_DEBUG_SHIRQ_FIXME |
6ce51c43 | 2033 | if (!retval && (irqflags & IRQF_SHARED)) { |
a304e1b8 DW |
2034 | /* |
2035 | * It's a shared IRQ -- the driver ought to be prepared for it | |
2036 | * to happen immediately, so let's make sure.... | |
377bf1e4 AV |
2037 | * We disable the irq to make sure that a 'real' IRQ doesn't |
2038 | * run in parallel with our fake. | |
a304e1b8 | 2039 | */ |
59845b1f | 2040 | unsigned long flags; |
a304e1b8 | 2041 | |
377bf1e4 | 2042 | disable_irq(irq); |
59845b1f | 2043 | local_irq_save(flags); |
377bf1e4 | 2044 | |
59845b1f | 2045 | handler(irq, dev_id); |
377bf1e4 | 2046 | |
59845b1f | 2047 | local_irq_restore(flags); |
377bf1e4 | 2048 | enable_irq(irq); |
a304e1b8 DW |
2049 | } |
2050 | #endif | |
1da177e4 LT |
2051 | return retval; |
2052 | } | |
3aa551c9 | 2053 | EXPORT_SYMBOL(request_threaded_irq); |
ae731f8d MZ |
2054 | |
2055 | /** | |
2056 | * request_any_context_irq - allocate an interrupt line | |
2057 | * @irq: Interrupt line to allocate | |
2058 | * @handler: Function to be called when the IRQ occurs. | |
2059 | * Threaded handler for threaded interrupts. | |
2060 | * @flags: Interrupt type flags | |
2061 | * @name: An ascii name for the claiming device | |
2062 | * @dev_id: A cookie passed back to the handler function | |
2063 | * | |
2064 | * This call allocates interrupt resources and enables the | |
2065 | * interrupt line and IRQ handling. It selects either a | |
2066 | * hardirq or threaded handling method depending on the | |
2067 | * context. | |
2068 | * | |
2069 | * On failure, it returns a negative value. On success, | |
2070 | * it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED. | |
2071 | */ | |
2072 | int request_any_context_irq(unsigned int irq, irq_handler_t handler, | |
2073 | unsigned long flags, const char *name, void *dev_id) | |
2074 | { | |
e237a551 | 2075 | struct irq_desc *desc; |
ae731f8d MZ |
2076 | int ret; |
2077 | ||
e237a551 CF |
2078 | if (irq == IRQ_NOTCONNECTED) |
2079 | return -ENOTCONN; | |
2080 | ||
2081 | desc = irq_to_desc(irq); | |
ae731f8d MZ |
2082 | if (!desc) |
2083 | return -EINVAL; | |
2084 | ||
1ccb4e61 | 2085 | if (irq_settings_is_nested_thread(desc)) { |
ae731f8d MZ |
2086 | ret = request_threaded_irq(irq, NULL, handler, |
2087 | flags, name, dev_id); | |
2088 | return !ret ? IRQC_IS_NESTED : ret; | |
2089 | } | |
2090 | ||
2091 | ret = request_irq(irq, handler, flags, name, dev_id); | |
2092 | return !ret ? IRQC_IS_HARDIRQ : ret; | |
2093 | } | |
2094 | EXPORT_SYMBOL_GPL(request_any_context_irq); | |
31d9d9b6 | 2095 | |
b525903c JT |
2096 | /** |
2097 | * request_nmi - allocate an interrupt line for NMI delivery | |
2098 | * @irq: Interrupt line to allocate | |
2099 | * @handler: Function to be called when the IRQ occurs. | |
2100 | * Threaded handler for threaded interrupts. | |
2101 | * @irqflags: Interrupt type flags | |
2102 | * @name: An ascii name for the claiming device | |
2103 | * @dev_id: A cookie passed back to the handler function | |
2104 | * | |
2105 | * This call allocates interrupt resources and enables the | |
2106 | * interrupt line and IRQ handling. It sets up the IRQ line | |
2107 | * to be handled as an NMI. | |
2108 | * | |
2109 | * An interrupt line delivering NMIs cannot be shared and IRQ handling | |
2110 | * cannot be threaded. | |
2111 | * | |
2112 | * Interrupt lines requested for NMI delivering must produce per cpu | |
2113 | * interrupts and have auto enabling setting disabled. | |
2114 | * | |
2115 | * Dev_id must be globally unique. Normally the address of the | |
2116 | * device data structure is used as the cookie. Since the handler | |
2117 | * receives this value it makes sense to use it. | |
2118 | * | |
2119 | * If the interrupt line cannot be used to deliver NMIs, function | |
2120 | * will fail and return a negative value. | |
2121 | */ | |
2122 | int request_nmi(unsigned int irq, irq_handler_t handler, | |
2123 | unsigned long irqflags, const char *name, void *dev_id) | |
2124 | { | |
2125 | struct irqaction *action; | |
2126 | struct irq_desc *desc; | |
2127 | unsigned long flags; | |
2128 | int retval; | |
2129 | ||
2130 | if (irq == IRQ_NOTCONNECTED) | |
2131 | return -ENOTCONN; | |
2132 | ||
2133 | /* NMI cannot be shared, used for Polling */ | |
2134 | if (irqflags & (IRQF_SHARED | IRQF_COND_SUSPEND | IRQF_IRQPOLL)) | |
2135 | return -EINVAL; | |
2136 | ||
2137 | if (!(irqflags & IRQF_PERCPU)) | |
2138 | return -EINVAL; | |
2139 | ||
2140 | if (!handler) | |
2141 | return -EINVAL; | |
2142 | ||
2143 | desc = irq_to_desc(irq); | |
2144 | ||
2145 | if (!desc || irq_settings_can_autoenable(desc) || | |
2146 | !irq_settings_can_request(desc) || | |
2147 | WARN_ON(irq_settings_is_per_cpu_devid(desc)) || | |
2148 | !irq_supports_nmi(desc)) | |
2149 | return -EINVAL; | |
2150 | ||
2151 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
2152 | if (!action) | |
2153 | return -ENOMEM; | |
2154 | ||
2155 | action->handler = handler; | |
2156 | action->flags = irqflags | IRQF_NO_THREAD | IRQF_NOBALANCING; | |
2157 | action->name = name; | |
2158 | action->dev_id = dev_id; | |
2159 | ||
2160 | retval = irq_chip_pm_get(&desc->irq_data); | |
2161 | if (retval < 0) | |
2162 | goto err_out; | |
2163 | ||
2164 | retval = __setup_irq(irq, desc, action); | |
2165 | if (retval) | |
2166 | goto err_irq_setup; | |
2167 | ||
2168 | raw_spin_lock_irqsave(&desc->lock, flags); | |
2169 | ||
2170 | /* Setup NMI state */ | |
2171 | desc->istate |= IRQS_NMI; | |
2172 | retval = irq_nmi_setup(desc); | |
2173 | if (retval) { | |
2174 | __cleanup_nmi(irq, desc); | |
2175 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2176 | return -EINVAL; | |
2177 | } | |
2178 | ||
2179 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2180 | ||
2181 | return 0; | |
2182 | ||
2183 | err_irq_setup: | |
2184 | irq_chip_pm_put(&desc->irq_data); | |
2185 | err_out: | |
2186 | kfree(action); | |
2187 | ||
2188 | return retval; | |
2189 | } | |
2190 | ||
1e7c5fd2 | 2191 | void enable_percpu_irq(unsigned int irq, unsigned int type) |
31d9d9b6 MZ |
2192 | { |
2193 | unsigned int cpu = smp_processor_id(); | |
2194 | unsigned long flags; | |
2195 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
2196 | ||
2197 | if (!desc) | |
2198 | return; | |
2199 | ||
f35ad083 MZ |
2200 | /* |
2201 | * If the trigger type is not specified by the caller, then | |
2202 | * use the default for this interrupt. | |
2203 | */ | |
1e7c5fd2 | 2204 | type &= IRQ_TYPE_SENSE_MASK; |
f35ad083 MZ |
2205 | if (type == IRQ_TYPE_NONE) |
2206 | type = irqd_get_trigger_type(&desc->irq_data); | |
2207 | ||
1e7c5fd2 MZ |
2208 | if (type != IRQ_TYPE_NONE) { |
2209 | int ret; | |
2210 | ||
a1ff541a | 2211 | ret = __irq_set_trigger(desc, type); |
1e7c5fd2 MZ |
2212 | |
2213 | if (ret) { | |
32cffdde | 2214 | WARN(1, "failed to set type for IRQ%d\n", irq); |
1e7c5fd2 MZ |
2215 | goto out; |
2216 | } | |
2217 | } | |
2218 | ||
31d9d9b6 | 2219 | irq_percpu_enable(desc, cpu); |
1e7c5fd2 | 2220 | out: |
31d9d9b6 MZ |
2221 | irq_put_desc_unlock(desc, flags); |
2222 | } | |
36a5df85 | 2223 | EXPORT_SYMBOL_GPL(enable_percpu_irq); |
31d9d9b6 | 2224 | |
4b078c3f JT |
2225 | void enable_percpu_nmi(unsigned int irq, unsigned int type) |
2226 | { | |
2227 | enable_percpu_irq(irq, type); | |
2228 | } | |
2229 | ||
f0cb3220 TP |
2230 | /** |
2231 | * irq_percpu_is_enabled - Check whether the per cpu irq is enabled | |
2232 | * @irq: Linux irq number to check for | |
2233 | * | |
2234 | * Must be called from a non migratable context. Returns the enable | |
2235 | * state of a per cpu interrupt on the current cpu. | |
2236 | */ | |
2237 | bool irq_percpu_is_enabled(unsigned int irq) | |
2238 | { | |
2239 | unsigned int cpu = smp_processor_id(); | |
2240 | struct irq_desc *desc; | |
2241 | unsigned long flags; | |
2242 | bool is_enabled; | |
2243 | ||
2244 | desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
2245 | if (!desc) | |
2246 | return false; | |
2247 | ||
2248 | is_enabled = cpumask_test_cpu(cpu, desc->percpu_enabled); | |
2249 | irq_put_desc_unlock(desc, flags); | |
2250 | ||
2251 | return is_enabled; | |
2252 | } | |
2253 | EXPORT_SYMBOL_GPL(irq_percpu_is_enabled); | |
2254 | ||
31d9d9b6 MZ |
2255 | void disable_percpu_irq(unsigned int irq) |
2256 | { | |
2257 | unsigned int cpu = smp_processor_id(); | |
2258 | unsigned long flags; | |
2259 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
2260 | ||
2261 | if (!desc) | |
2262 | return; | |
2263 | ||
2264 | irq_percpu_disable(desc, cpu); | |
2265 | irq_put_desc_unlock(desc, flags); | |
2266 | } | |
36a5df85 | 2267 | EXPORT_SYMBOL_GPL(disable_percpu_irq); |
31d9d9b6 | 2268 | |
4b078c3f JT |
2269 | void disable_percpu_nmi(unsigned int irq) |
2270 | { | |
2271 | disable_percpu_irq(irq); | |
2272 | } | |
2273 | ||
31d9d9b6 MZ |
2274 | /* |
2275 | * Internal function to unregister a percpu irqaction. | |
2276 | */ | |
2277 | static struct irqaction *__free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
2278 | { | |
2279 | struct irq_desc *desc = irq_to_desc(irq); | |
2280 | struct irqaction *action; | |
2281 | unsigned long flags; | |
2282 | ||
2283 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); | |
2284 | ||
2285 | if (!desc) | |
2286 | return NULL; | |
2287 | ||
2288 | raw_spin_lock_irqsave(&desc->lock, flags); | |
2289 | ||
2290 | action = desc->action; | |
2291 | if (!action || action->percpu_dev_id != dev_id) { | |
2292 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
2293 | goto bad; | |
2294 | } | |
2295 | ||
2296 | if (!cpumask_empty(desc->percpu_enabled)) { | |
2297 | WARN(1, "percpu IRQ %d still enabled on CPU%d!\n", | |
2298 | irq, cpumask_first(desc->percpu_enabled)); | |
2299 | goto bad; | |
2300 | } | |
2301 | ||
2302 | /* Found it - now remove it from the list of entries: */ | |
2303 | desc->action = NULL; | |
2304 | ||
4b078c3f JT |
2305 | desc->istate &= ~IRQS_NMI; |
2306 | ||
31d9d9b6 MZ |
2307 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
2308 | ||
2309 | unregister_handler_proc(irq, action); | |
2310 | ||
be45beb2 | 2311 | irq_chip_pm_put(&desc->irq_data); |
31d9d9b6 MZ |
2312 | module_put(desc->owner); |
2313 | return action; | |
2314 | ||
2315 | bad: | |
2316 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2317 | return NULL; | |
2318 | } | |
2319 | ||
2320 | /** | |
2321 | * remove_percpu_irq - free a per-cpu interrupt | |
2322 | * @irq: Interrupt line to free | |
2323 | * @act: irqaction for the interrupt | |
2324 | * | |
2325 | * Used to remove interrupts statically setup by the early boot process. | |
2326 | */ | |
2327 | void remove_percpu_irq(unsigned int irq, struct irqaction *act) | |
2328 | { | |
2329 | struct irq_desc *desc = irq_to_desc(irq); | |
2330 | ||
2331 | if (desc && irq_settings_is_per_cpu_devid(desc)) | |
2332 | __free_percpu_irq(irq, act->percpu_dev_id); | |
2333 | } | |
2334 | ||
2335 | /** | |
2336 | * free_percpu_irq - free an interrupt allocated with request_percpu_irq | |
2337 | * @irq: Interrupt line to free | |
2338 | * @dev_id: Device identity to free | |
2339 | * | |
2340 | * Remove a percpu interrupt handler. The handler is removed, but | |
2341 | * the interrupt line is not disabled. This must be done on each | |
2342 | * CPU before calling this function. The function does not return | |
2343 | * until any executing interrupts for this IRQ have completed. | |
2344 | * | |
2345 | * This function must not be called from interrupt context. | |
2346 | */ | |
2347 | void free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
2348 | { | |
2349 | struct irq_desc *desc = irq_to_desc(irq); | |
2350 | ||
2351 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
2352 | return; | |
2353 | ||
2354 | chip_bus_lock(desc); | |
2355 | kfree(__free_percpu_irq(irq, dev_id)); | |
2356 | chip_bus_sync_unlock(desc); | |
2357 | } | |
aec2e2ad | 2358 | EXPORT_SYMBOL_GPL(free_percpu_irq); |
31d9d9b6 | 2359 | |
4b078c3f JT |
2360 | void free_percpu_nmi(unsigned int irq, void __percpu *dev_id) |
2361 | { | |
2362 | struct irq_desc *desc = irq_to_desc(irq); | |
2363 | ||
2364 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
2365 | return; | |
2366 | ||
2367 | if (WARN_ON(!(desc->istate & IRQS_NMI))) | |
2368 | return; | |
2369 | ||
2370 | kfree(__free_percpu_irq(irq, dev_id)); | |
2371 | } | |
2372 | ||
31d9d9b6 MZ |
2373 | /** |
2374 | * setup_percpu_irq - setup a per-cpu interrupt | |
2375 | * @irq: Interrupt line to setup | |
2376 | * @act: irqaction for the interrupt | |
2377 | * | |
2378 | * Used to statically setup per-cpu interrupts in the early boot process. | |
2379 | */ | |
2380 | int setup_percpu_irq(unsigned int irq, struct irqaction *act) | |
2381 | { | |
2382 | struct irq_desc *desc = irq_to_desc(irq); | |
2383 | int retval; | |
2384 | ||
2385 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
2386 | return -EINVAL; | |
be45beb2 JH |
2387 | |
2388 | retval = irq_chip_pm_get(&desc->irq_data); | |
2389 | if (retval < 0) | |
2390 | return retval; | |
2391 | ||
31d9d9b6 | 2392 | retval = __setup_irq(irq, desc, act); |
31d9d9b6 | 2393 | |
be45beb2 JH |
2394 | if (retval) |
2395 | irq_chip_pm_put(&desc->irq_data); | |
2396 | ||
31d9d9b6 MZ |
2397 | return retval; |
2398 | } | |
2399 | ||
2400 | /** | |
c80081b9 | 2401 | * __request_percpu_irq - allocate a percpu interrupt line |
31d9d9b6 MZ |
2402 | * @irq: Interrupt line to allocate |
2403 | * @handler: Function to be called when the IRQ occurs. | |
c80081b9 | 2404 | * @flags: Interrupt type flags (IRQF_TIMER only) |
31d9d9b6 MZ |
2405 | * @devname: An ascii name for the claiming device |
2406 | * @dev_id: A percpu cookie passed back to the handler function | |
2407 | * | |
a1b7febd MR |
2408 | * This call allocates interrupt resources and enables the |
2409 | * interrupt on the local CPU. If the interrupt is supposed to be | |
2410 | * enabled on other CPUs, it has to be done on each CPU using | |
2411 | * enable_percpu_irq(). | |
31d9d9b6 MZ |
2412 | * |
2413 | * Dev_id must be globally unique. It is a per-cpu variable, and | |
2414 | * the handler gets called with the interrupted CPU's instance of | |
2415 | * that variable. | |
2416 | */ | |
c80081b9 DL |
2417 | int __request_percpu_irq(unsigned int irq, irq_handler_t handler, |
2418 | unsigned long flags, const char *devname, | |
2419 | void __percpu *dev_id) | |
31d9d9b6 MZ |
2420 | { |
2421 | struct irqaction *action; | |
2422 | struct irq_desc *desc; | |
2423 | int retval; | |
2424 | ||
2425 | if (!dev_id) | |
2426 | return -EINVAL; | |
2427 | ||
2428 | desc = irq_to_desc(irq); | |
2429 | if (!desc || !irq_settings_can_request(desc) || | |
2430 | !irq_settings_is_per_cpu_devid(desc)) | |
2431 | return -EINVAL; | |
2432 | ||
c80081b9 DL |
2433 | if (flags && flags != IRQF_TIMER) |
2434 | return -EINVAL; | |
2435 | ||
31d9d9b6 MZ |
2436 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); |
2437 | if (!action) | |
2438 | return -ENOMEM; | |
2439 | ||
2440 | action->handler = handler; | |
c80081b9 | 2441 | action->flags = flags | IRQF_PERCPU | IRQF_NO_SUSPEND; |
31d9d9b6 MZ |
2442 | action->name = devname; |
2443 | action->percpu_dev_id = dev_id; | |
2444 | ||
be45beb2 | 2445 | retval = irq_chip_pm_get(&desc->irq_data); |
4396f46c SL |
2446 | if (retval < 0) { |
2447 | kfree(action); | |
be45beb2 | 2448 | return retval; |
4396f46c | 2449 | } |
be45beb2 | 2450 | |
31d9d9b6 | 2451 | retval = __setup_irq(irq, desc, action); |
31d9d9b6 | 2452 | |
be45beb2 JH |
2453 | if (retval) { |
2454 | irq_chip_pm_put(&desc->irq_data); | |
31d9d9b6 | 2455 | kfree(action); |
be45beb2 | 2456 | } |
31d9d9b6 MZ |
2457 | |
2458 | return retval; | |
2459 | } | |
c80081b9 | 2460 | EXPORT_SYMBOL_GPL(__request_percpu_irq); |
1b7047ed | 2461 | |
4b078c3f JT |
2462 | /** |
2463 | * request_percpu_nmi - allocate a percpu interrupt line for NMI delivery | |
2464 | * @irq: Interrupt line to allocate | |
2465 | * @handler: Function to be called when the IRQ occurs. | |
2466 | * @name: An ascii name for the claiming device | |
2467 | * @dev_id: A percpu cookie passed back to the handler function | |
2468 | * | |
2469 | * This call allocates interrupt resources for a per CPU NMI. Per CPU NMIs | |
a5186694 JT |
2470 | * have to be setup on each CPU by calling prepare_percpu_nmi() before |
2471 | * being enabled on the same CPU by using enable_percpu_nmi(). | |
4b078c3f JT |
2472 | * |
2473 | * Dev_id must be globally unique. It is a per-cpu variable, and | |
2474 | * the handler gets called with the interrupted CPU's instance of | |
2475 | * that variable. | |
2476 | * | |
2477 | * Interrupt lines requested for NMI delivering should have auto enabling | |
2478 | * setting disabled. | |
2479 | * | |
2480 | * If the interrupt line cannot be used to deliver NMIs, function | |
2481 | * will fail returning a negative value. | |
2482 | */ | |
2483 | int request_percpu_nmi(unsigned int irq, irq_handler_t handler, | |
2484 | const char *name, void __percpu *dev_id) | |
2485 | { | |
2486 | struct irqaction *action; | |
2487 | struct irq_desc *desc; | |
2488 | unsigned long flags; | |
2489 | int retval; | |
2490 | ||
2491 | if (!handler) | |
2492 | return -EINVAL; | |
2493 | ||
2494 | desc = irq_to_desc(irq); | |
2495 | ||
2496 | if (!desc || !irq_settings_can_request(desc) || | |
2497 | !irq_settings_is_per_cpu_devid(desc) || | |
2498 | irq_settings_can_autoenable(desc) || | |
2499 | !irq_supports_nmi(desc)) | |
2500 | return -EINVAL; | |
2501 | ||
2502 | /* The line cannot already be NMI */ | |
2503 | if (desc->istate & IRQS_NMI) | |
2504 | return -EINVAL; | |
2505 | ||
2506 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
2507 | if (!action) | |
2508 | return -ENOMEM; | |
2509 | ||
2510 | action->handler = handler; | |
2511 | action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND | IRQF_NO_THREAD | |
2512 | | IRQF_NOBALANCING; | |
2513 | action->name = name; | |
2514 | action->percpu_dev_id = dev_id; | |
2515 | ||
2516 | retval = irq_chip_pm_get(&desc->irq_data); | |
2517 | if (retval < 0) | |
2518 | goto err_out; | |
2519 | ||
2520 | retval = __setup_irq(irq, desc, action); | |
2521 | if (retval) | |
2522 | goto err_irq_setup; | |
2523 | ||
2524 | raw_spin_lock_irqsave(&desc->lock, flags); | |
2525 | desc->istate |= IRQS_NMI; | |
2526 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2527 | ||
2528 | return 0; | |
2529 | ||
2530 | err_irq_setup: | |
2531 | irq_chip_pm_put(&desc->irq_data); | |
2532 | err_out: | |
2533 | kfree(action); | |
2534 | ||
2535 | return retval; | |
2536 | } | |
2537 | ||
2538 | /** | |
2539 | * prepare_percpu_nmi - performs CPU local setup for NMI delivery | |
2540 | * @irq: Interrupt line to prepare for NMI delivery | |
2541 | * | |
2542 | * This call prepares an interrupt line to deliver NMI on the current CPU, | |
2543 | * before that interrupt line gets enabled with enable_percpu_nmi(). | |
2544 | * | |
2545 | * As a CPU local operation, this should be called from non-preemptible | |
2546 | * context. | |
2547 | * | |
2548 | * If the interrupt line cannot be used to deliver NMIs, function | |
2549 | * will fail returning a negative value. | |
2550 | */ | |
2551 | int prepare_percpu_nmi(unsigned int irq) | |
2552 | { | |
2553 | unsigned long flags; | |
2554 | struct irq_desc *desc; | |
2555 | int ret = 0; | |
2556 | ||
2557 | WARN_ON(preemptible()); | |
2558 | ||
2559 | desc = irq_get_desc_lock(irq, &flags, | |
2560 | IRQ_GET_DESC_CHECK_PERCPU); | |
2561 | if (!desc) | |
2562 | return -EINVAL; | |
2563 | ||
2564 | if (WARN(!(desc->istate & IRQS_NMI), | |
2565 | KERN_ERR "prepare_percpu_nmi called for a non-NMI interrupt: irq %u\n", | |
2566 | irq)) { | |
2567 | ret = -EINVAL; | |
2568 | goto out; | |
2569 | } | |
2570 | ||
2571 | ret = irq_nmi_setup(desc); | |
2572 | if (ret) { | |
2573 | pr_err("Failed to setup NMI delivery: irq %u\n", irq); | |
2574 | goto out; | |
2575 | } | |
2576 | ||
2577 | out: | |
2578 | irq_put_desc_unlock(desc, flags); | |
2579 | return ret; | |
2580 | } | |
2581 | ||
2582 | /** | |
2583 | * teardown_percpu_nmi - undoes NMI setup of IRQ line | |
2584 | * @irq: Interrupt line from which CPU local NMI configuration should be | |
2585 | * removed | |
2586 | * | |
2587 | * This call undoes the setup done by prepare_percpu_nmi(). | |
2588 | * | |
2589 | * IRQ line should not be enabled for the current CPU. | |
2590 | * | |
2591 | * As a CPU local operation, this should be called from non-preemptible | |
2592 | * context. | |
2593 | */ | |
2594 | void teardown_percpu_nmi(unsigned int irq) | |
2595 | { | |
2596 | unsigned long flags; | |
2597 | struct irq_desc *desc; | |
2598 | ||
2599 | WARN_ON(preemptible()); | |
2600 | ||
2601 | desc = irq_get_desc_lock(irq, &flags, | |
2602 | IRQ_GET_DESC_CHECK_PERCPU); | |
2603 | if (!desc) | |
2604 | return; | |
2605 | ||
2606 | if (WARN_ON(!(desc->istate & IRQS_NMI))) | |
2607 | goto out; | |
2608 | ||
2609 | irq_nmi_teardown(desc); | |
2610 | out: | |
2611 | irq_put_desc_unlock(desc, flags); | |
2612 | } | |
2613 | ||
62e04686 TG |
2614 | int __irq_get_irqchip_state(struct irq_data *data, enum irqchip_irq_state which, |
2615 | bool *state) | |
2616 | { | |
2617 | struct irq_chip *chip; | |
2618 | int err = -EINVAL; | |
2619 | ||
2620 | do { | |
2621 | chip = irq_data_get_irq_chip(data); | |
1d0326f3 MV |
2622 | if (WARN_ON_ONCE(!chip)) |
2623 | return -ENODEV; | |
62e04686 TG |
2624 | if (chip->irq_get_irqchip_state) |
2625 | break; | |
2626 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
2627 | data = data->parent_data; | |
2628 | #else | |
2629 | data = NULL; | |
2630 | #endif | |
2631 | } while (data); | |
2632 | ||
2633 | if (data) | |
2634 | err = chip->irq_get_irqchip_state(data, which, state); | |
2635 | return err; | |
2636 | } | |
2637 | ||
1b7047ed MZ |
2638 | /** |
2639 | * irq_get_irqchip_state - returns the irqchip state of a interrupt. | |
2640 | * @irq: Interrupt line that is forwarded to a VM | |
2641 | * @which: One of IRQCHIP_STATE_* the caller wants to know about | |
2642 | * @state: a pointer to a boolean where the state is to be storeed | |
2643 | * | |
2644 | * This call snapshots the internal irqchip state of an | |
2645 | * interrupt, returning into @state the bit corresponding to | |
2646 | * stage @which | |
2647 | * | |
2648 | * This function should be called with preemption disabled if the | |
2649 | * interrupt controller has per-cpu registers. | |
2650 | */ | |
2651 | int irq_get_irqchip_state(unsigned int irq, enum irqchip_irq_state which, | |
2652 | bool *state) | |
2653 | { | |
2654 | struct irq_desc *desc; | |
2655 | struct irq_data *data; | |
1b7047ed MZ |
2656 | unsigned long flags; |
2657 | int err = -EINVAL; | |
2658 | ||
2659 | desc = irq_get_desc_buslock(irq, &flags, 0); | |
2660 | if (!desc) | |
2661 | return err; | |
2662 | ||
2663 | data = irq_desc_get_irq_data(desc); | |
2664 | ||
62e04686 | 2665 | err = __irq_get_irqchip_state(data, which, state); |
1b7047ed MZ |
2666 | |
2667 | irq_put_desc_busunlock(desc, flags); | |
2668 | return err; | |
2669 | } | |
1ee4fb3e | 2670 | EXPORT_SYMBOL_GPL(irq_get_irqchip_state); |
1b7047ed MZ |
2671 | |
2672 | /** | |
2673 | * irq_set_irqchip_state - set the state of a forwarded interrupt. | |
2674 | * @irq: Interrupt line that is forwarded to a VM | |
2675 | * @which: State to be restored (one of IRQCHIP_STATE_*) | |
2676 | * @val: Value corresponding to @which | |
2677 | * | |
2678 | * This call sets the internal irqchip state of an interrupt, | |
2679 | * depending on the value of @which. | |
2680 | * | |
2681 | * This function should be called with preemption disabled if the | |
2682 | * interrupt controller has per-cpu registers. | |
2683 | */ | |
2684 | int irq_set_irqchip_state(unsigned int irq, enum irqchip_irq_state which, | |
2685 | bool val) | |
2686 | { | |
2687 | struct irq_desc *desc; | |
2688 | struct irq_data *data; | |
2689 | struct irq_chip *chip; | |
2690 | unsigned long flags; | |
2691 | int err = -EINVAL; | |
2692 | ||
2693 | desc = irq_get_desc_buslock(irq, &flags, 0); | |
2694 | if (!desc) | |
2695 | return err; | |
2696 | ||
2697 | data = irq_desc_get_irq_data(desc); | |
2698 | ||
2699 | do { | |
2700 | chip = irq_data_get_irq_chip(data); | |
1d0326f3 MV |
2701 | if (WARN_ON_ONCE(!chip)) |
2702 | return -ENODEV; | |
1b7047ed MZ |
2703 | if (chip->irq_set_irqchip_state) |
2704 | break; | |
2705 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
2706 | data = data->parent_data; | |
2707 | #else | |
2708 | data = NULL; | |
2709 | #endif | |
2710 | } while (data); | |
2711 | ||
2712 | if (data) | |
2713 | err = chip->irq_set_irqchip_state(data, which, val); | |
2714 | ||
2715 | irq_put_desc_busunlock(desc, flags); | |
2716 | return err; | |
2717 | } | |
1ee4fb3e | 2718 | EXPORT_SYMBOL_GPL(irq_set_irqchip_state); |