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52a65ff5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
a34db9b2 IM |
3 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
4 | * Copyright (C) 2005-2006 Thomas Gleixner | |
1da177e4 LT |
5 | * |
6 | * This file contains driver APIs to the irq subsystem. | |
7 | */ | |
8 | ||
97fd75b7 AM |
9 | #define pr_fmt(fmt) "genirq: " fmt |
10 | ||
1da177e4 | 11 | #include <linux/irq.h> |
3aa551c9 | 12 | #include <linux/kthread.h> |
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/random.h> | |
15 | #include <linux/interrupt.h> | |
4001d8e8 | 16 | #include <linux/irqdomain.h> |
1aeb272c | 17 | #include <linux/slab.h> |
3aa551c9 | 18 | #include <linux/sched.h> |
8bd75c77 | 19 | #include <linux/sched/rt.h> |
0881e7bd | 20 | #include <linux/sched/task.h> |
11ea68f5 | 21 | #include <linux/sched/isolation.h> |
ae7e81c0 | 22 | #include <uapi/linux/sched/types.h> |
4d1d61a6 | 23 | #include <linux/task_work.h> |
1da177e4 LT |
24 | |
25 | #include "internals.h" | |
26 | ||
b6a32bbd | 27 | #if defined(CONFIG_IRQ_FORCED_THREADING) && !defined(CONFIG_PREEMPT_RT) |
8d32a307 | 28 | __read_mostly bool force_irqthreads; |
47b82e88 | 29 | EXPORT_SYMBOL_GPL(force_irqthreads); |
8d32a307 TG |
30 | |
31 | static int __init setup_forced_irqthreads(char *arg) | |
32 | { | |
33 | force_irqthreads = true; | |
34 | return 0; | |
35 | } | |
36 | early_param("threadirqs", setup_forced_irqthreads); | |
37 | #endif | |
38 | ||
62e04686 | 39 | static void __synchronize_hardirq(struct irq_desc *desc, bool sync_chip) |
1da177e4 | 40 | { |
62e04686 | 41 | struct irq_data *irqd = irq_desc_get_irq_data(desc); |
32f4125e | 42 | bool inprogress; |
1da177e4 | 43 | |
a98ce5c6 HX |
44 | do { |
45 | unsigned long flags; | |
46 | ||
47 | /* | |
48 | * Wait until we're out of the critical section. This might | |
49 | * give the wrong answer due to the lack of memory barriers. | |
50 | */ | |
32f4125e | 51 | while (irqd_irq_inprogress(&desc->irq_data)) |
a98ce5c6 HX |
52 | cpu_relax(); |
53 | ||
54 | /* Ok, that indicated we're done: double-check carefully. */ | |
239007b8 | 55 | raw_spin_lock_irqsave(&desc->lock, flags); |
32f4125e | 56 | inprogress = irqd_irq_inprogress(&desc->irq_data); |
62e04686 TG |
57 | |
58 | /* | |
59 | * If requested and supported, check at the chip whether it | |
60 | * is in flight at the hardware level, i.e. already pending | |
61 | * in a CPU and waiting for service and acknowledge. | |
62 | */ | |
63 | if (!inprogress && sync_chip) { | |
64 | /* | |
65 | * Ignore the return code. inprogress is only updated | |
66 | * when the chip supports it. | |
67 | */ | |
68 | __irq_get_irqchip_state(irqd, IRQCHIP_STATE_ACTIVE, | |
69 | &inprogress); | |
70 | } | |
239007b8 | 71 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
a98ce5c6 HX |
72 | |
73 | /* Oops, that failed? */ | |
32f4125e | 74 | } while (inprogress); |
18258f72 TG |
75 | } |
76 | ||
77 | /** | |
78 | * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs) | |
79 | * @irq: interrupt number to wait for | |
80 | * | |
81 | * This function waits for any pending hard IRQ handlers for this | |
82 | * interrupt to complete before returning. If you use this | |
83 | * function while holding a resource the IRQ handler may need you | |
84 | * will deadlock. It does not take associated threaded handlers | |
85 | * into account. | |
86 | * | |
87 | * Do not use this for shutdown scenarios where you must be sure | |
88 | * that all parts (hardirq and threaded handler) have completed. | |
89 | * | |
02cea395 PZ |
90 | * Returns: false if a threaded handler is active. |
91 | * | |
18258f72 | 92 | * This function may be called - with care - from IRQ context. |
62e04686 TG |
93 | * |
94 | * It does not check whether there is an interrupt in flight at the | |
95 | * hardware level, but not serviced yet, as this might deadlock when | |
96 | * called with interrupts disabled and the target CPU of the interrupt | |
97 | * is the current CPU. | |
18258f72 | 98 | */ |
02cea395 | 99 | bool synchronize_hardirq(unsigned int irq) |
18258f72 TG |
100 | { |
101 | struct irq_desc *desc = irq_to_desc(irq); | |
3aa551c9 | 102 | |
02cea395 | 103 | if (desc) { |
62e04686 | 104 | __synchronize_hardirq(desc, false); |
02cea395 PZ |
105 | return !atomic_read(&desc->threads_active); |
106 | } | |
107 | ||
108 | return true; | |
18258f72 TG |
109 | } |
110 | EXPORT_SYMBOL(synchronize_hardirq); | |
111 | ||
112 | /** | |
113 | * synchronize_irq - wait for pending IRQ handlers (on other CPUs) | |
114 | * @irq: interrupt number to wait for | |
115 | * | |
116 | * This function waits for any pending IRQ handlers for this interrupt | |
117 | * to complete before returning. If you use this function while | |
118 | * holding a resource the IRQ handler may need you will deadlock. | |
119 | * | |
1d21f2af TG |
120 | * Can only be called from preemptible code as it might sleep when |
121 | * an interrupt thread is associated to @irq. | |
62e04686 TG |
122 | * |
123 | * It optionally makes sure (when the irq chip supports that method) | |
124 | * that the interrupt is not pending in any CPU and waiting for | |
125 | * service. | |
18258f72 TG |
126 | */ |
127 | void synchronize_irq(unsigned int irq) | |
128 | { | |
129 | struct irq_desc *desc = irq_to_desc(irq); | |
130 | ||
131 | if (desc) { | |
62e04686 | 132 | __synchronize_hardirq(desc, true); |
18258f72 TG |
133 | /* |
134 | * We made sure that no hardirq handler is | |
135 | * running. Now verify that no threaded handlers are | |
136 | * active. | |
137 | */ | |
138 | wait_event(desc->wait_for_threads, | |
139 | !atomic_read(&desc->threads_active)); | |
140 | } | |
1da177e4 | 141 | } |
1da177e4 LT |
142 | EXPORT_SYMBOL(synchronize_irq); |
143 | ||
3aa551c9 TG |
144 | #ifdef CONFIG_SMP |
145 | cpumask_var_t irq_default_affinity; | |
146 | ||
9c255583 | 147 | static bool __irq_can_set_affinity(struct irq_desc *desc) |
e019c249 JL |
148 | { |
149 | if (!desc || !irqd_can_balance(&desc->irq_data) || | |
150 | !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity) | |
9c255583 TG |
151 | return false; |
152 | return true; | |
e019c249 JL |
153 | } |
154 | ||
771ee3b0 TG |
155 | /** |
156 | * irq_can_set_affinity - Check if the affinity of a given irq can be set | |
157 | * @irq: Interrupt to check | |
158 | * | |
159 | */ | |
160 | int irq_can_set_affinity(unsigned int irq) | |
161 | { | |
e019c249 | 162 | return __irq_can_set_affinity(irq_to_desc(irq)); |
771ee3b0 TG |
163 | } |
164 | ||
9c255583 TG |
165 | /** |
166 | * irq_can_set_affinity_usr - Check if affinity of a irq can be set from user space | |
167 | * @irq: Interrupt to check | |
168 | * | |
169 | * Like irq_can_set_affinity() above, but additionally checks for the | |
170 | * AFFINITY_MANAGED flag. | |
171 | */ | |
172 | bool irq_can_set_affinity_usr(unsigned int irq) | |
173 | { | |
174 | struct irq_desc *desc = irq_to_desc(irq); | |
175 | ||
176 | return __irq_can_set_affinity(desc) && | |
177 | !irqd_affinity_is_managed(&desc->irq_data); | |
178 | } | |
179 | ||
591d2fb0 TG |
180 | /** |
181 | * irq_set_thread_affinity - Notify irq threads to adjust affinity | |
182 | * @desc: irq descriptor which has affitnity changed | |
183 | * | |
184 | * We just set IRQTF_AFFINITY and delegate the affinity setting | |
185 | * to the interrupt thread itself. We can not call | |
186 | * set_cpus_allowed_ptr() here as we hold desc->lock and this | |
187 | * code can be called from hard interrupt context. | |
188 | */ | |
189 | void irq_set_thread_affinity(struct irq_desc *desc) | |
3aa551c9 | 190 | { |
f944b5a7 | 191 | struct irqaction *action; |
3aa551c9 | 192 | |
f944b5a7 | 193 | for_each_action_of_desc(desc, action) |
3aa551c9 | 194 | if (action->thread) |
591d2fb0 | 195 | set_bit(IRQTF_AFFINITY, &action->thread_flags); |
3aa551c9 TG |
196 | } |
197 | ||
baedb87d | 198 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK |
19e1d4e9 TG |
199 | static void irq_validate_effective_affinity(struct irq_data *data) |
200 | { | |
19e1d4e9 TG |
201 | const struct cpumask *m = irq_data_get_effective_affinity_mask(data); |
202 | struct irq_chip *chip = irq_data_get_irq_chip(data); | |
203 | ||
204 | if (!cpumask_empty(m)) | |
205 | return; | |
206 | pr_warn_once("irq_chip %s did not update eff. affinity mask of irq %u\n", | |
207 | chip->name, data->irq); | |
19e1d4e9 TG |
208 | } |
209 | ||
baedb87d TG |
210 | static inline void irq_init_effective_affinity(struct irq_data *data, |
211 | const struct cpumask *mask) | |
212 | { | |
213 | cpumask_copy(irq_data_get_effective_affinity_mask(data), mask); | |
214 | } | |
215 | #else | |
216 | static inline void irq_validate_effective_affinity(struct irq_data *data) { } | |
217 | static inline void irq_init_effective_affinity(struct irq_data *data, | |
218 | const struct cpumask *mask) { } | |
219 | #endif | |
220 | ||
818b0f3b JL |
221 | int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, |
222 | bool force) | |
223 | { | |
224 | struct irq_desc *desc = irq_data_to_desc(data); | |
225 | struct irq_chip *chip = irq_data_get_irq_chip(data); | |
226 | int ret; | |
227 | ||
e43b3b58 TG |
228 | if (!chip || !chip->irq_set_affinity) |
229 | return -EINVAL; | |
230 | ||
11ea68f5 ML |
231 | /* |
232 | * If this is a managed interrupt and housekeeping is enabled on | |
233 | * it check whether the requested affinity mask intersects with | |
234 | * a housekeeping CPU. If so, then remove the isolated CPUs from | |
235 | * the mask and just keep the housekeeping CPU(s). This prevents | |
236 | * the affinity setter from routing the interrupt to an isolated | |
237 | * CPU to avoid that I/O submitted from a housekeeping CPU causes | |
238 | * interrupts on an isolated one. | |
239 | * | |
240 | * If the masks do not intersect or include online CPU(s) then | |
241 | * keep the requested mask. The isolated target CPUs are only | |
242 | * receiving interrupts when the I/O operation was submitted | |
243 | * directly from them. | |
244 | * | |
245 | * If all housekeeping CPUs in the affinity mask are offline, the | |
246 | * interrupt will be migrated by the CPU hotplug code once a | |
247 | * housekeeping CPU which belongs to the affinity mask comes | |
248 | * online. | |
249 | */ | |
250 | if (irqd_affinity_is_managed(data) && | |
251 | housekeeping_enabled(HK_FLAG_MANAGED_IRQ)) { | |
252 | const struct cpumask *hk_mask, *prog_mask; | |
253 | ||
254 | static DEFINE_RAW_SPINLOCK(tmp_mask_lock); | |
255 | static struct cpumask tmp_mask; | |
256 | ||
257 | hk_mask = housekeeping_cpumask(HK_FLAG_MANAGED_IRQ); | |
258 | ||
259 | raw_spin_lock(&tmp_mask_lock); | |
260 | cpumask_and(&tmp_mask, mask, hk_mask); | |
261 | if (!cpumask_intersects(&tmp_mask, cpu_online_mask)) | |
262 | prog_mask = mask; | |
263 | else | |
264 | prog_mask = &tmp_mask; | |
265 | ret = chip->irq_set_affinity(data, prog_mask, force); | |
266 | raw_spin_unlock(&tmp_mask_lock); | |
267 | } else { | |
268 | ret = chip->irq_set_affinity(data, mask, force); | |
269 | } | |
818b0f3b JL |
270 | switch (ret) { |
271 | case IRQ_SET_MASK_OK: | |
2cb62547 | 272 | case IRQ_SET_MASK_OK_DONE: |
9df872fa | 273 | cpumask_copy(desc->irq_common_data.affinity, mask); |
df561f66 | 274 | fallthrough; |
818b0f3b | 275 | case IRQ_SET_MASK_OK_NOCOPY: |
19e1d4e9 | 276 | irq_validate_effective_affinity(data); |
818b0f3b JL |
277 | irq_set_thread_affinity(desc); |
278 | ret = 0; | |
279 | } | |
280 | ||
281 | return ret; | |
282 | } | |
283 | ||
12f47073 TG |
284 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
285 | static inline int irq_set_affinity_pending(struct irq_data *data, | |
286 | const struct cpumask *dest) | |
287 | { | |
288 | struct irq_desc *desc = irq_data_to_desc(data); | |
289 | ||
290 | irqd_set_move_pending(data); | |
291 | irq_copy_pending(desc, dest); | |
292 | return 0; | |
293 | } | |
294 | #else | |
295 | static inline int irq_set_affinity_pending(struct irq_data *data, | |
296 | const struct cpumask *dest) | |
297 | { | |
298 | return -EBUSY; | |
299 | } | |
300 | #endif | |
301 | ||
302 | static int irq_try_set_affinity(struct irq_data *data, | |
303 | const struct cpumask *dest, bool force) | |
304 | { | |
305 | int ret = irq_do_set_affinity(data, dest, force); | |
306 | ||
307 | /* | |
308 | * In case that the underlying vector management is busy and the | |
309 | * architecture supports the generic pending mechanism then utilize | |
310 | * this to avoid returning an error to user space. | |
311 | */ | |
312 | if (ret == -EBUSY && !force) | |
313 | ret = irq_set_affinity_pending(data, dest); | |
314 | return ret; | |
315 | } | |
316 | ||
baedb87d TG |
317 | static bool irq_set_affinity_deactivated(struct irq_data *data, |
318 | const struct cpumask *mask, bool force) | |
319 | { | |
320 | struct irq_desc *desc = irq_data_to_desc(data); | |
321 | ||
322 | /* | |
f0c7baca TG |
323 | * Handle irq chips which can handle affinity only in activated |
324 | * state correctly | |
325 | * | |
baedb87d TG |
326 | * If the interrupt is not yet activated, just store the affinity |
327 | * mask and do not call the chip driver at all. On activation the | |
328 | * driver has to make sure anyway that the interrupt is in a | |
329 | * useable state so startup works. | |
330 | */ | |
f0c7baca TG |
331 | if (!IS_ENABLED(CONFIG_IRQ_DOMAIN_HIERARCHY) || |
332 | irqd_is_activated(data) || !irqd_affinity_on_activate(data)) | |
baedb87d TG |
333 | return false; |
334 | ||
335 | cpumask_copy(desc->irq_common_data.affinity, mask); | |
336 | irq_init_effective_affinity(data, mask); | |
337 | irqd_set(data, IRQD_AFFINITY_SET); | |
338 | return true; | |
339 | } | |
340 | ||
01f8fa4f TG |
341 | int irq_set_affinity_locked(struct irq_data *data, const struct cpumask *mask, |
342 | bool force) | |
771ee3b0 | 343 | { |
c2d0c555 DD |
344 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
345 | struct irq_desc *desc = irq_data_to_desc(data); | |
1fa46f1f | 346 | int ret = 0; |
771ee3b0 | 347 | |
c2d0c555 | 348 | if (!chip || !chip->irq_set_affinity) |
771ee3b0 TG |
349 | return -EINVAL; |
350 | ||
baedb87d TG |
351 | if (irq_set_affinity_deactivated(data, mask, force)) |
352 | return 0; | |
353 | ||
12f47073 TG |
354 | if (irq_can_move_pcntxt(data) && !irqd_is_setaffinity_pending(data)) { |
355 | ret = irq_try_set_affinity(data, mask, force); | |
1fa46f1f | 356 | } else { |
c2d0c555 | 357 | irqd_set_move_pending(data); |
1fa46f1f | 358 | irq_copy_pending(desc, mask); |
57b150cc | 359 | } |
1fa46f1f | 360 | |
cd7eab44 BH |
361 | if (desc->affinity_notify) { |
362 | kref_get(&desc->affinity_notify->kref); | |
df81dfcf EC |
363 | if (!schedule_work(&desc->affinity_notify->work)) { |
364 | /* Work was already scheduled, drop our extra ref */ | |
365 | kref_put(&desc->affinity_notify->kref, | |
366 | desc->affinity_notify->release); | |
367 | } | |
cd7eab44 | 368 | } |
c2d0c555 DD |
369 | irqd_set(data, IRQD_AFFINITY_SET); |
370 | ||
371 | return ret; | |
372 | } | |
373 | ||
01f8fa4f | 374 | int __irq_set_affinity(unsigned int irq, const struct cpumask *mask, bool force) |
c2d0c555 DD |
375 | { |
376 | struct irq_desc *desc = irq_to_desc(irq); | |
377 | unsigned long flags; | |
378 | int ret; | |
379 | ||
380 | if (!desc) | |
381 | return -EINVAL; | |
382 | ||
383 | raw_spin_lock_irqsave(&desc->lock, flags); | |
01f8fa4f | 384 | ret = irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask, force); |
239007b8 | 385 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1fa46f1f | 386 | return ret; |
771ee3b0 TG |
387 | } |
388 | ||
e7a297b0 PWJ |
389 | int irq_set_affinity_hint(unsigned int irq, const struct cpumask *m) |
390 | { | |
e7a297b0 | 391 | unsigned long flags; |
31d9d9b6 | 392 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
e7a297b0 PWJ |
393 | |
394 | if (!desc) | |
395 | return -EINVAL; | |
e7a297b0 | 396 | desc->affinity_hint = m; |
02725e74 | 397 | irq_put_desc_unlock(desc, flags); |
e2e64a93 | 398 | /* set the initial affinity to prevent every interrupt being on CPU0 */ |
4fe7ffb7 JB |
399 | if (m) |
400 | __irq_set_affinity(irq, m, false); | |
e7a297b0 PWJ |
401 | return 0; |
402 | } | |
403 | EXPORT_SYMBOL_GPL(irq_set_affinity_hint); | |
404 | ||
cd7eab44 BH |
405 | static void irq_affinity_notify(struct work_struct *work) |
406 | { | |
407 | struct irq_affinity_notify *notify = | |
408 | container_of(work, struct irq_affinity_notify, work); | |
409 | struct irq_desc *desc = irq_to_desc(notify->irq); | |
410 | cpumask_var_t cpumask; | |
411 | unsigned long flags; | |
412 | ||
1fa46f1f | 413 | if (!desc || !alloc_cpumask_var(&cpumask, GFP_KERNEL)) |
cd7eab44 BH |
414 | goto out; |
415 | ||
416 | raw_spin_lock_irqsave(&desc->lock, flags); | |
0ef5ca1e | 417 | if (irq_move_pending(&desc->irq_data)) |
1fa46f1f | 418 | irq_get_pending(cpumask, desc); |
cd7eab44 | 419 | else |
9df872fa | 420 | cpumask_copy(cpumask, desc->irq_common_data.affinity); |
cd7eab44 BH |
421 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
422 | ||
423 | notify->notify(notify, cpumask); | |
424 | ||
425 | free_cpumask_var(cpumask); | |
426 | out: | |
427 | kref_put(¬ify->kref, notify->release); | |
428 | } | |
429 | ||
430 | /** | |
431 | * irq_set_affinity_notifier - control notification of IRQ affinity changes | |
432 | * @irq: Interrupt for which to enable/disable notification | |
433 | * @notify: Context for notification, or %NULL to disable | |
434 | * notification. Function pointers must be initialised; | |
435 | * the other fields will be initialised by this function. | |
436 | * | |
437 | * Must be called in process context. Notification may only be enabled | |
438 | * after the IRQ is allocated and must be disabled before the IRQ is | |
439 | * freed using free_irq(). | |
440 | */ | |
441 | int | |
442 | irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify) | |
443 | { | |
444 | struct irq_desc *desc = irq_to_desc(irq); | |
445 | struct irq_affinity_notify *old_notify; | |
446 | unsigned long flags; | |
447 | ||
448 | /* The release function is promised process context */ | |
449 | might_sleep(); | |
450 | ||
b525903c | 451 | if (!desc || desc->istate & IRQS_NMI) |
cd7eab44 BH |
452 | return -EINVAL; |
453 | ||
454 | /* Complete initialisation of *notify */ | |
455 | if (notify) { | |
456 | notify->irq = irq; | |
457 | kref_init(¬ify->kref); | |
458 | INIT_WORK(¬ify->work, irq_affinity_notify); | |
459 | } | |
460 | ||
461 | raw_spin_lock_irqsave(&desc->lock, flags); | |
462 | old_notify = desc->affinity_notify; | |
463 | desc->affinity_notify = notify; | |
464 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
465 | ||
59c39840 | 466 | if (old_notify) { |
df81dfcf EC |
467 | if (cancel_work_sync(&old_notify->work)) { |
468 | /* Pending work had a ref, put that one too */ | |
469 | kref_put(&old_notify->kref, old_notify->release); | |
470 | } | |
cd7eab44 | 471 | kref_put(&old_notify->kref, old_notify->release); |
59c39840 | 472 | } |
cd7eab44 BH |
473 | |
474 | return 0; | |
475 | } | |
476 | EXPORT_SYMBOL_GPL(irq_set_affinity_notifier); | |
477 | ||
18404756 MK |
478 | #ifndef CONFIG_AUTO_IRQ_AFFINITY |
479 | /* | |
480 | * Generic version of the affinity autoselector. | |
481 | */ | |
43564bd9 | 482 | int irq_setup_affinity(struct irq_desc *desc) |
18404756 | 483 | { |
569bda8d | 484 | struct cpumask *set = irq_default_affinity; |
cba4235e TG |
485 | int ret, node = irq_desc_get_node(desc); |
486 | static DEFINE_RAW_SPINLOCK(mask_lock); | |
487 | static struct cpumask mask; | |
569bda8d | 488 | |
b008207c | 489 | /* Excludes PER_CPU and NO_BALANCE interrupts */ |
e019c249 | 490 | if (!__irq_can_set_affinity(desc)) |
18404756 MK |
491 | return 0; |
492 | ||
cba4235e | 493 | raw_spin_lock(&mask_lock); |
f6d87f4b | 494 | /* |
9332ef9d | 495 | * Preserve the managed affinity setting and a userspace affinity |
06ee6d57 | 496 | * setup, but make sure that one of the targets is online. |
f6d87f4b | 497 | */ |
06ee6d57 TG |
498 | if (irqd_affinity_is_managed(&desc->irq_data) || |
499 | irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) { | |
9df872fa | 500 | if (cpumask_intersects(desc->irq_common_data.affinity, |
569bda8d | 501 | cpu_online_mask)) |
9df872fa | 502 | set = desc->irq_common_data.affinity; |
0c6f8a8b | 503 | else |
2bdd1055 | 504 | irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET); |
f6d87f4b | 505 | } |
18404756 | 506 | |
cba4235e | 507 | cpumask_and(&mask, cpu_online_mask, set); |
bddda606 SR |
508 | if (cpumask_empty(&mask)) |
509 | cpumask_copy(&mask, cpu_online_mask); | |
510 | ||
241fc640 PB |
511 | if (node != NUMA_NO_NODE) { |
512 | const struct cpumask *nodemask = cpumask_of_node(node); | |
513 | ||
514 | /* make sure at least one of the cpus in nodemask is online */ | |
cba4235e TG |
515 | if (cpumask_intersects(&mask, nodemask)) |
516 | cpumask_and(&mask, &mask, nodemask); | |
241fc640 | 517 | } |
cba4235e TG |
518 | ret = irq_do_set_affinity(&desc->irq_data, &mask, false); |
519 | raw_spin_unlock(&mask_lock); | |
520 | return ret; | |
18404756 | 521 | } |
f6d87f4b | 522 | #else |
a8a98eac | 523 | /* Wrapper for ALPHA specific affinity selector magic */ |
cba4235e | 524 | int irq_setup_affinity(struct irq_desc *desc) |
f6d87f4b | 525 | { |
cba4235e | 526 | return irq_select_affinity(irq_desc_get_irq(desc)); |
f6d87f4b | 527 | } |
cba6437a TG |
528 | #endif /* CONFIG_AUTO_IRQ_AFFINITY */ |
529 | #endif /* CONFIG_SMP */ | |
18404756 | 530 | |
1da177e4 | 531 | |
fcf1ae2f FW |
532 | /** |
533 | * irq_set_vcpu_affinity - Set vcpu affinity for the interrupt | |
534 | * @irq: interrupt number to set affinity | |
250a53d6 CD |
535 | * @vcpu_info: vCPU specific data or pointer to a percpu array of vCPU |
536 | * specific data for percpu_devid interrupts | |
fcf1ae2f FW |
537 | * |
538 | * This function uses the vCPU specific data to set the vCPU | |
539 | * affinity for an irq. The vCPU specific data is passed from | |
540 | * outside, such as KVM. One example code path is as below: | |
541 | * KVM -> IOMMU -> irq_set_vcpu_affinity(). | |
542 | */ | |
543 | int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info) | |
544 | { | |
545 | unsigned long flags; | |
546 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
547 | struct irq_data *data; | |
548 | struct irq_chip *chip; | |
549 | int ret = -ENOSYS; | |
550 | ||
551 | if (!desc) | |
552 | return -EINVAL; | |
553 | ||
554 | data = irq_desc_get_irq_data(desc); | |
0abce64a MZ |
555 | do { |
556 | chip = irq_data_get_irq_chip(data); | |
557 | if (chip && chip->irq_set_vcpu_affinity) | |
558 | break; | |
559 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
560 | data = data->parent_data; | |
561 | #else | |
562 | data = NULL; | |
563 | #endif | |
564 | } while (data); | |
565 | ||
566 | if (data) | |
fcf1ae2f FW |
567 | ret = chip->irq_set_vcpu_affinity(data, vcpu_info); |
568 | irq_put_desc_unlock(desc, flags); | |
569 | ||
570 | return ret; | |
571 | } | |
572 | EXPORT_SYMBOL_GPL(irq_set_vcpu_affinity); | |
573 | ||
79ff1cda | 574 | void __disable_irq(struct irq_desc *desc) |
0a0c5168 | 575 | { |
3aae994f | 576 | if (!desc->depth++) |
87923470 | 577 | irq_disable(desc); |
0a0c5168 RW |
578 | } |
579 | ||
02725e74 TG |
580 | static int __disable_irq_nosync(unsigned int irq) |
581 | { | |
582 | unsigned long flags; | |
31d9d9b6 | 583 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 TG |
584 | |
585 | if (!desc) | |
586 | return -EINVAL; | |
79ff1cda | 587 | __disable_irq(desc); |
02725e74 TG |
588 | irq_put_desc_busunlock(desc, flags); |
589 | return 0; | |
590 | } | |
591 | ||
1da177e4 LT |
592 | /** |
593 | * disable_irq_nosync - disable an irq without waiting | |
594 | * @irq: Interrupt to disable | |
595 | * | |
596 | * Disable the selected interrupt line. Disables and Enables are | |
597 | * nested. | |
598 | * Unlike disable_irq(), this function does not ensure existing | |
599 | * instances of the IRQ handler have completed before returning. | |
600 | * | |
601 | * This function may be called from IRQ context. | |
602 | */ | |
603 | void disable_irq_nosync(unsigned int irq) | |
604 | { | |
02725e74 | 605 | __disable_irq_nosync(irq); |
1da177e4 | 606 | } |
1da177e4 LT |
607 | EXPORT_SYMBOL(disable_irq_nosync); |
608 | ||
609 | /** | |
610 | * disable_irq - disable an irq and wait for completion | |
611 | * @irq: Interrupt to disable | |
612 | * | |
613 | * Disable the selected interrupt line. Enables and Disables are | |
614 | * nested. | |
615 | * This function waits for any pending IRQ handlers for this interrupt | |
616 | * to complete before returning. If you use this function while | |
617 | * holding a resource the IRQ handler may need you will deadlock. | |
618 | * | |
619 | * This function may be called - with care - from IRQ context. | |
620 | */ | |
621 | void disable_irq(unsigned int irq) | |
622 | { | |
02725e74 | 623 | if (!__disable_irq_nosync(irq)) |
1da177e4 LT |
624 | synchronize_irq(irq); |
625 | } | |
1da177e4 LT |
626 | EXPORT_SYMBOL(disable_irq); |
627 | ||
02cea395 PZ |
628 | /** |
629 | * disable_hardirq - disables an irq and waits for hardirq completion | |
630 | * @irq: Interrupt to disable | |
631 | * | |
632 | * Disable the selected interrupt line. Enables and Disables are | |
633 | * nested. | |
634 | * This function waits for any pending hard IRQ handlers for this | |
635 | * interrupt to complete before returning. If you use this function while | |
636 | * holding a resource the hard IRQ handler may need you will deadlock. | |
637 | * | |
638 | * When used to optimistically disable an interrupt from atomic context | |
639 | * the return value must be checked. | |
640 | * | |
641 | * Returns: false if a threaded handler is active. | |
642 | * | |
643 | * This function may be called - with care - from IRQ context. | |
644 | */ | |
645 | bool disable_hardirq(unsigned int irq) | |
646 | { | |
647 | if (!__disable_irq_nosync(irq)) | |
648 | return synchronize_hardirq(irq); | |
649 | ||
650 | return false; | |
651 | } | |
652 | EXPORT_SYMBOL_GPL(disable_hardirq); | |
653 | ||
b525903c JT |
654 | /** |
655 | * disable_nmi_nosync - disable an nmi without waiting | |
656 | * @irq: Interrupt to disable | |
657 | * | |
658 | * Disable the selected interrupt line. Disables and enables are | |
659 | * nested. | |
660 | * The interrupt to disable must have been requested through request_nmi. | |
661 | * Unlike disable_nmi(), this function does not ensure existing | |
662 | * instances of the IRQ handler have completed before returning. | |
663 | */ | |
664 | void disable_nmi_nosync(unsigned int irq) | |
665 | { | |
666 | disable_irq_nosync(irq); | |
667 | } | |
668 | ||
79ff1cda | 669 | void __enable_irq(struct irq_desc *desc) |
1adb0850 TG |
670 | { |
671 | switch (desc->depth) { | |
672 | case 0: | |
0a0c5168 | 673 | err_out: |
79ff1cda JL |
674 | WARN(1, KERN_WARNING "Unbalanced enable for IRQ %d\n", |
675 | irq_desc_get_irq(desc)); | |
1adb0850 TG |
676 | break; |
677 | case 1: { | |
c531e836 | 678 | if (desc->istate & IRQS_SUSPENDED) |
0a0c5168 | 679 | goto err_out; |
1adb0850 | 680 | /* Prevent probing on this irq: */ |
1ccb4e61 | 681 | irq_settings_set_noprobe(desc); |
201d7f47 TG |
682 | /* |
683 | * Call irq_startup() not irq_enable() here because the | |
684 | * interrupt might be marked NOAUTOEN. So irq_startup() | |
685 | * needs to be invoked when it gets enabled the first | |
686 | * time. If it was already started up, then irq_startup() | |
687 | * will invoke irq_enable() under the hood. | |
688 | */ | |
c942cee4 | 689 | irq_startup(desc, IRQ_RESEND, IRQ_START_FORCE); |
201d7f47 | 690 | break; |
1adb0850 TG |
691 | } |
692 | default: | |
693 | desc->depth--; | |
694 | } | |
695 | } | |
696 | ||
1da177e4 LT |
697 | /** |
698 | * enable_irq - enable handling of an irq | |
699 | * @irq: Interrupt to enable | |
700 | * | |
701 | * Undoes the effect of one call to disable_irq(). If this | |
702 | * matches the last disable, processing of interrupts on this | |
703 | * IRQ line is re-enabled. | |
704 | * | |
70aedd24 | 705 | * This function may be called from IRQ context only when |
6b8ff312 | 706 | * desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL ! |
1da177e4 LT |
707 | */ |
708 | void enable_irq(unsigned int irq) | |
709 | { | |
1da177e4 | 710 | unsigned long flags; |
31d9d9b6 | 711 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
1da177e4 | 712 | |
7d94f7ca | 713 | if (!desc) |
c2b5a251 | 714 | return; |
50f7c032 TG |
715 | if (WARN(!desc->irq_data.chip, |
716 | KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq)) | |
02725e74 | 717 | goto out; |
2656c366 | 718 | |
79ff1cda | 719 | __enable_irq(desc); |
02725e74 TG |
720 | out: |
721 | irq_put_desc_busunlock(desc, flags); | |
1da177e4 | 722 | } |
1da177e4 LT |
723 | EXPORT_SYMBOL(enable_irq); |
724 | ||
b525903c JT |
725 | /** |
726 | * enable_nmi - enable handling of an nmi | |
727 | * @irq: Interrupt to enable | |
728 | * | |
729 | * The interrupt to enable must have been requested through request_nmi. | |
730 | * Undoes the effect of one call to disable_nmi(). If this | |
731 | * matches the last disable, processing of interrupts on this | |
732 | * IRQ line is re-enabled. | |
733 | */ | |
734 | void enable_nmi(unsigned int irq) | |
735 | { | |
736 | enable_irq(irq); | |
737 | } | |
738 | ||
0c5d1eb7 | 739 | static int set_irq_wake_real(unsigned int irq, unsigned int on) |
2db87321 | 740 | { |
08678b08 | 741 | struct irq_desc *desc = irq_to_desc(irq); |
2db87321 UKK |
742 | int ret = -ENXIO; |
743 | ||
60f96b41 SS |
744 | if (irq_desc_get_chip(desc)->flags & IRQCHIP_SKIP_SET_WAKE) |
745 | return 0; | |
746 | ||
2f7e99bb TG |
747 | if (desc->irq_data.chip->irq_set_wake) |
748 | ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on); | |
2db87321 UKK |
749 | |
750 | return ret; | |
751 | } | |
752 | ||
ba9a2331 | 753 | /** |
a0cd9ca2 | 754 | * irq_set_irq_wake - control irq power management wakeup |
ba9a2331 TG |
755 | * @irq: interrupt to control |
756 | * @on: enable/disable power management wakeup | |
757 | * | |
15a647eb DB |
758 | * Enable/disable power management wakeup mode, which is |
759 | * disabled by default. Enables and disables must match, | |
760 | * just as they match for non-wakeup mode support. | |
761 | * | |
762 | * Wakeup mode lets this IRQ wake the system from sleep | |
763 | * states like "suspend to RAM". | |
f9f21cea SB |
764 | * |
765 | * Note: irq enable/disable state is completely orthogonal | |
766 | * to the enable/disable state of irq wake. An irq can be | |
767 | * disabled with disable_irq() and still wake the system as | |
768 | * long as the irq has wake enabled. If this does not hold, | |
769 | * then the underlying irq chip and the related driver need | |
770 | * to be investigated. | |
ba9a2331 | 771 | */ |
a0cd9ca2 | 772 | int irq_set_irq_wake(unsigned int irq, unsigned int on) |
ba9a2331 | 773 | { |
ba9a2331 | 774 | unsigned long flags; |
31d9d9b6 | 775 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
2db87321 | 776 | int ret = 0; |
ba9a2331 | 777 | |
13863a66 JJ |
778 | if (!desc) |
779 | return -EINVAL; | |
780 | ||
b525903c JT |
781 | /* Don't use NMIs as wake up interrupts please */ |
782 | if (desc->istate & IRQS_NMI) { | |
783 | ret = -EINVAL; | |
784 | goto out_unlock; | |
785 | } | |
786 | ||
15a647eb DB |
787 | /* wakeup-capable irqs can be shared between drivers that |
788 | * don't need to have the same sleep mode behaviors. | |
789 | */ | |
15a647eb | 790 | if (on) { |
2db87321 UKK |
791 | if (desc->wake_depth++ == 0) { |
792 | ret = set_irq_wake_real(irq, on); | |
793 | if (ret) | |
794 | desc->wake_depth = 0; | |
795 | else | |
7f94226f | 796 | irqd_set(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 797 | } |
15a647eb DB |
798 | } else { |
799 | if (desc->wake_depth == 0) { | |
7a2c4770 | 800 | WARN(1, "Unbalanced IRQ %d wake disable\n", irq); |
2db87321 UKK |
801 | } else if (--desc->wake_depth == 0) { |
802 | ret = set_irq_wake_real(irq, on); | |
803 | if (ret) | |
804 | desc->wake_depth = 1; | |
805 | else | |
7f94226f | 806 | irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 807 | } |
15a647eb | 808 | } |
b525903c JT |
809 | |
810 | out_unlock: | |
02725e74 | 811 | irq_put_desc_busunlock(desc, flags); |
ba9a2331 TG |
812 | return ret; |
813 | } | |
a0cd9ca2 | 814 | EXPORT_SYMBOL(irq_set_irq_wake); |
ba9a2331 | 815 | |
1da177e4 LT |
816 | /* |
817 | * Internal function that tells the architecture code whether a | |
818 | * particular irq has been exclusively allocated or is available | |
819 | * for driver use. | |
820 | */ | |
821 | int can_request_irq(unsigned int irq, unsigned long irqflags) | |
822 | { | |
cc8c3b78 | 823 | unsigned long flags; |
31d9d9b6 | 824 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
02725e74 | 825 | int canrequest = 0; |
1da177e4 | 826 | |
7d94f7ca YL |
827 | if (!desc) |
828 | return 0; | |
829 | ||
02725e74 | 830 | if (irq_settings_can_request(desc)) { |
2779db8d BH |
831 | if (!desc->action || |
832 | irqflags & desc->action->flags & IRQF_SHARED) | |
833 | canrequest = 1; | |
02725e74 TG |
834 | } |
835 | irq_put_desc_unlock(desc, flags); | |
836 | return canrequest; | |
1da177e4 LT |
837 | } |
838 | ||
a1ff541a | 839 | int __irq_set_trigger(struct irq_desc *desc, unsigned long flags) |
82736f4d | 840 | { |
6b8ff312 | 841 | struct irq_chip *chip = desc->irq_data.chip; |
d4d5e089 | 842 | int ret, unmask = 0; |
82736f4d | 843 | |
b2ba2c30 | 844 | if (!chip || !chip->irq_set_type) { |
82736f4d UKK |
845 | /* |
846 | * IRQF_TRIGGER_* but the PIC does not support multiple | |
847 | * flow-types? | |
848 | */ | |
a1ff541a JL |
849 | pr_debug("No set_type function for IRQ %d (%s)\n", |
850 | irq_desc_get_irq(desc), | |
f5d89470 | 851 | chip ? (chip->name ? : "unknown") : "unknown"); |
82736f4d UKK |
852 | return 0; |
853 | } | |
854 | ||
d4d5e089 | 855 | if (chip->flags & IRQCHIP_SET_TYPE_MASKED) { |
32f4125e | 856 | if (!irqd_irq_masked(&desc->irq_data)) |
d4d5e089 | 857 | mask_irq(desc); |
32f4125e | 858 | if (!irqd_irq_disabled(&desc->irq_data)) |
d4d5e089 TG |
859 | unmask = 1; |
860 | } | |
861 | ||
00b992de AK |
862 | /* Mask all flags except trigger mode */ |
863 | flags &= IRQ_TYPE_SENSE_MASK; | |
b2ba2c30 | 864 | ret = chip->irq_set_type(&desc->irq_data, flags); |
82736f4d | 865 | |
876dbd4c TG |
866 | switch (ret) { |
867 | case IRQ_SET_MASK_OK: | |
2cb62547 | 868 | case IRQ_SET_MASK_OK_DONE: |
876dbd4c TG |
869 | irqd_clear(&desc->irq_data, IRQD_TRIGGER_MASK); |
870 | irqd_set(&desc->irq_data, flags); | |
df561f66 | 871 | fallthrough; |
876dbd4c TG |
872 | |
873 | case IRQ_SET_MASK_OK_NOCOPY: | |
874 | flags = irqd_get_trigger_type(&desc->irq_data); | |
875 | irq_settings_set_trigger_mask(desc, flags); | |
876 | irqd_clear(&desc->irq_data, IRQD_LEVEL); | |
877 | irq_settings_clr_level(desc); | |
878 | if (flags & IRQ_TYPE_LEVEL_MASK) { | |
879 | irq_settings_set_level(desc); | |
880 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
881 | } | |
46732475 | 882 | |
d4d5e089 | 883 | ret = 0; |
8fff39e0 | 884 | break; |
876dbd4c | 885 | default: |
d75f773c | 886 | pr_err("Setting trigger mode %lu for irq %u failed (%pS)\n", |
a1ff541a | 887 | flags, irq_desc_get_irq(desc), chip->irq_set_type); |
0c5d1eb7 | 888 | } |
d4d5e089 TG |
889 | if (unmask) |
890 | unmask_irq(desc); | |
82736f4d UKK |
891 | return ret; |
892 | } | |
893 | ||
293a7a0a TG |
894 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
895 | int irq_set_parent(int irq, int parent_irq) | |
896 | { | |
897 | unsigned long flags; | |
898 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
899 | ||
900 | if (!desc) | |
901 | return -EINVAL; | |
902 | ||
903 | desc->parent_irq = parent_irq; | |
904 | ||
905 | irq_put_desc_unlock(desc, flags); | |
906 | return 0; | |
907 | } | |
3118dac5 | 908 | EXPORT_SYMBOL_GPL(irq_set_parent); |
293a7a0a TG |
909 | #endif |
910 | ||
b25c340c TG |
911 | /* |
912 | * Default primary interrupt handler for threaded interrupts. Is | |
913 | * assigned as primary handler when request_threaded_irq is called | |
914 | * with handler == NULL. Useful for oneshot interrupts. | |
915 | */ | |
916 | static irqreturn_t irq_default_primary_handler(int irq, void *dev_id) | |
917 | { | |
918 | return IRQ_WAKE_THREAD; | |
919 | } | |
920 | ||
399b5da2 TG |
921 | /* |
922 | * Primary handler for nested threaded interrupts. Should never be | |
923 | * called. | |
924 | */ | |
925 | static irqreturn_t irq_nested_primary_handler(int irq, void *dev_id) | |
926 | { | |
927 | WARN(1, "Primary handler called for nested irq %d\n", irq); | |
928 | return IRQ_NONE; | |
929 | } | |
930 | ||
2a1d3ab8 TG |
931 | static irqreturn_t irq_forced_secondary_handler(int irq, void *dev_id) |
932 | { | |
933 | WARN(1, "Secondary action handler called for irq %d\n", irq); | |
934 | return IRQ_NONE; | |
935 | } | |
936 | ||
3aa551c9 TG |
937 | static int irq_wait_for_interrupt(struct irqaction *action) |
938 | { | |
519cc865 LW |
939 | for (;;) { |
940 | set_current_state(TASK_INTERRUPTIBLE); | |
550acb19 | 941 | |
519cc865 LW |
942 | if (kthread_should_stop()) { |
943 | /* may need to run one last time */ | |
944 | if (test_and_clear_bit(IRQTF_RUNTHREAD, | |
945 | &action->thread_flags)) { | |
946 | __set_current_state(TASK_RUNNING); | |
947 | return 0; | |
948 | } | |
949 | __set_current_state(TASK_RUNNING); | |
950 | return -1; | |
951 | } | |
f48fe81e TG |
952 | |
953 | if (test_and_clear_bit(IRQTF_RUNTHREAD, | |
954 | &action->thread_flags)) { | |
3aa551c9 TG |
955 | __set_current_state(TASK_RUNNING); |
956 | return 0; | |
f48fe81e TG |
957 | } |
958 | schedule(); | |
3aa551c9 | 959 | } |
3aa551c9 TG |
960 | } |
961 | ||
b25c340c TG |
962 | /* |
963 | * Oneshot interrupts keep the irq line masked until the threaded | |
964 | * handler finished. unmask if the interrupt has not been disabled and | |
965 | * is marked MASKED. | |
966 | */ | |
b5faba21 | 967 | static void irq_finalize_oneshot(struct irq_desc *desc, |
f3f79e38 | 968 | struct irqaction *action) |
b25c340c | 969 | { |
2a1d3ab8 TG |
970 | if (!(desc->istate & IRQS_ONESHOT) || |
971 | action->handler == irq_forced_secondary_handler) | |
b5faba21 | 972 | return; |
0b1adaa0 | 973 | again: |
3876ec9e | 974 | chip_bus_lock(desc); |
239007b8 | 975 | raw_spin_lock_irq(&desc->lock); |
0b1adaa0 TG |
976 | |
977 | /* | |
978 | * Implausible though it may be we need to protect us against | |
979 | * the following scenario: | |
980 | * | |
981 | * The thread is faster done than the hard interrupt handler | |
982 | * on the other CPU. If we unmask the irq line then the | |
983 | * interrupt can come in again and masks the line, leaves due | |
009b4c3b | 984 | * to IRQS_INPROGRESS and the irq line is masked forever. |
b5faba21 TG |
985 | * |
986 | * This also serializes the state of shared oneshot handlers | |
987 | * versus "desc->threads_onehsot |= action->thread_mask;" in | |
988 | * irq_wake_thread(). See the comment there which explains the | |
989 | * serialization. | |
0b1adaa0 | 990 | */ |
32f4125e | 991 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) { |
0b1adaa0 | 992 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 993 | chip_bus_sync_unlock(desc); |
0b1adaa0 TG |
994 | cpu_relax(); |
995 | goto again; | |
996 | } | |
997 | ||
b5faba21 TG |
998 | /* |
999 | * Now check again, whether the thread should run. Otherwise | |
1000 | * we would clear the threads_oneshot bit of this thread which | |
1001 | * was just set. | |
1002 | */ | |
f3f79e38 | 1003 | if (test_bit(IRQTF_RUNTHREAD, &action->thread_flags)) |
b5faba21 TG |
1004 | goto out_unlock; |
1005 | ||
1006 | desc->threads_oneshot &= ~action->thread_mask; | |
1007 | ||
32f4125e TG |
1008 | if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && |
1009 | irqd_irq_masked(&desc->irq_data)) | |
328a4978 | 1010 | unmask_threaded_irq(desc); |
32f4125e | 1011 | |
b5faba21 | 1012 | out_unlock: |
239007b8 | 1013 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 1014 | chip_bus_sync_unlock(desc); |
b25c340c TG |
1015 | } |
1016 | ||
61f38261 | 1017 | #ifdef CONFIG_SMP |
591d2fb0 | 1018 | /* |
b04c644e | 1019 | * Check whether we need to change the affinity of the interrupt thread. |
591d2fb0 TG |
1020 | */ |
1021 | static void | |
1022 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) | |
1023 | { | |
1024 | cpumask_var_t mask; | |
04aa530e | 1025 | bool valid = true; |
591d2fb0 TG |
1026 | |
1027 | if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags)) | |
1028 | return; | |
1029 | ||
1030 | /* | |
1031 | * In case we are out of memory we set IRQTF_AFFINITY again and | |
1032 | * try again next time | |
1033 | */ | |
1034 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { | |
1035 | set_bit(IRQTF_AFFINITY, &action->thread_flags); | |
1036 | return; | |
1037 | } | |
1038 | ||
239007b8 | 1039 | raw_spin_lock_irq(&desc->lock); |
04aa530e TG |
1040 | /* |
1041 | * This code is triggered unconditionally. Check the affinity | |
1042 | * mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out. | |
1043 | */ | |
cbf86999 TG |
1044 | if (cpumask_available(desc->irq_common_data.affinity)) { |
1045 | const struct cpumask *m; | |
1046 | ||
1047 | m = irq_data_get_effective_affinity_mask(&desc->irq_data); | |
1048 | cpumask_copy(mask, m); | |
1049 | } else { | |
04aa530e | 1050 | valid = false; |
cbf86999 | 1051 | } |
239007b8 | 1052 | raw_spin_unlock_irq(&desc->lock); |
591d2fb0 | 1053 | |
04aa530e TG |
1054 | if (valid) |
1055 | set_cpus_allowed_ptr(current, mask); | |
591d2fb0 TG |
1056 | free_cpumask_var(mask); |
1057 | } | |
61f38261 BP |
1058 | #else |
1059 | static inline void | |
1060 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { } | |
1061 | #endif | |
591d2fb0 | 1062 | |
8d32a307 | 1063 | /* |
c5f48c0a | 1064 | * Interrupts which are not explicitly requested as threaded |
8d32a307 TG |
1065 | * interrupts rely on the implicit bh/preempt disable of the hard irq |
1066 | * context. So we need to disable bh here to avoid deadlocks and other | |
1067 | * side effects. | |
1068 | */ | |
3a43e05f | 1069 | static irqreturn_t |
8d32a307 TG |
1070 | irq_forced_thread_fn(struct irq_desc *desc, struct irqaction *action) |
1071 | { | |
3a43e05f SAS |
1072 | irqreturn_t ret; |
1073 | ||
8d32a307 | 1074 | local_bh_disable(); |
3a43e05f | 1075 | ret = action->thread_fn(action->irq, action->dev_id); |
746a923b LW |
1076 | if (ret == IRQ_HANDLED) |
1077 | atomic_inc(&desc->threads_handled); | |
1078 | ||
f3f79e38 | 1079 | irq_finalize_oneshot(desc, action); |
8d32a307 | 1080 | local_bh_enable(); |
3a43e05f | 1081 | return ret; |
8d32a307 TG |
1082 | } |
1083 | ||
1084 | /* | |
f788e7bf | 1085 | * Interrupts explicitly requested as threaded interrupts want to be |
8d32a307 TG |
1086 | * preemtible - many of them need to sleep and wait for slow busses to |
1087 | * complete. | |
1088 | */ | |
3a43e05f SAS |
1089 | static irqreturn_t irq_thread_fn(struct irq_desc *desc, |
1090 | struct irqaction *action) | |
8d32a307 | 1091 | { |
3a43e05f SAS |
1092 | irqreturn_t ret; |
1093 | ||
1094 | ret = action->thread_fn(action->irq, action->dev_id); | |
746a923b LW |
1095 | if (ret == IRQ_HANDLED) |
1096 | atomic_inc(&desc->threads_handled); | |
1097 | ||
f3f79e38 | 1098 | irq_finalize_oneshot(desc, action); |
3a43e05f | 1099 | return ret; |
8d32a307 TG |
1100 | } |
1101 | ||
7140ea19 IY |
1102 | static void wake_threads_waitq(struct irq_desc *desc) |
1103 | { | |
c685689f | 1104 | if (atomic_dec_and_test(&desc->threads_active)) |
7140ea19 IY |
1105 | wake_up(&desc->wait_for_threads); |
1106 | } | |
1107 | ||
67d12145 | 1108 | static void irq_thread_dtor(struct callback_head *unused) |
4d1d61a6 ON |
1109 | { |
1110 | struct task_struct *tsk = current; | |
1111 | struct irq_desc *desc; | |
1112 | struct irqaction *action; | |
1113 | ||
1114 | if (WARN_ON_ONCE(!(current->flags & PF_EXITING))) | |
1115 | return; | |
1116 | ||
1117 | action = kthread_data(tsk); | |
1118 | ||
fb21affa | 1119 | pr_err("exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n", |
19af395d | 1120 | tsk->comm, tsk->pid, action->irq); |
4d1d61a6 ON |
1121 | |
1122 | ||
1123 | desc = irq_to_desc(action->irq); | |
1124 | /* | |
1125 | * If IRQTF_RUNTHREAD is set, we need to decrement | |
1126 | * desc->threads_active and wake possible waiters. | |
1127 | */ | |
1128 | if (test_and_clear_bit(IRQTF_RUNTHREAD, &action->thread_flags)) | |
1129 | wake_threads_waitq(desc); | |
1130 | ||
1131 | /* Prevent a stale desc->threads_oneshot */ | |
1132 | irq_finalize_oneshot(desc, action); | |
1133 | } | |
1134 | ||
2a1d3ab8 TG |
1135 | static void irq_wake_secondary(struct irq_desc *desc, struct irqaction *action) |
1136 | { | |
1137 | struct irqaction *secondary = action->secondary; | |
1138 | ||
1139 | if (WARN_ON_ONCE(!secondary)) | |
1140 | return; | |
1141 | ||
1142 | raw_spin_lock_irq(&desc->lock); | |
1143 | __irq_wake_thread(desc, secondary); | |
1144 | raw_spin_unlock_irq(&desc->lock); | |
1145 | } | |
1146 | ||
3aa551c9 TG |
1147 | /* |
1148 | * Interrupt handler thread | |
1149 | */ | |
1150 | static int irq_thread(void *data) | |
1151 | { | |
67d12145 | 1152 | struct callback_head on_exit_work; |
3aa551c9 TG |
1153 | struct irqaction *action = data; |
1154 | struct irq_desc *desc = irq_to_desc(action->irq); | |
3a43e05f SAS |
1155 | irqreturn_t (*handler_fn)(struct irq_desc *desc, |
1156 | struct irqaction *action); | |
3aa551c9 | 1157 | |
540b60e2 | 1158 | if (force_irqthreads && test_bit(IRQTF_FORCED_THREAD, |
8d32a307 TG |
1159 | &action->thread_flags)) |
1160 | handler_fn = irq_forced_thread_fn; | |
1161 | else | |
1162 | handler_fn = irq_thread_fn; | |
1163 | ||
41f9d29f | 1164 | init_task_work(&on_exit_work, irq_thread_dtor); |
4d1d61a6 | 1165 | task_work_add(current, &on_exit_work, false); |
3aa551c9 | 1166 | |
f3de44ed SM |
1167 | irq_thread_check_affinity(desc, action); |
1168 | ||
3aa551c9 | 1169 | while (!irq_wait_for_interrupt(action)) { |
7140ea19 | 1170 | irqreturn_t action_ret; |
3aa551c9 | 1171 | |
591d2fb0 TG |
1172 | irq_thread_check_affinity(desc, action); |
1173 | ||
7140ea19 | 1174 | action_ret = handler_fn(desc, action); |
2a1d3ab8 TG |
1175 | if (action_ret == IRQ_WAKE_THREAD) |
1176 | irq_wake_secondary(desc, action); | |
3aa551c9 | 1177 | |
7140ea19 | 1178 | wake_threads_waitq(desc); |
3aa551c9 TG |
1179 | } |
1180 | ||
7140ea19 IY |
1181 | /* |
1182 | * This is the regular exit path. __free_irq() is stopping the | |
1183 | * thread via kthread_stop() after calling | |
519cc865 | 1184 | * synchronize_hardirq(). So neither IRQTF_RUNTHREAD nor the |
836557bd | 1185 | * oneshot mask bit can be set. |
3aa551c9 | 1186 | */ |
4d1d61a6 | 1187 | task_work_cancel(current, irq_thread_dtor); |
3aa551c9 TG |
1188 | return 0; |
1189 | } | |
1190 | ||
a92444c6 TG |
1191 | /** |
1192 | * irq_wake_thread - wake the irq thread for the action identified by dev_id | |
1193 | * @irq: Interrupt line | |
1194 | * @dev_id: Device identity for which the thread should be woken | |
1195 | * | |
1196 | */ | |
1197 | void irq_wake_thread(unsigned int irq, void *dev_id) | |
1198 | { | |
1199 | struct irq_desc *desc = irq_to_desc(irq); | |
1200 | struct irqaction *action; | |
1201 | unsigned long flags; | |
1202 | ||
1203 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
1204 | return; | |
1205 | ||
1206 | raw_spin_lock_irqsave(&desc->lock, flags); | |
f944b5a7 | 1207 | for_each_action_of_desc(desc, action) { |
a92444c6 TG |
1208 | if (action->dev_id == dev_id) { |
1209 | if (action->thread) | |
1210 | __irq_wake_thread(desc, action); | |
1211 | break; | |
1212 | } | |
1213 | } | |
1214 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1215 | } | |
1216 | EXPORT_SYMBOL_GPL(irq_wake_thread); | |
1217 | ||
2a1d3ab8 | 1218 | static int irq_setup_forced_threading(struct irqaction *new) |
8d32a307 TG |
1219 | { |
1220 | if (!force_irqthreads) | |
2a1d3ab8 | 1221 | return 0; |
8d32a307 | 1222 | if (new->flags & (IRQF_NO_THREAD | IRQF_PERCPU | IRQF_ONESHOT)) |
2a1d3ab8 | 1223 | return 0; |
8d32a307 | 1224 | |
d1f0301b TG |
1225 | /* |
1226 | * No further action required for interrupts which are requested as | |
1227 | * threaded interrupts already | |
1228 | */ | |
1229 | if (new->handler == irq_default_primary_handler) | |
1230 | return 0; | |
1231 | ||
8d32a307 TG |
1232 | new->flags |= IRQF_ONESHOT; |
1233 | ||
2a1d3ab8 TG |
1234 | /* |
1235 | * Handle the case where we have a real primary handler and a | |
1236 | * thread handler. We force thread them as well by creating a | |
1237 | * secondary action. | |
1238 | */ | |
d1f0301b | 1239 | if (new->handler && new->thread_fn) { |
2a1d3ab8 TG |
1240 | /* Allocate the secondary action */ |
1241 | new->secondary = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
1242 | if (!new->secondary) | |
1243 | return -ENOMEM; | |
1244 | new->secondary->handler = irq_forced_secondary_handler; | |
1245 | new->secondary->thread_fn = new->thread_fn; | |
1246 | new->secondary->dev_id = new->dev_id; | |
1247 | new->secondary->irq = new->irq; | |
1248 | new->secondary->name = new->name; | |
8d32a307 | 1249 | } |
2a1d3ab8 TG |
1250 | /* Deal with the primary handler */ |
1251 | set_bit(IRQTF_FORCED_THREAD, &new->thread_flags); | |
1252 | new->thread_fn = new->handler; | |
1253 | new->handler = irq_default_primary_handler; | |
1254 | return 0; | |
8d32a307 TG |
1255 | } |
1256 | ||
c1bacbae TG |
1257 | static int irq_request_resources(struct irq_desc *desc) |
1258 | { | |
1259 | struct irq_data *d = &desc->irq_data; | |
1260 | struct irq_chip *c = d->chip; | |
1261 | ||
1262 | return c->irq_request_resources ? c->irq_request_resources(d) : 0; | |
1263 | } | |
1264 | ||
1265 | static void irq_release_resources(struct irq_desc *desc) | |
1266 | { | |
1267 | struct irq_data *d = &desc->irq_data; | |
1268 | struct irq_chip *c = d->chip; | |
1269 | ||
1270 | if (c->irq_release_resources) | |
1271 | c->irq_release_resources(d); | |
1272 | } | |
1273 | ||
b525903c JT |
1274 | static bool irq_supports_nmi(struct irq_desc *desc) |
1275 | { | |
1276 | struct irq_data *d = irq_desc_get_irq_data(desc); | |
1277 | ||
1278 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
1279 | /* Only IRQs directly managed by the root irqchip can be set as NMI */ | |
1280 | if (d->parent_data) | |
1281 | return false; | |
1282 | #endif | |
1283 | /* Don't support NMIs for chips behind a slow bus */ | |
1284 | if (d->chip->irq_bus_lock || d->chip->irq_bus_sync_unlock) | |
1285 | return false; | |
1286 | ||
1287 | return d->chip->flags & IRQCHIP_SUPPORTS_NMI; | |
1288 | } | |
1289 | ||
1290 | static int irq_nmi_setup(struct irq_desc *desc) | |
1291 | { | |
1292 | struct irq_data *d = irq_desc_get_irq_data(desc); | |
1293 | struct irq_chip *c = d->chip; | |
1294 | ||
1295 | return c->irq_nmi_setup ? c->irq_nmi_setup(d) : -EINVAL; | |
1296 | } | |
1297 | ||
1298 | static void irq_nmi_teardown(struct irq_desc *desc) | |
1299 | { | |
1300 | struct irq_data *d = irq_desc_get_irq_data(desc); | |
1301 | struct irq_chip *c = d->chip; | |
1302 | ||
1303 | if (c->irq_nmi_teardown) | |
1304 | c->irq_nmi_teardown(d); | |
1305 | } | |
1306 | ||
2a1d3ab8 TG |
1307 | static int |
1308 | setup_irq_thread(struct irqaction *new, unsigned int irq, bool secondary) | |
1309 | { | |
1310 | struct task_struct *t; | |
2a1d3ab8 TG |
1311 | |
1312 | if (!secondary) { | |
1313 | t = kthread_create(irq_thread, new, "irq/%d-%s", irq, | |
1314 | new->name); | |
1315 | } else { | |
1316 | t = kthread_create(irq_thread, new, "irq/%d-s-%s", irq, | |
1317 | new->name); | |
2a1d3ab8 TG |
1318 | } |
1319 | ||
1320 | if (IS_ERR(t)) | |
1321 | return PTR_ERR(t); | |
1322 | ||
7a40798c | 1323 | sched_set_fifo(t); |
2a1d3ab8 TG |
1324 | |
1325 | /* | |
1326 | * We keep the reference to the task struct even if | |
1327 | * the thread dies to avoid that the interrupt code | |
1328 | * references an already freed task_struct. | |
1329 | */ | |
7b3c92b8 | 1330 | new->thread = get_task_struct(t); |
2a1d3ab8 TG |
1331 | /* |
1332 | * Tell the thread to set its affinity. This is | |
1333 | * important for shared interrupt handlers as we do | |
1334 | * not invoke setup_affinity() for the secondary | |
1335 | * handlers as everything is already set up. Even for | |
1336 | * interrupts marked with IRQF_NO_BALANCE this is | |
1337 | * correct as we want the thread to move to the cpu(s) | |
1338 | * on which the requesting code placed the interrupt. | |
1339 | */ | |
1340 | set_bit(IRQTF_AFFINITY, &new->thread_flags); | |
1341 | return 0; | |
1342 | } | |
1343 | ||
1da177e4 LT |
1344 | /* |
1345 | * Internal function to register an irqaction - typically used to | |
1346 | * allocate special interrupts that are part of the architecture. | |
19d39a38 TG |
1347 | * |
1348 | * Locking rules: | |
1349 | * | |
1350 | * desc->request_mutex Provides serialization against a concurrent free_irq() | |
1351 | * chip_bus_lock Provides serialization for slow bus operations | |
1352 | * desc->lock Provides serialization against hard interrupts | |
1353 | * | |
1354 | * chip_bus_lock and desc->lock are sufficient for all other management and | |
1355 | * interrupt related functions. desc->request_mutex solely serializes | |
1356 | * request/free_irq(). | |
1da177e4 | 1357 | */ |
d3c60047 | 1358 | static int |
327ec569 | 1359 | __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) |
1da177e4 | 1360 | { |
f17c7545 | 1361 | struct irqaction *old, **old_ptr; |
b5faba21 | 1362 | unsigned long flags, thread_mask = 0; |
3b8249e7 | 1363 | int ret, nested, shared = 0; |
1da177e4 | 1364 | |
7d94f7ca | 1365 | if (!desc) |
c2b5a251 MW |
1366 | return -EINVAL; |
1367 | ||
6b8ff312 | 1368 | if (desc->irq_data.chip == &no_irq_chip) |
1da177e4 | 1369 | return -ENOSYS; |
b6873807 SAS |
1370 | if (!try_module_get(desc->owner)) |
1371 | return -ENODEV; | |
1da177e4 | 1372 | |
2a1d3ab8 TG |
1373 | new->irq = irq; |
1374 | ||
4b357dae JH |
1375 | /* |
1376 | * If the trigger type is not specified by the caller, | |
1377 | * then use the default for this interrupt. | |
1378 | */ | |
1379 | if (!(new->flags & IRQF_TRIGGER_MASK)) | |
1380 | new->flags |= irqd_get_trigger_type(&desc->irq_data); | |
1381 | ||
3aa551c9 | 1382 | /* |
399b5da2 TG |
1383 | * Check whether the interrupt nests into another interrupt |
1384 | * thread. | |
1385 | */ | |
1ccb4e61 | 1386 | nested = irq_settings_is_nested_thread(desc); |
399b5da2 | 1387 | if (nested) { |
b6873807 SAS |
1388 | if (!new->thread_fn) { |
1389 | ret = -EINVAL; | |
1390 | goto out_mput; | |
1391 | } | |
399b5da2 TG |
1392 | /* |
1393 | * Replace the primary handler which was provided from | |
1394 | * the driver for non nested interrupt handling by the | |
1395 | * dummy function which warns when called. | |
1396 | */ | |
1397 | new->handler = irq_nested_primary_handler; | |
8d32a307 | 1398 | } else { |
2a1d3ab8 TG |
1399 | if (irq_settings_can_thread(desc)) { |
1400 | ret = irq_setup_forced_threading(new); | |
1401 | if (ret) | |
1402 | goto out_mput; | |
1403 | } | |
399b5da2 TG |
1404 | } |
1405 | ||
3aa551c9 | 1406 | /* |
399b5da2 TG |
1407 | * Create a handler thread when a thread function is supplied |
1408 | * and the interrupt does not nest into another interrupt | |
1409 | * thread. | |
3aa551c9 | 1410 | */ |
399b5da2 | 1411 | if (new->thread_fn && !nested) { |
2a1d3ab8 TG |
1412 | ret = setup_irq_thread(new, irq, false); |
1413 | if (ret) | |
b6873807 | 1414 | goto out_mput; |
2a1d3ab8 TG |
1415 | if (new->secondary) { |
1416 | ret = setup_irq_thread(new->secondary, irq, true); | |
1417 | if (ret) | |
1418 | goto out_thread; | |
b6873807 | 1419 | } |
3aa551c9 TG |
1420 | } |
1421 | ||
dc9b229a TG |
1422 | /* |
1423 | * Drivers are often written to work w/o knowledge about the | |
1424 | * underlying irq chip implementation, so a request for a | |
1425 | * threaded irq without a primary hard irq context handler | |
1426 | * requires the ONESHOT flag to be set. Some irq chips like | |
1427 | * MSI based interrupts are per se one shot safe. Check the | |
1428 | * chip flags, so we can avoid the unmask dance at the end of | |
1429 | * the threaded handler for those. | |
1430 | */ | |
1431 | if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE) | |
1432 | new->flags &= ~IRQF_ONESHOT; | |
1433 | ||
19d39a38 TG |
1434 | /* |
1435 | * Protects against a concurrent __free_irq() call which might wait | |
519cc865 | 1436 | * for synchronize_hardirq() to complete without holding the optional |
836557bd LW |
1437 | * chip bus lock and desc->lock. Also protects against handing out |
1438 | * a recycled oneshot thread_mask bit while it's still in use by | |
1439 | * its previous owner. | |
19d39a38 | 1440 | */ |
9114014c | 1441 | mutex_lock(&desc->request_mutex); |
19d39a38 TG |
1442 | |
1443 | /* | |
1444 | * Acquire bus lock as the irq_request_resources() callback below | |
1445 | * might rely on the serialization or the magic power management | |
1446 | * functions which are abusing the irq_bus_lock() callback, | |
1447 | */ | |
1448 | chip_bus_lock(desc); | |
1449 | ||
1450 | /* First installed action requests resources. */ | |
46e48e25 TG |
1451 | if (!desc->action) { |
1452 | ret = irq_request_resources(desc); | |
1453 | if (ret) { | |
1454 | pr_err("Failed to request resources for %s (irq %d) on irqchip %s\n", | |
1455 | new->name, irq, desc->irq_data.chip->name); | |
19d39a38 | 1456 | goto out_bus_unlock; |
46e48e25 TG |
1457 | } |
1458 | } | |
9114014c | 1459 | |
1da177e4 LT |
1460 | /* |
1461 | * The following block of code has to be executed atomically | |
19d39a38 TG |
1462 | * protected against a concurrent interrupt and any of the other |
1463 | * management calls which are not serialized via | |
1464 | * desc->request_mutex or the optional bus lock. | |
1da177e4 | 1465 | */ |
239007b8 | 1466 | raw_spin_lock_irqsave(&desc->lock, flags); |
f17c7545 IM |
1467 | old_ptr = &desc->action; |
1468 | old = *old_ptr; | |
06fcb0c6 | 1469 | if (old) { |
e76de9f8 TG |
1470 | /* |
1471 | * Can't share interrupts unless both agree to and are | |
1472 | * the same type (level, edge, polarity). So both flag | |
3cca53b0 | 1473 | * fields must have IRQF_SHARED set and the bits which |
9d591edd TG |
1474 | * set the trigger type must match. Also all must |
1475 | * agree on ONESHOT. | |
b525903c | 1476 | * Interrupt lines used for NMIs cannot be shared. |
e76de9f8 | 1477 | */ |
4f8413a3 MZ |
1478 | unsigned int oldtype; |
1479 | ||
b525903c JT |
1480 | if (desc->istate & IRQS_NMI) { |
1481 | pr_err("Invalid attempt to share NMI for %s (irq %d) on irqchip %s.\n", | |
1482 | new->name, irq, desc->irq_data.chip->name); | |
1483 | ret = -EINVAL; | |
1484 | goto out_unlock; | |
1485 | } | |
1486 | ||
4f8413a3 MZ |
1487 | /* |
1488 | * If nobody did set the configuration before, inherit | |
1489 | * the one provided by the requester. | |
1490 | */ | |
1491 | if (irqd_trigger_type_was_set(&desc->irq_data)) { | |
1492 | oldtype = irqd_get_trigger_type(&desc->irq_data); | |
1493 | } else { | |
1494 | oldtype = new->flags & IRQF_TRIGGER_MASK; | |
1495 | irqd_set_trigger_type(&desc->irq_data, oldtype); | |
1496 | } | |
382bd4de | 1497 | |
3cca53b0 | 1498 | if (!((old->flags & new->flags) & IRQF_SHARED) || |
382bd4de | 1499 | (oldtype != (new->flags & IRQF_TRIGGER_MASK)) || |
f5d89470 | 1500 | ((old->flags ^ new->flags) & IRQF_ONESHOT)) |
f5163427 DS |
1501 | goto mismatch; |
1502 | ||
f5163427 | 1503 | /* All handlers must agree on per-cpuness */ |
3cca53b0 TG |
1504 | if ((old->flags & IRQF_PERCPU) != |
1505 | (new->flags & IRQF_PERCPU)) | |
f5163427 | 1506 | goto mismatch; |
1da177e4 LT |
1507 | |
1508 | /* add new interrupt at end of irq queue */ | |
1509 | do { | |
52abb700 TG |
1510 | /* |
1511 | * Or all existing action->thread_mask bits, | |
1512 | * so we can find the next zero bit for this | |
1513 | * new action. | |
1514 | */ | |
b5faba21 | 1515 | thread_mask |= old->thread_mask; |
f17c7545 IM |
1516 | old_ptr = &old->next; |
1517 | old = *old_ptr; | |
1da177e4 LT |
1518 | } while (old); |
1519 | shared = 1; | |
1520 | } | |
1521 | ||
b5faba21 | 1522 | /* |
52abb700 TG |
1523 | * Setup the thread mask for this irqaction for ONESHOT. For |
1524 | * !ONESHOT irqs the thread mask is 0 so we can avoid a | |
1525 | * conditional in irq_wake_thread(). | |
b5faba21 | 1526 | */ |
52abb700 TG |
1527 | if (new->flags & IRQF_ONESHOT) { |
1528 | /* | |
1529 | * Unlikely to have 32 resp 64 irqs sharing one line, | |
1530 | * but who knows. | |
1531 | */ | |
1532 | if (thread_mask == ~0UL) { | |
1533 | ret = -EBUSY; | |
cba4235e | 1534 | goto out_unlock; |
52abb700 TG |
1535 | } |
1536 | /* | |
1537 | * The thread_mask for the action is or'ed to | |
1538 | * desc->thread_active to indicate that the | |
1539 | * IRQF_ONESHOT thread handler has been woken, but not | |
1540 | * yet finished. The bit is cleared when a thread | |
1541 | * completes. When all threads of a shared interrupt | |
1542 | * line have completed desc->threads_active becomes | |
1543 | * zero and the interrupt line is unmasked. See | |
1544 | * handle.c:irq_wake_thread() for further information. | |
1545 | * | |
1546 | * If no thread is woken by primary (hard irq context) | |
1547 | * interrupt handlers, then desc->threads_active is | |
1548 | * also checked for zero to unmask the irq line in the | |
1549 | * affected hard irq flow handlers | |
1550 | * (handle_[fasteoi|level]_irq). | |
1551 | * | |
1552 | * The new action gets the first zero bit of | |
1553 | * thread_mask assigned. See the loop above which or's | |
1554 | * all existing action->thread_mask bits. | |
1555 | */ | |
ffc661c9 | 1556 | new->thread_mask = 1UL << ffz(thread_mask); |
1c6c6952 | 1557 | |
dc9b229a TG |
1558 | } else if (new->handler == irq_default_primary_handler && |
1559 | !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) { | |
1c6c6952 TG |
1560 | /* |
1561 | * The interrupt was requested with handler = NULL, so | |
1562 | * we use the default primary handler for it. But it | |
1563 | * does not have the oneshot flag set. In combination | |
1564 | * with level interrupts this is deadly, because the | |
1565 | * default primary handler just wakes the thread, then | |
1566 | * the irq lines is reenabled, but the device still | |
1567 | * has the level irq asserted. Rinse and repeat.... | |
1568 | * | |
1569 | * While this works for edge type interrupts, we play | |
1570 | * it safe and reject unconditionally because we can't | |
1571 | * say for sure which type this interrupt really | |
1572 | * has. The type flags are unreliable as the | |
1573 | * underlying chip implementation can override them. | |
1574 | */ | |
025af39b LC |
1575 | pr_err("Threaded irq requested with handler=NULL and !ONESHOT for %s (irq %d)\n", |
1576 | new->name, irq); | |
1c6c6952 | 1577 | ret = -EINVAL; |
cba4235e | 1578 | goto out_unlock; |
b5faba21 | 1579 | } |
b5faba21 | 1580 | |
1da177e4 | 1581 | if (!shared) { |
3aa551c9 TG |
1582 | init_waitqueue_head(&desc->wait_for_threads); |
1583 | ||
e76de9f8 | 1584 | /* Setup the type (level, edge polarity) if configured: */ |
3cca53b0 | 1585 | if (new->flags & IRQF_TRIGGER_MASK) { |
a1ff541a JL |
1586 | ret = __irq_set_trigger(desc, |
1587 | new->flags & IRQF_TRIGGER_MASK); | |
82736f4d | 1588 | |
19d39a38 | 1589 | if (ret) |
cba4235e | 1590 | goto out_unlock; |
091738a2 | 1591 | } |
6a6de9ef | 1592 | |
c942cee4 TG |
1593 | /* |
1594 | * Activate the interrupt. That activation must happen | |
1595 | * independently of IRQ_NOAUTOEN. request_irq() can fail | |
1596 | * and the callers are supposed to handle | |
1597 | * that. enable_irq() of an interrupt requested with | |
1598 | * IRQ_NOAUTOEN is not supposed to fail. The activation | |
1599 | * keeps it in shutdown mode, it merily associates | |
1600 | * resources if necessary and if that's not possible it | |
1601 | * fails. Interrupts which are in managed shutdown mode | |
1602 | * will simply ignore that activation request. | |
1603 | */ | |
1604 | ret = irq_activate(desc); | |
1605 | if (ret) | |
1606 | goto out_unlock; | |
1607 | ||
009b4c3b | 1608 | desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \ |
32f4125e TG |
1609 | IRQS_ONESHOT | IRQS_WAITING); |
1610 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
94d39e1f | 1611 | |
a005677b TG |
1612 | if (new->flags & IRQF_PERCPU) { |
1613 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
1614 | irq_settings_set_per_cpu(desc); | |
1615 | } | |
6a58fb3b | 1616 | |
b25c340c | 1617 | if (new->flags & IRQF_ONESHOT) |
3d67baec | 1618 | desc->istate |= IRQS_ONESHOT; |
b25c340c | 1619 | |
2e051552 TG |
1620 | /* Exclude IRQ from balancing if requested */ |
1621 | if (new->flags & IRQF_NOBALANCING) { | |
1622 | irq_settings_set_no_balancing(desc); | |
1623 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
1624 | } | |
1625 | ||
04c848d3 | 1626 | if (irq_settings_can_autoenable(desc)) { |
4cde9c6b | 1627 | irq_startup(desc, IRQ_RESEND, IRQ_START_COND); |
04c848d3 TG |
1628 | } else { |
1629 | /* | |
1630 | * Shared interrupts do not go well with disabling | |
1631 | * auto enable. The sharing interrupt might request | |
1632 | * it while it's still disabled and then wait for | |
1633 | * interrupts forever. | |
1634 | */ | |
1635 | WARN_ON_ONCE(new->flags & IRQF_SHARED); | |
e76de9f8 TG |
1636 | /* Undo nested disables: */ |
1637 | desc->depth = 1; | |
04c848d3 | 1638 | } |
18404756 | 1639 | |
876dbd4c TG |
1640 | } else if (new->flags & IRQF_TRIGGER_MASK) { |
1641 | unsigned int nmsk = new->flags & IRQF_TRIGGER_MASK; | |
7ee7e87d | 1642 | unsigned int omsk = irqd_get_trigger_type(&desc->irq_data); |
876dbd4c TG |
1643 | |
1644 | if (nmsk != omsk) | |
1645 | /* hope the handler works with current trigger mode */ | |
a395d6a7 | 1646 | pr_warn("irq %d uses trigger mode %u; requested %u\n", |
7ee7e87d | 1647 | irq, omsk, nmsk); |
1da177e4 | 1648 | } |
82736f4d | 1649 | |
f17c7545 | 1650 | *old_ptr = new; |
82736f4d | 1651 | |
cab303be TG |
1652 | irq_pm_install_action(desc, new); |
1653 | ||
8528b0f1 LT |
1654 | /* Reset broken irq detection when installing new handler */ |
1655 | desc->irq_count = 0; | |
1656 | desc->irqs_unhandled = 0; | |
1adb0850 TG |
1657 | |
1658 | /* | |
1659 | * Check whether we disabled the irq via the spurious handler | |
1660 | * before. Reenable it and give it another chance. | |
1661 | */ | |
7acdd53e TG |
1662 | if (shared && (desc->istate & IRQS_SPURIOUS_DISABLED)) { |
1663 | desc->istate &= ~IRQS_SPURIOUS_DISABLED; | |
79ff1cda | 1664 | __enable_irq(desc); |
1adb0850 TG |
1665 | } |
1666 | ||
239007b8 | 1667 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3a90795e | 1668 | chip_bus_sync_unlock(desc); |
9114014c | 1669 | mutex_unlock(&desc->request_mutex); |
1da177e4 | 1670 | |
b2d3d61a DL |
1671 | irq_setup_timings(desc, new); |
1672 | ||
69ab8494 TG |
1673 | /* |
1674 | * Strictly no need to wake it up, but hung_task complains | |
1675 | * when no hard interrupt wakes the thread up. | |
1676 | */ | |
1677 | if (new->thread) | |
1678 | wake_up_process(new->thread); | |
2a1d3ab8 TG |
1679 | if (new->secondary) |
1680 | wake_up_process(new->secondary->thread); | |
69ab8494 | 1681 | |
2c6927a3 | 1682 | register_irq_proc(irq, desc); |
1da177e4 LT |
1683 | new->dir = NULL; |
1684 | register_handler_proc(irq, new); | |
1da177e4 | 1685 | return 0; |
f5163427 DS |
1686 | |
1687 | mismatch: | |
3cca53b0 | 1688 | if (!(new->flags & IRQF_PROBE_SHARED)) { |
97fd75b7 | 1689 | pr_err("Flags mismatch irq %d. %08x (%s) vs. %08x (%s)\n", |
f5d89470 TG |
1690 | irq, new->flags, new->name, old->flags, old->name); |
1691 | #ifdef CONFIG_DEBUG_SHIRQ | |
13e87ec6 | 1692 | dump_stack(); |
3f050447 | 1693 | #endif |
f5d89470 | 1694 | } |
3aa551c9 TG |
1695 | ret = -EBUSY; |
1696 | ||
cba4235e | 1697 | out_unlock: |
1c389795 | 1698 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3b8249e7 | 1699 | |
46e48e25 TG |
1700 | if (!desc->action) |
1701 | irq_release_resources(desc); | |
19d39a38 TG |
1702 | out_bus_unlock: |
1703 | chip_bus_sync_unlock(desc); | |
9114014c TG |
1704 | mutex_unlock(&desc->request_mutex); |
1705 | ||
3aa551c9 | 1706 | out_thread: |
3aa551c9 TG |
1707 | if (new->thread) { |
1708 | struct task_struct *t = new->thread; | |
1709 | ||
1710 | new->thread = NULL; | |
05d74efa | 1711 | kthread_stop(t); |
3aa551c9 TG |
1712 | put_task_struct(t); |
1713 | } | |
2a1d3ab8 TG |
1714 | if (new->secondary && new->secondary->thread) { |
1715 | struct task_struct *t = new->secondary->thread; | |
1716 | ||
1717 | new->secondary->thread = NULL; | |
1718 | kthread_stop(t); | |
1719 | put_task_struct(t); | |
1720 | } | |
b6873807 SAS |
1721 | out_mput: |
1722 | module_put(desc->owner); | |
3aa551c9 | 1723 | return ret; |
1da177e4 LT |
1724 | } |
1725 | ||
31d9d9b6 | 1726 | /* |
cbf94f06 MD |
1727 | * Internal function to unregister an irqaction - used to free |
1728 | * regular and special interrupts that are part of the architecture. | |
1da177e4 | 1729 | */ |
83ac4ca9 | 1730 | static struct irqaction *__free_irq(struct irq_desc *desc, void *dev_id) |
1da177e4 | 1731 | { |
83ac4ca9 | 1732 | unsigned irq = desc->irq_data.irq; |
f17c7545 | 1733 | struct irqaction *action, **action_ptr; |
1da177e4 LT |
1734 | unsigned long flags; |
1735 | ||
ae88a23b | 1736 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); |
7d94f7ca | 1737 | |
9114014c | 1738 | mutex_lock(&desc->request_mutex); |
abc7e40c | 1739 | chip_bus_lock(desc); |
239007b8 | 1740 | raw_spin_lock_irqsave(&desc->lock, flags); |
ae88a23b IM |
1741 | |
1742 | /* | |
1743 | * There can be multiple actions per IRQ descriptor, find the right | |
1744 | * one based on the dev_id: | |
1745 | */ | |
f17c7545 | 1746 | action_ptr = &desc->action; |
1da177e4 | 1747 | for (;;) { |
f17c7545 | 1748 | action = *action_ptr; |
1da177e4 | 1749 | |
ae88a23b IM |
1750 | if (!action) { |
1751 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
239007b8 | 1752 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
abc7e40c | 1753 | chip_bus_sync_unlock(desc); |
19d39a38 | 1754 | mutex_unlock(&desc->request_mutex); |
f21cfb25 | 1755 | return NULL; |
ae88a23b | 1756 | } |
1da177e4 | 1757 | |
8316e381 IM |
1758 | if (action->dev_id == dev_id) |
1759 | break; | |
f17c7545 | 1760 | action_ptr = &action->next; |
ae88a23b | 1761 | } |
dbce706e | 1762 | |
ae88a23b | 1763 | /* Found it - now remove it from the list of entries: */ |
f17c7545 | 1764 | *action_ptr = action->next; |
ae88a23b | 1765 | |
cab303be TG |
1766 | irq_pm_remove_action(desc, action); |
1767 | ||
ae88a23b | 1768 | /* If this was the last handler, shut down the IRQ line: */ |
c1bacbae | 1769 | if (!desc->action) { |
e9849777 | 1770 | irq_settings_clr_disable_unlazy(desc); |
4001d8e8 | 1771 | /* Only shutdown. Deactivate after synchronize_hardirq() */ |
46999238 | 1772 | irq_shutdown(desc); |
c1bacbae | 1773 | } |
3aa551c9 | 1774 | |
e7a297b0 PWJ |
1775 | #ifdef CONFIG_SMP |
1776 | /* make sure affinity_hint is cleaned up */ | |
1777 | if (WARN_ON_ONCE(desc->affinity_hint)) | |
1778 | desc->affinity_hint = NULL; | |
1779 | #endif | |
1780 | ||
239007b8 | 1781 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
19d39a38 TG |
1782 | /* |
1783 | * Drop bus_lock here so the changes which were done in the chip | |
1784 | * callbacks above are synced out to the irq chips which hang | |
519cc865 | 1785 | * behind a slow bus (I2C, SPI) before calling synchronize_hardirq(). |
19d39a38 TG |
1786 | * |
1787 | * Aside of that the bus_lock can also be taken from the threaded | |
1788 | * handler in irq_finalize_oneshot() which results in a deadlock | |
519cc865 | 1789 | * because kthread_stop() would wait forever for the thread to |
19d39a38 TG |
1790 | * complete, which is blocked on the bus lock. |
1791 | * | |
1792 | * The still held desc->request_mutex() protects against a | |
1793 | * concurrent request_irq() of this irq so the release of resources | |
1794 | * and timing data is properly serialized. | |
1795 | */ | |
abc7e40c | 1796 | chip_bus_sync_unlock(desc); |
ae88a23b IM |
1797 | |
1798 | unregister_handler_proc(irq, action); | |
1799 | ||
62e04686 TG |
1800 | /* |
1801 | * Make sure it's not being used on another CPU and if the chip | |
1802 | * supports it also make sure that there is no (not yet serviced) | |
1803 | * interrupt in flight at the hardware level. | |
1804 | */ | |
1805 | __synchronize_hardirq(desc, true); | |
1da177e4 | 1806 | |
70edcd77 | 1807 | #ifdef CONFIG_DEBUG_SHIRQ |
ae88a23b IM |
1808 | /* |
1809 | * It's a shared IRQ -- the driver ought to be prepared for an IRQ | |
1810 | * event to happen even now it's being freed, so let's make sure that | |
1811 | * is so by doing an extra call to the handler .... | |
1812 | * | |
1813 | * ( We do this after actually deregistering it, to make sure that a | |
0a13ec0b | 1814 | * 'real' IRQ doesn't run in parallel with our fake. ) |
ae88a23b IM |
1815 | */ |
1816 | if (action->flags & IRQF_SHARED) { | |
1817 | local_irq_save(flags); | |
1818 | action->handler(irq, dev_id); | |
1819 | local_irq_restore(flags); | |
1da177e4 | 1820 | } |
ae88a23b | 1821 | #endif |
2d860ad7 | 1822 | |
519cc865 LW |
1823 | /* |
1824 | * The action has already been removed above, but the thread writes | |
1825 | * its oneshot mask bit when it completes. Though request_mutex is | |
1826 | * held across this which prevents __setup_irq() from handing out | |
1827 | * the same bit to a newly requested action. | |
1828 | */ | |
2d860ad7 | 1829 | if (action->thread) { |
05d74efa | 1830 | kthread_stop(action->thread); |
2d860ad7 | 1831 | put_task_struct(action->thread); |
2a1d3ab8 TG |
1832 | if (action->secondary && action->secondary->thread) { |
1833 | kthread_stop(action->secondary->thread); | |
1834 | put_task_struct(action->secondary->thread); | |
1835 | } | |
2d860ad7 LT |
1836 | } |
1837 | ||
19d39a38 | 1838 | /* Last action releases resources */ |
2343877f | 1839 | if (!desc->action) { |
19d39a38 TG |
1840 | /* |
1841 | * Reaquire bus lock as irq_release_resources() might | |
1842 | * require it to deallocate resources over the slow bus. | |
1843 | */ | |
1844 | chip_bus_lock(desc); | |
4001d8e8 TG |
1845 | /* |
1846 | * There is no interrupt on the fly anymore. Deactivate it | |
1847 | * completely. | |
1848 | */ | |
1849 | raw_spin_lock_irqsave(&desc->lock, flags); | |
1850 | irq_domain_deactivate_irq(&desc->irq_data); | |
1851 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1852 | ||
46e48e25 | 1853 | irq_release_resources(desc); |
19d39a38 | 1854 | chip_bus_sync_unlock(desc); |
2343877f TG |
1855 | irq_remove_timings(desc); |
1856 | } | |
46e48e25 | 1857 | |
9114014c TG |
1858 | mutex_unlock(&desc->request_mutex); |
1859 | ||
be45beb2 | 1860 | irq_chip_pm_put(&desc->irq_data); |
b6873807 | 1861 | module_put(desc->owner); |
2a1d3ab8 | 1862 | kfree(action->secondary); |
f21cfb25 MD |
1863 | return action; |
1864 | } | |
1865 | ||
1866 | /** | |
1867 | * free_irq - free an interrupt allocated with request_irq | |
1868 | * @irq: Interrupt line to free | |
1869 | * @dev_id: Device identity to free | |
1870 | * | |
1871 | * Remove an interrupt handler. The handler is removed and if the | |
1872 | * interrupt line is no longer in use by any driver it is disabled. | |
1873 | * On a shared IRQ the caller must ensure the interrupt is disabled | |
1874 | * on the card it drives before calling this function. The function | |
1875 | * does not return until any executing interrupts for this IRQ | |
1876 | * have completed. | |
1877 | * | |
1878 | * This function must not be called from interrupt context. | |
25ce4be7 CH |
1879 | * |
1880 | * Returns the devname argument passed to request_irq. | |
f21cfb25 | 1881 | */ |
25ce4be7 | 1882 | const void *free_irq(unsigned int irq, void *dev_id) |
f21cfb25 | 1883 | { |
70aedd24 | 1884 | struct irq_desc *desc = irq_to_desc(irq); |
25ce4be7 CH |
1885 | struct irqaction *action; |
1886 | const char *devname; | |
70aedd24 | 1887 | |
31d9d9b6 | 1888 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
25ce4be7 | 1889 | return NULL; |
70aedd24 | 1890 | |
cd7eab44 BH |
1891 | #ifdef CONFIG_SMP |
1892 | if (WARN_ON(desc->affinity_notify)) | |
1893 | desc->affinity_notify = NULL; | |
1894 | #endif | |
1895 | ||
83ac4ca9 | 1896 | action = __free_irq(desc, dev_id); |
2827a418 AM |
1897 | |
1898 | if (!action) | |
1899 | return NULL; | |
1900 | ||
25ce4be7 CH |
1901 | devname = action->name; |
1902 | kfree(action); | |
1903 | return devname; | |
1da177e4 | 1904 | } |
1da177e4 LT |
1905 | EXPORT_SYMBOL(free_irq); |
1906 | ||
b525903c JT |
1907 | /* This function must be called with desc->lock held */ |
1908 | static const void *__cleanup_nmi(unsigned int irq, struct irq_desc *desc) | |
1909 | { | |
1910 | const char *devname = NULL; | |
1911 | ||
1912 | desc->istate &= ~IRQS_NMI; | |
1913 | ||
1914 | if (!WARN_ON(desc->action == NULL)) { | |
1915 | irq_pm_remove_action(desc, desc->action); | |
1916 | devname = desc->action->name; | |
1917 | unregister_handler_proc(irq, desc->action); | |
1918 | ||
1919 | kfree(desc->action); | |
1920 | desc->action = NULL; | |
1921 | } | |
1922 | ||
1923 | irq_settings_clr_disable_unlazy(desc); | |
4001d8e8 | 1924 | irq_shutdown_and_deactivate(desc); |
b525903c JT |
1925 | |
1926 | irq_release_resources(desc); | |
1927 | ||
1928 | irq_chip_pm_put(&desc->irq_data); | |
1929 | module_put(desc->owner); | |
1930 | ||
1931 | return devname; | |
1932 | } | |
1933 | ||
1934 | const void *free_nmi(unsigned int irq, void *dev_id) | |
1935 | { | |
1936 | struct irq_desc *desc = irq_to_desc(irq); | |
1937 | unsigned long flags; | |
1938 | const void *devname; | |
1939 | ||
1940 | if (!desc || WARN_ON(!(desc->istate & IRQS_NMI))) | |
1941 | return NULL; | |
1942 | ||
1943 | if (WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
1944 | return NULL; | |
1945 | ||
1946 | /* NMI still enabled */ | |
1947 | if (WARN_ON(desc->depth == 0)) | |
1948 | disable_nmi_nosync(irq); | |
1949 | ||
1950 | raw_spin_lock_irqsave(&desc->lock, flags); | |
1951 | ||
1952 | irq_nmi_teardown(desc); | |
1953 | devname = __cleanup_nmi(irq, desc); | |
1954 | ||
1955 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1956 | ||
1957 | return devname; | |
1958 | } | |
1959 | ||
1da177e4 | 1960 | /** |
3aa551c9 | 1961 | * request_threaded_irq - allocate an interrupt line |
1da177e4 | 1962 | * @irq: Interrupt line to allocate |
3aa551c9 TG |
1963 | * @handler: Function to be called when the IRQ occurs. |
1964 | * Primary handler for threaded interrupts | |
b25c340c TG |
1965 | * If NULL and thread_fn != NULL the default |
1966 | * primary handler is installed | |
f48fe81e TG |
1967 | * @thread_fn: Function called from the irq handler thread |
1968 | * If NULL, no irq thread is created | |
1da177e4 LT |
1969 | * @irqflags: Interrupt type flags |
1970 | * @devname: An ascii name for the claiming device | |
1971 | * @dev_id: A cookie passed back to the handler function | |
1972 | * | |
1973 | * This call allocates interrupt resources and enables the | |
1974 | * interrupt line and IRQ handling. From the point this | |
1975 | * call is made your handler function may be invoked. Since | |
1976 | * your handler function must clear any interrupt the board | |
1977 | * raises, you must take care both to initialise your hardware | |
1978 | * and to set up the interrupt handler in the right order. | |
1979 | * | |
3aa551c9 | 1980 | * If you want to set up a threaded irq handler for your device |
6d21af4f | 1981 | * then you need to supply @handler and @thread_fn. @handler is |
3aa551c9 TG |
1982 | * still called in hard interrupt context and has to check |
1983 | * whether the interrupt originates from the device. If yes it | |
1984 | * needs to disable the interrupt on the device and return | |
39a2eddb | 1985 | * IRQ_WAKE_THREAD which will wake up the handler thread and run |
3aa551c9 TG |
1986 | * @thread_fn. This split handler design is necessary to support |
1987 | * shared interrupts. | |
1988 | * | |
1da177e4 LT |
1989 | * Dev_id must be globally unique. Normally the address of the |
1990 | * device data structure is used as the cookie. Since the handler | |
1991 | * receives this value it makes sense to use it. | |
1992 | * | |
1993 | * If your interrupt is shared you must pass a non NULL dev_id | |
1994 | * as this is required when freeing the interrupt. | |
1995 | * | |
1996 | * Flags: | |
1997 | * | |
3cca53b0 | 1998 | * IRQF_SHARED Interrupt is shared |
0c5d1eb7 | 1999 | * IRQF_TRIGGER_* Specify active edge(s) or level |
1da177e4 LT |
2000 | * |
2001 | */ | |
3aa551c9 TG |
2002 | int request_threaded_irq(unsigned int irq, irq_handler_t handler, |
2003 | irq_handler_t thread_fn, unsigned long irqflags, | |
2004 | const char *devname, void *dev_id) | |
1da177e4 | 2005 | { |
06fcb0c6 | 2006 | struct irqaction *action; |
08678b08 | 2007 | struct irq_desc *desc; |
d3c60047 | 2008 | int retval; |
1da177e4 | 2009 | |
e237a551 CF |
2010 | if (irq == IRQ_NOTCONNECTED) |
2011 | return -ENOTCONN; | |
2012 | ||
1da177e4 LT |
2013 | /* |
2014 | * Sanity-check: shared interrupts must pass in a real dev-ID, | |
2015 | * otherwise we'll have trouble later trying to figure out | |
2016 | * which interrupt is which (messes up the interrupt freeing | |
2017 | * logic etc). | |
17f48034 RW |
2018 | * |
2019 | * Also IRQF_COND_SUSPEND only makes sense for shared interrupts and | |
2020 | * it cannot be set along with IRQF_NO_SUSPEND. | |
1da177e4 | 2021 | */ |
17f48034 RW |
2022 | if (((irqflags & IRQF_SHARED) && !dev_id) || |
2023 | (!(irqflags & IRQF_SHARED) && (irqflags & IRQF_COND_SUSPEND)) || | |
2024 | ((irqflags & IRQF_NO_SUSPEND) && (irqflags & IRQF_COND_SUSPEND))) | |
1da177e4 | 2025 | return -EINVAL; |
7d94f7ca | 2026 | |
cb5bc832 | 2027 | desc = irq_to_desc(irq); |
7d94f7ca | 2028 | if (!desc) |
1da177e4 | 2029 | return -EINVAL; |
7d94f7ca | 2030 | |
31d9d9b6 MZ |
2031 | if (!irq_settings_can_request(desc) || |
2032 | WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
6550c775 | 2033 | return -EINVAL; |
b25c340c TG |
2034 | |
2035 | if (!handler) { | |
2036 | if (!thread_fn) | |
2037 | return -EINVAL; | |
2038 | handler = irq_default_primary_handler; | |
2039 | } | |
1da177e4 | 2040 | |
45535732 | 2041 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); |
1da177e4 LT |
2042 | if (!action) |
2043 | return -ENOMEM; | |
2044 | ||
2045 | action->handler = handler; | |
3aa551c9 | 2046 | action->thread_fn = thread_fn; |
1da177e4 | 2047 | action->flags = irqflags; |
1da177e4 | 2048 | action->name = devname; |
1da177e4 LT |
2049 | action->dev_id = dev_id; |
2050 | ||
be45beb2 | 2051 | retval = irq_chip_pm_get(&desc->irq_data); |
4396f46c SL |
2052 | if (retval < 0) { |
2053 | kfree(action); | |
be45beb2 | 2054 | return retval; |
4396f46c | 2055 | } |
be45beb2 | 2056 | |
d3c60047 | 2057 | retval = __setup_irq(irq, desc, action); |
70aedd24 | 2058 | |
2a1d3ab8 | 2059 | if (retval) { |
be45beb2 | 2060 | irq_chip_pm_put(&desc->irq_data); |
2a1d3ab8 | 2061 | kfree(action->secondary); |
377bf1e4 | 2062 | kfree(action); |
2a1d3ab8 | 2063 | } |
377bf1e4 | 2064 | |
6d83f94d | 2065 | #ifdef CONFIG_DEBUG_SHIRQ_FIXME |
6ce51c43 | 2066 | if (!retval && (irqflags & IRQF_SHARED)) { |
a304e1b8 DW |
2067 | /* |
2068 | * It's a shared IRQ -- the driver ought to be prepared for it | |
2069 | * to happen immediately, so let's make sure.... | |
377bf1e4 AV |
2070 | * We disable the irq to make sure that a 'real' IRQ doesn't |
2071 | * run in parallel with our fake. | |
a304e1b8 | 2072 | */ |
59845b1f | 2073 | unsigned long flags; |
a304e1b8 | 2074 | |
377bf1e4 | 2075 | disable_irq(irq); |
59845b1f | 2076 | local_irq_save(flags); |
377bf1e4 | 2077 | |
59845b1f | 2078 | handler(irq, dev_id); |
377bf1e4 | 2079 | |
59845b1f | 2080 | local_irq_restore(flags); |
377bf1e4 | 2081 | enable_irq(irq); |
a304e1b8 DW |
2082 | } |
2083 | #endif | |
1da177e4 LT |
2084 | return retval; |
2085 | } | |
3aa551c9 | 2086 | EXPORT_SYMBOL(request_threaded_irq); |
ae731f8d MZ |
2087 | |
2088 | /** | |
2089 | * request_any_context_irq - allocate an interrupt line | |
2090 | * @irq: Interrupt line to allocate | |
2091 | * @handler: Function to be called when the IRQ occurs. | |
2092 | * Threaded handler for threaded interrupts. | |
2093 | * @flags: Interrupt type flags | |
2094 | * @name: An ascii name for the claiming device | |
2095 | * @dev_id: A cookie passed back to the handler function | |
2096 | * | |
2097 | * This call allocates interrupt resources and enables the | |
2098 | * interrupt line and IRQ handling. It selects either a | |
2099 | * hardirq or threaded handling method depending on the | |
2100 | * context. | |
2101 | * | |
2102 | * On failure, it returns a negative value. On success, | |
2103 | * it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED. | |
2104 | */ | |
2105 | int request_any_context_irq(unsigned int irq, irq_handler_t handler, | |
2106 | unsigned long flags, const char *name, void *dev_id) | |
2107 | { | |
e237a551 | 2108 | struct irq_desc *desc; |
ae731f8d MZ |
2109 | int ret; |
2110 | ||
e237a551 CF |
2111 | if (irq == IRQ_NOTCONNECTED) |
2112 | return -ENOTCONN; | |
2113 | ||
2114 | desc = irq_to_desc(irq); | |
ae731f8d MZ |
2115 | if (!desc) |
2116 | return -EINVAL; | |
2117 | ||
1ccb4e61 | 2118 | if (irq_settings_is_nested_thread(desc)) { |
ae731f8d MZ |
2119 | ret = request_threaded_irq(irq, NULL, handler, |
2120 | flags, name, dev_id); | |
2121 | return !ret ? IRQC_IS_NESTED : ret; | |
2122 | } | |
2123 | ||
2124 | ret = request_irq(irq, handler, flags, name, dev_id); | |
2125 | return !ret ? IRQC_IS_HARDIRQ : ret; | |
2126 | } | |
2127 | EXPORT_SYMBOL_GPL(request_any_context_irq); | |
31d9d9b6 | 2128 | |
b525903c JT |
2129 | /** |
2130 | * request_nmi - allocate an interrupt line for NMI delivery | |
2131 | * @irq: Interrupt line to allocate | |
2132 | * @handler: Function to be called when the IRQ occurs. | |
2133 | * Threaded handler for threaded interrupts. | |
2134 | * @irqflags: Interrupt type flags | |
2135 | * @name: An ascii name for the claiming device | |
2136 | * @dev_id: A cookie passed back to the handler function | |
2137 | * | |
2138 | * This call allocates interrupt resources and enables the | |
2139 | * interrupt line and IRQ handling. It sets up the IRQ line | |
2140 | * to be handled as an NMI. | |
2141 | * | |
2142 | * An interrupt line delivering NMIs cannot be shared and IRQ handling | |
2143 | * cannot be threaded. | |
2144 | * | |
2145 | * Interrupt lines requested for NMI delivering must produce per cpu | |
2146 | * interrupts and have auto enabling setting disabled. | |
2147 | * | |
2148 | * Dev_id must be globally unique. Normally the address of the | |
2149 | * device data structure is used as the cookie. Since the handler | |
2150 | * receives this value it makes sense to use it. | |
2151 | * | |
2152 | * If the interrupt line cannot be used to deliver NMIs, function | |
2153 | * will fail and return a negative value. | |
2154 | */ | |
2155 | int request_nmi(unsigned int irq, irq_handler_t handler, | |
2156 | unsigned long irqflags, const char *name, void *dev_id) | |
2157 | { | |
2158 | struct irqaction *action; | |
2159 | struct irq_desc *desc; | |
2160 | unsigned long flags; | |
2161 | int retval; | |
2162 | ||
2163 | if (irq == IRQ_NOTCONNECTED) | |
2164 | return -ENOTCONN; | |
2165 | ||
2166 | /* NMI cannot be shared, used for Polling */ | |
2167 | if (irqflags & (IRQF_SHARED | IRQF_COND_SUSPEND | IRQF_IRQPOLL)) | |
2168 | return -EINVAL; | |
2169 | ||
2170 | if (!(irqflags & IRQF_PERCPU)) | |
2171 | return -EINVAL; | |
2172 | ||
2173 | if (!handler) | |
2174 | return -EINVAL; | |
2175 | ||
2176 | desc = irq_to_desc(irq); | |
2177 | ||
2178 | if (!desc || irq_settings_can_autoenable(desc) || | |
2179 | !irq_settings_can_request(desc) || | |
2180 | WARN_ON(irq_settings_is_per_cpu_devid(desc)) || | |
2181 | !irq_supports_nmi(desc)) | |
2182 | return -EINVAL; | |
2183 | ||
2184 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
2185 | if (!action) | |
2186 | return -ENOMEM; | |
2187 | ||
2188 | action->handler = handler; | |
2189 | action->flags = irqflags | IRQF_NO_THREAD | IRQF_NOBALANCING; | |
2190 | action->name = name; | |
2191 | action->dev_id = dev_id; | |
2192 | ||
2193 | retval = irq_chip_pm_get(&desc->irq_data); | |
2194 | if (retval < 0) | |
2195 | goto err_out; | |
2196 | ||
2197 | retval = __setup_irq(irq, desc, action); | |
2198 | if (retval) | |
2199 | goto err_irq_setup; | |
2200 | ||
2201 | raw_spin_lock_irqsave(&desc->lock, flags); | |
2202 | ||
2203 | /* Setup NMI state */ | |
2204 | desc->istate |= IRQS_NMI; | |
2205 | retval = irq_nmi_setup(desc); | |
2206 | if (retval) { | |
2207 | __cleanup_nmi(irq, desc); | |
2208 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2209 | return -EINVAL; | |
2210 | } | |
2211 | ||
2212 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2213 | ||
2214 | return 0; | |
2215 | ||
2216 | err_irq_setup: | |
2217 | irq_chip_pm_put(&desc->irq_data); | |
2218 | err_out: | |
2219 | kfree(action); | |
2220 | ||
2221 | return retval; | |
2222 | } | |
2223 | ||
1e7c5fd2 | 2224 | void enable_percpu_irq(unsigned int irq, unsigned int type) |
31d9d9b6 MZ |
2225 | { |
2226 | unsigned int cpu = smp_processor_id(); | |
2227 | unsigned long flags; | |
2228 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
2229 | ||
2230 | if (!desc) | |
2231 | return; | |
2232 | ||
f35ad083 MZ |
2233 | /* |
2234 | * If the trigger type is not specified by the caller, then | |
2235 | * use the default for this interrupt. | |
2236 | */ | |
1e7c5fd2 | 2237 | type &= IRQ_TYPE_SENSE_MASK; |
f35ad083 MZ |
2238 | if (type == IRQ_TYPE_NONE) |
2239 | type = irqd_get_trigger_type(&desc->irq_data); | |
2240 | ||
1e7c5fd2 MZ |
2241 | if (type != IRQ_TYPE_NONE) { |
2242 | int ret; | |
2243 | ||
a1ff541a | 2244 | ret = __irq_set_trigger(desc, type); |
1e7c5fd2 MZ |
2245 | |
2246 | if (ret) { | |
32cffdde | 2247 | WARN(1, "failed to set type for IRQ%d\n", irq); |
1e7c5fd2 MZ |
2248 | goto out; |
2249 | } | |
2250 | } | |
2251 | ||
31d9d9b6 | 2252 | irq_percpu_enable(desc, cpu); |
1e7c5fd2 | 2253 | out: |
31d9d9b6 MZ |
2254 | irq_put_desc_unlock(desc, flags); |
2255 | } | |
36a5df85 | 2256 | EXPORT_SYMBOL_GPL(enable_percpu_irq); |
31d9d9b6 | 2257 | |
4b078c3f JT |
2258 | void enable_percpu_nmi(unsigned int irq, unsigned int type) |
2259 | { | |
2260 | enable_percpu_irq(irq, type); | |
2261 | } | |
2262 | ||
f0cb3220 TP |
2263 | /** |
2264 | * irq_percpu_is_enabled - Check whether the per cpu irq is enabled | |
2265 | * @irq: Linux irq number to check for | |
2266 | * | |
2267 | * Must be called from a non migratable context. Returns the enable | |
2268 | * state of a per cpu interrupt on the current cpu. | |
2269 | */ | |
2270 | bool irq_percpu_is_enabled(unsigned int irq) | |
2271 | { | |
2272 | unsigned int cpu = smp_processor_id(); | |
2273 | struct irq_desc *desc; | |
2274 | unsigned long flags; | |
2275 | bool is_enabled; | |
2276 | ||
2277 | desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
2278 | if (!desc) | |
2279 | return false; | |
2280 | ||
2281 | is_enabled = cpumask_test_cpu(cpu, desc->percpu_enabled); | |
2282 | irq_put_desc_unlock(desc, flags); | |
2283 | ||
2284 | return is_enabled; | |
2285 | } | |
2286 | EXPORT_SYMBOL_GPL(irq_percpu_is_enabled); | |
2287 | ||
31d9d9b6 MZ |
2288 | void disable_percpu_irq(unsigned int irq) |
2289 | { | |
2290 | unsigned int cpu = smp_processor_id(); | |
2291 | unsigned long flags; | |
2292 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
2293 | ||
2294 | if (!desc) | |
2295 | return; | |
2296 | ||
2297 | irq_percpu_disable(desc, cpu); | |
2298 | irq_put_desc_unlock(desc, flags); | |
2299 | } | |
36a5df85 | 2300 | EXPORT_SYMBOL_GPL(disable_percpu_irq); |
31d9d9b6 | 2301 | |
4b078c3f JT |
2302 | void disable_percpu_nmi(unsigned int irq) |
2303 | { | |
2304 | disable_percpu_irq(irq); | |
2305 | } | |
2306 | ||
31d9d9b6 MZ |
2307 | /* |
2308 | * Internal function to unregister a percpu irqaction. | |
2309 | */ | |
2310 | static struct irqaction *__free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
2311 | { | |
2312 | struct irq_desc *desc = irq_to_desc(irq); | |
2313 | struct irqaction *action; | |
2314 | unsigned long flags; | |
2315 | ||
2316 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); | |
2317 | ||
2318 | if (!desc) | |
2319 | return NULL; | |
2320 | ||
2321 | raw_spin_lock_irqsave(&desc->lock, flags); | |
2322 | ||
2323 | action = desc->action; | |
2324 | if (!action || action->percpu_dev_id != dev_id) { | |
2325 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
2326 | goto bad; | |
2327 | } | |
2328 | ||
2329 | if (!cpumask_empty(desc->percpu_enabled)) { | |
2330 | WARN(1, "percpu IRQ %d still enabled on CPU%d!\n", | |
2331 | irq, cpumask_first(desc->percpu_enabled)); | |
2332 | goto bad; | |
2333 | } | |
2334 | ||
2335 | /* Found it - now remove it from the list of entries: */ | |
2336 | desc->action = NULL; | |
2337 | ||
4b078c3f JT |
2338 | desc->istate &= ~IRQS_NMI; |
2339 | ||
31d9d9b6 MZ |
2340 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
2341 | ||
2342 | unregister_handler_proc(irq, action); | |
2343 | ||
be45beb2 | 2344 | irq_chip_pm_put(&desc->irq_data); |
31d9d9b6 MZ |
2345 | module_put(desc->owner); |
2346 | return action; | |
2347 | ||
2348 | bad: | |
2349 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2350 | return NULL; | |
2351 | } | |
2352 | ||
2353 | /** | |
2354 | * remove_percpu_irq - free a per-cpu interrupt | |
2355 | * @irq: Interrupt line to free | |
2356 | * @act: irqaction for the interrupt | |
2357 | * | |
2358 | * Used to remove interrupts statically setup by the early boot process. | |
2359 | */ | |
2360 | void remove_percpu_irq(unsigned int irq, struct irqaction *act) | |
2361 | { | |
2362 | struct irq_desc *desc = irq_to_desc(irq); | |
2363 | ||
2364 | if (desc && irq_settings_is_per_cpu_devid(desc)) | |
2365 | __free_percpu_irq(irq, act->percpu_dev_id); | |
2366 | } | |
2367 | ||
2368 | /** | |
2369 | * free_percpu_irq - free an interrupt allocated with request_percpu_irq | |
2370 | * @irq: Interrupt line to free | |
2371 | * @dev_id: Device identity to free | |
2372 | * | |
2373 | * Remove a percpu interrupt handler. The handler is removed, but | |
2374 | * the interrupt line is not disabled. This must be done on each | |
2375 | * CPU before calling this function. The function does not return | |
2376 | * until any executing interrupts for this IRQ have completed. | |
2377 | * | |
2378 | * This function must not be called from interrupt context. | |
2379 | */ | |
2380 | void free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
2381 | { | |
2382 | struct irq_desc *desc = irq_to_desc(irq); | |
2383 | ||
2384 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
2385 | return; | |
2386 | ||
2387 | chip_bus_lock(desc); | |
2388 | kfree(__free_percpu_irq(irq, dev_id)); | |
2389 | chip_bus_sync_unlock(desc); | |
2390 | } | |
aec2e2ad | 2391 | EXPORT_SYMBOL_GPL(free_percpu_irq); |
31d9d9b6 | 2392 | |
4b078c3f JT |
2393 | void free_percpu_nmi(unsigned int irq, void __percpu *dev_id) |
2394 | { | |
2395 | struct irq_desc *desc = irq_to_desc(irq); | |
2396 | ||
2397 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
2398 | return; | |
2399 | ||
2400 | if (WARN_ON(!(desc->istate & IRQS_NMI))) | |
2401 | return; | |
2402 | ||
2403 | kfree(__free_percpu_irq(irq, dev_id)); | |
2404 | } | |
2405 | ||
31d9d9b6 MZ |
2406 | /** |
2407 | * setup_percpu_irq - setup a per-cpu interrupt | |
2408 | * @irq: Interrupt line to setup | |
2409 | * @act: irqaction for the interrupt | |
2410 | * | |
2411 | * Used to statically setup per-cpu interrupts in the early boot process. | |
2412 | */ | |
2413 | int setup_percpu_irq(unsigned int irq, struct irqaction *act) | |
2414 | { | |
2415 | struct irq_desc *desc = irq_to_desc(irq); | |
2416 | int retval; | |
2417 | ||
2418 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
2419 | return -EINVAL; | |
be45beb2 JH |
2420 | |
2421 | retval = irq_chip_pm_get(&desc->irq_data); | |
2422 | if (retval < 0) | |
2423 | return retval; | |
2424 | ||
31d9d9b6 | 2425 | retval = __setup_irq(irq, desc, act); |
31d9d9b6 | 2426 | |
be45beb2 JH |
2427 | if (retval) |
2428 | irq_chip_pm_put(&desc->irq_data); | |
2429 | ||
31d9d9b6 MZ |
2430 | return retval; |
2431 | } | |
2432 | ||
2433 | /** | |
c80081b9 | 2434 | * __request_percpu_irq - allocate a percpu interrupt line |
31d9d9b6 MZ |
2435 | * @irq: Interrupt line to allocate |
2436 | * @handler: Function to be called when the IRQ occurs. | |
c80081b9 | 2437 | * @flags: Interrupt type flags (IRQF_TIMER only) |
31d9d9b6 MZ |
2438 | * @devname: An ascii name for the claiming device |
2439 | * @dev_id: A percpu cookie passed back to the handler function | |
2440 | * | |
a1b7febd MR |
2441 | * This call allocates interrupt resources and enables the |
2442 | * interrupt on the local CPU. If the interrupt is supposed to be | |
2443 | * enabled on other CPUs, it has to be done on each CPU using | |
2444 | * enable_percpu_irq(). | |
31d9d9b6 MZ |
2445 | * |
2446 | * Dev_id must be globally unique. It is a per-cpu variable, and | |
2447 | * the handler gets called with the interrupted CPU's instance of | |
2448 | * that variable. | |
2449 | */ | |
c80081b9 DL |
2450 | int __request_percpu_irq(unsigned int irq, irq_handler_t handler, |
2451 | unsigned long flags, const char *devname, | |
2452 | void __percpu *dev_id) | |
31d9d9b6 MZ |
2453 | { |
2454 | struct irqaction *action; | |
2455 | struct irq_desc *desc; | |
2456 | int retval; | |
2457 | ||
2458 | if (!dev_id) | |
2459 | return -EINVAL; | |
2460 | ||
2461 | desc = irq_to_desc(irq); | |
2462 | if (!desc || !irq_settings_can_request(desc) || | |
2463 | !irq_settings_is_per_cpu_devid(desc)) | |
2464 | return -EINVAL; | |
2465 | ||
c80081b9 DL |
2466 | if (flags && flags != IRQF_TIMER) |
2467 | return -EINVAL; | |
2468 | ||
31d9d9b6 MZ |
2469 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); |
2470 | if (!action) | |
2471 | return -ENOMEM; | |
2472 | ||
2473 | action->handler = handler; | |
c80081b9 | 2474 | action->flags = flags | IRQF_PERCPU | IRQF_NO_SUSPEND; |
31d9d9b6 MZ |
2475 | action->name = devname; |
2476 | action->percpu_dev_id = dev_id; | |
2477 | ||
be45beb2 | 2478 | retval = irq_chip_pm_get(&desc->irq_data); |
4396f46c SL |
2479 | if (retval < 0) { |
2480 | kfree(action); | |
be45beb2 | 2481 | return retval; |
4396f46c | 2482 | } |
be45beb2 | 2483 | |
31d9d9b6 | 2484 | retval = __setup_irq(irq, desc, action); |
31d9d9b6 | 2485 | |
be45beb2 JH |
2486 | if (retval) { |
2487 | irq_chip_pm_put(&desc->irq_data); | |
31d9d9b6 | 2488 | kfree(action); |
be45beb2 | 2489 | } |
31d9d9b6 MZ |
2490 | |
2491 | return retval; | |
2492 | } | |
c80081b9 | 2493 | EXPORT_SYMBOL_GPL(__request_percpu_irq); |
1b7047ed | 2494 | |
4b078c3f JT |
2495 | /** |
2496 | * request_percpu_nmi - allocate a percpu interrupt line for NMI delivery | |
2497 | * @irq: Interrupt line to allocate | |
2498 | * @handler: Function to be called when the IRQ occurs. | |
2499 | * @name: An ascii name for the claiming device | |
2500 | * @dev_id: A percpu cookie passed back to the handler function | |
2501 | * | |
2502 | * This call allocates interrupt resources for a per CPU NMI. Per CPU NMIs | |
a5186694 JT |
2503 | * have to be setup on each CPU by calling prepare_percpu_nmi() before |
2504 | * being enabled on the same CPU by using enable_percpu_nmi(). | |
4b078c3f JT |
2505 | * |
2506 | * Dev_id must be globally unique. It is a per-cpu variable, and | |
2507 | * the handler gets called with the interrupted CPU's instance of | |
2508 | * that variable. | |
2509 | * | |
2510 | * Interrupt lines requested for NMI delivering should have auto enabling | |
2511 | * setting disabled. | |
2512 | * | |
2513 | * If the interrupt line cannot be used to deliver NMIs, function | |
2514 | * will fail returning a negative value. | |
2515 | */ | |
2516 | int request_percpu_nmi(unsigned int irq, irq_handler_t handler, | |
2517 | const char *name, void __percpu *dev_id) | |
2518 | { | |
2519 | struct irqaction *action; | |
2520 | struct irq_desc *desc; | |
2521 | unsigned long flags; | |
2522 | int retval; | |
2523 | ||
2524 | if (!handler) | |
2525 | return -EINVAL; | |
2526 | ||
2527 | desc = irq_to_desc(irq); | |
2528 | ||
2529 | if (!desc || !irq_settings_can_request(desc) || | |
2530 | !irq_settings_is_per_cpu_devid(desc) || | |
2531 | irq_settings_can_autoenable(desc) || | |
2532 | !irq_supports_nmi(desc)) | |
2533 | return -EINVAL; | |
2534 | ||
2535 | /* The line cannot already be NMI */ | |
2536 | if (desc->istate & IRQS_NMI) | |
2537 | return -EINVAL; | |
2538 | ||
2539 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
2540 | if (!action) | |
2541 | return -ENOMEM; | |
2542 | ||
2543 | action->handler = handler; | |
2544 | action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND | IRQF_NO_THREAD | |
2545 | | IRQF_NOBALANCING; | |
2546 | action->name = name; | |
2547 | action->percpu_dev_id = dev_id; | |
2548 | ||
2549 | retval = irq_chip_pm_get(&desc->irq_data); | |
2550 | if (retval < 0) | |
2551 | goto err_out; | |
2552 | ||
2553 | retval = __setup_irq(irq, desc, action); | |
2554 | if (retval) | |
2555 | goto err_irq_setup; | |
2556 | ||
2557 | raw_spin_lock_irqsave(&desc->lock, flags); | |
2558 | desc->istate |= IRQS_NMI; | |
2559 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2560 | ||
2561 | return 0; | |
2562 | ||
2563 | err_irq_setup: | |
2564 | irq_chip_pm_put(&desc->irq_data); | |
2565 | err_out: | |
2566 | kfree(action); | |
2567 | ||
2568 | return retval; | |
2569 | } | |
2570 | ||
2571 | /** | |
2572 | * prepare_percpu_nmi - performs CPU local setup for NMI delivery | |
2573 | * @irq: Interrupt line to prepare for NMI delivery | |
2574 | * | |
2575 | * This call prepares an interrupt line to deliver NMI on the current CPU, | |
2576 | * before that interrupt line gets enabled with enable_percpu_nmi(). | |
2577 | * | |
2578 | * As a CPU local operation, this should be called from non-preemptible | |
2579 | * context. | |
2580 | * | |
2581 | * If the interrupt line cannot be used to deliver NMIs, function | |
2582 | * will fail returning a negative value. | |
2583 | */ | |
2584 | int prepare_percpu_nmi(unsigned int irq) | |
2585 | { | |
2586 | unsigned long flags; | |
2587 | struct irq_desc *desc; | |
2588 | int ret = 0; | |
2589 | ||
2590 | WARN_ON(preemptible()); | |
2591 | ||
2592 | desc = irq_get_desc_lock(irq, &flags, | |
2593 | IRQ_GET_DESC_CHECK_PERCPU); | |
2594 | if (!desc) | |
2595 | return -EINVAL; | |
2596 | ||
2597 | if (WARN(!(desc->istate & IRQS_NMI), | |
2598 | KERN_ERR "prepare_percpu_nmi called for a non-NMI interrupt: irq %u\n", | |
2599 | irq)) { | |
2600 | ret = -EINVAL; | |
2601 | goto out; | |
2602 | } | |
2603 | ||
2604 | ret = irq_nmi_setup(desc); | |
2605 | if (ret) { | |
2606 | pr_err("Failed to setup NMI delivery: irq %u\n", irq); | |
2607 | goto out; | |
2608 | } | |
2609 | ||
2610 | out: | |
2611 | irq_put_desc_unlock(desc, flags); | |
2612 | return ret; | |
2613 | } | |
2614 | ||
2615 | /** | |
2616 | * teardown_percpu_nmi - undoes NMI setup of IRQ line | |
2617 | * @irq: Interrupt line from which CPU local NMI configuration should be | |
2618 | * removed | |
2619 | * | |
2620 | * This call undoes the setup done by prepare_percpu_nmi(). | |
2621 | * | |
2622 | * IRQ line should not be enabled for the current CPU. | |
2623 | * | |
2624 | * As a CPU local operation, this should be called from non-preemptible | |
2625 | * context. | |
2626 | */ | |
2627 | void teardown_percpu_nmi(unsigned int irq) | |
2628 | { | |
2629 | unsigned long flags; | |
2630 | struct irq_desc *desc; | |
2631 | ||
2632 | WARN_ON(preemptible()); | |
2633 | ||
2634 | desc = irq_get_desc_lock(irq, &flags, | |
2635 | IRQ_GET_DESC_CHECK_PERCPU); | |
2636 | if (!desc) | |
2637 | return; | |
2638 | ||
2639 | if (WARN_ON(!(desc->istate & IRQS_NMI))) | |
2640 | goto out; | |
2641 | ||
2642 | irq_nmi_teardown(desc); | |
2643 | out: | |
2644 | irq_put_desc_unlock(desc, flags); | |
2645 | } | |
2646 | ||
62e04686 TG |
2647 | int __irq_get_irqchip_state(struct irq_data *data, enum irqchip_irq_state which, |
2648 | bool *state) | |
2649 | { | |
2650 | struct irq_chip *chip; | |
2651 | int err = -EINVAL; | |
2652 | ||
2653 | do { | |
2654 | chip = irq_data_get_irq_chip(data); | |
1d0326f3 MV |
2655 | if (WARN_ON_ONCE(!chip)) |
2656 | return -ENODEV; | |
62e04686 TG |
2657 | if (chip->irq_get_irqchip_state) |
2658 | break; | |
2659 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
2660 | data = data->parent_data; | |
2661 | #else | |
2662 | data = NULL; | |
2663 | #endif | |
2664 | } while (data); | |
2665 | ||
2666 | if (data) | |
2667 | err = chip->irq_get_irqchip_state(data, which, state); | |
2668 | return err; | |
2669 | } | |
2670 | ||
1b7047ed MZ |
2671 | /** |
2672 | * irq_get_irqchip_state - returns the irqchip state of a interrupt. | |
2673 | * @irq: Interrupt line that is forwarded to a VM | |
2674 | * @which: One of IRQCHIP_STATE_* the caller wants to know about | |
2675 | * @state: a pointer to a boolean where the state is to be storeed | |
2676 | * | |
2677 | * This call snapshots the internal irqchip state of an | |
2678 | * interrupt, returning into @state the bit corresponding to | |
2679 | * stage @which | |
2680 | * | |
2681 | * This function should be called with preemption disabled if the | |
2682 | * interrupt controller has per-cpu registers. | |
2683 | */ | |
2684 | int irq_get_irqchip_state(unsigned int irq, enum irqchip_irq_state which, | |
2685 | bool *state) | |
2686 | { | |
2687 | struct irq_desc *desc; | |
2688 | struct irq_data *data; | |
1b7047ed MZ |
2689 | unsigned long flags; |
2690 | int err = -EINVAL; | |
2691 | ||
2692 | desc = irq_get_desc_buslock(irq, &flags, 0); | |
2693 | if (!desc) | |
2694 | return err; | |
2695 | ||
2696 | data = irq_desc_get_irq_data(desc); | |
2697 | ||
62e04686 | 2698 | err = __irq_get_irqchip_state(data, which, state); |
1b7047ed MZ |
2699 | |
2700 | irq_put_desc_busunlock(desc, flags); | |
2701 | return err; | |
2702 | } | |
1ee4fb3e | 2703 | EXPORT_SYMBOL_GPL(irq_get_irqchip_state); |
1b7047ed MZ |
2704 | |
2705 | /** | |
2706 | * irq_set_irqchip_state - set the state of a forwarded interrupt. | |
2707 | * @irq: Interrupt line that is forwarded to a VM | |
2708 | * @which: State to be restored (one of IRQCHIP_STATE_*) | |
2709 | * @val: Value corresponding to @which | |
2710 | * | |
2711 | * This call sets the internal irqchip state of an interrupt, | |
2712 | * depending on the value of @which. | |
2713 | * | |
2714 | * This function should be called with preemption disabled if the | |
2715 | * interrupt controller has per-cpu registers. | |
2716 | */ | |
2717 | int irq_set_irqchip_state(unsigned int irq, enum irqchip_irq_state which, | |
2718 | bool val) | |
2719 | { | |
2720 | struct irq_desc *desc; | |
2721 | struct irq_data *data; | |
2722 | struct irq_chip *chip; | |
2723 | unsigned long flags; | |
2724 | int err = -EINVAL; | |
2725 | ||
2726 | desc = irq_get_desc_buslock(irq, &flags, 0); | |
2727 | if (!desc) | |
2728 | return err; | |
2729 | ||
2730 | data = irq_desc_get_irq_data(desc); | |
2731 | ||
2732 | do { | |
2733 | chip = irq_data_get_irq_chip(data); | |
f107cee9 GR |
2734 | if (WARN_ON_ONCE(!chip)) { |
2735 | err = -ENODEV; | |
2736 | goto out_unlock; | |
2737 | } | |
1b7047ed MZ |
2738 | if (chip->irq_set_irqchip_state) |
2739 | break; | |
2740 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
2741 | data = data->parent_data; | |
2742 | #else | |
2743 | data = NULL; | |
2744 | #endif | |
2745 | } while (data); | |
2746 | ||
2747 | if (data) | |
2748 | err = chip->irq_set_irqchip_state(data, which, val); | |
2749 | ||
f107cee9 | 2750 | out_unlock: |
1b7047ed MZ |
2751 | irq_put_desc_busunlock(desc, flags); |
2752 | return err; | |
2753 | } | |
1ee4fb3e | 2754 | EXPORT_SYMBOL_GPL(irq_set_irqchip_state); |