Merge tag 'efi-efivars-removal-for-v5.20' of git://git.kernel.org/pub/scm/linux/kerne...
[linux-2.6-block.git] / kernel / irq / manage.c
CommitLineData
52a65ff5 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
a34db9b2
IM
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006 Thomas Gleixner
1da177e4
LT
5 *
6 * This file contains driver APIs to the irq subsystem.
7 */
8
97fd75b7
AM
9#define pr_fmt(fmt) "genirq: " fmt
10
1da177e4 11#include <linux/irq.h>
3aa551c9 12#include <linux/kthread.h>
1da177e4
LT
13#include <linux/module.h>
14#include <linux/random.h>
15#include <linux/interrupt.h>
4001d8e8 16#include <linux/irqdomain.h>
1aeb272c 17#include <linux/slab.h>
3aa551c9 18#include <linux/sched.h>
8bd75c77 19#include <linux/sched/rt.h>
0881e7bd 20#include <linux/sched/task.h>
11ea68f5 21#include <linux/sched/isolation.h>
ae7e81c0 22#include <uapi/linux/sched/types.h>
4d1d61a6 23#include <linux/task_work.h>
1da177e4
LT
24
25#include "internals.h"
26
b6a32bbd 27#if defined(CONFIG_IRQ_FORCED_THREADING) && !defined(CONFIG_PREEMPT_RT)
91cc470e 28DEFINE_STATIC_KEY_FALSE(force_irqthreads_key);
8d32a307
TG
29
30static int __init setup_forced_irqthreads(char *arg)
31{
91cc470e 32 static_branch_enable(&force_irqthreads_key);
8d32a307
TG
33 return 0;
34}
35early_param("threadirqs", setup_forced_irqthreads);
36#endif
37
62e04686 38static void __synchronize_hardirq(struct irq_desc *desc, bool sync_chip)
1da177e4 39{
62e04686 40 struct irq_data *irqd = irq_desc_get_irq_data(desc);
32f4125e 41 bool inprogress;
1da177e4 42
a98ce5c6
HX
43 do {
44 unsigned long flags;
45
46 /*
47 * Wait until we're out of the critical section. This might
48 * give the wrong answer due to the lack of memory barriers.
49 */
32f4125e 50 while (irqd_irq_inprogress(&desc->irq_data))
a98ce5c6
HX
51 cpu_relax();
52
53 /* Ok, that indicated we're done: double-check carefully. */
239007b8 54 raw_spin_lock_irqsave(&desc->lock, flags);
32f4125e 55 inprogress = irqd_irq_inprogress(&desc->irq_data);
62e04686
TG
56
57 /*
58 * If requested and supported, check at the chip whether it
59 * is in flight at the hardware level, i.e. already pending
60 * in a CPU and waiting for service and acknowledge.
61 */
62 if (!inprogress && sync_chip) {
63 /*
64 * Ignore the return code. inprogress is only updated
65 * when the chip supports it.
66 */
67 __irq_get_irqchip_state(irqd, IRQCHIP_STATE_ACTIVE,
68 &inprogress);
69 }
239007b8 70 raw_spin_unlock_irqrestore(&desc->lock, flags);
a98ce5c6
HX
71
72 /* Oops, that failed? */
32f4125e 73 } while (inprogress);
18258f72
TG
74}
75
76/**
77 * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs)
78 * @irq: interrupt number to wait for
79 *
80 * This function waits for any pending hard IRQ handlers for this
81 * interrupt to complete before returning. If you use this
82 * function while holding a resource the IRQ handler may need you
83 * will deadlock. It does not take associated threaded handlers
84 * into account.
85 *
86 * Do not use this for shutdown scenarios where you must be sure
87 * that all parts (hardirq and threaded handler) have completed.
88 *
02cea395
PZ
89 * Returns: false if a threaded handler is active.
90 *
18258f72 91 * This function may be called - with care - from IRQ context.
62e04686
TG
92 *
93 * It does not check whether there is an interrupt in flight at the
94 * hardware level, but not serviced yet, as this might deadlock when
95 * called with interrupts disabled and the target CPU of the interrupt
96 * is the current CPU.
18258f72 97 */
02cea395 98bool synchronize_hardirq(unsigned int irq)
18258f72
TG
99{
100 struct irq_desc *desc = irq_to_desc(irq);
3aa551c9 101
02cea395 102 if (desc) {
62e04686 103 __synchronize_hardirq(desc, false);
02cea395
PZ
104 return !atomic_read(&desc->threads_active);
105 }
106
107 return true;
18258f72
TG
108}
109EXPORT_SYMBOL(synchronize_hardirq);
110
111/**
112 * synchronize_irq - wait for pending IRQ handlers (on other CPUs)
113 * @irq: interrupt number to wait for
114 *
115 * This function waits for any pending IRQ handlers for this interrupt
116 * to complete before returning. If you use this function while
117 * holding a resource the IRQ handler may need you will deadlock.
118 *
1d21f2af
TG
119 * Can only be called from preemptible code as it might sleep when
120 * an interrupt thread is associated to @irq.
62e04686
TG
121 *
122 * It optionally makes sure (when the irq chip supports that method)
123 * that the interrupt is not pending in any CPU and waiting for
124 * service.
18258f72
TG
125 */
126void synchronize_irq(unsigned int irq)
127{
128 struct irq_desc *desc = irq_to_desc(irq);
129
130 if (desc) {
62e04686 131 __synchronize_hardirq(desc, true);
18258f72
TG
132 /*
133 * We made sure that no hardirq handler is
134 * running. Now verify that no threaded handlers are
135 * active.
136 */
137 wait_event(desc->wait_for_threads,
138 !atomic_read(&desc->threads_active));
139 }
1da177e4 140}
1da177e4
LT
141EXPORT_SYMBOL(synchronize_irq);
142
3aa551c9
TG
143#ifdef CONFIG_SMP
144cpumask_var_t irq_default_affinity;
145
9c255583 146static bool __irq_can_set_affinity(struct irq_desc *desc)
e019c249
JL
147{
148 if (!desc || !irqd_can_balance(&desc->irq_data) ||
149 !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity)
9c255583
TG
150 return false;
151 return true;
e019c249
JL
152}
153
771ee3b0
TG
154/**
155 * irq_can_set_affinity - Check if the affinity of a given irq can be set
156 * @irq: Interrupt to check
157 *
158 */
159int irq_can_set_affinity(unsigned int irq)
160{
e019c249 161 return __irq_can_set_affinity(irq_to_desc(irq));
771ee3b0
TG
162}
163
9c255583
TG
164/**
165 * irq_can_set_affinity_usr - Check if affinity of a irq can be set from user space
166 * @irq: Interrupt to check
167 *
168 * Like irq_can_set_affinity() above, but additionally checks for the
169 * AFFINITY_MANAGED flag.
170 */
171bool irq_can_set_affinity_usr(unsigned int irq)
172{
173 struct irq_desc *desc = irq_to_desc(irq);
174
175 return __irq_can_set_affinity(desc) &&
176 !irqd_affinity_is_managed(&desc->irq_data);
177}
178
591d2fb0
TG
179/**
180 * irq_set_thread_affinity - Notify irq threads to adjust affinity
5c982c58 181 * @desc: irq descriptor which has affinity changed
591d2fb0
TG
182 *
183 * We just set IRQTF_AFFINITY and delegate the affinity setting
184 * to the interrupt thread itself. We can not call
185 * set_cpus_allowed_ptr() here as we hold desc->lock and this
186 * code can be called from hard interrupt context.
187 */
188void irq_set_thread_affinity(struct irq_desc *desc)
3aa551c9 189{
f944b5a7 190 struct irqaction *action;
3aa551c9 191
f944b5a7 192 for_each_action_of_desc(desc, action)
3aa551c9 193 if (action->thread)
591d2fb0 194 set_bit(IRQTF_AFFINITY, &action->thread_flags);
3aa551c9
TG
195}
196
baedb87d 197#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
19e1d4e9
TG
198static void irq_validate_effective_affinity(struct irq_data *data)
199{
19e1d4e9
TG
200 const struct cpumask *m = irq_data_get_effective_affinity_mask(data);
201 struct irq_chip *chip = irq_data_get_irq_chip(data);
202
203 if (!cpumask_empty(m))
204 return;
205 pr_warn_once("irq_chip %s did not update eff. affinity mask of irq %u\n",
206 chip->name, data->irq);
19e1d4e9 207}
baedb87d
TG
208#else
209static inline void irq_validate_effective_affinity(struct irq_data *data) { }
baedb87d
TG
210#endif
211
818b0f3b
JL
212int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask,
213 bool force)
214{
215 struct irq_desc *desc = irq_data_to_desc(data);
216 struct irq_chip *chip = irq_data_get_irq_chip(data);
33de0aa4 217 const struct cpumask *prog_mask;
818b0f3b
JL
218 int ret;
219
33de0aa4
MZ
220 static DEFINE_RAW_SPINLOCK(tmp_mask_lock);
221 static struct cpumask tmp_mask;
222
e43b3b58
TG
223 if (!chip || !chip->irq_set_affinity)
224 return -EINVAL;
225
33de0aa4 226 raw_spin_lock(&tmp_mask_lock);
11ea68f5
ML
227 /*
228 * If this is a managed interrupt and housekeeping is enabled on
229 * it check whether the requested affinity mask intersects with
230 * a housekeeping CPU. If so, then remove the isolated CPUs from
231 * the mask and just keep the housekeeping CPU(s). This prevents
232 * the affinity setter from routing the interrupt to an isolated
233 * CPU to avoid that I/O submitted from a housekeeping CPU causes
234 * interrupts on an isolated one.
235 *
236 * If the masks do not intersect or include online CPU(s) then
237 * keep the requested mask. The isolated target CPUs are only
238 * receiving interrupts when the I/O operation was submitted
239 * directly from them.
240 *
241 * If all housekeeping CPUs in the affinity mask are offline, the
242 * interrupt will be migrated by the CPU hotplug code once a
243 * housekeeping CPU which belongs to the affinity mask comes
244 * online.
245 */
246 if (irqd_affinity_is_managed(data) &&
04d4e665 247 housekeeping_enabled(HK_TYPE_MANAGED_IRQ)) {
33de0aa4 248 const struct cpumask *hk_mask;
11ea68f5 249
04d4e665 250 hk_mask = housekeeping_cpumask(HK_TYPE_MANAGED_IRQ);
11ea68f5 251
11ea68f5
ML
252 cpumask_and(&tmp_mask, mask, hk_mask);
253 if (!cpumask_intersects(&tmp_mask, cpu_online_mask))
254 prog_mask = mask;
255 else
256 prog_mask = &tmp_mask;
11ea68f5 257 } else {
33de0aa4 258 prog_mask = mask;
11ea68f5 259 }
33de0aa4 260
c48c8b82
MZ
261 /*
262 * Make sure we only provide online CPUs to the irqchip,
263 * unless we are being asked to force the affinity (in which
264 * case we do as we are told).
265 */
33de0aa4 266 cpumask_and(&tmp_mask, prog_mask, cpu_online_mask);
c48c8b82 267 if (!force && !cpumask_empty(&tmp_mask))
33de0aa4 268 ret = chip->irq_set_affinity(data, &tmp_mask, force);
c48c8b82
MZ
269 else if (force)
270 ret = chip->irq_set_affinity(data, mask, force);
33de0aa4
MZ
271 else
272 ret = -EINVAL;
273
274 raw_spin_unlock(&tmp_mask_lock);
275
818b0f3b
JL
276 switch (ret) {
277 case IRQ_SET_MASK_OK:
2cb62547 278 case IRQ_SET_MASK_OK_DONE:
9df872fa 279 cpumask_copy(desc->irq_common_data.affinity, mask);
df561f66 280 fallthrough;
818b0f3b 281 case IRQ_SET_MASK_OK_NOCOPY:
19e1d4e9 282 irq_validate_effective_affinity(data);
818b0f3b
JL
283 irq_set_thread_affinity(desc);
284 ret = 0;
285 }
286
287 return ret;
288}
289
12f47073
TG
290#ifdef CONFIG_GENERIC_PENDING_IRQ
291static inline int irq_set_affinity_pending(struct irq_data *data,
292 const struct cpumask *dest)
293{
294 struct irq_desc *desc = irq_data_to_desc(data);
295
296 irqd_set_move_pending(data);
297 irq_copy_pending(desc, dest);
298 return 0;
299}
300#else
301static inline int irq_set_affinity_pending(struct irq_data *data,
302 const struct cpumask *dest)
303{
304 return -EBUSY;
305}
306#endif
307
308static int irq_try_set_affinity(struct irq_data *data,
309 const struct cpumask *dest, bool force)
310{
311 int ret = irq_do_set_affinity(data, dest, force);
312
313 /*
314 * In case that the underlying vector management is busy and the
315 * architecture supports the generic pending mechanism then utilize
316 * this to avoid returning an error to user space.
317 */
318 if (ret == -EBUSY && !force)
319 ret = irq_set_affinity_pending(data, dest);
320 return ret;
321}
322
baedb87d
TG
323static bool irq_set_affinity_deactivated(struct irq_data *data,
324 const struct cpumask *mask, bool force)
325{
326 struct irq_desc *desc = irq_data_to_desc(data);
327
328 /*
f0c7baca
TG
329 * Handle irq chips which can handle affinity only in activated
330 * state correctly
331 *
baedb87d
TG
332 * If the interrupt is not yet activated, just store the affinity
333 * mask and do not call the chip driver at all. On activation the
334 * driver has to make sure anyway that the interrupt is in a
a359f757 335 * usable state so startup works.
baedb87d 336 */
f0c7baca
TG
337 if (!IS_ENABLED(CONFIG_IRQ_DOMAIN_HIERARCHY) ||
338 irqd_is_activated(data) || !irqd_affinity_on_activate(data))
baedb87d
TG
339 return false;
340
341 cpumask_copy(desc->irq_common_data.affinity, mask);
61030630 342 irq_data_update_effective_affinity(data, mask);
baedb87d
TG
343 irqd_set(data, IRQD_AFFINITY_SET);
344 return true;
345}
346
01f8fa4f
TG
347int irq_set_affinity_locked(struct irq_data *data, const struct cpumask *mask,
348 bool force)
771ee3b0 349{
c2d0c555
DD
350 struct irq_chip *chip = irq_data_get_irq_chip(data);
351 struct irq_desc *desc = irq_data_to_desc(data);
1fa46f1f 352 int ret = 0;
771ee3b0 353
c2d0c555 354 if (!chip || !chip->irq_set_affinity)
771ee3b0
TG
355 return -EINVAL;
356
baedb87d
TG
357 if (irq_set_affinity_deactivated(data, mask, force))
358 return 0;
359
12f47073
TG
360 if (irq_can_move_pcntxt(data) && !irqd_is_setaffinity_pending(data)) {
361 ret = irq_try_set_affinity(data, mask, force);
1fa46f1f 362 } else {
c2d0c555 363 irqd_set_move_pending(data);
1fa46f1f 364 irq_copy_pending(desc, mask);
57b150cc 365 }
1fa46f1f 366
cd7eab44
BH
367 if (desc->affinity_notify) {
368 kref_get(&desc->affinity_notify->kref);
df81dfcf
EC
369 if (!schedule_work(&desc->affinity_notify->work)) {
370 /* Work was already scheduled, drop our extra ref */
371 kref_put(&desc->affinity_notify->kref,
372 desc->affinity_notify->release);
373 }
cd7eab44 374 }
c2d0c555
DD
375 irqd_set(data, IRQD_AFFINITY_SET);
376
377 return ret;
378}
379
1d3aec89
JG
380/**
381 * irq_update_affinity_desc - Update affinity management for an interrupt
382 * @irq: The interrupt number to update
383 * @affinity: Pointer to the affinity descriptor
384 *
385 * This interface can be used to configure the affinity management of
386 * interrupts which have been allocated already.
387 *
388 * There are certain limitations on when it may be used - attempts to use it
389 * for when the kernel is configured for generic IRQ reservation mode (in
390 * config GENERIC_IRQ_RESERVATION_MODE) will fail, as it may conflict with
391 * managed/non-managed interrupt accounting. In addition, attempts to use it on
392 * an interrupt which is already started or which has already been configured
393 * as managed will also fail, as these mean invalid init state or double init.
394 */
395int irq_update_affinity_desc(unsigned int irq,
396 struct irq_affinity_desc *affinity)
397{
398 struct irq_desc *desc;
399 unsigned long flags;
400 bool activated;
401 int ret = 0;
402
403 /*
404 * Supporting this with the reservation scheme used by x86 needs
405 * some more thought. Fail it for now.
406 */
407 if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE))
408 return -EOPNOTSUPP;
409
410 desc = irq_get_desc_buslock(irq, &flags, 0);
411 if (!desc)
412 return -EINVAL;
413
414 /* Requires the interrupt to be shut down */
415 if (irqd_is_started(&desc->irq_data)) {
416 ret = -EBUSY;
417 goto out_unlock;
418 }
419
420 /* Interrupts which are already managed cannot be modified */
421 if (irqd_affinity_is_managed(&desc->irq_data)) {
422 ret = -EBUSY;
423 goto out_unlock;
424 }
425
426 /*
427 * Deactivate the interrupt. That's required to undo
428 * anything an earlier activation has established.
429 */
430 activated = irqd_is_activated(&desc->irq_data);
431 if (activated)
432 irq_domain_deactivate_irq(&desc->irq_data);
433
434 if (affinity->is_managed) {
435 irqd_set(&desc->irq_data, IRQD_AFFINITY_MANAGED);
436 irqd_set(&desc->irq_data, IRQD_MANAGED_SHUTDOWN);
437 }
438
439 cpumask_copy(desc->irq_common_data.affinity, &affinity->mask);
440
441 /* Restore the activation state */
442 if (activated)
443 irq_domain_activate_irq(&desc->irq_data, false);
444
445out_unlock:
446 irq_put_desc_busunlock(desc, flags);
447 return ret;
448}
449
4d80d6ca
TG
450static int __irq_set_affinity(unsigned int irq, const struct cpumask *mask,
451 bool force)
c2d0c555
DD
452{
453 struct irq_desc *desc = irq_to_desc(irq);
454 unsigned long flags;
455 int ret;
456
457 if (!desc)
458 return -EINVAL;
459
460 raw_spin_lock_irqsave(&desc->lock, flags);
01f8fa4f 461 ret = irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask, force);
239007b8 462 raw_spin_unlock_irqrestore(&desc->lock, flags);
1fa46f1f 463 return ret;
771ee3b0
TG
464}
465
4d80d6ca
TG
466/**
467 * irq_set_affinity - Set the irq affinity of a given irq
468 * @irq: Interrupt to set affinity
469 * @cpumask: cpumask
470 *
471 * Fails if cpumask does not contain an online CPU
472 */
473int irq_set_affinity(unsigned int irq, const struct cpumask *cpumask)
474{
475 return __irq_set_affinity(irq, cpumask, false);
476}
477EXPORT_SYMBOL_GPL(irq_set_affinity);
478
479/**
480 * irq_force_affinity - Force the irq affinity of a given irq
481 * @irq: Interrupt to set affinity
482 * @cpumask: cpumask
483 *
484 * Same as irq_set_affinity, but without checking the mask against
485 * online cpus.
486 *
487 * Solely for low level cpu hotplug code, where we need to make per
488 * cpu interrupts affine before the cpu becomes online.
489 */
490int irq_force_affinity(unsigned int irq, const struct cpumask *cpumask)
491{
492 return __irq_set_affinity(irq, cpumask, true);
493}
494EXPORT_SYMBOL_GPL(irq_force_affinity);
495
65c7cded
TG
496int __irq_apply_affinity_hint(unsigned int irq, const struct cpumask *m,
497 bool setaffinity)
e7a297b0 498{
e7a297b0 499 unsigned long flags;
31d9d9b6 500 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
e7a297b0
PWJ
501
502 if (!desc)
503 return -EINVAL;
e7a297b0 504 desc->affinity_hint = m;
02725e74 505 irq_put_desc_unlock(desc, flags);
65c7cded 506 if (m && setaffinity)
4fe7ffb7 507 __irq_set_affinity(irq, m, false);
e7a297b0
PWJ
508 return 0;
509}
65c7cded 510EXPORT_SYMBOL_GPL(__irq_apply_affinity_hint);
e7a297b0 511
cd7eab44
BH
512static void irq_affinity_notify(struct work_struct *work)
513{
514 struct irq_affinity_notify *notify =
515 container_of(work, struct irq_affinity_notify, work);
516 struct irq_desc *desc = irq_to_desc(notify->irq);
517 cpumask_var_t cpumask;
518 unsigned long flags;
519
1fa46f1f 520 if (!desc || !alloc_cpumask_var(&cpumask, GFP_KERNEL))
cd7eab44
BH
521 goto out;
522
523 raw_spin_lock_irqsave(&desc->lock, flags);
0ef5ca1e 524 if (irq_move_pending(&desc->irq_data))
1fa46f1f 525 irq_get_pending(cpumask, desc);
cd7eab44 526 else
9df872fa 527 cpumask_copy(cpumask, desc->irq_common_data.affinity);
cd7eab44
BH
528 raw_spin_unlock_irqrestore(&desc->lock, flags);
529
530 notify->notify(notify, cpumask);
531
532 free_cpumask_var(cpumask);
533out:
534 kref_put(&notify->kref, notify->release);
535}
536
537/**
538 * irq_set_affinity_notifier - control notification of IRQ affinity changes
539 * @irq: Interrupt for which to enable/disable notification
540 * @notify: Context for notification, or %NULL to disable
541 * notification. Function pointers must be initialised;
542 * the other fields will be initialised by this function.
543 *
544 * Must be called in process context. Notification may only be enabled
545 * after the IRQ is allocated and must be disabled before the IRQ is
546 * freed using free_irq().
547 */
548int
549irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify)
550{
551 struct irq_desc *desc = irq_to_desc(irq);
552 struct irq_affinity_notify *old_notify;
553 unsigned long flags;
554
555 /* The release function is promised process context */
556 might_sleep();
557
b525903c 558 if (!desc || desc->istate & IRQS_NMI)
cd7eab44
BH
559 return -EINVAL;
560
561 /* Complete initialisation of *notify */
562 if (notify) {
563 notify->irq = irq;
564 kref_init(&notify->kref);
565 INIT_WORK(&notify->work, irq_affinity_notify);
566 }
567
568 raw_spin_lock_irqsave(&desc->lock, flags);
569 old_notify = desc->affinity_notify;
570 desc->affinity_notify = notify;
571 raw_spin_unlock_irqrestore(&desc->lock, flags);
572
59c39840 573 if (old_notify) {
df81dfcf
EC
574 if (cancel_work_sync(&old_notify->work)) {
575 /* Pending work had a ref, put that one too */
576 kref_put(&old_notify->kref, old_notify->release);
577 }
cd7eab44 578 kref_put(&old_notify->kref, old_notify->release);
59c39840 579 }
cd7eab44
BH
580
581 return 0;
582}
583EXPORT_SYMBOL_GPL(irq_set_affinity_notifier);
584
18404756
MK
585#ifndef CONFIG_AUTO_IRQ_AFFINITY
586/*
587 * Generic version of the affinity autoselector.
588 */
43564bd9 589int irq_setup_affinity(struct irq_desc *desc)
18404756 590{
569bda8d 591 struct cpumask *set = irq_default_affinity;
cba4235e
TG
592 int ret, node = irq_desc_get_node(desc);
593 static DEFINE_RAW_SPINLOCK(mask_lock);
594 static struct cpumask mask;
569bda8d 595
b008207c 596 /* Excludes PER_CPU and NO_BALANCE interrupts */
e019c249 597 if (!__irq_can_set_affinity(desc))
18404756
MK
598 return 0;
599
cba4235e 600 raw_spin_lock(&mask_lock);
f6d87f4b 601 /*
9332ef9d 602 * Preserve the managed affinity setting and a userspace affinity
06ee6d57 603 * setup, but make sure that one of the targets is online.
f6d87f4b 604 */
06ee6d57
TG
605 if (irqd_affinity_is_managed(&desc->irq_data) ||
606 irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) {
9df872fa 607 if (cpumask_intersects(desc->irq_common_data.affinity,
569bda8d 608 cpu_online_mask))
9df872fa 609 set = desc->irq_common_data.affinity;
0c6f8a8b 610 else
2bdd1055 611 irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET);
f6d87f4b 612 }
18404756 613
cba4235e 614 cpumask_and(&mask, cpu_online_mask, set);
bddda606
SR
615 if (cpumask_empty(&mask))
616 cpumask_copy(&mask, cpu_online_mask);
617
241fc640
PB
618 if (node != NUMA_NO_NODE) {
619 const struct cpumask *nodemask = cpumask_of_node(node);
620
621 /* make sure at least one of the cpus in nodemask is online */
cba4235e
TG
622 if (cpumask_intersects(&mask, nodemask))
623 cpumask_and(&mask, &mask, nodemask);
241fc640 624 }
cba4235e
TG
625 ret = irq_do_set_affinity(&desc->irq_data, &mask, false);
626 raw_spin_unlock(&mask_lock);
627 return ret;
18404756 628}
f6d87f4b 629#else
a8a98eac 630/* Wrapper for ALPHA specific affinity selector magic */
cba4235e 631int irq_setup_affinity(struct irq_desc *desc)
f6d87f4b 632{
cba4235e 633 return irq_select_affinity(irq_desc_get_irq(desc));
f6d87f4b 634}
cba6437a
TG
635#endif /* CONFIG_AUTO_IRQ_AFFINITY */
636#endif /* CONFIG_SMP */
18404756 637
1da177e4 638
fcf1ae2f
FW
639/**
640 * irq_set_vcpu_affinity - Set vcpu affinity for the interrupt
641 * @irq: interrupt number to set affinity
250a53d6
CD
642 * @vcpu_info: vCPU specific data or pointer to a percpu array of vCPU
643 * specific data for percpu_devid interrupts
fcf1ae2f
FW
644 *
645 * This function uses the vCPU specific data to set the vCPU
646 * affinity for an irq. The vCPU specific data is passed from
647 * outside, such as KVM. One example code path is as below:
648 * KVM -> IOMMU -> irq_set_vcpu_affinity().
649 */
650int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info)
651{
652 unsigned long flags;
653 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
654 struct irq_data *data;
655 struct irq_chip *chip;
656 int ret = -ENOSYS;
657
658 if (!desc)
659 return -EINVAL;
660
661 data = irq_desc_get_irq_data(desc);
0abce64a
MZ
662 do {
663 chip = irq_data_get_irq_chip(data);
664 if (chip && chip->irq_set_vcpu_affinity)
665 break;
666#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
667 data = data->parent_data;
668#else
669 data = NULL;
670#endif
671 } while (data);
672
673 if (data)
fcf1ae2f
FW
674 ret = chip->irq_set_vcpu_affinity(data, vcpu_info);
675 irq_put_desc_unlock(desc, flags);
676
677 return ret;
678}
679EXPORT_SYMBOL_GPL(irq_set_vcpu_affinity);
680
79ff1cda 681void __disable_irq(struct irq_desc *desc)
0a0c5168 682{
3aae994f 683 if (!desc->depth++)
87923470 684 irq_disable(desc);
0a0c5168
RW
685}
686
02725e74
TG
687static int __disable_irq_nosync(unsigned int irq)
688{
689 unsigned long flags;
31d9d9b6 690 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74
TG
691
692 if (!desc)
693 return -EINVAL;
79ff1cda 694 __disable_irq(desc);
02725e74
TG
695 irq_put_desc_busunlock(desc, flags);
696 return 0;
697}
698
1da177e4
LT
699/**
700 * disable_irq_nosync - disable an irq without waiting
701 * @irq: Interrupt to disable
702 *
703 * Disable the selected interrupt line. Disables and Enables are
704 * nested.
705 * Unlike disable_irq(), this function does not ensure existing
706 * instances of the IRQ handler have completed before returning.
707 *
708 * This function may be called from IRQ context.
709 */
710void disable_irq_nosync(unsigned int irq)
711{
02725e74 712 __disable_irq_nosync(irq);
1da177e4 713}
1da177e4
LT
714EXPORT_SYMBOL(disable_irq_nosync);
715
716/**
717 * disable_irq - disable an irq and wait for completion
718 * @irq: Interrupt to disable
719 *
720 * Disable the selected interrupt line. Enables and Disables are
721 * nested.
722 * This function waits for any pending IRQ handlers for this interrupt
723 * to complete before returning. If you use this function while
724 * holding a resource the IRQ handler may need you will deadlock.
725 *
726 * This function may be called - with care - from IRQ context.
727 */
728void disable_irq(unsigned int irq)
729{
02725e74 730 if (!__disable_irq_nosync(irq))
1da177e4
LT
731 synchronize_irq(irq);
732}
1da177e4
LT
733EXPORT_SYMBOL(disable_irq);
734
02cea395
PZ
735/**
736 * disable_hardirq - disables an irq and waits for hardirq completion
737 * @irq: Interrupt to disable
738 *
739 * Disable the selected interrupt line. Enables and Disables are
740 * nested.
741 * This function waits for any pending hard IRQ handlers for this
742 * interrupt to complete before returning. If you use this function while
743 * holding a resource the hard IRQ handler may need you will deadlock.
744 *
745 * When used to optimistically disable an interrupt from atomic context
746 * the return value must be checked.
747 *
748 * Returns: false if a threaded handler is active.
749 *
750 * This function may be called - with care - from IRQ context.
751 */
752bool disable_hardirq(unsigned int irq)
753{
754 if (!__disable_irq_nosync(irq))
755 return synchronize_hardirq(irq);
756
757 return false;
758}
759EXPORT_SYMBOL_GPL(disable_hardirq);
760
b525903c
JT
761/**
762 * disable_nmi_nosync - disable an nmi without waiting
763 * @irq: Interrupt to disable
764 *
765 * Disable the selected interrupt line. Disables and enables are
766 * nested.
767 * The interrupt to disable must have been requested through request_nmi.
768 * Unlike disable_nmi(), this function does not ensure existing
769 * instances of the IRQ handler have completed before returning.
770 */
771void disable_nmi_nosync(unsigned int irq)
772{
773 disable_irq_nosync(irq);
774}
775
79ff1cda 776void __enable_irq(struct irq_desc *desc)
1adb0850
TG
777{
778 switch (desc->depth) {
779 case 0:
0a0c5168 780 err_out:
79ff1cda
JL
781 WARN(1, KERN_WARNING "Unbalanced enable for IRQ %d\n",
782 irq_desc_get_irq(desc));
1adb0850
TG
783 break;
784 case 1: {
c531e836 785 if (desc->istate & IRQS_SUSPENDED)
0a0c5168 786 goto err_out;
1adb0850 787 /* Prevent probing on this irq: */
1ccb4e61 788 irq_settings_set_noprobe(desc);
201d7f47
TG
789 /*
790 * Call irq_startup() not irq_enable() here because the
791 * interrupt might be marked NOAUTOEN. So irq_startup()
792 * needs to be invoked when it gets enabled the first
793 * time. If it was already started up, then irq_startup()
794 * will invoke irq_enable() under the hood.
795 */
c942cee4 796 irq_startup(desc, IRQ_RESEND, IRQ_START_FORCE);
201d7f47 797 break;
1adb0850
TG
798 }
799 default:
800 desc->depth--;
801 }
802}
803
1da177e4
LT
804/**
805 * enable_irq - enable handling of an irq
806 * @irq: Interrupt to enable
807 *
808 * Undoes the effect of one call to disable_irq(). If this
809 * matches the last disable, processing of interrupts on this
810 * IRQ line is re-enabled.
811 *
70aedd24 812 * This function may be called from IRQ context only when
6b8ff312 813 * desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL !
1da177e4
LT
814 */
815void enable_irq(unsigned int irq)
816{
1da177e4 817 unsigned long flags;
31d9d9b6 818 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
1da177e4 819
7d94f7ca 820 if (!desc)
c2b5a251 821 return;
50f7c032
TG
822 if (WARN(!desc->irq_data.chip,
823 KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq))
02725e74 824 goto out;
2656c366 825
79ff1cda 826 __enable_irq(desc);
02725e74
TG
827out:
828 irq_put_desc_busunlock(desc, flags);
1da177e4 829}
1da177e4
LT
830EXPORT_SYMBOL(enable_irq);
831
b525903c
JT
832/**
833 * enable_nmi - enable handling of an nmi
834 * @irq: Interrupt to enable
835 *
836 * The interrupt to enable must have been requested through request_nmi.
837 * Undoes the effect of one call to disable_nmi(). If this
838 * matches the last disable, processing of interrupts on this
839 * IRQ line is re-enabled.
840 */
841void enable_nmi(unsigned int irq)
842{
843 enable_irq(irq);
844}
845
0c5d1eb7 846static int set_irq_wake_real(unsigned int irq, unsigned int on)
2db87321 847{
08678b08 848 struct irq_desc *desc = irq_to_desc(irq);
2db87321
UKK
849 int ret = -ENXIO;
850
60f96b41
SS
851 if (irq_desc_get_chip(desc)->flags & IRQCHIP_SKIP_SET_WAKE)
852 return 0;
853
2f7e99bb
TG
854 if (desc->irq_data.chip->irq_set_wake)
855 ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on);
2db87321
UKK
856
857 return ret;
858}
859
ba9a2331 860/**
a0cd9ca2 861 * irq_set_irq_wake - control irq power management wakeup
ba9a2331
TG
862 * @irq: interrupt to control
863 * @on: enable/disable power management wakeup
864 *
15a647eb
DB
865 * Enable/disable power management wakeup mode, which is
866 * disabled by default. Enables and disables must match,
867 * just as they match for non-wakeup mode support.
868 *
869 * Wakeup mode lets this IRQ wake the system from sleep
870 * states like "suspend to RAM".
f9f21cea
SB
871 *
872 * Note: irq enable/disable state is completely orthogonal
873 * to the enable/disable state of irq wake. An irq can be
874 * disabled with disable_irq() and still wake the system as
875 * long as the irq has wake enabled. If this does not hold,
876 * then the underlying irq chip and the related driver need
877 * to be investigated.
ba9a2331 878 */
a0cd9ca2 879int irq_set_irq_wake(unsigned int irq, unsigned int on)
ba9a2331 880{
ba9a2331 881 unsigned long flags;
31d9d9b6 882 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
2db87321 883 int ret = 0;
ba9a2331 884
13863a66
JJ
885 if (!desc)
886 return -EINVAL;
887
b525903c
JT
888 /* Don't use NMIs as wake up interrupts please */
889 if (desc->istate & IRQS_NMI) {
890 ret = -EINVAL;
891 goto out_unlock;
892 }
893
15a647eb
DB
894 /* wakeup-capable irqs can be shared between drivers that
895 * don't need to have the same sleep mode behaviors.
896 */
15a647eb 897 if (on) {
2db87321
UKK
898 if (desc->wake_depth++ == 0) {
899 ret = set_irq_wake_real(irq, on);
900 if (ret)
901 desc->wake_depth = 0;
902 else
7f94226f 903 irqd_set(&desc->irq_data, IRQD_WAKEUP_STATE);
2db87321 904 }
15a647eb
DB
905 } else {
906 if (desc->wake_depth == 0) {
7a2c4770 907 WARN(1, "Unbalanced IRQ %d wake disable\n", irq);
2db87321
UKK
908 } else if (--desc->wake_depth == 0) {
909 ret = set_irq_wake_real(irq, on);
910 if (ret)
911 desc->wake_depth = 1;
912 else
7f94226f 913 irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE);
2db87321 914 }
15a647eb 915 }
b525903c
JT
916
917out_unlock:
02725e74 918 irq_put_desc_busunlock(desc, flags);
ba9a2331
TG
919 return ret;
920}
a0cd9ca2 921EXPORT_SYMBOL(irq_set_irq_wake);
ba9a2331 922
1da177e4
LT
923/*
924 * Internal function that tells the architecture code whether a
925 * particular irq has been exclusively allocated or is available
926 * for driver use.
927 */
928int can_request_irq(unsigned int irq, unsigned long irqflags)
929{
cc8c3b78 930 unsigned long flags;
31d9d9b6 931 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
02725e74 932 int canrequest = 0;
1da177e4 933
7d94f7ca
YL
934 if (!desc)
935 return 0;
936
02725e74 937 if (irq_settings_can_request(desc)) {
2779db8d
BH
938 if (!desc->action ||
939 irqflags & desc->action->flags & IRQF_SHARED)
940 canrequest = 1;
02725e74
TG
941 }
942 irq_put_desc_unlock(desc, flags);
943 return canrequest;
1da177e4
LT
944}
945
a1ff541a 946int __irq_set_trigger(struct irq_desc *desc, unsigned long flags)
82736f4d 947{
6b8ff312 948 struct irq_chip *chip = desc->irq_data.chip;
d4d5e089 949 int ret, unmask = 0;
82736f4d 950
b2ba2c30 951 if (!chip || !chip->irq_set_type) {
82736f4d
UKK
952 /*
953 * IRQF_TRIGGER_* but the PIC does not support multiple
954 * flow-types?
955 */
a1ff541a
JL
956 pr_debug("No set_type function for IRQ %d (%s)\n",
957 irq_desc_get_irq(desc),
f5d89470 958 chip ? (chip->name ? : "unknown") : "unknown");
82736f4d
UKK
959 return 0;
960 }
961
d4d5e089 962 if (chip->flags & IRQCHIP_SET_TYPE_MASKED) {
32f4125e 963 if (!irqd_irq_masked(&desc->irq_data))
d4d5e089 964 mask_irq(desc);
32f4125e 965 if (!irqd_irq_disabled(&desc->irq_data))
d4d5e089
TG
966 unmask = 1;
967 }
968
00b992de
AK
969 /* Mask all flags except trigger mode */
970 flags &= IRQ_TYPE_SENSE_MASK;
b2ba2c30 971 ret = chip->irq_set_type(&desc->irq_data, flags);
82736f4d 972
876dbd4c
TG
973 switch (ret) {
974 case IRQ_SET_MASK_OK:
2cb62547 975 case IRQ_SET_MASK_OK_DONE:
876dbd4c
TG
976 irqd_clear(&desc->irq_data, IRQD_TRIGGER_MASK);
977 irqd_set(&desc->irq_data, flags);
df561f66 978 fallthrough;
876dbd4c
TG
979
980 case IRQ_SET_MASK_OK_NOCOPY:
981 flags = irqd_get_trigger_type(&desc->irq_data);
982 irq_settings_set_trigger_mask(desc, flags);
983 irqd_clear(&desc->irq_data, IRQD_LEVEL);
984 irq_settings_clr_level(desc);
985 if (flags & IRQ_TYPE_LEVEL_MASK) {
986 irq_settings_set_level(desc);
987 irqd_set(&desc->irq_data, IRQD_LEVEL);
988 }
46732475 989
d4d5e089 990 ret = 0;
8fff39e0 991 break;
876dbd4c 992 default:
d75f773c 993 pr_err("Setting trigger mode %lu for irq %u failed (%pS)\n",
a1ff541a 994 flags, irq_desc_get_irq(desc), chip->irq_set_type);
0c5d1eb7 995 }
d4d5e089
TG
996 if (unmask)
997 unmask_irq(desc);
82736f4d
UKK
998 return ret;
999}
1000
293a7a0a
TG
1001#ifdef CONFIG_HARDIRQS_SW_RESEND
1002int irq_set_parent(int irq, int parent_irq)
1003{
1004 unsigned long flags;
1005 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
1006
1007 if (!desc)
1008 return -EINVAL;
1009
1010 desc->parent_irq = parent_irq;
1011
1012 irq_put_desc_unlock(desc, flags);
1013 return 0;
1014}
3118dac5 1015EXPORT_SYMBOL_GPL(irq_set_parent);
293a7a0a
TG
1016#endif
1017
b25c340c
TG
1018/*
1019 * Default primary interrupt handler for threaded interrupts. Is
1020 * assigned as primary handler when request_threaded_irq is called
1021 * with handler == NULL. Useful for oneshot interrupts.
1022 */
1023static irqreturn_t irq_default_primary_handler(int irq, void *dev_id)
1024{
1025 return IRQ_WAKE_THREAD;
1026}
1027
399b5da2
TG
1028/*
1029 * Primary handler for nested threaded interrupts. Should never be
1030 * called.
1031 */
1032static irqreturn_t irq_nested_primary_handler(int irq, void *dev_id)
1033{
1034 WARN(1, "Primary handler called for nested irq %d\n", irq);
1035 return IRQ_NONE;
1036}
1037
2a1d3ab8
TG
1038static irqreturn_t irq_forced_secondary_handler(int irq, void *dev_id)
1039{
1040 WARN(1, "Secondary action handler called for irq %d\n", irq);
1041 return IRQ_NONE;
1042}
1043
3aa551c9
TG
1044static int irq_wait_for_interrupt(struct irqaction *action)
1045{
519cc865
LW
1046 for (;;) {
1047 set_current_state(TASK_INTERRUPTIBLE);
550acb19 1048
519cc865
LW
1049 if (kthread_should_stop()) {
1050 /* may need to run one last time */
1051 if (test_and_clear_bit(IRQTF_RUNTHREAD,
1052 &action->thread_flags)) {
1053 __set_current_state(TASK_RUNNING);
1054 return 0;
1055 }
1056 __set_current_state(TASK_RUNNING);
1057 return -1;
1058 }
f48fe81e
TG
1059
1060 if (test_and_clear_bit(IRQTF_RUNTHREAD,
1061 &action->thread_flags)) {
3aa551c9
TG
1062 __set_current_state(TASK_RUNNING);
1063 return 0;
f48fe81e
TG
1064 }
1065 schedule();
3aa551c9 1066 }
3aa551c9
TG
1067}
1068
b25c340c
TG
1069/*
1070 * Oneshot interrupts keep the irq line masked until the threaded
1071 * handler finished. unmask if the interrupt has not been disabled and
1072 * is marked MASKED.
1073 */
b5faba21 1074static void irq_finalize_oneshot(struct irq_desc *desc,
f3f79e38 1075 struct irqaction *action)
b25c340c 1076{
2a1d3ab8
TG
1077 if (!(desc->istate & IRQS_ONESHOT) ||
1078 action->handler == irq_forced_secondary_handler)
b5faba21 1079 return;
0b1adaa0 1080again:
3876ec9e 1081 chip_bus_lock(desc);
239007b8 1082 raw_spin_lock_irq(&desc->lock);
0b1adaa0
TG
1083
1084 /*
1085 * Implausible though it may be we need to protect us against
1086 * the following scenario:
1087 *
1088 * The thread is faster done than the hard interrupt handler
1089 * on the other CPU. If we unmask the irq line then the
1090 * interrupt can come in again and masks the line, leaves due
009b4c3b 1091 * to IRQS_INPROGRESS and the irq line is masked forever.
b5faba21
TG
1092 *
1093 * This also serializes the state of shared oneshot handlers
a359f757 1094 * versus "desc->threads_oneshot |= action->thread_mask;" in
b5faba21
TG
1095 * irq_wake_thread(). See the comment there which explains the
1096 * serialization.
0b1adaa0 1097 */
32f4125e 1098 if (unlikely(irqd_irq_inprogress(&desc->irq_data))) {
0b1adaa0 1099 raw_spin_unlock_irq(&desc->lock);
3876ec9e 1100 chip_bus_sync_unlock(desc);
0b1adaa0
TG
1101 cpu_relax();
1102 goto again;
1103 }
1104
b5faba21
TG
1105 /*
1106 * Now check again, whether the thread should run. Otherwise
1107 * we would clear the threads_oneshot bit of this thread which
1108 * was just set.
1109 */
f3f79e38 1110 if (test_bit(IRQTF_RUNTHREAD, &action->thread_flags))
b5faba21
TG
1111 goto out_unlock;
1112
1113 desc->threads_oneshot &= ~action->thread_mask;
1114
32f4125e
TG
1115 if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) &&
1116 irqd_irq_masked(&desc->irq_data))
328a4978 1117 unmask_threaded_irq(desc);
32f4125e 1118
b5faba21 1119out_unlock:
239007b8 1120 raw_spin_unlock_irq(&desc->lock);
3876ec9e 1121 chip_bus_sync_unlock(desc);
b25c340c
TG
1122}
1123
61f38261 1124#ifdef CONFIG_SMP
591d2fb0 1125/*
b04c644e 1126 * Check whether we need to change the affinity of the interrupt thread.
591d2fb0
TG
1127 */
1128static void
1129irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action)
1130{
1131 cpumask_var_t mask;
04aa530e 1132 bool valid = true;
591d2fb0
TG
1133
1134 if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags))
1135 return;
1136
1137 /*
1138 * In case we are out of memory we set IRQTF_AFFINITY again and
1139 * try again next time
1140 */
1141 if (!alloc_cpumask_var(&mask, GFP_KERNEL)) {
1142 set_bit(IRQTF_AFFINITY, &action->thread_flags);
1143 return;
1144 }
1145
239007b8 1146 raw_spin_lock_irq(&desc->lock);
04aa530e
TG
1147 /*
1148 * This code is triggered unconditionally. Check the affinity
1149 * mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out.
1150 */
cbf86999
TG
1151 if (cpumask_available(desc->irq_common_data.affinity)) {
1152 const struct cpumask *m;
1153
1154 m = irq_data_get_effective_affinity_mask(&desc->irq_data);
1155 cpumask_copy(mask, m);
1156 } else {
04aa530e 1157 valid = false;
cbf86999 1158 }
239007b8 1159 raw_spin_unlock_irq(&desc->lock);
591d2fb0 1160
04aa530e
TG
1161 if (valid)
1162 set_cpus_allowed_ptr(current, mask);
591d2fb0
TG
1163 free_cpumask_var(mask);
1164}
61f38261
BP
1165#else
1166static inline void
1167irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { }
1168#endif
591d2fb0 1169
8d32a307 1170/*
c5f48c0a 1171 * Interrupts which are not explicitly requested as threaded
8d32a307
TG
1172 * interrupts rely on the implicit bh/preempt disable of the hard irq
1173 * context. So we need to disable bh here to avoid deadlocks and other
1174 * side effects.
1175 */
3a43e05f 1176static irqreturn_t
8d32a307
TG
1177irq_forced_thread_fn(struct irq_desc *desc, struct irqaction *action)
1178{
3a43e05f
SAS
1179 irqreturn_t ret;
1180
8d32a307 1181 local_bh_disable();
81e2073c
TG
1182 if (!IS_ENABLED(CONFIG_PREEMPT_RT))
1183 local_irq_disable();
3a43e05f 1184 ret = action->thread_fn(action->irq, action->dev_id);
746a923b
LW
1185 if (ret == IRQ_HANDLED)
1186 atomic_inc(&desc->threads_handled);
1187
f3f79e38 1188 irq_finalize_oneshot(desc, action);
81e2073c
TG
1189 if (!IS_ENABLED(CONFIG_PREEMPT_RT))
1190 local_irq_enable();
8d32a307 1191 local_bh_enable();
3a43e05f 1192 return ret;
8d32a307
TG
1193}
1194
1195/*
f788e7bf 1196 * Interrupts explicitly requested as threaded interrupts want to be
5c982c58 1197 * preemptible - many of them need to sleep and wait for slow busses to
8d32a307
TG
1198 * complete.
1199 */
3a43e05f
SAS
1200static irqreturn_t irq_thread_fn(struct irq_desc *desc,
1201 struct irqaction *action)
8d32a307 1202{
3a43e05f
SAS
1203 irqreturn_t ret;
1204
1205 ret = action->thread_fn(action->irq, action->dev_id);
746a923b
LW
1206 if (ret == IRQ_HANDLED)
1207 atomic_inc(&desc->threads_handled);
1208
f3f79e38 1209 irq_finalize_oneshot(desc, action);
3a43e05f 1210 return ret;
8d32a307
TG
1211}
1212
7140ea19
IY
1213static void wake_threads_waitq(struct irq_desc *desc)
1214{
c685689f 1215 if (atomic_dec_and_test(&desc->threads_active))
7140ea19
IY
1216 wake_up(&desc->wait_for_threads);
1217}
1218
67d12145 1219static void irq_thread_dtor(struct callback_head *unused)
4d1d61a6
ON
1220{
1221 struct task_struct *tsk = current;
1222 struct irq_desc *desc;
1223 struct irqaction *action;
1224
1225 if (WARN_ON_ONCE(!(current->flags & PF_EXITING)))
1226 return;
1227
1228 action = kthread_data(tsk);
1229
fb21affa 1230 pr_err("exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n",
19af395d 1231 tsk->comm, tsk->pid, action->irq);
4d1d61a6
ON
1232
1233
1234 desc = irq_to_desc(action->irq);
1235 /*
1236 * If IRQTF_RUNTHREAD is set, we need to decrement
1237 * desc->threads_active and wake possible waiters.
1238 */
1239 if (test_and_clear_bit(IRQTF_RUNTHREAD, &action->thread_flags))
1240 wake_threads_waitq(desc);
1241
1242 /* Prevent a stale desc->threads_oneshot */
1243 irq_finalize_oneshot(desc, action);
1244}
1245
2a1d3ab8
TG
1246static void irq_wake_secondary(struct irq_desc *desc, struct irqaction *action)
1247{
1248 struct irqaction *secondary = action->secondary;
1249
1250 if (WARN_ON_ONCE(!secondary))
1251 return;
1252
1253 raw_spin_lock_irq(&desc->lock);
1254 __irq_wake_thread(desc, secondary);
1255 raw_spin_unlock_irq(&desc->lock);
1256}
1257
8707898e
TP
1258/*
1259 * Internal function to notify that a interrupt thread is ready.
1260 */
1261static void irq_thread_set_ready(struct irq_desc *desc,
1262 struct irqaction *action)
1263{
1264 set_bit(IRQTF_READY, &action->thread_flags);
1265 wake_up(&desc->wait_for_threads);
1266}
1267
1268/*
1269 * Internal function to wake up a interrupt thread and wait until it is
1270 * ready.
1271 */
1272static void wake_up_and_wait_for_irq_thread_ready(struct irq_desc *desc,
1273 struct irqaction *action)
1274{
1275 if (!action || !action->thread)
1276 return;
1277
1278 wake_up_process(action->thread);
1279 wait_event(desc->wait_for_threads,
1280 test_bit(IRQTF_READY, &action->thread_flags));
1281}
1282
3aa551c9
TG
1283/*
1284 * Interrupt handler thread
1285 */
1286static int irq_thread(void *data)
1287{
67d12145 1288 struct callback_head on_exit_work;
3aa551c9
TG
1289 struct irqaction *action = data;
1290 struct irq_desc *desc = irq_to_desc(action->irq);
3a43e05f
SAS
1291 irqreturn_t (*handler_fn)(struct irq_desc *desc,
1292 struct irqaction *action);
3aa551c9 1293
8707898e
TP
1294 irq_thread_set_ready(desc, action);
1295
e739f98b
TG
1296 sched_set_fifo(current);
1297
91cc470e
TL
1298 if (force_irqthreads() && test_bit(IRQTF_FORCED_THREAD,
1299 &action->thread_flags))
8d32a307
TG
1300 handler_fn = irq_forced_thread_fn;
1301 else
1302 handler_fn = irq_thread_fn;
1303
41f9d29f 1304 init_task_work(&on_exit_work, irq_thread_dtor);
91989c70 1305 task_work_add(current, &on_exit_work, TWA_NONE);
3aa551c9 1306
f3de44ed
SM
1307 irq_thread_check_affinity(desc, action);
1308
3aa551c9 1309 while (!irq_wait_for_interrupt(action)) {
7140ea19 1310 irqreturn_t action_ret;
3aa551c9 1311
591d2fb0
TG
1312 irq_thread_check_affinity(desc, action);
1313
7140ea19 1314 action_ret = handler_fn(desc, action);
2a1d3ab8
TG
1315 if (action_ret == IRQ_WAKE_THREAD)
1316 irq_wake_secondary(desc, action);
3aa551c9 1317
7140ea19 1318 wake_threads_waitq(desc);
3aa551c9
TG
1319 }
1320
7140ea19
IY
1321 /*
1322 * This is the regular exit path. __free_irq() is stopping the
1323 * thread via kthread_stop() after calling
519cc865 1324 * synchronize_hardirq(). So neither IRQTF_RUNTHREAD nor the
836557bd 1325 * oneshot mask bit can be set.
3aa551c9 1326 */
4d1d61a6 1327 task_work_cancel(current, irq_thread_dtor);
3aa551c9
TG
1328 return 0;
1329}
1330
a92444c6
TG
1331/**
1332 * irq_wake_thread - wake the irq thread for the action identified by dev_id
1333 * @irq: Interrupt line
1334 * @dev_id: Device identity for which the thread should be woken
1335 *
1336 */
1337void irq_wake_thread(unsigned int irq, void *dev_id)
1338{
1339 struct irq_desc *desc = irq_to_desc(irq);
1340 struct irqaction *action;
1341 unsigned long flags;
1342
1343 if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc)))
1344 return;
1345
1346 raw_spin_lock_irqsave(&desc->lock, flags);
f944b5a7 1347 for_each_action_of_desc(desc, action) {
a92444c6
TG
1348 if (action->dev_id == dev_id) {
1349 if (action->thread)
1350 __irq_wake_thread(desc, action);
1351 break;
1352 }
1353 }
1354 raw_spin_unlock_irqrestore(&desc->lock, flags);
1355}
1356EXPORT_SYMBOL_GPL(irq_wake_thread);
1357
2a1d3ab8 1358static int irq_setup_forced_threading(struct irqaction *new)
8d32a307 1359{
91cc470e 1360 if (!force_irqthreads())
2a1d3ab8 1361 return 0;
8d32a307 1362 if (new->flags & (IRQF_NO_THREAD | IRQF_PERCPU | IRQF_ONESHOT))
2a1d3ab8 1363 return 0;
8d32a307 1364
d1f0301b
TG
1365 /*
1366 * No further action required for interrupts which are requested as
1367 * threaded interrupts already
1368 */
1369 if (new->handler == irq_default_primary_handler)
1370 return 0;
1371
8d32a307
TG
1372 new->flags |= IRQF_ONESHOT;
1373
2a1d3ab8
TG
1374 /*
1375 * Handle the case where we have a real primary handler and a
1376 * thread handler. We force thread them as well by creating a
1377 * secondary action.
1378 */
d1f0301b 1379 if (new->handler && new->thread_fn) {
2a1d3ab8
TG
1380 /* Allocate the secondary action */
1381 new->secondary = kzalloc(sizeof(struct irqaction), GFP_KERNEL);
1382 if (!new->secondary)
1383 return -ENOMEM;
1384 new->secondary->handler = irq_forced_secondary_handler;
1385 new->secondary->thread_fn = new->thread_fn;
1386 new->secondary->dev_id = new->dev_id;
1387 new->secondary->irq = new->irq;
1388 new->secondary->name = new->name;
8d32a307 1389 }
2a1d3ab8
TG
1390 /* Deal with the primary handler */
1391 set_bit(IRQTF_FORCED_THREAD, &new->thread_flags);
1392 new->thread_fn = new->handler;
1393 new->handler = irq_default_primary_handler;
1394 return 0;
8d32a307
TG
1395}
1396
c1bacbae
TG
1397static int irq_request_resources(struct irq_desc *desc)
1398{
1399 struct irq_data *d = &desc->irq_data;
1400 struct irq_chip *c = d->chip;
1401
1402 return c->irq_request_resources ? c->irq_request_resources(d) : 0;
1403}
1404
1405static void irq_release_resources(struct irq_desc *desc)
1406{
1407 struct irq_data *d = &desc->irq_data;
1408 struct irq_chip *c = d->chip;
1409
1410 if (c->irq_release_resources)
1411 c->irq_release_resources(d);
1412}
1413
b525903c
JT
1414static bool irq_supports_nmi(struct irq_desc *desc)
1415{
1416 struct irq_data *d = irq_desc_get_irq_data(desc);
1417
1418#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
1419 /* Only IRQs directly managed by the root irqchip can be set as NMI */
1420 if (d->parent_data)
1421 return false;
1422#endif
1423 /* Don't support NMIs for chips behind a slow bus */
1424 if (d->chip->irq_bus_lock || d->chip->irq_bus_sync_unlock)
1425 return false;
1426
1427 return d->chip->flags & IRQCHIP_SUPPORTS_NMI;
1428}
1429
1430static int irq_nmi_setup(struct irq_desc *desc)
1431{
1432 struct irq_data *d = irq_desc_get_irq_data(desc);
1433 struct irq_chip *c = d->chip;
1434
1435 return c->irq_nmi_setup ? c->irq_nmi_setup(d) : -EINVAL;
1436}
1437
1438static void irq_nmi_teardown(struct irq_desc *desc)
1439{
1440 struct irq_data *d = irq_desc_get_irq_data(desc);
1441 struct irq_chip *c = d->chip;
1442
1443 if (c->irq_nmi_teardown)
1444 c->irq_nmi_teardown(d);
1445}
1446
2a1d3ab8
TG
1447static int
1448setup_irq_thread(struct irqaction *new, unsigned int irq, bool secondary)
1449{
1450 struct task_struct *t;
2a1d3ab8
TG
1451
1452 if (!secondary) {
1453 t = kthread_create(irq_thread, new, "irq/%d-%s", irq,
1454 new->name);
1455 } else {
1456 t = kthread_create(irq_thread, new, "irq/%d-s-%s", irq,
1457 new->name);
2a1d3ab8
TG
1458 }
1459
1460 if (IS_ERR(t))
1461 return PTR_ERR(t);
1462
2a1d3ab8
TG
1463 /*
1464 * We keep the reference to the task struct even if
1465 * the thread dies to avoid that the interrupt code
1466 * references an already freed task_struct.
1467 */
7b3c92b8 1468 new->thread = get_task_struct(t);
2a1d3ab8
TG
1469 /*
1470 * Tell the thread to set its affinity. This is
1471 * important for shared interrupt handlers as we do
1472 * not invoke setup_affinity() for the secondary
1473 * handlers as everything is already set up. Even for
1474 * interrupts marked with IRQF_NO_BALANCE this is
1475 * correct as we want the thread to move to the cpu(s)
1476 * on which the requesting code placed the interrupt.
1477 */
1478 set_bit(IRQTF_AFFINITY, &new->thread_flags);
1479 return 0;
1480}
1481
1da177e4
LT
1482/*
1483 * Internal function to register an irqaction - typically used to
1484 * allocate special interrupts that are part of the architecture.
19d39a38
TG
1485 *
1486 * Locking rules:
1487 *
1488 * desc->request_mutex Provides serialization against a concurrent free_irq()
1489 * chip_bus_lock Provides serialization for slow bus operations
1490 * desc->lock Provides serialization against hard interrupts
1491 *
1492 * chip_bus_lock and desc->lock are sufficient for all other management and
1493 * interrupt related functions. desc->request_mutex solely serializes
1494 * request/free_irq().
1da177e4 1495 */
d3c60047 1496static int
327ec569 1497__setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new)
1da177e4 1498{
f17c7545 1499 struct irqaction *old, **old_ptr;
b5faba21 1500 unsigned long flags, thread_mask = 0;
3b8249e7 1501 int ret, nested, shared = 0;
1da177e4 1502
7d94f7ca 1503 if (!desc)
c2b5a251
MW
1504 return -EINVAL;
1505
6b8ff312 1506 if (desc->irq_data.chip == &no_irq_chip)
1da177e4 1507 return -ENOSYS;
b6873807
SAS
1508 if (!try_module_get(desc->owner))
1509 return -ENODEV;
1da177e4 1510
2a1d3ab8
TG
1511 new->irq = irq;
1512
4b357dae
JH
1513 /*
1514 * If the trigger type is not specified by the caller,
1515 * then use the default for this interrupt.
1516 */
1517 if (!(new->flags & IRQF_TRIGGER_MASK))
1518 new->flags |= irqd_get_trigger_type(&desc->irq_data);
1519
3aa551c9 1520 /*
399b5da2
TG
1521 * Check whether the interrupt nests into another interrupt
1522 * thread.
1523 */
1ccb4e61 1524 nested = irq_settings_is_nested_thread(desc);
399b5da2 1525 if (nested) {
b6873807
SAS
1526 if (!new->thread_fn) {
1527 ret = -EINVAL;
1528 goto out_mput;
1529 }
399b5da2
TG
1530 /*
1531 * Replace the primary handler which was provided from
1532 * the driver for non nested interrupt handling by the
1533 * dummy function which warns when called.
1534 */
1535 new->handler = irq_nested_primary_handler;
8d32a307 1536 } else {
2a1d3ab8
TG
1537 if (irq_settings_can_thread(desc)) {
1538 ret = irq_setup_forced_threading(new);
1539 if (ret)
1540 goto out_mput;
1541 }
399b5da2
TG
1542 }
1543
3aa551c9 1544 /*
399b5da2
TG
1545 * Create a handler thread when a thread function is supplied
1546 * and the interrupt does not nest into another interrupt
1547 * thread.
3aa551c9 1548 */
399b5da2 1549 if (new->thread_fn && !nested) {
2a1d3ab8
TG
1550 ret = setup_irq_thread(new, irq, false);
1551 if (ret)
b6873807 1552 goto out_mput;
2a1d3ab8
TG
1553 if (new->secondary) {
1554 ret = setup_irq_thread(new->secondary, irq, true);
1555 if (ret)
1556 goto out_thread;
b6873807 1557 }
3aa551c9
TG
1558 }
1559
dc9b229a
TG
1560 /*
1561 * Drivers are often written to work w/o knowledge about the
1562 * underlying irq chip implementation, so a request for a
1563 * threaded irq without a primary hard irq context handler
1564 * requires the ONESHOT flag to be set. Some irq chips like
1565 * MSI based interrupts are per se one shot safe. Check the
1566 * chip flags, so we can avoid the unmask dance at the end of
1567 * the threaded handler for those.
1568 */
1569 if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)
1570 new->flags &= ~IRQF_ONESHOT;
1571
19d39a38
TG
1572 /*
1573 * Protects against a concurrent __free_irq() call which might wait
519cc865 1574 * for synchronize_hardirq() to complete without holding the optional
836557bd
LW
1575 * chip bus lock and desc->lock. Also protects against handing out
1576 * a recycled oneshot thread_mask bit while it's still in use by
1577 * its previous owner.
19d39a38 1578 */
9114014c 1579 mutex_lock(&desc->request_mutex);
19d39a38
TG
1580
1581 /*
1582 * Acquire bus lock as the irq_request_resources() callback below
1583 * might rely on the serialization or the magic power management
1584 * functions which are abusing the irq_bus_lock() callback,
1585 */
1586 chip_bus_lock(desc);
1587
1588 /* First installed action requests resources. */
46e48e25
TG
1589 if (!desc->action) {
1590 ret = irq_request_resources(desc);
1591 if (ret) {
1592 pr_err("Failed to request resources for %s (irq %d) on irqchip %s\n",
1593 new->name, irq, desc->irq_data.chip->name);
19d39a38 1594 goto out_bus_unlock;
46e48e25
TG
1595 }
1596 }
9114014c 1597
1da177e4
LT
1598 /*
1599 * The following block of code has to be executed atomically
19d39a38
TG
1600 * protected against a concurrent interrupt and any of the other
1601 * management calls which are not serialized via
1602 * desc->request_mutex or the optional bus lock.
1da177e4 1603 */
239007b8 1604 raw_spin_lock_irqsave(&desc->lock, flags);
f17c7545
IM
1605 old_ptr = &desc->action;
1606 old = *old_ptr;
06fcb0c6 1607 if (old) {
e76de9f8
TG
1608 /*
1609 * Can't share interrupts unless both agree to and are
1610 * the same type (level, edge, polarity). So both flag
3cca53b0 1611 * fields must have IRQF_SHARED set and the bits which
9d591edd
TG
1612 * set the trigger type must match. Also all must
1613 * agree on ONESHOT.
b525903c 1614 * Interrupt lines used for NMIs cannot be shared.
e76de9f8 1615 */
4f8413a3
MZ
1616 unsigned int oldtype;
1617
b525903c
JT
1618 if (desc->istate & IRQS_NMI) {
1619 pr_err("Invalid attempt to share NMI for %s (irq %d) on irqchip %s.\n",
1620 new->name, irq, desc->irq_data.chip->name);
1621 ret = -EINVAL;
1622 goto out_unlock;
1623 }
1624
4f8413a3
MZ
1625 /*
1626 * If nobody did set the configuration before, inherit
1627 * the one provided by the requester.
1628 */
1629 if (irqd_trigger_type_was_set(&desc->irq_data)) {
1630 oldtype = irqd_get_trigger_type(&desc->irq_data);
1631 } else {
1632 oldtype = new->flags & IRQF_TRIGGER_MASK;
1633 irqd_set_trigger_type(&desc->irq_data, oldtype);
1634 }
382bd4de 1635
3cca53b0 1636 if (!((old->flags & new->flags) & IRQF_SHARED) ||
382bd4de 1637 (oldtype != (new->flags & IRQF_TRIGGER_MASK)) ||
f5d89470 1638 ((old->flags ^ new->flags) & IRQF_ONESHOT))
f5163427
DS
1639 goto mismatch;
1640
f5163427 1641 /* All handlers must agree on per-cpuness */
3cca53b0
TG
1642 if ((old->flags & IRQF_PERCPU) !=
1643 (new->flags & IRQF_PERCPU))
f5163427 1644 goto mismatch;
1da177e4
LT
1645
1646 /* add new interrupt at end of irq queue */
1647 do {
52abb700
TG
1648 /*
1649 * Or all existing action->thread_mask bits,
1650 * so we can find the next zero bit for this
1651 * new action.
1652 */
b5faba21 1653 thread_mask |= old->thread_mask;
f17c7545
IM
1654 old_ptr = &old->next;
1655 old = *old_ptr;
1da177e4
LT
1656 } while (old);
1657 shared = 1;
1658 }
1659
b5faba21 1660 /*
52abb700
TG
1661 * Setup the thread mask for this irqaction for ONESHOT. For
1662 * !ONESHOT irqs the thread mask is 0 so we can avoid a
1663 * conditional in irq_wake_thread().
b5faba21 1664 */
52abb700
TG
1665 if (new->flags & IRQF_ONESHOT) {
1666 /*
1667 * Unlikely to have 32 resp 64 irqs sharing one line,
1668 * but who knows.
1669 */
1670 if (thread_mask == ~0UL) {
1671 ret = -EBUSY;
cba4235e 1672 goto out_unlock;
52abb700
TG
1673 }
1674 /*
1675 * The thread_mask for the action is or'ed to
1676 * desc->thread_active to indicate that the
1677 * IRQF_ONESHOT thread handler has been woken, but not
1678 * yet finished. The bit is cleared when a thread
1679 * completes. When all threads of a shared interrupt
1680 * line have completed desc->threads_active becomes
1681 * zero and the interrupt line is unmasked. See
1682 * handle.c:irq_wake_thread() for further information.
1683 *
1684 * If no thread is woken by primary (hard irq context)
1685 * interrupt handlers, then desc->threads_active is
1686 * also checked for zero to unmask the irq line in the
1687 * affected hard irq flow handlers
1688 * (handle_[fasteoi|level]_irq).
1689 *
1690 * The new action gets the first zero bit of
1691 * thread_mask assigned. See the loop above which or's
1692 * all existing action->thread_mask bits.
1693 */
ffc661c9 1694 new->thread_mask = 1UL << ffz(thread_mask);
1c6c6952 1695
dc9b229a
TG
1696 } else if (new->handler == irq_default_primary_handler &&
1697 !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) {
1c6c6952
TG
1698 /*
1699 * The interrupt was requested with handler = NULL, so
1700 * we use the default primary handler for it. But it
1701 * does not have the oneshot flag set. In combination
1702 * with level interrupts this is deadly, because the
1703 * default primary handler just wakes the thread, then
1704 * the irq lines is reenabled, but the device still
1705 * has the level irq asserted. Rinse and repeat....
1706 *
1707 * While this works for edge type interrupts, we play
1708 * it safe and reject unconditionally because we can't
1709 * say for sure which type this interrupt really
1710 * has. The type flags are unreliable as the
1711 * underlying chip implementation can override them.
1712 */
025af39b
LC
1713 pr_err("Threaded irq requested with handler=NULL and !ONESHOT for %s (irq %d)\n",
1714 new->name, irq);
1c6c6952 1715 ret = -EINVAL;
cba4235e 1716 goto out_unlock;
b5faba21 1717 }
b5faba21 1718
1da177e4 1719 if (!shared) {
e76de9f8 1720 /* Setup the type (level, edge polarity) if configured: */
3cca53b0 1721 if (new->flags & IRQF_TRIGGER_MASK) {
a1ff541a
JL
1722 ret = __irq_set_trigger(desc,
1723 new->flags & IRQF_TRIGGER_MASK);
82736f4d 1724
19d39a38 1725 if (ret)
cba4235e 1726 goto out_unlock;
091738a2 1727 }
6a6de9ef 1728
c942cee4
TG
1729 /*
1730 * Activate the interrupt. That activation must happen
1731 * independently of IRQ_NOAUTOEN. request_irq() can fail
1732 * and the callers are supposed to handle
1733 * that. enable_irq() of an interrupt requested with
1734 * IRQ_NOAUTOEN is not supposed to fail. The activation
1735 * keeps it in shutdown mode, it merily associates
1736 * resources if necessary and if that's not possible it
1737 * fails. Interrupts which are in managed shutdown mode
1738 * will simply ignore that activation request.
1739 */
1740 ret = irq_activate(desc);
1741 if (ret)
1742 goto out_unlock;
1743
009b4c3b 1744 desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \
32f4125e
TG
1745 IRQS_ONESHOT | IRQS_WAITING);
1746 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
94d39e1f 1747
a005677b
TG
1748 if (new->flags & IRQF_PERCPU) {
1749 irqd_set(&desc->irq_data, IRQD_PER_CPU);
1750 irq_settings_set_per_cpu(desc);
c2b1063e
TG
1751 if (new->flags & IRQF_NO_DEBUG)
1752 irq_settings_set_no_debug(desc);
a005677b 1753 }
6a58fb3b 1754
c2b1063e
TG
1755 if (noirqdebug)
1756 irq_settings_set_no_debug(desc);
1757
b25c340c 1758 if (new->flags & IRQF_ONESHOT)
3d67baec 1759 desc->istate |= IRQS_ONESHOT;
b25c340c 1760
2e051552
TG
1761 /* Exclude IRQ from balancing if requested */
1762 if (new->flags & IRQF_NOBALANCING) {
1763 irq_settings_set_no_balancing(desc);
1764 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
1765 }
1766
cbe16f35
BS
1767 if (!(new->flags & IRQF_NO_AUTOEN) &&
1768 irq_settings_can_autoenable(desc)) {
4cde9c6b 1769 irq_startup(desc, IRQ_RESEND, IRQ_START_COND);
04c848d3
TG
1770 } else {
1771 /*
1772 * Shared interrupts do not go well with disabling
1773 * auto enable. The sharing interrupt might request
1774 * it while it's still disabled and then wait for
1775 * interrupts forever.
1776 */
1777 WARN_ON_ONCE(new->flags & IRQF_SHARED);
e76de9f8
TG
1778 /* Undo nested disables: */
1779 desc->depth = 1;
04c848d3 1780 }
18404756 1781
876dbd4c
TG
1782 } else if (new->flags & IRQF_TRIGGER_MASK) {
1783 unsigned int nmsk = new->flags & IRQF_TRIGGER_MASK;
7ee7e87d 1784 unsigned int omsk = irqd_get_trigger_type(&desc->irq_data);
876dbd4c
TG
1785
1786 if (nmsk != omsk)
1787 /* hope the handler works with current trigger mode */
a395d6a7 1788 pr_warn("irq %d uses trigger mode %u; requested %u\n",
7ee7e87d 1789 irq, omsk, nmsk);
1da177e4 1790 }
82736f4d 1791
f17c7545 1792 *old_ptr = new;
82736f4d 1793
cab303be
TG
1794 irq_pm_install_action(desc, new);
1795
8528b0f1
LT
1796 /* Reset broken irq detection when installing new handler */
1797 desc->irq_count = 0;
1798 desc->irqs_unhandled = 0;
1adb0850
TG
1799
1800 /*
1801 * Check whether we disabled the irq via the spurious handler
1802 * before. Reenable it and give it another chance.
1803 */
7acdd53e
TG
1804 if (shared && (desc->istate & IRQS_SPURIOUS_DISABLED)) {
1805 desc->istate &= ~IRQS_SPURIOUS_DISABLED;
79ff1cda 1806 __enable_irq(desc);
1adb0850
TG
1807 }
1808
239007b8 1809 raw_spin_unlock_irqrestore(&desc->lock, flags);
3a90795e 1810 chip_bus_sync_unlock(desc);
9114014c 1811 mutex_unlock(&desc->request_mutex);
1da177e4 1812
b2d3d61a
DL
1813 irq_setup_timings(desc, new);
1814
8707898e
TP
1815 wake_up_and_wait_for_irq_thread_ready(desc, new);
1816 wake_up_and_wait_for_irq_thread_ready(desc, new->secondary);
69ab8494 1817
2c6927a3 1818 register_irq_proc(irq, desc);
1da177e4
LT
1819 new->dir = NULL;
1820 register_handler_proc(irq, new);
1da177e4 1821 return 0;
f5163427
DS
1822
1823mismatch:
3cca53b0 1824 if (!(new->flags & IRQF_PROBE_SHARED)) {
97fd75b7 1825 pr_err("Flags mismatch irq %d. %08x (%s) vs. %08x (%s)\n",
f5d89470
TG
1826 irq, new->flags, new->name, old->flags, old->name);
1827#ifdef CONFIG_DEBUG_SHIRQ
13e87ec6 1828 dump_stack();
3f050447 1829#endif
f5d89470 1830 }
3aa551c9
TG
1831 ret = -EBUSY;
1832
cba4235e 1833out_unlock:
1c389795 1834 raw_spin_unlock_irqrestore(&desc->lock, flags);
3b8249e7 1835
46e48e25
TG
1836 if (!desc->action)
1837 irq_release_resources(desc);
19d39a38
TG
1838out_bus_unlock:
1839 chip_bus_sync_unlock(desc);
9114014c
TG
1840 mutex_unlock(&desc->request_mutex);
1841
3aa551c9 1842out_thread:
3aa551c9
TG
1843 if (new->thread) {
1844 struct task_struct *t = new->thread;
1845
1846 new->thread = NULL;
05d74efa 1847 kthread_stop(t);
3aa551c9
TG
1848 put_task_struct(t);
1849 }
2a1d3ab8
TG
1850 if (new->secondary && new->secondary->thread) {
1851 struct task_struct *t = new->secondary->thread;
1852
1853 new->secondary->thread = NULL;
1854 kthread_stop(t);
1855 put_task_struct(t);
1856 }
b6873807
SAS
1857out_mput:
1858 module_put(desc->owner);
3aa551c9 1859 return ret;
1da177e4
LT
1860}
1861
31d9d9b6 1862/*
cbf94f06
MD
1863 * Internal function to unregister an irqaction - used to free
1864 * regular and special interrupts that are part of the architecture.
1da177e4 1865 */
83ac4ca9 1866static struct irqaction *__free_irq(struct irq_desc *desc, void *dev_id)
1da177e4 1867{
83ac4ca9 1868 unsigned irq = desc->irq_data.irq;
f17c7545 1869 struct irqaction *action, **action_ptr;
1da177e4
LT
1870 unsigned long flags;
1871
ae88a23b 1872 WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq);
7d94f7ca 1873
9114014c 1874 mutex_lock(&desc->request_mutex);
abc7e40c 1875 chip_bus_lock(desc);
239007b8 1876 raw_spin_lock_irqsave(&desc->lock, flags);
ae88a23b
IM
1877
1878 /*
1879 * There can be multiple actions per IRQ descriptor, find the right
1880 * one based on the dev_id:
1881 */
f17c7545 1882 action_ptr = &desc->action;
1da177e4 1883 for (;;) {
f17c7545 1884 action = *action_ptr;
1da177e4 1885
ae88a23b
IM
1886 if (!action) {
1887 WARN(1, "Trying to free already-free IRQ %d\n", irq);
239007b8 1888 raw_spin_unlock_irqrestore(&desc->lock, flags);
abc7e40c 1889 chip_bus_sync_unlock(desc);
19d39a38 1890 mutex_unlock(&desc->request_mutex);
f21cfb25 1891 return NULL;
ae88a23b 1892 }
1da177e4 1893
8316e381
IM
1894 if (action->dev_id == dev_id)
1895 break;
f17c7545 1896 action_ptr = &action->next;
ae88a23b 1897 }
dbce706e 1898
ae88a23b 1899 /* Found it - now remove it from the list of entries: */
f17c7545 1900 *action_ptr = action->next;
ae88a23b 1901
cab303be
TG
1902 irq_pm_remove_action(desc, action);
1903
ae88a23b 1904 /* If this was the last handler, shut down the IRQ line: */
c1bacbae 1905 if (!desc->action) {
e9849777 1906 irq_settings_clr_disable_unlazy(desc);
4001d8e8 1907 /* Only shutdown. Deactivate after synchronize_hardirq() */
46999238 1908 irq_shutdown(desc);
c1bacbae 1909 }
3aa551c9 1910
e7a297b0
PWJ
1911#ifdef CONFIG_SMP
1912 /* make sure affinity_hint is cleaned up */
1913 if (WARN_ON_ONCE(desc->affinity_hint))
1914 desc->affinity_hint = NULL;
1915#endif
1916
239007b8 1917 raw_spin_unlock_irqrestore(&desc->lock, flags);
19d39a38
TG
1918 /*
1919 * Drop bus_lock here so the changes which were done in the chip
1920 * callbacks above are synced out to the irq chips which hang
519cc865 1921 * behind a slow bus (I2C, SPI) before calling synchronize_hardirq().
19d39a38
TG
1922 *
1923 * Aside of that the bus_lock can also be taken from the threaded
1924 * handler in irq_finalize_oneshot() which results in a deadlock
519cc865 1925 * because kthread_stop() would wait forever for the thread to
19d39a38
TG
1926 * complete, which is blocked on the bus lock.
1927 *
1928 * The still held desc->request_mutex() protects against a
1929 * concurrent request_irq() of this irq so the release of resources
1930 * and timing data is properly serialized.
1931 */
abc7e40c 1932 chip_bus_sync_unlock(desc);
ae88a23b
IM
1933
1934 unregister_handler_proc(irq, action);
1935
62e04686
TG
1936 /*
1937 * Make sure it's not being used on another CPU and if the chip
1938 * supports it also make sure that there is no (not yet serviced)
1939 * interrupt in flight at the hardware level.
1940 */
1941 __synchronize_hardirq(desc, true);
1da177e4 1942
70edcd77 1943#ifdef CONFIG_DEBUG_SHIRQ
ae88a23b
IM
1944 /*
1945 * It's a shared IRQ -- the driver ought to be prepared for an IRQ
1946 * event to happen even now it's being freed, so let's make sure that
1947 * is so by doing an extra call to the handler ....
1948 *
1949 * ( We do this after actually deregistering it, to make sure that a
0a13ec0b 1950 * 'real' IRQ doesn't run in parallel with our fake. )
ae88a23b
IM
1951 */
1952 if (action->flags & IRQF_SHARED) {
1953 local_irq_save(flags);
1954 action->handler(irq, dev_id);
1955 local_irq_restore(flags);
1da177e4 1956 }
ae88a23b 1957#endif
2d860ad7 1958
519cc865
LW
1959 /*
1960 * The action has already been removed above, but the thread writes
1961 * its oneshot mask bit when it completes. Though request_mutex is
1962 * held across this which prevents __setup_irq() from handing out
1963 * the same bit to a newly requested action.
1964 */
2d860ad7 1965 if (action->thread) {
05d74efa 1966 kthread_stop(action->thread);
2d860ad7 1967 put_task_struct(action->thread);
2a1d3ab8
TG
1968 if (action->secondary && action->secondary->thread) {
1969 kthread_stop(action->secondary->thread);
1970 put_task_struct(action->secondary->thread);
1971 }
2d860ad7
LT
1972 }
1973
19d39a38 1974 /* Last action releases resources */
2343877f 1975 if (!desc->action) {
19d39a38 1976 /*
a359f757 1977 * Reacquire bus lock as irq_release_resources() might
19d39a38
TG
1978 * require it to deallocate resources over the slow bus.
1979 */
1980 chip_bus_lock(desc);
4001d8e8
TG
1981 /*
1982 * There is no interrupt on the fly anymore. Deactivate it
1983 * completely.
1984 */
1985 raw_spin_lock_irqsave(&desc->lock, flags);
1986 irq_domain_deactivate_irq(&desc->irq_data);
1987 raw_spin_unlock_irqrestore(&desc->lock, flags);
1988
46e48e25 1989 irq_release_resources(desc);
19d39a38 1990 chip_bus_sync_unlock(desc);
2343877f
TG
1991 irq_remove_timings(desc);
1992 }
46e48e25 1993
9114014c
TG
1994 mutex_unlock(&desc->request_mutex);
1995
be45beb2 1996 irq_chip_pm_put(&desc->irq_data);
b6873807 1997 module_put(desc->owner);
2a1d3ab8 1998 kfree(action->secondary);
f21cfb25
MD
1999 return action;
2000}
2001
2002/**
2003 * free_irq - free an interrupt allocated with request_irq
2004 * @irq: Interrupt line to free
2005 * @dev_id: Device identity to free
2006 *
2007 * Remove an interrupt handler. The handler is removed and if the
2008 * interrupt line is no longer in use by any driver it is disabled.
2009 * On a shared IRQ the caller must ensure the interrupt is disabled
2010 * on the card it drives before calling this function. The function
2011 * does not return until any executing interrupts for this IRQ
2012 * have completed.
2013 *
2014 * This function must not be called from interrupt context.
25ce4be7
CH
2015 *
2016 * Returns the devname argument passed to request_irq.
f21cfb25 2017 */
25ce4be7 2018const void *free_irq(unsigned int irq, void *dev_id)
f21cfb25 2019{
70aedd24 2020 struct irq_desc *desc = irq_to_desc(irq);
25ce4be7
CH
2021 struct irqaction *action;
2022 const char *devname;
70aedd24 2023
31d9d9b6 2024 if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc)))
25ce4be7 2025 return NULL;
70aedd24 2026
cd7eab44
BH
2027#ifdef CONFIG_SMP
2028 if (WARN_ON(desc->affinity_notify))
2029 desc->affinity_notify = NULL;
2030#endif
2031
83ac4ca9 2032 action = __free_irq(desc, dev_id);
2827a418
AM
2033
2034 if (!action)
2035 return NULL;
2036
25ce4be7
CH
2037 devname = action->name;
2038 kfree(action);
2039 return devname;
1da177e4 2040}
1da177e4
LT
2041EXPORT_SYMBOL(free_irq);
2042
b525903c
JT
2043/* This function must be called with desc->lock held */
2044static const void *__cleanup_nmi(unsigned int irq, struct irq_desc *desc)
2045{
2046 const char *devname = NULL;
2047
2048 desc->istate &= ~IRQS_NMI;
2049
2050 if (!WARN_ON(desc->action == NULL)) {
2051 irq_pm_remove_action(desc, desc->action);
2052 devname = desc->action->name;
2053 unregister_handler_proc(irq, desc->action);
2054
2055 kfree(desc->action);
2056 desc->action = NULL;
2057 }
2058
2059 irq_settings_clr_disable_unlazy(desc);
4001d8e8 2060 irq_shutdown_and_deactivate(desc);
b525903c
JT
2061
2062 irq_release_resources(desc);
2063
2064 irq_chip_pm_put(&desc->irq_data);
2065 module_put(desc->owner);
2066
2067 return devname;
2068}
2069
2070const void *free_nmi(unsigned int irq, void *dev_id)
2071{
2072 struct irq_desc *desc = irq_to_desc(irq);
2073 unsigned long flags;
2074 const void *devname;
2075
2076 if (!desc || WARN_ON(!(desc->istate & IRQS_NMI)))
2077 return NULL;
2078
2079 if (WARN_ON(irq_settings_is_per_cpu_devid(desc)))
2080 return NULL;
2081
2082 /* NMI still enabled */
2083 if (WARN_ON(desc->depth == 0))
2084 disable_nmi_nosync(irq);
2085
2086 raw_spin_lock_irqsave(&desc->lock, flags);
2087
2088 irq_nmi_teardown(desc);
2089 devname = __cleanup_nmi(irq, desc);
2090
2091 raw_spin_unlock_irqrestore(&desc->lock, flags);
2092
2093 return devname;
2094}
2095
1da177e4 2096/**
3aa551c9 2097 * request_threaded_irq - allocate an interrupt line
1da177e4 2098 * @irq: Interrupt line to allocate
3aa551c9 2099 * @handler: Function to be called when the IRQ occurs.
61377ec1
JS
2100 * Primary handler for threaded interrupts.
2101 * If handler is NULL and thread_fn != NULL
2102 * the default primary handler is installed.
f48fe81e
TG
2103 * @thread_fn: Function called from the irq handler thread
2104 * If NULL, no irq thread is created
1da177e4
LT
2105 * @irqflags: Interrupt type flags
2106 * @devname: An ascii name for the claiming device
2107 * @dev_id: A cookie passed back to the handler function
2108 *
2109 * This call allocates interrupt resources and enables the
2110 * interrupt line and IRQ handling. From the point this
2111 * call is made your handler function may be invoked. Since
2112 * your handler function must clear any interrupt the board
2113 * raises, you must take care both to initialise your hardware
2114 * and to set up the interrupt handler in the right order.
2115 *
3aa551c9 2116 * If you want to set up a threaded irq handler for your device
6d21af4f 2117 * then you need to supply @handler and @thread_fn. @handler is
3aa551c9
TG
2118 * still called in hard interrupt context and has to check
2119 * whether the interrupt originates from the device. If yes it
2120 * needs to disable the interrupt on the device and return
39a2eddb 2121 * IRQ_WAKE_THREAD which will wake up the handler thread and run
3aa551c9
TG
2122 * @thread_fn. This split handler design is necessary to support
2123 * shared interrupts.
2124 *
1da177e4
LT
2125 * Dev_id must be globally unique. Normally the address of the
2126 * device data structure is used as the cookie. Since the handler
2127 * receives this value it makes sense to use it.
2128 *
2129 * If your interrupt is shared you must pass a non NULL dev_id
2130 * as this is required when freeing the interrupt.
2131 *
2132 * Flags:
2133 *
3cca53b0 2134 * IRQF_SHARED Interrupt is shared
0c5d1eb7 2135 * IRQF_TRIGGER_* Specify active edge(s) or level
04c2721d 2136 * IRQF_ONESHOT Run thread_fn with interrupt line masked
1da177e4 2137 */
3aa551c9
TG
2138int request_threaded_irq(unsigned int irq, irq_handler_t handler,
2139 irq_handler_t thread_fn, unsigned long irqflags,
2140 const char *devname, void *dev_id)
1da177e4 2141{
06fcb0c6 2142 struct irqaction *action;
08678b08 2143 struct irq_desc *desc;
d3c60047 2144 int retval;
1da177e4 2145
e237a551
CF
2146 if (irq == IRQ_NOTCONNECTED)
2147 return -ENOTCONN;
2148
1da177e4
LT
2149 /*
2150 * Sanity-check: shared interrupts must pass in a real dev-ID,
2151 * otherwise we'll have trouble later trying to figure out
2152 * which interrupt is which (messes up the interrupt freeing
2153 * logic etc).
17f48034 2154 *
cbe16f35
BS
2155 * Also shared interrupts do not go well with disabling auto enable.
2156 * The sharing interrupt might request it while it's still disabled
2157 * and then wait for interrupts forever.
2158 *
17f48034
RW
2159 * Also IRQF_COND_SUSPEND only makes sense for shared interrupts and
2160 * it cannot be set along with IRQF_NO_SUSPEND.
1da177e4 2161 */
17f48034 2162 if (((irqflags & IRQF_SHARED) && !dev_id) ||
cbe16f35 2163 ((irqflags & IRQF_SHARED) && (irqflags & IRQF_NO_AUTOEN)) ||
17f48034
RW
2164 (!(irqflags & IRQF_SHARED) && (irqflags & IRQF_COND_SUSPEND)) ||
2165 ((irqflags & IRQF_NO_SUSPEND) && (irqflags & IRQF_COND_SUSPEND)))
1da177e4 2166 return -EINVAL;
7d94f7ca 2167
cb5bc832 2168 desc = irq_to_desc(irq);
7d94f7ca 2169 if (!desc)
1da177e4 2170 return -EINVAL;
7d94f7ca 2171
31d9d9b6
MZ
2172 if (!irq_settings_can_request(desc) ||
2173 WARN_ON(irq_settings_is_per_cpu_devid(desc)))
6550c775 2174 return -EINVAL;
b25c340c
TG
2175
2176 if (!handler) {
2177 if (!thread_fn)
2178 return -EINVAL;
2179 handler = irq_default_primary_handler;
2180 }
1da177e4 2181
45535732 2182 action = kzalloc(sizeof(struct irqaction), GFP_KERNEL);
1da177e4
LT
2183 if (!action)
2184 return -ENOMEM;
2185
2186 action->handler = handler;
3aa551c9 2187 action->thread_fn = thread_fn;
1da177e4 2188 action->flags = irqflags;
1da177e4 2189 action->name = devname;
1da177e4
LT
2190 action->dev_id = dev_id;
2191
be45beb2 2192 retval = irq_chip_pm_get(&desc->irq_data);
4396f46c
SL
2193 if (retval < 0) {
2194 kfree(action);
be45beb2 2195 return retval;
4396f46c 2196 }
be45beb2 2197
d3c60047 2198 retval = __setup_irq(irq, desc, action);
70aedd24 2199
2a1d3ab8 2200 if (retval) {
be45beb2 2201 irq_chip_pm_put(&desc->irq_data);
2a1d3ab8 2202 kfree(action->secondary);
377bf1e4 2203 kfree(action);
2a1d3ab8 2204 }
377bf1e4 2205
6d83f94d 2206#ifdef CONFIG_DEBUG_SHIRQ_FIXME
6ce51c43 2207 if (!retval && (irqflags & IRQF_SHARED)) {
a304e1b8
DW
2208 /*
2209 * It's a shared IRQ -- the driver ought to be prepared for it
2210 * to happen immediately, so let's make sure....
377bf1e4
AV
2211 * We disable the irq to make sure that a 'real' IRQ doesn't
2212 * run in parallel with our fake.
a304e1b8 2213 */
59845b1f 2214 unsigned long flags;
a304e1b8 2215
377bf1e4 2216 disable_irq(irq);
59845b1f 2217 local_irq_save(flags);
377bf1e4 2218
59845b1f 2219 handler(irq, dev_id);
377bf1e4 2220
59845b1f 2221 local_irq_restore(flags);
377bf1e4 2222 enable_irq(irq);
a304e1b8
DW
2223 }
2224#endif
1da177e4
LT
2225 return retval;
2226}
3aa551c9 2227EXPORT_SYMBOL(request_threaded_irq);
ae731f8d
MZ
2228
2229/**
2230 * request_any_context_irq - allocate an interrupt line
2231 * @irq: Interrupt line to allocate
2232 * @handler: Function to be called when the IRQ occurs.
2233 * Threaded handler for threaded interrupts.
2234 * @flags: Interrupt type flags
2235 * @name: An ascii name for the claiming device
2236 * @dev_id: A cookie passed back to the handler function
2237 *
2238 * This call allocates interrupt resources and enables the
2239 * interrupt line and IRQ handling. It selects either a
2240 * hardirq or threaded handling method depending on the
2241 * context.
2242 *
2243 * On failure, it returns a negative value. On success,
2244 * it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED.
2245 */
2246int request_any_context_irq(unsigned int irq, irq_handler_t handler,
2247 unsigned long flags, const char *name, void *dev_id)
2248{
e237a551 2249 struct irq_desc *desc;
ae731f8d
MZ
2250 int ret;
2251
e237a551
CF
2252 if (irq == IRQ_NOTCONNECTED)
2253 return -ENOTCONN;
2254
2255 desc = irq_to_desc(irq);
ae731f8d
MZ
2256 if (!desc)
2257 return -EINVAL;
2258
1ccb4e61 2259 if (irq_settings_is_nested_thread(desc)) {
ae731f8d
MZ
2260 ret = request_threaded_irq(irq, NULL, handler,
2261 flags, name, dev_id);
2262 return !ret ? IRQC_IS_NESTED : ret;
2263 }
2264
2265 ret = request_irq(irq, handler, flags, name, dev_id);
2266 return !ret ? IRQC_IS_HARDIRQ : ret;
2267}
2268EXPORT_SYMBOL_GPL(request_any_context_irq);
31d9d9b6 2269
b525903c
JT
2270/**
2271 * request_nmi - allocate an interrupt line for NMI delivery
2272 * @irq: Interrupt line to allocate
2273 * @handler: Function to be called when the IRQ occurs.
2274 * Threaded handler for threaded interrupts.
2275 * @irqflags: Interrupt type flags
2276 * @name: An ascii name for the claiming device
2277 * @dev_id: A cookie passed back to the handler function
2278 *
2279 * This call allocates interrupt resources and enables the
2280 * interrupt line and IRQ handling. It sets up the IRQ line
2281 * to be handled as an NMI.
2282 *
2283 * An interrupt line delivering NMIs cannot be shared and IRQ handling
2284 * cannot be threaded.
2285 *
2286 * Interrupt lines requested for NMI delivering must produce per cpu
2287 * interrupts and have auto enabling setting disabled.
2288 *
2289 * Dev_id must be globally unique. Normally the address of the
2290 * device data structure is used as the cookie. Since the handler
2291 * receives this value it makes sense to use it.
2292 *
2293 * If the interrupt line cannot be used to deliver NMIs, function
2294 * will fail and return a negative value.
2295 */
2296int request_nmi(unsigned int irq, irq_handler_t handler,
2297 unsigned long irqflags, const char *name, void *dev_id)
2298{
2299 struct irqaction *action;
2300 struct irq_desc *desc;
2301 unsigned long flags;
2302 int retval;
2303
2304 if (irq == IRQ_NOTCONNECTED)
2305 return -ENOTCONN;
2306
2307 /* NMI cannot be shared, used for Polling */
2308 if (irqflags & (IRQF_SHARED | IRQF_COND_SUSPEND | IRQF_IRQPOLL))
2309 return -EINVAL;
2310
2311 if (!(irqflags & IRQF_PERCPU))
2312 return -EINVAL;
2313
2314 if (!handler)
2315 return -EINVAL;
2316
2317 desc = irq_to_desc(irq);
2318
cbe16f35
BS
2319 if (!desc || (irq_settings_can_autoenable(desc) &&
2320 !(irqflags & IRQF_NO_AUTOEN)) ||
b525903c
JT
2321 !irq_settings_can_request(desc) ||
2322 WARN_ON(irq_settings_is_per_cpu_devid(desc)) ||
2323 !irq_supports_nmi(desc))
2324 return -EINVAL;
2325
2326 action = kzalloc(sizeof(struct irqaction), GFP_KERNEL);
2327 if (!action)
2328 return -ENOMEM;
2329
2330 action->handler = handler;
2331 action->flags = irqflags | IRQF_NO_THREAD | IRQF_NOBALANCING;
2332 action->name = name;
2333 action->dev_id = dev_id;
2334
2335 retval = irq_chip_pm_get(&desc->irq_data);
2336 if (retval < 0)
2337 goto err_out;
2338
2339 retval = __setup_irq(irq, desc, action);
2340 if (retval)
2341 goto err_irq_setup;
2342
2343 raw_spin_lock_irqsave(&desc->lock, flags);
2344
2345 /* Setup NMI state */
2346 desc->istate |= IRQS_NMI;
2347 retval = irq_nmi_setup(desc);
2348 if (retval) {
2349 __cleanup_nmi(irq, desc);
2350 raw_spin_unlock_irqrestore(&desc->lock, flags);
2351 return -EINVAL;
2352 }
2353
2354 raw_spin_unlock_irqrestore(&desc->lock, flags);
2355
2356 return 0;
2357
2358err_irq_setup:
2359 irq_chip_pm_put(&desc->irq_data);
2360err_out:
2361 kfree(action);
2362
2363 return retval;
2364}
2365
1e7c5fd2 2366void enable_percpu_irq(unsigned int irq, unsigned int type)
31d9d9b6
MZ
2367{
2368 unsigned int cpu = smp_processor_id();
2369 unsigned long flags;
2370 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU);
2371
2372 if (!desc)
2373 return;
2374
f35ad083
MZ
2375 /*
2376 * If the trigger type is not specified by the caller, then
2377 * use the default for this interrupt.
2378 */
1e7c5fd2 2379 type &= IRQ_TYPE_SENSE_MASK;
f35ad083
MZ
2380 if (type == IRQ_TYPE_NONE)
2381 type = irqd_get_trigger_type(&desc->irq_data);
2382
1e7c5fd2
MZ
2383 if (type != IRQ_TYPE_NONE) {
2384 int ret;
2385
a1ff541a 2386 ret = __irq_set_trigger(desc, type);
1e7c5fd2
MZ
2387
2388 if (ret) {
32cffdde 2389 WARN(1, "failed to set type for IRQ%d\n", irq);
1e7c5fd2
MZ
2390 goto out;
2391 }
2392 }
2393
31d9d9b6 2394 irq_percpu_enable(desc, cpu);
1e7c5fd2 2395out:
31d9d9b6
MZ
2396 irq_put_desc_unlock(desc, flags);
2397}
36a5df85 2398EXPORT_SYMBOL_GPL(enable_percpu_irq);
31d9d9b6 2399
4b078c3f
JT
2400void enable_percpu_nmi(unsigned int irq, unsigned int type)
2401{
2402 enable_percpu_irq(irq, type);
2403}
2404
f0cb3220
TP
2405/**
2406 * irq_percpu_is_enabled - Check whether the per cpu irq is enabled
2407 * @irq: Linux irq number to check for
2408 *
2409 * Must be called from a non migratable context. Returns the enable
2410 * state of a per cpu interrupt on the current cpu.
2411 */
2412bool irq_percpu_is_enabled(unsigned int irq)
2413{
2414 unsigned int cpu = smp_processor_id();
2415 struct irq_desc *desc;
2416 unsigned long flags;
2417 bool is_enabled;
2418
2419 desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU);
2420 if (!desc)
2421 return false;
2422
2423 is_enabled = cpumask_test_cpu(cpu, desc->percpu_enabled);
2424 irq_put_desc_unlock(desc, flags);
2425
2426 return is_enabled;
2427}
2428EXPORT_SYMBOL_GPL(irq_percpu_is_enabled);
2429
31d9d9b6
MZ
2430void disable_percpu_irq(unsigned int irq)
2431{
2432 unsigned int cpu = smp_processor_id();
2433 unsigned long flags;
2434 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU);
2435
2436 if (!desc)
2437 return;
2438
2439 irq_percpu_disable(desc, cpu);
2440 irq_put_desc_unlock(desc, flags);
2441}
36a5df85 2442EXPORT_SYMBOL_GPL(disable_percpu_irq);
31d9d9b6 2443
4b078c3f
JT
2444void disable_percpu_nmi(unsigned int irq)
2445{
2446 disable_percpu_irq(irq);
2447}
2448
31d9d9b6
MZ
2449/*
2450 * Internal function to unregister a percpu irqaction.
2451 */
2452static struct irqaction *__free_percpu_irq(unsigned int irq, void __percpu *dev_id)
2453{
2454 struct irq_desc *desc = irq_to_desc(irq);
2455 struct irqaction *action;
2456 unsigned long flags;
2457
2458 WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq);
2459
2460 if (!desc)
2461 return NULL;
2462
2463 raw_spin_lock_irqsave(&desc->lock, flags);
2464
2465 action = desc->action;
2466 if (!action || action->percpu_dev_id != dev_id) {
2467 WARN(1, "Trying to free already-free IRQ %d\n", irq);
2468 goto bad;
2469 }
2470
2471 if (!cpumask_empty(desc->percpu_enabled)) {
2472 WARN(1, "percpu IRQ %d still enabled on CPU%d!\n",
2473 irq, cpumask_first(desc->percpu_enabled));
2474 goto bad;
2475 }
2476
2477 /* Found it - now remove it from the list of entries: */
2478 desc->action = NULL;
2479
4b078c3f
JT
2480 desc->istate &= ~IRQS_NMI;
2481
31d9d9b6
MZ
2482 raw_spin_unlock_irqrestore(&desc->lock, flags);
2483
2484 unregister_handler_proc(irq, action);
2485
be45beb2 2486 irq_chip_pm_put(&desc->irq_data);
31d9d9b6
MZ
2487 module_put(desc->owner);
2488 return action;
2489
2490bad:
2491 raw_spin_unlock_irqrestore(&desc->lock, flags);
2492 return NULL;
2493}
2494
2495/**
2496 * remove_percpu_irq - free a per-cpu interrupt
2497 * @irq: Interrupt line to free
2498 * @act: irqaction for the interrupt
2499 *
2500 * Used to remove interrupts statically setup by the early boot process.
2501 */
2502void remove_percpu_irq(unsigned int irq, struct irqaction *act)
2503{
2504 struct irq_desc *desc = irq_to_desc(irq);
2505
2506 if (desc && irq_settings_is_per_cpu_devid(desc))
2507 __free_percpu_irq(irq, act->percpu_dev_id);
2508}
2509
2510/**
2511 * free_percpu_irq - free an interrupt allocated with request_percpu_irq
2512 * @irq: Interrupt line to free
2513 * @dev_id: Device identity to free
2514 *
2515 * Remove a percpu interrupt handler. The handler is removed, but
2516 * the interrupt line is not disabled. This must be done on each
2517 * CPU before calling this function. The function does not return
2518 * until any executing interrupts for this IRQ have completed.
2519 *
2520 * This function must not be called from interrupt context.
2521 */
2522void free_percpu_irq(unsigned int irq, void __percpu *dev_id)
2523{
2524 struct irq_desc *desc = irq_to_desc(irq);
2525
2526 if (!desc || !irq_settings_is_per_cpu_devid(desc))
2527 return;
2528
2529 chip_bus_lock(desc);
2530 kfree(__free_percpu_irq(irq, dev_id));
2531 chip_bus_sync_unlock(desc);
2532}
aec2e2ad 2533EXPORT_SYMBOL_GPL(free_percpu_irq);
31d9d9b6 2534
4b078c3f
JT
2535void free_percpu_nmi(unsigned int irq, void __percpu *dev_id)
2536{
2537 struct irq_desc *desc = irq_to_desc(irq);
2538
2539 if (!desc || !irq_settings_is_per_cpu_devid(desc))
2540 return;
2541
2542 if (WARN_ON(!(desc->istate & IRQS_NMI)))
2543 return;
2544
2545 kfree(__free_percpu_irq(irq, dev_id));
2546}
2547
31d9d9b6
MZ
2548/**
2549 * setup_percpu_irq - setup a per-cpu interrupt
2550 * @irq: Interrupt line to setup
2551 * @act: irqaction for the interrupt
2552 *
2553 * Used to statically setup per-cpu interrupts in the early boot process.
2554 */
2555int setup_percpu_irq(unsigned int irq, struct irqaction *act)
2556{
2557 struct irq_desc *desc = irq_to_desc(irq);
2558 int retval;
2559
2560 if (!desc || !irq_settings_is_per_cpu_devid(desc))
2561 return -EINVAL;
be45beb2
JH
2562
2563 retval = irq_chip_pm_get(&desc->irq_data);
2564 if (retval < 0)
2565 return retval;
2566
31d9d9b6 2567 retval = __setup_irq(irq, desc, act);
31d9d9b6 2568
be45beb2
JH
2569 if (retval)
2570 irq_chip_pm_put(&desc->irq_data);
2571
31d9d9b6
MZ
2572 return retval;
2573}
2574
2575/**
c80081b9 2576 * __request_percpu_irq - allocate a percpu interrupt line
31d9d9b6
MZ
2577 * @irq: Interrupt line to allocate
2578 * @handler: Function to be called when the IRQ occurs.
c80081b9 2579 * @flags: Interrupt type flags (IRQF_TIMER only)
31d9d9b6
MZ
2580 * @devname: An ascii name for the claiming device
2581 * @dev_id: A percpu cookie passed back to the handler function
2582 *
a1b7febd
MR
2583 * This call allocates interrupt resources and enables the
2584 * interrupt on the local CPU. If the interrupt is supposed to be
2585 * enabled on other CPUs, it has to be done on each CPU using
2586 * enable_percpu_irq().
31d9d9b6
MZ
2587 *
2588 * Dev_id must be globally unique. It is a per-cpu variable, and
2589 * the handler gets called with the interrupted CPU's instance of
2590 * that variable.
2591 */
c80081b9
DL
2592int __request_percpu_irq(unsigned int irq, irq_handler_t handler,
2593 unsigned long flags, const char *devname,
2594 void __percpu *dev_id)
31d9d9b6
MZ
2595{
2596 struct irqaction *action;
2597 struct irq_desc *desc;
2598 int retval;
2599
2600 if (!dev_id)
2601 return -EINVAL;
2602
2603 desc = irq_to_desc(irq);
2604 if (!desc || !irq_settings_can_request(desc) ||
2605 !irq_settings_is_per_cpu_devid(desc))
2606 return -EINVAL;
2607
c80081b9
DL
2608 if (flags && flags != IRQF_TIMER)
2609 return -EINVAL;
2610
31d9d9b6
MZ
2611 action = kzalloc(sizeof(struct irqaction), GFP_KERNEL);
2612 if (!action)
2613 return -ENOMEM;
2614
2615 action->handler = handler;
c80081b9 2616 action->flags = flags | IRQF_PERCPU | IRQF_NO_SUSPEND;
31d9d9b6
MZ
2617 action->name = devname;
2618 action->percpu_dev_id = dev_id;
2619
be45beb2 2620 retval = irq_chip_pm_get(&desc->irq_data);
4396f46c
SL
2621 if (retval < 0) {
2622 kfree(action);
be45beb2 2623 return retval;
4396f46c 2624 }
be45beb2 2625
31d9d9b6 2626 retval = __setup_irq(irq, desc, action);
31d9d9b6 2627
be45beb2
JH
2628 if (retval) {
2629 irq_chip_pm_put(&desc->irq_data);
31d9d9b6 2630 kfree(action);
be45beb2 2631 }
31d9d9b6
MZ
2632
2633 return retval;
2634}
c80081b9 2635EXPORT_SYMBOL_GPL(__request_percpu_irq);
1b7047ed 2636
4b078c3f
JT
2637/**
2638 * request_percpu_nmi - allocate a percpu interrupt line for NMI delivery
2639 * @irq: Interrupt line to allocate
2640 * @handler: Function to be called when the IRQ occurs.
2641 * @name: An ascii name for the claiming device
2642 * @dev_id: A percpu cookie passed back to the handler function
2643 *
2644 * This call allocates interrupt resources for a per CPU NMI. Per CPU NMIs
a5186694
JT
2645 * have to be setup on each CPU by calling prepare_percpu_nmi() before
2646 * being enabled on the same CPU by using enable_percpu_nmi().
4b078c3f
JT
2647 *
2648 * Dev_id must be globally unique. It is a per-cpu variable, and
2649 * the handler gets called with the interrupted CPU's instance of
2650 * that variable.
2651 *
2652 * Interrupt lines requested for NMI delivering should have auto enabling
2653 * setting disabled.
2654 *
2655 * If the interrupt line cannot be used to deliver NMIs, function
2656 * will fail returning a negative value.
2657 */
2658int request_percpu_nmi(unsigned int irq, irq_handler_t handler,
2659 const char *name, void __percpu *dev_id)
2660{
2661 struct irqaction *action;
2662 struct irq_desc *desc;
2663 unsigned long flags;
2664 int retval;
2665
2666 if (!handler)
2667 return -EINVAL;
2668
2669 desc = irq_to_desc(irq);
2670
2671 if (!desc || !irq_settings_can_request(desc) ||
2672 !irq_settings_is_per_cpu_devid(desc) ||
2673 irq_settings_can_autoenable(desc) ||
2674 !irq_supports_nmi(desc))
2675 return -EINVAL;
2676
2677 /* The line cannot already be NMI */
2678 if (desc->istate & IRQS_NMI)
2679 return -EINVAL;
2680
2681 action = kzalloc(sizeof(struct irqaction), GFP_KERNEL);
2682 if (!action)
2683 return -ENOMEM;
2684
2685 action->handler = handler;
2686 action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND | IRQF_NO_THREAD
2687 | IRQF_NOBALANCING;
2688 action->name = name;
2689 action->percpu_dev_id = dev_id;
2690
2691 retval = irq_chip_pm_get(&desc->irq_data);
2692 if (retval < 0)
2693 goto err_out;
2694
2695 retval = __setup_irq(irq, desc, action);
2696 if (retval)
2697 goto err_irq_setup;
2698
2699 raw_spin_lock_irqsave(&desc->lock, flags);
2700 desc->istate |= IRQS_NMI;
2701 raw_spin_unlock_irqrestore(&desc->lock, flags);
2702
2703 return 0;
2704
2705err_irq_setup:
2706 irq_chip_pm_put(&desc->irq_data);
2707err_out:
2708 kfree(action);
2709
2710 return retval;
2711}
2712
2713/**
2714 * prepare_percpu_nmi - performs CPU local setup for NMI delivery
2715 * @irq: Interrupt line to prepare for NMI delivery
2716 *
2717 * This call prepares an interrupt line to deliver NMI on the current CPU,
2718 * before that interrupt line gets enabled with enable_percpu_nmi().
2719 *
2720 * As a CPU local operation, this should be called from non-preemptible
2721 * context.
2722 *
2723 * If the interrupt line cannot be used to deliver NMIs, function
2724 * will fail returning a negative value.
2725 */
2726int prepare_percpu_nmi(unsigned int irq)
2727{
2728 unsigned long flags;
2729 struct irq_desc *desc;
2730 int ret = 0;
2731
2732 WARN_ON(preemptible());
2733
2734 desc = irq_get_desc_lock(irq, &flags,
2735 IRQ_GET_DESC_CHECK_PERCPU);
2736 if (!desc)
2737 return -EINVAL;
2738
2739 if (WARN(!(desc->istate & IRQS_NMI),
2740 KERN_ERR "prepare_percpu_nmi called for a non-NMI interrupt: irq %u\n",
2741 irq)) {
2742 ret = -EINVAL;
2743 goto out;
2744 }
2745
2746 ret = irq_nmi_setup(desc);
2747 if (ret) {
2748 pr_err("Failed to setup NMI delivery: irq %u\n", irq);
2749 goto out;
2750 }
2751
2752out:
2753 irq_put_desc_unlock(desc, flags);
2754 return ret;
2755}
2756
2757/**
2758 * teardown_percpu_nmi - undoes NMI setup of IRQ line
2759 * @irq: Interrupt line from which CPU local NMI configuration should be
2760 * removed
2761 *
2762 * This call undoes the setup done by prepare_percpu_nmi().
2763 *
2764 * IRQ line should not be enabled for the current CPU.
2765 *
2766 * As a CPU local operation, this should be called from non-preemptible
2767 * context.
2768 */
2769void teardown_percpu_nmi(unsigned int irq)
2770{
2771 unsigned long flags;
2772 struct irq_desc *desc;
2773
2774 WARN_ON(preemptible());
2775
2776 desc = irq_get_desc_lock(irq, &flags,
2777 IRQ_GET_DESC_CHECK_PERCPU);
2778 if (!desc)
2779 return;
2780
2781 if (WARN_ON(!(desc->istate & IRQS_NMI)))
2782 goto out;
2783
2784 irq_nmi_teardown(desc);
2785out:
2786 irq_put_desc_unlock(desc, flags);
2787}
2788
62e04686
TG
2789int __irq_get_irqchip_state(struct irq_data *data, enum irqchip_irq_state which,
2790 bool *state)
2791{
2792 struct irq_chip *chip;
2793 int err = -EINVAL;
2794
2795 do {
2796 chip = irq_data_get_irq_chip(data);
1d0326f3
MV
2797 if (WARN_ON_ONCE(!chip))
2798 return -ENODEV;
62e04686
TG
2799 if (chip->irq_get_irqchip_state)
2800 break;
2801#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
2802 data = data->parent_data;
2803#else
2804 data = NULL;
2805#endif
2806 } while (data);
2807
2808 if (data)
2809 err = chip->irq_get_irqchip_state(data, which, state);
2810 return err;
2811}
2812
1b7047ed
MZ
2813/**
2814 * irq_get_irqchip_state - returns the irqchip state of a interrupt.
2815 * @irq: Interrupt line that is forwarded to a VM
2816 * @which: One of IRQCHIP_STATE_* the caller wants to know about
5c982c58 2817 * @state: a pointer to a boolean where the state is to be stored
1b7047ed
MZ
2818 *
2819 * This call snapshots the internal irqchip state of an
2820 * interrupt, returning into @state the bit corresponding to
2821 * stage @which
2822 *
2823 * This function should be called with preemption disabled if the
2824 * interrupt controller has per-cpu registers.
2825 */
2826int irq_get_irqchip_state(unsigned int irq, enum irqchip_irq_state which,
2827 bool *state)
2828{
2829 struct irq_desc *desc;
2830 struct irq_data *data;
1b7047ed
MZ
2831 unsigned long flags;
2832 int err = -EINVAL;
2833
2834 desc = irq_get_desc_buslock(irq, &flags, 0);
2835 if (!desc)
2836 return err;
2837
2838 data = irq_desc_get_irq_data(desc);
2839
62e04686 2840 err = __irq_get_irqchip_state(data, which, state);
1b7047ed
MZ
2841
2842 irq_put_desc_busunlock(desc, flags);
2843 return err;
2844}
1ee4fb3e 2845EXPORT_SYMBOL_GPL(irq_get_irqchip_state);
1b7047ed
MZ
2846
2847/**
2848 * irq_set_irqchip_state - set the state of a forwarded interrupt.
2849 * @irq: Interrupt line that is forwarded to a VM
2850 * @which: State to be restored (one of IRQCHIP_STATE_*)
2851 * @val: Value corresponding to @which
2852 *
2853 * This call sets the internal irqchip state of an interrupt,
2854 * depending on the value of @which.
2855 *
e1a6af4b 2856 * This function should be called with migration disabled if the
1b7047ed
MZ
2857 * interrupt controller has per-cpu registers.
2858 */
2859int irq_set_irqchip_state(unsigned int irq, enum irqchip_irq_state which,
2860 bool val)
2861{
2862 struct irq_desc *desc;
2863 struct irq_data *data;
2864 struct irq_chip *chip;
2865 unsigned long flags;
2866 int err = -EINVAL;
2867
2868 desc = irq_get_desc_buslock(irq, &flags, 0);
2869 if (!desc)
2870 return err;
2871
2872 data = irq_desc_get_irq_data(desc);
2873
2874 do {
2875 chip = irq_data_get_irq_chip(data);
f107cee9
GR
2876 if (WARN_ON_ONCE(!chip)) {
2877 err = -ENODEV;
2878 goto out_unlock;
2879 }
1b7047ed
MZ
2880 if (chip->irq_set_irqchip_state)
2881 break;
2882#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
2883 data = data->parent_data;
2884#else
2885 data = NULL;
2886#endif
2887 } while (data);
2888
2889 if (data)
2890 err = chip->irq_set_irqchip_state(data, which, val);
2891
f107cee9 2892out_unlock:
1b7047ed
MZ
2893 irq_put_desc_busunlock(desc, flags);
2894 return err;
2895}
1ee4fb3e 2896EXPORT_SYMBOL_GPL(irq_set_irqchip_state);
a313357e
TG
2897
2898/**
2899 * irq_has_action - Check whether an interrupt is requested
2900 * @irq: The linux irq number
2901 *
2902 * Returns: A snapshot of the current state
2903 */
2904bool irq_has_action(unsigned int irq)
2905{
2906 bool res;
2907
2908 rcu_read_lock();
2909 res = irq_desc_has_action(irq_to_desc(irq));
2910 rcu_read_unlock();
2911 return res;
2912}
2913EXPORT_SYMBOL_GPL(irq_has_action);
fdd02963
TG
2914
2915/**
2916 * irq_check_status_bit - Check whether bits in the irq descriptor status are set
2917 * @irq: The linux irq number
2918 * @bitmask: The bitmask to evaluate
2919 *
2920 * Returns: True if one of the bits in @bitmask is set
2921 */
2922bool irq_check_status_bit(unsigned int irq, unsigned int bitmask)
2923{
2924 struct irq_desc *desc;
2925 bool res = false;
2926
2927 rcu_read_lock();
2928 desc = irq_to_desc(irq);
2929 if (desc)
2930 res = !!(desc->status_use_accessors & bitmask);
2931 rcu_read_unlock();
2932 return res;
2933}
ce09ccc5 2934EXPORT_SYMBOL_GPL(irq_check_status_bit);