Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel_stat.h> | |
17 | ||
18 | #include "internals.h" | |
19 | ||
3a16d713 EB |
20 | /** |
21 | * dynamic_irq_init - initialize a dynamically allocated irq | |
22 | * @irq: irq number to initialize | |
23 | */ | |
24 | void dynamic_irq_init(unsigned int irq) | |
25 | { | |
26 | struct irq_desc *desc; | |
27 | unsigned long flags; | |
28 | ||
29 | if (irq >= NR_IRQS) { | |
30 | printk(KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); | |
31 | WARN_ON(1); | |
32 | return; | |
33 | } | |
34 | ||
35 | /* Ensure we don't have left over values from a previous use of this irq */ | |
36 | desc = irq_desc + irq; | |
37 | spin_lock_irqsave(&desc->lock, flags); | |
38 | desc->status = IRQ_DISABLED; | |
39 | desc->chip = &no_irq_chip; | |
40 | desc->handle_irq = handle_bad_irq; | |
41 | desc->depth = 1; | |
5b912c10 | 42 | desc->msi_desc = NULL; |
3a16d713 EB |
43 | desc->handler_data = NULL; |
44 | desc->chip_data = NULL; | |
45 | desc->action = NULL; | |
46 | desc->irq_count = 0; | |
47 | desc->irqs_unhandled = 0; | |
48 | #ifdef CONFIG_SMP | |
49 | desc->affinity = CPU_MASK_ALL; | |
50 | #endif | |
51 | spin_unlock_irqrestore(&desc->lock, flags); | |
52 | } | |
53 | ||
54 | /** | |
55 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq | |
56 | * @irq: irq number to initialize | |
57 | */ | |
58 | void dynamic_irq_cleanup(unsigned int irq) | |
59 | { | |
60 | struct irq_desc *desc; | |
61 | unsigned long flags; | |
62 | ||
63 | if (irq >= NR_IRQS) { | |
64 | printk(KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); | |
65 | WARN_ON(1); | |
66 | return; | |
67 | } | |
68 | ||
69 | desc = irq_desc + irq; | |
70 | spin_lock_irqsave(&desc->lock, flags); | |
1f80025e EB |
71 | if (desc->action) { |
72 | spin_unlock_irqrestore(&desc->lock, flags); | |
73 | printk(KERN_ERR "Destroying IRQ%d without calling free_irq\n", | |
74 | irq); | |
75 | WARN_ON(1); | |
76 | return; | |
77 | } | |
5b912c10 EB |
78 | desc->msi_desc = NULL; |
79 | desc->handler_data = NULL; | |
80 | desc->chip_data = NULL; | |
3a16d713 EB |
81 | desc->handle_irq = handle_bad_irq; |
82 | desc->chip = &no_irq_chip; | |
83 | spin_unlock_irqrestore(&desc->lock, flags); | |
84 | } | |
85 | ||
86 | ||
dd87eb3a TG |
87 | /** |
88 | * set_irq_chip - set the irq chip for an irq | |
89 | * @irq: irq number | |
90 | * @chip: pointer to irq chip description structure | |
91 | */ | |
92 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
93 | { | |
94 | struct irq_desc *desc; | |
95 | unsigned long flags; | |
96 | ||
97 | if (irq >= NR_IRQS) { | |
98 | printk(KERN_ERR "Trying to install chip for IRQ%d\n", irq); | |
99 | WARN_ON(1); | |
100 | return -EINVAL; | |
101 | } | |
102 | ||
103 | if (!chip) | |
104 | chip = &no_irq_chip; | |
105 | ||
106 | desc = irq_desc + irq; | |
107 | spin_lock_irqsave(&desc->lock, flags); | |
108 | irq_chip_set_defaults(chip); | |
109 | desc->chip = chip; | |
dd87eb3a TG |
110 | spin_unlock_irqrestore(&desc->lock, flags); |
111 | ||
112 | return 0; | |
113 | } | |
114 | EXPORT_SYMBOL(set_irq_chip); | |
115 | ||
116 | /** | |
117 | * set_irq_type - set the irq type for an irq | |
118 | * @irq: irq number | |
119 | * @type: interrupt type - see include/linux/interrupt.h | |
120 | */ | |
121 | int set_irq_type(unsigned int irq, unsigned int type) | |
122 | { | |
123 | struct irq_desc *desc; | |
124 | unsigned long flags; | |
125 | int ret = -ENXIO; | |
126 | ||
127 | if (irq >= NR_IRQS) { | |
128 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); | |
129 | return -ENODEV; | |
130 | } | |
131 | ||
132 | desc = irq_desc + irq; | |
133 | if (desc->chip->set_type) { | |
134 | spin_lock_irqsave(&desc->lock, flags); | |
135 | ret = desc->chip->set_type(irq, type); | |
136 | spin_unlock_irqrestore(&desc->lock, flags); | |
137 | } | |
138 | return ret; | |
139 | } | |
140 | EXPORT_SYMBOL(set_irq_type); | |
141 | ||
142 | /** | |
143 | * set_irq_data - set irq type data for an irq | |
144 | * @irq: Interrupt number | |
145 | * @data: Pointer to interrupt specific data | |
146 | * | |
147 | * Set the hardware irq controller data for an irq | |
148 | */ | |
149 | int set_irq_data(unsigned int irq, void *data) | |
150 | { | |
151 | struct irq_desc *desc; | |
152 | unsigned long flags; | |
153 | ||
154 | if (irq >= NR_IRQS) { | |
155 | printk(KERN_ERR | |
156 | "Trying to install controller data for IRQ%d\n", irq); | |
157 | return -EINVAL; | |
158 | } | |
159 | ||
160 | desc = irq_desc + irq; | |
161 | spin_lock_irqsave(&desc->lock, flags); | |
162 | desc->handler_data = data; | |
163 | spin_unlock_irqrestore(&desc->lock, flags); | |
164 | return 0; | |
165 | } | |
166 | EXPORT_SYMBOL(set_irq_data); | |
167 | ||
5b912c10 EB |
168 | /** |
169 | * set_irq_data - set irq type data for an irq | |
170 | * @irq: Interrupt number | |
472900b8 | 171 | * @entry: Pointer to MSI descriptor data |
5b912c10 EB |
172 | * |
173 | * Set the hardware irq controller data for an irq | |
174 | */ | |
175 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) | |
176 | { | |
177 | struct irq_desc *desc; | |
178 | unsigned long flags; | |
179 | ||
180 | if (irq >= NR_IRQS) { | |
181 | printk(KERN_ERR | |
182 | "Trying to install msi data for IRQ%d\n", irq); | |
183 | return -EINVAL; | |
184 | } | |
185 | desc = irq_desc + irq; | |
186 | spin_lock_irqsave(&desc->lock, flags); | |
187 | desc->msi_desc = entry; | |
188 | spin_unlock_irqrestore(&desc->lock, flags); | |
189 | return 0; | |
190 | } | |
191 | ||
dd87eb3a TG |
192 | /** |
193 | * set_irq_chip_data - set irq chip data for an irq | |
194 | * @irq: Interrupt number | |
195 | * @data: Pointer to chip specific data | |
196 | * | |
197 | * Set the hardware irq chip data for an irq | |
198 | */ | |
199 | int set_irq_chip_data(unsigned int irq, void *data) | |
200 | { | |
201 | struct irq_desc *desc = irq_desc + irq; | |
202 | unsigned long flags; | |
203 | ||
204 | if (irq >= NR_IRQS || !desc->chip) { | |
205 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); | |
206 | return -EINVAL; | |
207 | } | |
208 | ||
209 | spin_lock_irqsave(&desc->lock, flags); | |
210 | desc->chip_data = data; | |
211 | spin_unlock_irqrestore(&desc->lock, flags); | |
212 | ||
213 | return 0; | |
214 | } | |
215 | EXPORT_SYMBOL(set_irq_chip_data); | |
216 | ||
217 | /* | |
218 | * default enable function | |
219 | */ | |
220 | static void default_enable(unsigned int irq) | |
221 | { | |
222 | struct irq_desc *desc = irq_desc + irq; | |
223 | ||
224 | desc->chip->unmask(irq); | |
225 | desc->status &= ~IRQ_MASKED; | |
226 | } | |
227 | ||
228 | /* | |
229 | * default disable function | |
230 | */ | |
231 | static void default_disable(unsigned int irq) | |
232 | { | |
dd87eb3a TG |
233 | } |
234 | ||
235 | /* | |
236 | * default startup function | |
237 | */ | |
238 | static unsigned int default_startup(unsigned int irq) | |
239 | { | |
240 | irq_desc[irq].chip->enable(irq); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | /* | |
246 | * Fixup enable/disable function pointers | |
247 | */ | |
248 | void irq_chip_set_defaults(struct irq_chip *chip) | |
249 | { | |
250 | if (!chip->enable) | |
251 | chip->enable = default_enable; | |
252 | if (!chip->disable) | |
253 | chip->disable = default_disable; | |
254 | if (!chip->startup) | |
255 | chip->startup = default_startup; | |
256 | if (!chip->shutdown) | |
257 | chip->shutdown = chip->disable; | |
258 | if (!chip->name) | |
259 | chip->name = chip->typename; | |
b86432b4 ZY |
260 | if (!chip->end) |
261 | chip->end = dummy_irq_chip.end; | |
dd87eb3a TG |
262 | } |
263 | ||
264 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) | |
265 | { | |
266 | if (desc->chip->mask_ack) | |
267 | desc->chip->mask_ack(irq); | |
268 | else { | |
269 | desc->chip->mask(irq); | |
270 | desc->chip->ack(irq); | |
271 | } | |
272 | } | |
273 | ||
274 | /** | |
275 | * handle_simple_irq - Simple and software-decoded IRQs. | |
276 | * @irq: the interrupt number | |
277 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
278 | * |
279 | * Simple interrupts are either sent from a demultiplexing interrupt | |
280 | * handler or come from hardware, where no interrupt hardware control | |
281 | * is necessary. | |
282 | * | |
283 | * Note: The caller is expected to handle the ack, clear, mask and | |
284 | * unmask issues if necessary. | |
285 | */ | |
286 | void fastcall | |
7d12e780 | 287 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
288 | { |
289 | struct irqaction *action; | |
290 | irqreturn_t action_ret; | |
291 | const unsigned int cpu = smp_processor_id(); | |
292 | ||
293 | spin_lock(&desc->lock); | |
294 | ||
295 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
296 | goto out_unlock; | |
dd87eb3a TG |
297 | kstat_cpu(cpu).irqs[irq]++; |
298 | ||
299 | action = desc->action; | |
76d21601 IM |
300 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
301 | if (desc->chip->mask) | |
302 | desc->chip->mask(irq); | |
303 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
304 | desc->status |= IRQ_PENDING; | |
dd87eb3a | 305 | goto out_unlock; |
76d21601 | 306 | } |
dd87eb3a | 307 | |
76d21601 | 308 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING | IRQ_PENDING); |
dd87eb3a TG |
309 | desc->status |= IRQ_INPROGRESS; |
310 | spin_unlock(&desc->lock); | |
311 | ||
7d12e780 | 312 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 313 | if (!noirqdebug) |
7d12e780 | 314 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
315 | |
316 | spin_lock(&desc->lock); | |
317 | desc->status &= ~IRQ_INPROGRESS; | |
318 | out_unlock: | |
319 | spin_unlock(&desc->lock); | |
320 | } | |
321 | ||
322 | /** | |
323 | * handle_level_irq - Level type irq handler | |
324 | * @irq: the interrupt number | |
325 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
326 | * |
327 | * Level type interrupts are active as long as the hardware line has | |
328 | * the active level. This may require to mask the interrupt and unmask | |
329 | * it after the associated handler has acknowledged the device, so the | |
330 | * interrupt line is back to inactive. | |
331 | */ | |
332 | void fastcall | |
7d12e780 | 333 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
334 | { |
335 | unsigned int cpu = smp_processor_id(); | |
336 | struct irqaction *action; | |
337 | irqreturn_t action_ret; | |
338 | ||
339 | spin_lock(&desc->lock); | |
340 | mask_ack_irq(desc, irq); | |
341 | ||
342 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
86998aa6 | 343 | goto out_unlock; |
dd87eb3a TG |
344 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
345 | kstat_cpu(cpu).irqs[irq]++; | |
346 | ||
347 | /* | |
348 | * If its disabled or no action available | |
349 | * keep it masked and get out of here | |
350 | */ | |
351 | action = desc->action; | |
5a43a066 BH |
352 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
353 | desc->status |= IRQ_PENDING; | |
86998aa6 | 354 | goto out_unlock; |
5a43a066 | 355 | } |
dd87eb3a TG |
356 | |
357 | desc->status |= IRQ_INPROGRESS; | |
5a43a066 | 358 | desc->status &= ~IRQ_PENDING; |
dd87eb3a TG |
359 | spin_unlock(&desc->lock); |
360 | ||
7d12e780 | 361 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 362 | if (!noirqdebug) |
7d12e780 | 363 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
364 | |
365 | spin_lock(&desc->lock); | |
366 | desc->status &= ~IRQ_INPROGRESS; | |
dd87eb3a TG |
367 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) |
368 | desc->chip->unmask(irq); | |
86998aa6 | 369 | out_unlock: |
dd87eb3a TG |
370 | spin_unlock(&desc->lock); |
371 | } | |
372 | ||
373 | /** | |
47c2a3aa | 374 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
375 | * @irq: the interrupt number |
376 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 377 | * |
47c2a3aa | 378 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
379 | * call when the interrupt has been serviced. This enables support |
380 | * for modern forms of interrupt handlers, which handle the flow | |
381 | * details in hardware, transparently. | |
382 | */ | |
383 | void fastcall | |
7d12e780 | 384 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
385 | { |
386 | unsigned int cpu = smp_processor_id(); | |
387 | struct irqaction *action; | |
388 | irqreturn_t action_ret; | |
389 | ||
390 | spin_lock(&desc->lock); | |
391 | ||
392 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
393 | goto out; | |
394 | ||
395 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
396 | kstat_cpu(cpu).irqs[irq]++; | |
397 | ||
398 | /* | |
399 | * If its disabled or no action available | |
76d21601 | 400 | * then mask it and get out of here: |
dd87eb3a TG |
401 | */ |
402 | action = desc->action; | |
98bb244b BH |
403 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
404 | desc->status |= IRQ_PENDING; | |
76d21601 IM |
405 | if (desc->chip->mask) |
406 | desc->chip->mask(irq); | |
dd87eb3a | 407 | goto out; |
98bb244b | 408 | } |
dd87eb3a TG |
409 | |
410 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 411 | desc->status &= ~IRQ_PENDING; |
dd87eb3a TG |
412 | spin_unlock(&desc->lock); |
413 | ||
7d12e780 | 414 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 415 | if (!noirqdebug) |
7d12e780 | 416 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
417 | |
418 | spin_lock(&desc->lock); | |
419 | desc->status &= ~IRQ_INPROGRESS; | |
420 | out: | |
47c2a3aa | 421 | desc->chip->eoi(irq); |
dd87eb3a TG |
422 | |
423 | spin_unlock(&desc->lock); | |
424 | } | |
425 | ||
426 | /** | |
427 | * handle_edge_irq - edge type IRQ handler | |
428 | * @irq: the interrupt number | |
429 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
430 | * |
431 | * Interrupt occures on the falling and/or rising edge of a hardware | |
432 | * signal. The occurence is latched into the irq controller hardware | |
433 | * and must be acked in order to be reenabled. After the ack another | |
434 | * interrupt can happen on the same source even before the first one | |
435 | * is handled by the assosiacted event handler. If this happens it | |
436 | * might be necessary to disable (mask) the interrupt depending on the | |
437 | * controller hardware. This requires to reenable the interrupt inside | |
438 | * of the loop which handles the interrupts which have arrived while | |
439 | * the handler was running. If all pending interrupts are handled, the | |
440 | * loop is left. | |
441 | */ | |
442 | void fastcall | |
7d12e780 | 443 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
444 | { |
445 | const unsigned int cpu = smp_processor_id(); | |
446 | ||
447 | spin_lock(&desc->lock); | |
448 | ||
449 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
450 | ||
451 | /* | |
452 | * If we're currently running this IRQ, or its disabled, | |
453 | * we shouldn't process the IRQ. Mark it pending, handle | |
454 | * the necessary masking and go out | |
455 | */ | |
456 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
457 | !desc->action)) { | |
458 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
459 | mask_ack_irq(desc, irq); | |
460 | goto out_unlock; | |
461 | } | |
462 | ||
463 | kstat_cpu(cpu).irqs[irq]++; | |
464 | ||
465 | /* Start handling the irq */ | |
466 | desc->chip->ack(irq); | |
467 | ||
468 | /* Mark the IRQ currently in progress.*/ | |
469 | desc->status |= IRQ_INPROGRESS; | |
470 | ||
471 | do { | |
472 | struct irqaction *action = desc->action; | |
473 | irqreturn_t action_ret; | |
474 | ||
475 | if (unlikely(!action)) { | |
476 | desc->chip->mask(irq); | |
477 | goto out_unlock; | |
478 | } | |
479 | ||
480 | /* | |
481 | * When another irq arrived while we were handling | |
482 | * one, we could have masked the irq. | |
483 | * Renable it, if it was not disabled in meantime. | |
484 | */ | |
485 | if (unlikely((desc->status & | |
486 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
487 | (IRQ_PENDING | IRQ_MASKED))) { | |
488 | desc->chip->unmask(irq); | |
489 | desc->status &= ~IRQ_MASKED; | |
490 | } | |
491 | ||
492 | desc->status &= ~IRQ_PENDING; | |
493 | spin_unlock(&desc->lock); | |
7d12e780 | 494 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 495 | if (!noirqdebug) |
7d12e780 | 496 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
497 | spin_lock(&desc->lock); |
498 | ||
499 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
500 | ||
501 | desc->status &= ~IRQ_INPROGRESS; | |
502 | out_unlock: | |
503 | spin_unlock(&desc->lock); | |
504 | } | |
505 | ||
506 | #ifdef CONFIG_SMP | |
507 | /** | |
508 | * handle_percpu_IRQ - Per CPU local irq handler | |
509 | * @irq: the interrupt number | |
510 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
511 | * |
512 | * Per CPU interrupts on SMP machines without locking requirements | |
513 | */ | |
514 | void fastcall | |
7d12e780 | 515 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
516 | { |
517 | irqreturn_t action_ret; | |
518 | ||
519 | kstat_this_cpu.irqs[irq]++; | |
520 | ||
521 | if (desc->chip->ack) | |
522 | desc->chip->ack(irq); | |
523 | ||
7d12e780 | 524 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 525 | if (!noirqdebug) |
7d12e780 | 526 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
527 | |
528 | if (desc->chip->eoi) | |
529 | desc->chip->eoi(irq); | |
530 | } | |
531 | ||
532 | #endif /* CONFIG_SMP */ | |
533 | ||
534 | void | |
a460e745 IM |
535 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
536 | const char *name) | |
dd87eb3a TG |
537 | { |
538 | struct irq_desc *desc; | |
539 | unsigned long flags; | |
540 | ||
541 | if (irq >= NR_IRQS) { | |
542 | printk(KERN_ERR | |
543 | "Trying to install type control for IRQ%d\n", irq); | |
544 | return; | |
545 | } | |
546 | ||
547 | desc = irq_desc + irq; | |
548 | ||
549 | if (!handle) | |
550 | handle = handle_bad_irq; | |
9d7ac8be | 551 | else if (desc->chip == &no_irq_chip) { |
f8b5473f | 552 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 553 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
554 | /* |
555 | * Some ARM implementations install a handler for really dumb | |
556 | * interrupt hardware without setting an irq_chip. This worked | |
557 | * with the ARM no_irq_chip but the check in setup_irq would | |
558 | * prevent us to setup the interrupt at all. Switch it to | |
559 | * dummy_irq_chip for easy transition. | |
560 | */ | |
561 | desc->chip = &dummy_irq_chip; | |
562 | } | |
dd87eb3a TG |
563 | |
564 | spin_lock_irqsave(&desc->lock, flags); | |
565 | ||
566 | /* Uninstall? */ | |
567 | if (handle == handle_bad_irq) { | |
5575ddf7 JB |
568 | if (desc->chip != &no_irq_chip) |
569 | mask_ack_irq(desc, irq); | |
dd87eb3a TG |
570 | desc->status |= IRQ_DISABLED; |
571 | desc->depth = 1; | |
572 | } | |
573 | desc->handle_irq = handle; | |
a460e745 | 574 | desc->name = name; |
dd87eb3a TG |
575 | |
576 | if (handle != handle_bad_irq && is_chained) { | |
577 | desc->status &= ~IRQ_DISABLED; | |
578 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | |
579 | desc->depth = 0; | |
580 | desc->chip->unmask(irq); | |
581 | } | |
582 | spin_unlock_irqrestore(&desc->lock, flags); | |
583 | } | |
584 | ||
585 | void | |
586 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 587 | irq_flow_handler_t handle) |
dd87eb3a TG |
588 | { |
589 | set_irq_chip(irq, chip); | |
a460e745 | 590 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
591 | } |
592 | ||
a460e745 IM |
593 | void |
594 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
595 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 596 | { |
a460e745 IM |
597 | set_irq_chip(irq, chip); |
598 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 599 | } |