Commit | Line | Data |
---|---|---|
dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
21 | /** | |
a0cd9ca2 | 22 | * irq_set_chip - set the irq chip for an irq |
dd87eb3a TG |
23 | * @irq: irq number |
24 | * @chip: pointer to irq chip description structure | |
25 | */ | |
a0cd9ca2 | 26 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
dd87eb3a | 27 | { |
d3c60047 | 28 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
29 | unsigned long flags; |
30 | ||
7d94f7ca | 31 | if (!desc) { |
261c40c1 | 32 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
dd87eb3a TG |
33 | return -EINVAL; |
34 | } | |
35 | ||
36 | if (!chip) | |
37 | chip = &no_irq_chip; | |
38 | ||
239007b8 | 39 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a | 40 | irq_chip_set_defaults(chip); |
6b8ff312 | 41 | desc->irq_data.chip = chip; |
239007b8 | 42 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
43 | |
44 | return 0; | |
45 | } | |
a0cd9ca2 | 46 | EXPORT_SYMBOL(irq_set_chip); |
dd87eb3a TG |
47 | |
48 | /** | |
a0cd9ca2 | 49 | * irq_set_type - set the irq trigger type for an irq |
dd87eb3a | 50 | * @irq: irq number |
0c5d1eb7 | 51 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a | 52 | */ |
a0cd9ca2 | 53 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
dd87eb3a | 54 | { |
d3c60047 | 55 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
56 | unsigned long flags; |
57 | int ret = -ENXIO; | |
58 | ||
7d94f7ca | 59 | if (!desc) { |
dd87eb3a TG |
60 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
61 | return -ENODEV; | |
62 | } | |
63 | ||
f2b662da | 64 | type &= IRQ_TYPE_SENSE_MASK; |
0c5d1eb7 DB |
65 | if (type == IRQ_TYPE_NONE) |
66 | return 0; | |
67 | ||
43abe43c | 68 | chip_bus_lock(desc); |
239007b8 | 69 | raw_spin_lock_irqsave(&desc->lock, flags); |
0b3682ba | 70 | ret = __irq_set_trigger(desc, irq, type); |
239007b8 | 71 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
43abe43c | 72 | chip_bus_sync_unlock(desc); |
dd87eb3a TG |
73 | return ret; |
74 | } | |
a0cd9ca2 | 75 | EXPORT_SYMBOL(irq_set_irq_type); |
dd87eb3a TG |
76 | |
77 | /** | |
a0cd9ca2 | 78 | * irq_set_handler_data - set irq handler data for an irq |
dd87eb3a TG |
79 | * @irq: Interrupt number |
80 | * @data: Pointer to interrupt specific data | |
81 | * | |
82 | * Set the hardware irq controller data for an irq | |
83 | */ | |
a0cd9ca2 | 84 | int irq_set_handler_data(unsigned int irq, void *data) |
dd87eb3a | 85 | { |
d3c60047 | 86 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
87 | unsigned long flags; |
88 | ||
7d94f7ca | 89 | if (!desc) { |
dd87eb3a TG |
90 | printk(KERN_ERR |
91 | "Trying to install controller data for IRQ%d\n", irq); | |
92 | return -EINVAL; | |
93 | } | |
94 | ||
239007b8 | 95 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 96 | desc->irq_data.handler_data = data; |
239007b8 | 97 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
98 | return 0; |
99 | } | |
a0cd9ca2 | 100 | EXPORT_SYMBOL(irq_set_handler_data); |
dd87eb3a | 101 | |
5b912c10 | 102 | /** |
a0cd9ca2 | 103 | * irq_set_msi_desc - set MSI descriptor data for an irq |
5b912c10 | 104 | * @irq: Interrupt number |
472900b8 | 105 | * @entry: Pointer to MSI descriptor data |
5b912c10 | 106 | * |
24b26d42 | 107 | * Set the MSI descriptor entry for an irq |
5b912c10 | 108 | */ |
a0cd9ca2 | 109 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) |
5b912c10 | 110 | { |
d3c60047 | 111 | struct irq_desc *desc = irq_to_desc(irq); |
5b912c10 EB |
112 | unsigned long flags; |
113 | ||
7d94f7ca | 114 | if (!desc) { |
5b912c10 EB |
115 | printk(KERN_ERR |
116 | "Trying to install msi data for IRQ%d\n", irq); | |
117 | return -EINVAL; | |
118 | } | |
7d94f7ca | 119 | |
239007b8 | 120 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 121 | desc->irq_data.msi_desc = entry; |
7fe3730d ME |
122 | if (entry) |
123 | entry->irq = irq; | |
239007b8 | 124 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
5b912c10 EB |
125 | return 0; |
126 | } | |
127 | ||
dd87eb3a | 128 | /** |
a0cd9ca2 | 129 | * irq_set_chip_data - set irq chip data for an irq |
dd87eb3a TG |
130 | * @irq: Interrupt number |
131 | * @data: Pointer to chip specific data | |
132 | * | |
133 | * Set the hardware irq chip data for an irq | |
134 | */ | |
a0cd9ca2 | 135 | int irq_set_chip_data(unsigned int irq, void *data) |
dd87eb3a | 136 | { |
d3c60047 | 137 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
138 | unsigned long flags; |
139 | ||
7d94f7ca YL |
140 | if (!desc) { |
141 | printk(KERN_ERR | |
142 | "Trying to install chip data for IRQ%d\n", irq); | |
143 | return -EINVAL; | |
144 | } | |
145 | ||
6b8ff312 | 146 | if (!desc->irq_data.chip) { |
dd87eb3a TG |
147 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
148 | return -EINVAL; | |
149 | } | |
150 | ||
239007b8 | 151 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 152 | desc->irq_data.chip_data = data; |
239007b8 | 153 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
154 | |
155 | return 0; | |
156 | } | |
a0cd9ca2 | 157 | EXPORT_SYMBOL(irq_set_chip_data); |
dd87eb3a | 158 | |
f303a6dd TG |
159 | struct irq_data *irq_get_irq_data(unsigned int irq) |
160 | { | |
161 | struct irq_desc *desc = irq_to_desc(irq); | |
162 | ||
163 | return desc ? &desc->irq_data : NULL; | |
164 | } | |
165 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
166 | ||
c1594b77 TG |
167 | static void irq_state_clr_disabled(struct irq_desc *desc) |
168 | { | |
169 | desc->istate &= ~IRQS_DISABLED; | |
170 | irq_compat_clr_disabled(desc); | |
171 | } | |
172 | ||
173 | static void irq_state_set_disabled(struct irq_desc *desc) | |
174 | { | |
175 | desc->istate |= IRQS_DISABLED; | |
176 | irq_compat_set_disabled(desc); | |
177 | } | |
178 | ||
6e40262e TG |
179 | static void irq_state_clr_masked(struct irq_desc *desc) |
180 | { | |
181 | desc->istate &= ~IRQS_MASKED; | |
182 | irq_compat_clr_masked(desc); | |
183 | } | |
184 | ||
185 | static void irq_state_set_masked(struct irq_desc *desc) | |
186 | { | |
187 | desc->istate |= IRQS_MASKED; | |
188 | irq_compat_set_masked(desc); | |
189 | } | |
190 | ||
46999238 TG |
191 | int irq_startup(struct irq_desc *desc) |
192 | { | |
c1594b77 | 193 | irq_state_clr_disabled(desc); |
46999238 TG |
194 | desc->depth = 0; |
195 | ||
3aae994f TG |
196 | if (desc->irq_data.chip->irq_startup) { |
197 | int ret = desc->irq_data.chip->irq_startup(&desc->irq_data); | |
6e40262e | 198 | irq_state_clr_masked(desc); |
3aae994f TG |
199 | return ret; |
200 | } | |
46999238 | 201 | |
87923470 | 202 | irq_enable(desc); |
46999238 TG |
203 | return 0; |
204 | } | |
205 | ||
206 | void irq_shutdown(struct irq_desc *desc) | |
207 | { | |
c1594b77 | 208 | irq_state_set_disabled(desc); |
46999238 | 209 | desc->depth = 1; |
50f7c032 TG |
210 | if (desc->irq_data.chip->irq_shutdown) |
211 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | |
212 | if (desc->irq_data.chip->irq_disable) | |
213 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
214 | else | |
215 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 216 | irq_state_set_masked(desc); |
46999238 TG |
217 | } |
218 | ||
87923470 TG |
219 | void irq_enable(struct irq_desc *desc) |
220 | { | |
c1594b77 | 221 | irq_state_clr_disabled(desc); |
50f7c032 TG |
222 | if (desc->irq_data.chip->irq_enable) |
223 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
224 | else | |
225 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 226 | irq_state_clr_masked(desc); |
dd87eb3a TG |
227 | } |
228 | ||
50f7c032 | 229 | void irq_disable(struct irq_desc *desc) |
89d694b9 | 230 | { |
c1594b77 | 231 | irq_state_set_disabled(desc); |
50f7c032 TG |
232 | if (desc->irq_data.chip->irq_disable) { |
233 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
50f7c032 | 234 | } |
6e40262e | 235 | irq_state_set_masked(desc); |
89d694b9 TG |
236 | } |
237 | ||
bd151412 | 238 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
3876ec9e | 239 | /* Temporary migration helpers */ |
e2c0f8ff TG |
240 | static void compat_irq_mask(struct irq_data *data) |
241 | { | |
242 | data->chip->mask(data->irq); | |
243 | } | |
244 | ||
0eda58b7 TG |
245 | static void compat_irq_unmask(struct irq_data *data) |
246 | { | |
247 | data->chip->unmask(data->irq); | |
248 | } | |
249 | ||
22a49163 TG |
250 | static void compat_irq_ack(struct irq_data *data) |
251 | { | |
252 | data->chip->ack(data->irq); | |
253 | } | |
254 | ||
9205e31d TG |
255 | static void compat_irq_mask_ack(struct irq_data *data) |
256 | { | |
257 | data->chip->mask_ack(data->irq); | |
258 | } | |
259 | ||
0c5c1557 TG |
260 | static void compat_irq_eoi(struct irq_data *data) |
261 | { | |
262 | data->chip->eoi(data->irq); | |
263 | } | |
264 | ||
c5f75634 TG |
265 | static void compat_irq_enable(struct irq_data *data) |
266 | { | |
267 | data->chip->enable(data->irq); | |
268 | } | |
269 | ||
bc310dda TG |
270 | static void compat_irq_disable(struct irq_data *data) |
271 | { | |
272 | data->chip->disable(data->irq); | |
273 | } | |
274 | ||
275 | static void compat_irq_shutdown(struct irq_data *data) | |
276 | { | |
277 | data->chip->shutdown(data->irq); | |
278 | } | |
279 | ||
37e12df7 TG |
280 | static unsigned int compat_irq_startup(struct irq_data *data) |
281 | { | |
282 | return data->chip->startup(data->irq); | |
283 | } | |
284 | ||
c96b3b3c TG |
285 | static int compat_irq_set_affinity(struct irq_data *data, |
286 | const struct cpumask *dest, bool force) | |
287 | { | |
288 | return data->chip->set_affinity(data->irq, dest); | |
289 | } | |
290 | ||
b2ba2c30 TG |
291 | static int compat_irq_set_type(struct irq_data *data, unsigned int type) |
292 | { | |
293 | return data->chip->set_type(data->irq, type); | |
294 | } | |
295 | ||
2f7e99bb TG |
296 | static int compat_irq_set_wake(struct irq_data *data, unsigned int on) |
297 | { | |
298 | return data->chip->set_wake(data->irq, on); | |
299 | } | |
300 | ||
21e2b8c6 TG |
301 | static int compat_irq_retrigger(struct irq_data *data) |
302 | { | |
303 | return data->chip->retrigger(data->irq); | |
304 | } | |
305 | ||
3876ec9e TG |
306 | static void compat_bus_lock(struct irq_data *data) |
307 | { | |
308 | data->chip->bus_lock(data->irq); | |
309 | } | |
310 | ||
311 | static void compat_bus_sync_unlock(struct irq_data *data) | |
312 | { | |
313 | data->chip->bus_sync_unlock(data->irq); | |
314 | } | |
bd151412 | 315 | #endif |
3876ec9e | 316 | |
dd87eb3a TG |
317 | /* |
318 | * Fixup enable/disable function pointers | |
319 | */ | |
320 | void irq_chip_set_defaults(struct irq_chip *chip) | |
321 | { | |
bd151412 | 322 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
c5f75634 TG |
323 | if (chip->enable) |
324 | chip->irq_enable = compat_irq_enable; | |
bc310dda TG |
325 | if (chip->disable) |
326 | chip->irq_disable = compat_irq_disable; | |
327 | if (chip->shutdown) | |
328 | chip->irq_shutdown = compat_irq_shutdown; | |
37e12df7 TG |
329 | if (chip->startup) |
330 | chip->irq_startup = compat_irq_startup; | |
b86432b4 ZY |
331 | if (!chip->end) |
332 | chip->end = dummy_irq_chip.end; | |
3876ec9e TG |
333 | if (chip->bus_lock) |
334 | chip->irq_bus_lock = compat_bus_lock; | |
335 | if (chip->bus_sync_unlock) | |
336 | chip->irq_bus_sync_unlock = compat_bus_sync_unlock; | |
e2c0f8ff TG |
337 | if (chip->mask) |
338 | chip->irq_mask = compat_irq_mask; | |
0eda58b7 TG |
339 | if (chip->unmask) |
340 | chip->irq_unmask = compat_irq_unmask; | |
22a49163 TG |
341 | if (chip->ack) |
342 | chip->irq_ack = compat_irq_ack; | |
9205e31d TG |
343 | if (chip->mask_ack) |
344 | chip->irq_mask_ack = compat_irq_mask_ack; | |
0c5c1557 TG |
345 | if (chip->eoi) |
346 | chip->irq_eoi = compat_irq_eoi; | |
c96b3b3c TG |
347 | if (chip->set_affinity) |
348 | chip->irq_set_affinity = compat_irq_set_affinity; | |
b2ba2c30 TG |
349 | if (chip->set_type) |
350 | chip->irq_set_type = compat_irq_set_type; | |
2f7e99bb TG |
351 | if (chip->set_wake) |
352 | chip->irq_set_wake = compat_irq_set_wake; | |
21e2b8c6 TG |
353 | if (chip->retrigger) |
354 | chip->irq_retrigger = compat_irq_retrigger; | |
bd151412 | 355 | #endif |
dd87eb3a TG |
356 | } |
357 | ||
9205e31d | 358 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 359 | { |
9205e31d TG |
360 | if (desc->irq_data.chip->irq_mask_ack) |
361 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 362 | else { |
e2c0f8ff | 363 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
364 | if (desc->irq_data.chip->irq_ack) |
365 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 366 | } |
6e40262e | 367 | irq_state_set_masked(desc); |
0b1adaa0 TG |
368 | } |
369 | ||
d4d5e089 | 370 | void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 371 | { |
e2c0f8ff TG |
372 | if (desc->irq_data.chip->irq_mask) { |
373 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 374 | irq_state_set_masked(desc); |
0b1adaa0 TG |
375 | } |
376 | } | |
377 | ||
d4d5e089 | 378 | void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 379 | { |
0eda58b7 TG |
380 | if (desc->irq_data.chip->irq_unmask) { |
381 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 382 | irq_state_clr_masked(desc); |
0b1adaa0 | 383 | } |
dd87eb3a TG |
384 | } |
385 | ||
399b5da2 TG |
386 | /* |
387 | * handle_nested_irq - Handle a nested irq from a irq thread | |
388 | * @irq: the interrupt number | |
389 | * | |
390 | * Handle interrupts which are nested into a threaded interrupt | |
391 | * handler. The handler function is called inside the calling | |
392 | * threads context. | |
393 | */ | |
394 | void handle_nested_irq(unsigned int irq) | |
395 | { | |
396 | struct irq_desc *desc = irq_to_desc(irq); | |
397 | struct irqaction *action; | |
398 | irqreturn_t action_ret; | |
399 | ||
400 | might_sleep(); | |
401 | ||
239007b8 | 402 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
403 | |
404 | kstat_incr_irqs_this_cpu(irq, desc); | |
405 | ||
406 | action = desc->action; | |
c1594b77 | 407 | if (unlikely(!action || (desc->istate & IRQS_DISABLED))) |
399b5da2 TG |
408 | goto out_unlock; |
409 | ||
009b4c3b TG |
410 | irq_compat_set_progress(desc); |
411 | desc->istate |= IRQS_INPROGRESS; | |
239007b8 | 412 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
413 | |
414 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
415 | if (!noirqdebug) | |
416 | note_interrupt(irq, desc, action_ret); | |
417 | ||
239007b8 | 418 | raw_spin_lock_irq(&desc->lock); |
009b4c3b TG |
419 | desc->istate &= ~IRQS_INPROGRESS; |
420 | irq_compat_clr_progress(desc); | |
399b5da2 TG |
421 | |
422 | out_unlock: | |
239007b8 | 423 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
424 | } |
425 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
426 | ||
fe200ae4 TG |
427 | static bool irq_check_poll(struct irq_desc *desc) |
428 | { | |
6954b75b | 429 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
fe200ae4 TG |
430 | return false; |
431 | return irq_wait_for_poll(desc); | |
432 | } | |
433 | ||
dd87eb3a TG |
434 | /** |
435 | * handle_simple_irq - Simple and software-decoded IRQs. | |
436 | * @irq: the interrupt number | |
437 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
438 | * |
439 | * Simple interrupts are either sent from a demultiplexing interrupt | |
440 | * handler or come from hardware, where no interrupt hardware control | |
441 | * is necessary. | |
442 | * | |
443 | * Note: The caller is expected to handle the ack, clear, mask and | |
444 | * unmask issues if necessary. | |
445 | */ | |
7ad5b3a5 | 446 | void |
7d12e780 | 447 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 448 | { |
239007b8 | 449 | raw_spin_lock(&desc->lock); |
dd87eb3a | 450 | |
009b4c3b | 451 | if (unlikely(desc->istate & IRQS_INPROGRESS)) |
fe200ae4 TG |
452 | if (!irq_check_poll(desc)) |
453 | goto out_unlock; | |
454 | ||
163ef309 | 455 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 456 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 457 | |
c1594b77 | 458 | if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) |
dd87eb3a TG |
459 | goto out_unlock; |
460 | ||
107781e7 | 461 | handle_irq_event(desc); |
dd87eb3a | 462 | |
dd87eb3a | 463 | out_unlock: |
239007b8 | 464 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
465 | } |
466 | ||
467 | /** | |
468 | * handle_level_irq - Level type irq handler | |
469 | * @irq: the interrupt number | |
470 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
471 | * |
472 | * Level type interrupts are active as long as the hardware line has | |
473 | * the active level. This may require to mask the interrupt and unmask | |
474 | * it after the associated handler has acknowledged the device, so the | |
475 | * interrupt line is back to inactive. | |
476 | */ | |
7ad5b3a5 | 477 | void |
7d12e780 | 478 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 479 | { |
239007b8 | 480 | raw_spin_lock(&desc->lock); |
9205e31d | 481 | mask_ack_irq(desc); |
dd87eb3a | 482 | |
009b4c3b | 483 | if (unlikely(desc->istate & IRQS_INPROGRESS)) |
fe200ae4 TG |
484 | if (!irq_check_poll(desc)) |
485 | goto out_unlock; | |
486 | ||
163ef309 | 487 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 488 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
489 | |
490 | /* | |
491 | * If its disabled or no action available | |
492 | * keep it masked and get out of here | |
493 | */ | |
c1594b77 | 494 | if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) |
86998aa6 | 495 | goto out_unlock; |
dd87eb3a | 496 | |
1529866c | 497 | handle_irq_event(desc); |
b25c340c | 498 | |
c1594b77 | 499 | if (!(desc->istate & (IRQS_DISABLED | IRQS_ONESHOT))) |
0eda58b7 | 500 | unmask_irq(desc); |
86998aa6 | 501 | out_unlock: |
239007b8 | 502 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 503 | } |
14819ea1 | 504 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a TG |
505 | |
506 | /** | |
47c2a3aa | 507 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
508 | * @irq: the interrupt number |
509 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 510 | * |
47c2a3aa | 511 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
512 | * call when the interrupt has been serviced. This enables support |
513 | * for modern forms of interrupt handlers, which handle the flow | |
514 | * details in hardware, transparently. | |
515 | */ | |
7ad5b3a5 | 516 | void |
7d12e780 | 517 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 518 | { |
239007b8 | 519 | raw_spin_lock(&desc->lock); |
dd87eb3a | 520 | |
009b4c3b | 521 | if (unlikely(desc->istate & IRQS_INPROGRESS)) |
fe200ae4 TG |
522 | if (!irq_check_poll(desc)) |
523 | goto out; | |
dd87eb3a | 524 | |
163ef309 | 525 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 526 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
527 | |
528 | /* | |
529 | * If its disabled or no action available | |
76d21601 | 530 | * then mask it and get out of here: |
dd87eb3a | 531 | */ |
c1594b77 | 532 | if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) { |
2a0d6fb3 TG |
533 | irq_compat_set_pending(desc); |
534 | desc->istate |= IRQS_PENDING; | |
e2c0f8ff | 535 | mask_irq(desc); |
dd87eb3a | 536 | goto out; |
98bb244b | 537 | } |
a7ae4de5 | 538 | handle_irq_event(desc); |
dd87eb3a | 539 | out: |
0c5c1557 | 540 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
239007b8 | 541 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
542 | } |
543 | ||
544 | /** | |
545 | * handle_edge_irq - edge type IRQ handler | |
546 | * @irq: the interrupt number | |
547 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
548 | * |
549 | * Interrupt occures on the falling and/or rising edge of a hardware | |
550 | * signal. The occurence is latched into the irq controller hardware | |
551 | * and must be acked in order to be reenabled. After the ack another | |
552 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 553 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
554 | * might be necessary to disable (mask) the interrupt depending on the |
555 | * controller hardware. This requires to reenable the interrupt inside | |
556 | * of the loop which handles the interrupts which have arrived while | |
557 | * the handler was running. If all pending interrupts are handled, the | |
558 | * loop is left. | |
559 | */ | |
7ad5b3a5 | 560 | void |
7d12e780 | 561 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 562 | { |
239007b8 | 563 | raw_spin_lock(&desc->lock); |
dd87eb3a | 564 | |
163ef309 | 565 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
dd87eb3a TG |
566 | /* |
567 | * If we're currently running this IRQ, or its disabled, | |
568 | * we shouldn't process the IRQ. Mark it pending, handle | |
569 | * the necessary masking and go out | |
570 | */ | |
c1594b77 TG |
571 | if (unlikely((desc->istate & (IRQS_DISABLED | IRQS_INPROGRESS) || |
572 | !desc->action))) { | |
fe200ae4 | 573 | if (!irq_check_poll(desc)) { |
2a0d6fb3 TG |
574 | irq_compat_set_pending(desc); |
575 | desc->istate |= IRQS_PENDING; | |
fe200ae4 TG |
576 | mask_ack_irq(desc); |
577 | goto out_unlock; | |
578 | } | |
dd87eb3a | 579 | } |
d6c88a50 | 580 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
581 | |
582 | /* Start handling the irq */ | |
22a49163 | 583 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a | 584 | |
dd87eb3a | 585 | do { |
a60a5dc2 | 586 | if (unlikely(!desc->action)) { |
e2c0f8ff | 587 | mask_irq(desc); |
dd87eb3a TG |
588 | goto out_unlock; |
589 | } | |
590 | ||
591 | /* | |
592 | * When another irq arrived while we were handling | |
593 | * one, we could have masked the irq. | |
594 | * Renable it, if it was not disabled in meantime. | |
595 | */ | |
2a0d6fb3 | 596 | if (unlikely(desc->istate & IRQS_PENDING)) { |
c1594b77 | 597 | if (!(desc->istate & IRQS_DISABLED) && |
6e40262e | 598 | (desc->istate & IRQS_MASKED)) |
c1594b77 | 599 | unmask_irq(desc); |
dd87eb3a TG |
600 | } |
601 | ||
a60a5dc2 | 602 | handle_irq_event(desc); |
dd87eb3a | 603 | |
2a0d6fb3 | 604 | } while ((desc->istate & IRQS_PENDING) && |
c1594b77 | 605 | !(desc->istate & IRQS_DISABLED)); |
dd87eb3a | 606 | |
dd87eb3a | 607 | out_unlock: |
239007b8 | 608 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
609 | } |
610 | ||
dd87eb3a | 611 | /** |
24b26d42 | 612 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
613 | * @irq: the interrupt number |
614 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
615 | * |
616 | * Per CPU interrupts on SMP machines without locking requirements | |
617 | */ | |
7ad5b3a5 | 618 | void |
7d12e780 | 619 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 620 | { |
35e857cb | 621 | struct irq_chip *chip = irq_desc_get_chip(desc); |
dd87eb3a | 622 | |
d6c88a50 | 623 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 624 | |
849f061c TG |
625 | if (chip->irq_ack) |
626 | chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 627 | |
849f061c | 628 | handle_irq_event_percpu(desc, desc->action); |
dd87eb3a | 629 | |
849f061c TG |
630 | if (chip->irq_eoi) |
631 | chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
632 | } |
633 | ||
dd87eb3a | 634 | void |
a460e745 IM |
635 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
636 | const char *name) | |
dd87eb3a | 637 | { |
d3c60047 | 638 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
639 | unsigned long flags; |
640 | ||
7d94f7ca | 641 | if (!desc) { |
dd87eb3a TG |
642 | printk(KERN_ERR |
643 | "Trying to install type control for IRQ%d\n", irq); | |
644 | return; | |
645 | } | |
646 | ||
dd87eb3a TG |
647 | if (!handle) |
648 | handle = handle_bad_irq; | |
6b8ff312 | 649 | else if (desc->irq_data.chip == &no_irq_chip) { |
f8b5473f | 650 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 651 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
652 | /* |
653 | * Some ARM implementations install a handler for really dumb | |
654 | * interrupt hardware without setting an irq_chip. This worked | |
655 | * with the ARM no_irq_chip but the check in setup_irq would | |
656 | * prevent us to setup the interrupt at all. Switch it to | |
657 | * dummy_irq_chip for easy transition. | |
658 | */ | |
6b8ff312 | 659 | desc->irq_data.chip = &dummy_irq_chip; |
f8b5473f | 660 | } |
dd87eb3a | 661 | |
3876ec9e | 662 | chip_bus_lock(desc); |
239007b8 | 663 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a TG |
664 | |
665 | /* Uninstall? */ | |
666 | if (handle == handle_bad_irq) { | |
6b8ff312 | 667 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 668 | mask_ack_irq(desc); |
c1594b77 TG |
669 | irq_compat_set_disabled(desc); |
670 | desc->istate |= IRQS_DISABLED; | |
dd87eb3a TG |
671 | desc->depth = 1; |
672 | } | |
673 | desc->handle_irq = handle; | |
a460e745 | 674 | desc->name = name; |
dd87eb3a TG |
675 | |
676 | if (handle != handle_bad_irq && is_chained) { | |
1ccb4e61 TG |
677 | irq_settings_set_noprobe(desc); |
678 | irq_settings_set_norequest(desc); | |
46999238 | 679 | irq_startup(desc); |
dd87eb3a | 680 | } |
239007b8 | 681 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3876ec9e | 682 | chip_bus_sync_unlock(desc); |
dd87eb3a | 683 | } |
14819ea1 | 684 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
dd87eb3a TG |
685 | |
686 | void | |
687 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 688 | irq_flow_handler_t handle) |
dd87eb3a | 689 | { |
35e857cb | 690 | irq_set_chip(irq, chip); |
a460e745 | 691 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
692 | } |
693 | ||
a460e745 IM |
694 | void |
695 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
696 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 697 | { |
35e857cb | 698 | irq_set_chip(irq, chip); |
a460e745 | 699 | __set_irq_handler(irq, handle, 0, name); |
dd87eb3a | 700 | } |
46f4f8f6 | 701 | |
44247184 | 702 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 703 | { |
d3c60047 | 704 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
705 | unsigned long flags; |
706 | ||
44247184 | 707 | if (!desc) |
46f4f8f6 | 708 | return; |
46f4f8f6 | 709 | |
239007b8 | 710 | raw_spin_lock_irqsave(&desc->lock, flags); |
a005677b TG |
711 | |
712 | irq_settings_clr_and_set(desc, clr, set); | |
713 | ||
876dbd4c | 714 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
e1ef8241 | 715 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
a005677b TG |
716 | if (irq_settings_has_no_balance_set(desc)) |
717 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
718 | if (irq_settings_is_per_cpu(desc)) | |
719 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
e1ef8241 TG |
720 | if (irq_settings_can_move_pcntxt(desc)) |
721 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | |
a005677b | 722 | |
876dbd4c TG |
723 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
724 | ||
239007b8 | 725 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
46f4f8f6 | 726 | } |