Commit | Line | Data |
---|---|---|
dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
ced5b697 | 21 | static void dynamic_irq_init_x(unsigned int irq, bool keep_chip_data) |
3a16d713 | 22 | { |
0b8f1efa | 23 | struct irq_desc *desc; |
3a16d713 EB |
24 | unsigned long flags; |
25 | ||
0b8f1efa | 26 | desc = irq_to_desc(irq); |
7d94f7ca | 27 | if (!desc) { |
261c40c1 | 28 | WARN(1, KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); |
3a16d713 EB |
29 | return; |
30 | } | |
31 | ||
32 | /* Ensure we don't have left over values from a previous use of this irq */ | |
239007b8 | 33 | raw_spin_lock_irqsave(&desc->lock, flags); |
3a16d713 EB |
34 | desc->status = IRQ_DISABLED; |
35 | desc->chip = &no_irq_chip; | |
36 | desc->handle_irq = handle_bad_irq; | |
37 | desc->depth = 1; | |
5b912c10 | 38 | desc->msi_desc = NULL; |
3a16d713 | 39 | desc->handler_data = NULL; |
ced5b697 BP |
40 | if (!keep_chip_data) |
41 | desc->chip_data = NULL; | |
3a16d713 EB |
42 | desc->action = NULL; |
43 | desc->irq_count = 0; | |
44 | desc->irqs_unhandled = 0; | |
45 | #ifdef CONFIG_SMP | |
7f7ace0c MT |
46 | cpumask_setall(desc->affinity); |
47 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
48 | cpumask_clear(desc->pending_mask); | |
49 | #endif | |
3a16d713 | 50 | #endif |
239007b8 | 51 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3a16d713 EB |
52 | } |
53 | ||
54 | /** | |
ced5b697 | 55 | * dynamic_irq_init - initialize a dynamically allocated irq |
3a16d713 EB |
56 | * @irq: irq number to initialize |
57 | */ | |
ced5b697 BP |
58 | void dynamic_irq_init(unsigned int irq) |
59 | { | |
60 | dynamic_irq_init_x(irq, false); | |
61 | } | |
62 | ||
63 | /** | |
64 | * dynamic_irq_init_keep_chip_data - initialize a dynamically allocated irq | |
65 | * @irq: irq number to initialize | |
66 | * | |
67 | * does not set irq_to_desc(irq)->chip_data to NULL | |
68 | */ | |
69 | void dynamic_irq_init_keep_chip_data(unsigned int irq) | |
70 | { | |
71 | dynamic_irq_init_x(irq, true); | |
72 | } | |
73 | ||
74 | static void dynamic_irq_cleanup_x(unsigned int irq, bool keep_chip_data) | |
3a16d713 | 75 | { |
d3c60047 | 76 | struct irq_desc *desc = irq_to_desc(irq); |
3a16d713 EB |
77 | unsigned long flags; |
78 | ||
7d94f7ca | 79 | if (!desc) { |
261c40c1 | 80 | WARN(1, KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); |
3a16d713 EB |
81 | return; |
82 | } | |
83 | ||
239007b8 | 84 | raw_spin_lock_irqsave(&desc->lock, flags); |
1f80025e | 85 | if (desc->action) { |
239007b8 | 86 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
261c40c1 | 87 | WARN(1, KERN_ERR "Destroying IRQ%d without calling free_irq\n", |
1f80025e | 88 | irq); |
1f80025e EB |
89 | return; |
90 | } | |
5b912c10 EB |
91 | desc->msi_desc = NULL; |
92 | desc->handler_data = NULL; | |
ced5b697 BP |
93 | if (!keep_chip_data) |
94 | desc->chip_data = NULL; | |
3a16d713 EB |
95 | desc->handle_irq = handle_bad_irq; |
96 | desc->chip = &no_irq_chip; | |
b6f3b780 | 97 | desc->name = NULL; |
0f3c2a89 | 98 | clear_kstat_irqs(desc); |
239007b8 | 99 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3a16d713 EB |
100 | } |
101 | ||
ced5b697 BP |
102 | /** |
103 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq | |
104 | * @irq: irq number to initialize | |
105 | */ | |
106 | void dynamic_irq_cleanup(unsigned int irq) | |
107 | { | |
108 | dynamic_irq_cleanup_x(irq, false); | |
109 | } | |
110 | ||
111 | /** | |
112 | * dynamic_irq_cleanup_keep_chip_data - cleanup a dynamically allocated irq | |
113 | * @irq: irq number to initialize | |
114 | * | |
115 | * does not set irq_to_desc(irq)->chip_data to NULL | |
116 | */ | |
117 | void dynamic_irq_cleanup_keep_chip_data(unsigned int irq) | |
118 | { | |
119 | dynamic_irq_cleanup_x(irq, true); | |
120 | } | |
121 | ||
3a16d713 | 122 | |
dd87eb3a TG |
123 | /** |
124 | * set_irq_chip - set the irq chip for an irq | |
125 | * @irq: irq number | |
126 | * @chip: pointer to irq chip description structure | |
127 | */ | |
128 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
129 | { | |
d3c60047 | 130 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
131 | unsigned long flags; |
132 | ||
7d94f7ca | 133 | if (!desc) { |
261c40c1 | 134 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
dd87eb3a TG |
135 | return -EINVAL; |
136 | } | |
137 | ||
138 | if (!chip) | |
139 | chip = &no_irq_chip; | |
140 | ||
239007b8 | 141 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a TG |
142 | irq_chip_set_defaults(chip); |
143 | desc->chip = chip; | |
239007b8 | 144 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
145 | |
146 | return 0; | |
147 | } | |
148 | EXPORT_SYMBOL(set_irq_chip); | |
149 | ||
150 | /** | |
0c5d1eb7 | 151 | * set_irq_type - set the irq trigger type for an irq |
dd87eb3a | 152 | * @irq: irq number |
0c5d1eb7 | 153 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a TG |
154 | */ |
155 | int set_irq_type(unsigned int irq, unsigned int type) | |
156 | { | |
d3c60047 | 157 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
158 | unsigned long flags; |
159 | int ret = -ENXIO; | |
160 | ||
7d94f7ca | 161 | if (!desc) { |
dd87eb3a TG |
162 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
163 | return -ENODEV; | |
164 | } | |
165 | ||
f2b662da | 166 | type &= IRQ_TYPE_SENSE_MASK; |
0c5d1eb7 DB |
167 | if (type == IRQ_TYPE_NONE) |
168 | return 0; | |
169 | ||
239007b8 | 170 | raw_spin_lock_irqsave(&desc->lock, flags); |
0b3682ba | 171 | ret = __irq_set_trigger(desc, irq, type); |
239007b8 | 172 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
173 | return ret; |
174 | } | |
175 | EXPORT_SYMBOL(set_irq_type); | |
176 | ||
177 | /** | |
178 | * set_irq_data - set irq type data for an irq | |
179 | * @irq: Interrupt number | |
180 | * @data: Pointer to interrupt specific data | |
181 | * | |
182 | * Set the hardware irq controller data for an irq | |
183 | */ | |
184 | int set_irq_data(unsigned int irq, void *data) | |
185 | { | |
d3c60047 | 186 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
187 | unsigned long flags; |
188 | ||
7d94f7ca | 189 | if (!desc) { |
dd87eb3a TG |
190 | printk(KERN_ERR |
191 | "Trying to install controller data for IRQ%d\n", irq); | |
192 | return -EINVAL; | |
193 | } | |
194 | ||
239007b8 | 195 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a | 196 | desc->handler_data = data; |
239007b8 | 197 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
198 | return 0; |
199 | } | |
200 | EXPORT_SYMBOL(set_irq_data); | |
201 | ||
5b912c10 | 202 | /** |
24b26d42 | 203 | * set_irq_msi - set MSI descriptor data for an irq |
5b912c10 | 204 | * @irq: Interrupt number |
472900b8 | 205 | * @entry: Pointer to MSI descriptor data |
5b912c10 | 206 | * |
24b26d42 | 207 | * Set the MSI descriptor entry for an irq |
5b912c10 EB |
208 | */ |
209 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) | |
210 | { | |
d3c60047 | 211 | struct irq_desc *desc = irq_to_desc(irq); |
5b912c10 EB |
212 | unsigned long flags; |
213 | ||
7d94f7ca | 214 | if (!desc) { |
5b912c10 EB |
215 | printk(KERN_ERR |
216 | "Trying to install msi data for IRQ%d\n", irq); | |
217 | return -EINVAL; | |
218 | } | |
7d94f7ca | 219 | |
239007b8 | 220 | raw_spin_lock_irqsave(&desc->lock, flags); |
5b912c10 | 221 | desc->msi_desc = entry; |
7fe3730d ME |
222 | if (entry) |
223 | entry->irq = irq; | |
239007b8 | 224 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
5b912c10 EB |
225 | return 0; |
226 | } | |
227 | ||
dd87eb3a TG |
228 | /** |
229 | * set_irq_chip_data - set irq chip data for an irq | |
230 | * @irq: Interrupt number | |
231 | * @data: Pointer to chip specific data | |
232 | * | |
233 | * Set the hardware irq chip data for an irq | |
234 | */ | |
235 | int set_irq_chip_data(unsigned int irq, void *data) | |
236 | { | |
d3c60047 | 237 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
238 | unsigned long flags; |
239 | ||
7d94f7ca YL |
240 | if (!desc) { |
241 | printk(KERN_ERR | |
242 | "Trying to install chip data for IRQ%d\n", irq); | |
243 | return -EINVAL; | |
244 | } | |
245 | ||
246 | if (!desc->chip) { | |
dd87eb3a TG |
247 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
248 | return -EINVAL; | |
249 | } | |
250 | ||
239007b8 | 251 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a | 252 | desc->chip_data = data; |
239007b8 | 253 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
254 | |
255 | return 0; | |
256 | } | |
257 | EXPORT_SYMBOL(set_irq_chip_data); | |
258 | ||
399b5da2 TG |
259 | /** |
260 | * set_irq_nested_thread - Set/Reset the IRQ_NESTED_THREAD flag of an irq | |
261 | * | |
262 | * @irq: Interrupt number | |
263 | * @nest: 0 to clear / 1 to set the IRQ_NESTED_THREAD flag | |
264 | * | |
265 | * The IRQ_NESTED_THREAD flag indicates that on | |
266 | * request_threaded_irq() no separate interrupt thread should be | |
267 | * created for the irq as the handler are called nested in the | |
268 | * context of a demultiplexing interrupt handler thread. | |
269 | */ | |
270 | void set_irq_nested_thread(unsigned int irq, int nest) | |
271 | { | |
272 | struct irq_desc *desc = irq_to_desc(irq); | |
273 | unsigned long flags; | |
274 | ||
275 | if (!desc) | |
276 | return; | |
277 | ||
239007b8 | 278 | raw_spin_lock_irqsave(&desc->lock, flags); |
399b5da2 TG |
279 | if (nest) |
280 | desc->status |= IRQ_NESTED_THREAD; | |
281 | else | |
282 | desc->status &= ~IRQ_NESTED_THREAD; | |
239007b8 | 283 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
399b5da2 TG |
284 | } |
285 | EXPORT_SYMBOL_GPL(set_irq_nested_thread); | |
286 | ||
dd87eb3a TG |
287 | /* |
288 | * default enable function | |
289 | */ | |
290 | static void default_enable(unsigned int irq) | |
291 | { | |
d3c60047 | 292 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
293 | |
294 | desc->chip->unmask(irq); | |
295 | desc->status &= ~IRQ_MASKED; | |
296 | } | |
297 | ||
298 | /* | |
299 | * default disable function | |
300 | */ | |
301 | static void default_disable(unsigned int irq) | |
302 | { | |
dd87eb3a TG |
303 | } |
304 | ||
305 | /* | |
306 | * default startup function | |
307 | */ | |
308 | static unsigned int default_startup(unsigned int irq) | |
309 | { | |
d3c60047 | 310 | struct irq_desc *desc = irq_to_desc(irq); |
08678b08 | 311 | |
08678b08 | 312 | desc->chip->enable(irq); |
dd87eb3a TG |
313 | return 0; |
314 | } | |
315 | ||
89d694b9 TG |
316 | /* |
317 | * default shutdown function | |
318 | */ | |
319 | static void default_shutdown(unsigned int irq) | |
320 | { | |
d3c60047 | 321 | struct irq_desc *desc = irq_to_desc(irq); |
89d694b9 TG |
322 | |
323 | desc->chip->mask(irq); | |
324 | desc->status |= IRQ_MASKED; | |
325 | } | |
326 | ||
dd87eb3a TG |
327 | /* |
328 | * Fixup enable/disable function pointers | |
329 | */ | |
330 | void irq_chip_set_defaults(struct irq_chip *chip) | |
331 | { | |
332 | if (!chip->enable) | |
333 | chip->enable = default_enable; | |
334 | if (!chip->disable) | |
335 | chip->disable = default_disable; | |
336 | if (!chip->startup) | |
337 | chip->startup = default_startup; | |
89d694b9 TG |
338 | /* |
339 | * We use chip->disable, when the user provided its own. When | |
340 | * we have default_disable set for chip->disable, then we need | |
341 | * to use default_shutdown, otherwise the irq line is not | |
342 | * disabled on free_irq(): | |
343 | */ | |
dd87eb3a | 344 | if (!chip->shutdown) |
89d694b9 TG |
345 | chip->shutdown = chip->disable != default_disable ? |
346 | chip->disable : default_shutdown; | |
dd87eb3a TG |
347 | if (!chip->name) |
348 | chip->name = chip->typename; | |
b86432b4 ZY |
349 | if (!chip->end) |
350 | chip->end = dummy_irq_chip.end; | |
dd87eb3a TG |
351 | } |
352 | ||
353 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) | |
354 | { | |
355 | if (desc->chip->mask_ack) | |
356 | desc->chip->mask_ack(irq); | |
357 | else { | |
358 | desc->chip->mask(irq); | |
efdc64f0 WC |
359 | if (desc->chip->ack) |
360 | desc->chip->ack(irq); | |
dd87eb3a TG |
361 | } |
362 | } | |
363 | ||
399b5da2 TG |
364 | /* |
365 | * handle_nested_irq - Handle a nested irq from a irq thread | |
366 | * @irq: the interrupt number | |
367 | * | |
368 | * Handle interrupts which are nested into a threaded interrupt | |
369 | * handler. The handler function is called inside the calling | |
370 | * threads context. | |
371 | */ | |
372 | void handle_nested_irq(unsigned int irq) | |
373 | { | |
374 | struct irq_desc *desc = irq_to_desc(irq); | |
375 | struct irqaction *action; | |
376 | irqreturn_t action_ret; | |
377 | ||
378 | might_sleep(); | |
379 | ||
239007b8 | 380 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
381 | |
382 | kstat_incr_irqs_this_cpu(irq, desc); | |
383 | ||
384 | action = desc->action; | |
385 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | |
386 | goto out_unlock; | |
387 | ||
388 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 389 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
390 | |
391 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
392 | if (!noirqdebug) | |
393 | note_interrupt(irq, desc, action_ret); | |
394 | ||
239007b8 | 395 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
396 | desc->status &= ~IRQ_INPROGRESS; |
397 | ||
398 | out_unlock: | |
239007b8 | 399 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
400 | } |
401 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
402 | ||
dd87eb3a TG |
403 | /** |
404 | * handle_simple_irq - Simple and software-decoded IRQs. | |
405 | * @irq: the interrupt number | |
406 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
407 | * |
408 | * Simple interrupts are either sent from a demultiplexing interrupt | |
409 | * handler or come from hardware, where no interrupt hardware control | |
410 | * is necessary. | |
411 | * | |
412 | * Note: The caller is expected to handle the ack, clear, mask and | |
413 | * unmask issues if necessary. | |
414 | */ | |
7ad5b3a5 | 415 | void |
7d12e780 | 416 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
417 | { |
418 | struct irqaction *action; | |
419 | irqreturn_t action_ret; | |
dd87eb3a | 420 | |
239007b8 | 421 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
422 | |
423 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
424 | goto out_unlock; | |
971e5b35 | 425 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 426 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
427 | |
428 | action = desc->action; | |
971e5b35 | 429 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
dd87eb3a TG |
430 | goto out_unlock; |
431 | ||
432 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 433 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 434 | |
7d12e780 | 435 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 436 | if (!noirqdebug) |
7d12e780 | 437 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 438 | |
239007b8 | 439 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
440 | desc->status &= ~IRQ_INPROGRESS; |
441 | out_unlock: | |
239007b8 | 442 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
443 | } |
444 | ||
445 | /** | |
446 | * handle_level_irq - Level type irq handler | |
447 | * @irq: the interrupt number | |
448 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
449 | * |
450 | * Level type interrupts are active as long as the hardware line has | |
451 | * the active level. This may require to mask the interrupt and unmask | |
452 | * it after the associated handler has acknowledged the device, so the | |
453 | * interrupt line is back to inactive. | |
454 | */ | |
7ad5b3a5 | 455 | void |
7d12e780 | 456 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 457 | { |
dd87eb3a TG |
458 | struct irqaction *action; |
459 | irqreturn_t action_ret; | |
460 | ||
239007b8 | 461 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
462 | mask_ack_irq(desc, irq); |
463 | ||
464 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
86998aa6 | 465 | goto out_unlock; |
dd87eb3a | 466 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 467 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
468 | |
469 | /* | |
470 | * If its disabled or no action available | |
471 | * keep it masked and get out of here | |
472 | */ | |
473 | action = desc->action; | |
49663421 | 474 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
86998aa6 | 475 | goto out_unlock; |
dd87eb3a TG |
476 | |
477 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 478 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 479 | |
7d12e780 | 480 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 481 | if (!noirqdebug) |
7d12e780 | 482 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 483 | |
239007b8 | 484 | raw_spin_lock(&desc->lock); |
dd87eb3a | 485 | desc->status &= ~IRQ_INPROGRESS; |
b25c340c TG |
486 | |
487 | if (unlikely(desc->status & IRQ_ONESHOT)) | |
488 | desc->status |= IRQ_MASKED; | |
489 | else if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) | |
dd87eb3a | 490 | desc->chip->unmask(irq); |
86998aa6 | 491 | out_unlock: |
239007b8 | 492 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 493 | } |
14819ea1 | 494 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a TG |
495 | |
496 | /** | |
47c2a3aa | 497 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
498 | * @irq: the interrupt number |
499 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 500 | * |
47c2a3aa | 501 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
502 | * call when the interrupt has been serviced. This enables support |
503 | * for modern forms of interrupt handlers, which handle the flow | |
504 | * details in hardware, transparently. | |
505 | */ | |
7ad5b3a5 | 506 | void |
7d12e780 | 507 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 508 | { |
dd87eb3a TG |
509 | struct irqaction *action; |
510 | irqreturn_t action_ret; | |
511 | ||
239007b8 | 512 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
513 | |
514 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
515 | goto out; | |
516 | ||
517 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
d6c88a50 | 518 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
519 | |
520 | /* | |
521 | * If its disabled or no action available | |
76d21601 | 522 | * then mask it and get out of here: |
dd87eb3a TG |
523 | */ |
524 | action = desc->action; | |
98bb244b BH |
525 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
526 | desc->status |= IRQ_PENDING; | |
76d21601 IM |
527 | if (desc->chip->mask) |
528 | desc->chip->mask(irq); | |
dd87eb3a | 529 | goto out; |
98bb244b | 530 | } |
dd87eb3a TG |
531 | |
532 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 533 | desc->status &= ~IRQ_PENDING; |
239007b8 | 534 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 535 | |
7d12e780 | 536 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 537 | if (!noirqdebug) |
7d12e780 | 538 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 539 | |
239007b8 | 540 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
541 | desc->status &= ~IRQ_INPROGRESS; |
542 | out: | |
47c2a3aa | 543 | desc->chip->eoi(irq); |
dd87eb3a | 544 | |
239007b8 | 545 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
546 | } |
547 | ||
548 | /** | |
549 | * handle_edge_irq - edge type IRQ handler | |
550 | * @irq: the interrupt number | |
551 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
552 | * |
553 | * Interrupt occures on the falling and/or rising edge of a hardware | |
554 | * signal. The occurence is latched into the irq controller hardware | |
555 | * and must be acked in order to be reenabled. After the ack another | |
556 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 557 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
558 | * might be necessary to disable (mask) the interrupt depending on the |
559 | * controller hardware. This requires to reenable the interrupt inside | |
560 | * of the loop which handles the interrupts which have arrived while | |
561 | * the handler was running. If all pending interrupts are handled, the | |
562 | * loop is left. | |
563 | */ | |
7ad5b3a5 | 564 | void |
7d12e780 | 565 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 566 | { |
239007b8 | 567 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
568 | |
569 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
570 | ||
571 | /* | |
572 | * If we're currently running this IRQ, or its disabled, | |
573 | * we shouldn't process the IRQ. Mark it pending, handle | |
574 | * the necessary masking and go out | |
575 | */ | |
576 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
577 | !desc->action)) { | |
578 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
579 | mask_ack_irq(desc, irq); | |
580 | goto out_unlock; | |
581 | } | |
d6c88a50 | 582 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
583 | |
584 | /* Start handling the irq */ | |
4dbc9ca2 TG |
585 | if (desc->chip->ack) |
586 | desc->chip->ack(irq); | |
dd87eb3a TG |
587 | |
588 | /* Mark the IRQ currently in progress.*/ | |
589 | desc->status |= IRQ_INPROGRESS; | |
590 | ||
591 | do { | |
592 | struct irqaction *action = desc->action; | |
593 | irqreturn_t action_ret; | |
594 | ||
595 | if (unlikely(!action)) { | |
596 | desc->chip->mask(irq); | |
597 | goto out_unlock; | |
598 | } | |
599 | ||
600 | /* | |
601 | * When another irq arrived while we were handling | |
602 | * one, we could have masked the irq. | |
603 | * Renable it, if it was not disabled in meantime. | |
604 | */ | |
605 | if (unlikely((desc->status & | |
606 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
607 | (IRQ_PENDING | IRQ_MASKED))) { | |
608 | desc->chip->unmask(irq); | |
609 | desc->status &= ~IRQ_MASKED; | |
610 | } | |
611 | ||
612 | desc->status &= ~IRQ_PENDING; | |
239007b8 | 613 | raw_spin_unlock(&desc->lock); |
7d12e780 | 614 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 615 | if (!noirqdebug) |
7d12e780 | 616 | note_interrupt(irq, desc, action_ret); |
239007b8 | 617 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
618 | |
619 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
620 | ||
621 | desc->status &= ~IRQ_INPROGRESS; | |
622 | out_unlock: | |
239007b8 | 623 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
624 | } |
625 | ||
dd87eb3a | 626 | /** |
24b26d42 | 627 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
628 | * @irq: the interrupt number |
629 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
630 | * |
631 | * Per CPU interrupts on SMP machines without locking requirements | |
632 | */ | |
7ad5b3a5 | 633 | void |
7d12e780 | 634 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
635 | { |
636 | irqreturn_t action_ret; | |
637 | ||
d6c88a50 | 638 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
639 | |
640 | if (desc->chip->ack) | |
641 | desc->chip->ack(irq); | |
642 | ||
7d12e780 | 643 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 644 | if (!noirqdebug) |
7d12e780 | 645 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 646 | |
fcef5911 | 647 | if (desc->chip->eoi) |
dd87eb3a TG |
648 | desc->chip->eoi(irq); |
649 | } | |
650 | ||
dd87eb3a | 651 | void |
a460e745 IM |
652 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
653 | const char *name) | |
dd87eb3a | 654 | { |
d3c60047 | 655 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
656 | unsigned long flags; |
657 | ||
7d94f7ca | 658 | if (!desc) { |
dd87eb3a TG |
659 | printk(KERN_ERR |
660 | "Trying to install type control for IRQ%d\n", irq); | |
661 | return; | |
662 | } | |
663 | ||
dd87eb3a TG |
664 | if (!handle) |
665 | handle = handle_bad_irq; | |
9d7ac8be | 666 | else if (desc->chip == &no_irq_chip) { |
f8b5473f | 667 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 668 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
669 | /* |
670 | * Some ARM implementations install a handler for really dumb | |
671 | * interrupt hardware without setting an irq_chip. This worked | |
672 | * with the ARM no_irq_chip but the check in setup_irq would | |
673 | * prevent us to setup the interrupt at all. Switch it to | |
674 | * dummy_irq_chip for easy transition. | |
675 | */ | |
676 | desc->chip = &dummy_irq_chip; | |
677 | } | |
dd87eb3a | 678 | |
70aedd24 | 679 | chip_bus_lock(irq, desc); |
239007b8 | 680 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a TG |
681 | |
682 | /* Uninstall? */ | |
683 | if (handle == handle_bad_irq) { | |
fcef5911 | 684 | if (desc->chip != &no_irq_chip) |
5575ddf7 | 685 | mask_ack_irq(desc, irq); |
dd87eb3a TG |
686 | desc->status |= IRQ_DISABLED; |
687 | desc->depth = 1; | |
688 | } | |
689 | desc->handle_irq = handle; | |
a460e745 | 690 | desc->name = name; |
dd87eb3a TG |
691 | |
692 | if (handle != handle_bad_irq && is_chained) { | |
693 | desc->status &= ~IRQ_DISABLED; | |
694 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | |
695 | desc->depth = 0; | |
7e6e178a | 696 | desc->chip->startup(irq); |
dd87eb3a | 697 | } |
239007b8 | 698 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
70aedd24 | 699 | chip_bus_sync_unlock(irq, desc); |
dd87eb3a | 700 | } |
14819ea1 | 701 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
dd87eb3a TG |
702 | |
703 | void | |
704 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 705 | irq_flow_handler_t handle) |
dd87eb3a TG |
706 | { |
707 | set_irq_chip(irq, chip); | |
a460e745 | 708 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
709 | } |
710 | ||
a460e745 IM |
711 | void |
712 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
713 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 714 | { |
a460e745 IM |
715 | set_irq_chip(irq, chip); |
716 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 717 | } |
46f4f8f6 RB |
718 | |
719 | void __init set_irq_noprobe(unsigned int irq) | |
720 | { | |
d3c60047 | 721 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
722 | unsigned long flags; |
723 | ||
7d94f7ca | 724 | if (!desc) { |
46f4f8f6 | 725 | printk(KERN_ERR "Trying to mark IRQ%d non-probeable\n", irq); |
46f4f8f6 RB |
726 | return; |
727 | } | |
728 | ||
239007b8 | 729 | raw_spin_lock_irqsave(&desc->lock, flags); |
46f4f8f6 | 730 | desc->status |= IRQ_NOPROBE; |
239007b8 | 731 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
46f4f8f6 RB |
732 | } |
733 | ||
734 | void __init set_irq_probe(unsigned int irq) | |
735 | { | |
d3c60047 | 736 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
737 | unsigned long flags; |
738 | ||
7d94f7ca | 739 | if (!desc) { |
46f4f8f6 | 740 | printk(KERN_ERR "Trying to mark IRQ%d probeable\n", irq); |
46f4f8f6 RB |
741 | return; |
742 | } | |
743 | ||
239007b8 | 744 | raw_spin_lock_irqsave(&desc->lock, flags); |
46f4f8f6 | 745 | desc->status &= ~IRQ_NOPROBE; |
239007b8 | 746 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
46f4f8f6 | 747 | } |