Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
f8264e34 | 18 | #include <linux/irqdomain.h> |
dd87eb3a | 19 | |
f069686e SR |
20 | #include <trace/events/irq.h> |
21 | ||
dd87eb3a TG |
22 | #include "internals.h" |
23 | ||
e509bd7d MW |
24 | static irqreturn_t bad_chained_irq(int irq, void *dev_id) |
25 | { | |
26 | WARN_ONCE(1, "Chained irq %d should not call an action\n", irq); | |
27 | return IRQ_NONE; | |
28 | } | |
29 | ||
30 | /* | |
31 | * Chained handlers should never call action on their IRQ. This default | |
32 | * action will emit warning if such thing happens. | |
33 | */ | |
34 | struct irqaction chained_action = { | |
35 | .handler = bad_chained_irq, | |
36 | }; | |
37 | ||
dd87eb3a | 38 | /** |
a0cd9ca2 | 39 | * irq_set_chip - set the irq chip for an irq |
dd87eb3a TG |
40 | * @irq: irq number |
41 | * @chip: pointer to irq chip description structure | |
42 | */ | |
a0cd9ca2 | 43 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
dd87eb3a | 44 | { |
dd87eb3a | 45 | unsigned long flags; |
31d9d9b6 | 46 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 47 | |
02725e74 | 48 | if (!desc) |
dd87eb3a | 49 | return -EINVAL; |
dd87eb3a TG |
50 | |
51 | if (!chip) | |
52 | chip = &no_irq_chip; | |
53 | ||
6b8ff312 | 54 | desc->irq_data.chip = chip; |
02725e74 | 55 | irq_put_desc_unlock(desc, flags); |
d72274e5 DD |
56 | /* |
57 | * For !CONFIG_SPARSE_IRQ make the irq show up in | |
f63b6a05 | 58 | * allocated_irqs. |
d72274e5 | 59 | */ |
f63b6a05 | 60 | irq_mark_irq(irq); |
dd87eb3a TG |
61 | return 0; |
62 | } | |
a0cd9ca2 | 63 | EXPORT_SYMBOL(irq_set_chip); |
dd87eb3a TG |
64 | |
65 | /** | |
a0cd9ca2 | 66 | * irq_set_type - set the irq trigger type for an irq |
dd87eb3a | 67 | * @irq: irq number |
0c5d1eb7 | 68 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a | 69 | */ |
a0cd9ca2 | 70 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
dd87eb3a | 71 | { |
dd87eb3a | 72 | unsigned long flags; |
31d9d9b6 | 73 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 | 74 | int ret = 0; |
dd87eb3a | 75 | |
02725e74 TG |
76 | if (!desc) |
77 | return -EINVAL; | |
dd87eb3a | 78 | |
a1ff541a | 79 | ret = __irq_set_trigger(desc, type); |
02725e74 | 80 | irq_put_desc_busunlock(desc, flags); |
dd87eb3a TG |
81 | return ret; |
82 | } | |
a0cd9ca2 | 83 | EXPORT_SYMBOL(irq_set_irq_type); |
dd87eb3a TG |
84 | |
85 | /** | |
a0cd9ca2 | 86 | * irq_set_handler_data - set irq handler data for an irq |
dd87eb3a TG |
87 | * @irq: Interrupt number |
88 | * @data: Pointer to interrupt specific data | |
89 | * | |
90 | * Set the hardware irq controller data for an irq | |
91 | */ | |
a0cd9ca2 | 92 | int irq_set_handler_data(unsigned int irq, void *data) |
dd87eb3a | 93 | { |
dd87eb3a | 94 | unsigned long flags; |
31d9d9b6 | 95 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 96 | |
02725e74 | 97 | if (!desc) |
dd87eb3a | 98 | return -EINVAL; |
af7080e0 | 99 | desc->irq_common_data.handler_data = data; |
02725e74 | 100 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
101 | return 0; |
102 | } | |
a0cd9ca2 | 103 | EXPORT_SYMBOL(irq_set_handler_data); |
dd87eb3a | 104 | |
5b912c10 | 105 | /** |
51906e77 AG |
106 | * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset |
107 | * @irq_base: Interrupt number base | |
108 | * @irq_offset: Interrupt number offset | |
109 | * @entry: Pointer to MSI descriptor data | |
5b912c10 | 110 | * |
51906e77 | 111 | * Set the MSI descriptor entry for an irq at offset |
5b912c10 | 112 | */ |
51906e77 AG |
113 | int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
114 | struct msi_desc *entry) | |
5b912c10 | 115 | { |
5b912c10 | 116 | unsigned long flags; |
51906e77 | 117 | struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
5b912c10 | 118 | |
02725e74 | 119 | if (!desc) |
5b912c10 | 120 | return -EINVAL; |
b237721c | 121 | desc->irq_common_data.msi_desc = entry; |
51906e77 AG |
122 | if (entry && !irq_offset) |
123 | entry->irq = irq_base; | |
02725e74 | 124 | irq_put_desc_unlock(desc, flags); |
5b912c10 EB |
125 | return 0; |
126 | } | |
127 | ||
51906e77 AG |
128 | /** |
129 | * irq_set_msi_desc - set MSI descriptor data for an irq | |
130 | * @irq: Interrupt number | |
131 | * @entry: Pointer to MSI descriptor data | |
132 | * | |
133 | * Set the MSI descriptor entry for an irq | |
134 | */ | |
135 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) | |
136 | { | |
137 | return irq_set_msi_desc_off(irq, 0, entry); | |
138 | } | |
139 | ||
dd87eb3a | 140 | /** |
a0cd9ca2 | 141 | * irq_set_chip_data - set irq chip data for an irq |
dd87eb3a TG |
142 | * @irq: Interrupt number |
143 | * @data: Pointer to chip specific data | |
144 | * | |
145 | * Set the hardware irq chip data for an irq | |
146 | */ | |
a0cd9ca2 | 147 | int irq_set_chip_data(unsigned int irq, void *data) |
dd87eb3a | 148 | { |
dd87eb3a | 149 | unsigned long flags; |
31d9d9b6 | 150 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 151 | |
02725e74 | 152 | if (!desc) |
dd87eb3a | 153 | return -EINVAL; |
6b8ff312 | 154 | desc->irq_data.chip_data = data; |
02725e74 | 155 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
156 | return 0; |
157 | } | |
a0cd9ca2 | 158 | EXPORT_SYMBOL(irq_set_chip_data); |
dd87eb3a | 159 | |
f303a6dd TG |
160 | struct irq_data *irq_get_irq_data(unsigned int irq) |
161 | { | |
162 | struct irq_desc *desc = irq_to_desc(irq); | |
163 | ||
164 | return desc ? &desc->irq_data : NULL; | |
165 | } | |
166 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
167 | ||
c1594b77 TG |
168 | static void irq_state_clr_disabled(struct irq_desc *desc) |
169 | { | |
801a0e9a | 170 | irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
171 | } |
172 | ||
173 | static void irq_state_set_disabled(struct irq_desc *desc) | |
174 | { | |
801a0e9a | 175 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
176 | } |
177 | ||
6e40262e TG |
178 | static void irq_state_clr_masked(struct irq_desc *desc) |
179 | { | |
32f4125e | 180 | irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
181 | } |
182 | ||
183 | static void irq_state_set_masked(struct irq_desc *desc) | |
184 | { | |
32f4125e | 185 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
186 | } |
187 | ||
b4bc724e | 188 | int irq_startup(struct irq_desc *desc, bool resend) |
46999238 | 189 | { |
b4bc724e TG |
190 | int ret = 0; |
191 | ||
c1594b77 | 192 | irq_state_clr_disabled(desc); |
46999238 TG |
193 | desc->depth = 0; |
194 | ||
f8264e34 | 195 | irq_domain_activate_irq(&desc->irq_data); |
3aae994f | 196 | if (desc->irq_data.chip->irq_startup) { |
b4bc724e | 197 | ret = desc->irq_data.chip->irq_startup(&desc->irq_data); |
6e40262e | 198 | irq_state_clr_masked(desc); |
b4bc724e TG |
199 | } else { |
200 | irq_enable(desc); | |
3aae994f | 201 | } |
b4bc724e | 202 | if (resend) |
0798abeb | 203 | check_irq_resend(desc); |
b4bc724e | 204 | return ret; |
46999238 TG |
205 | } |
206 | ||
207 | void irq_shutdown(struct irq_desc *desc) | |
208 | { | |
c1594b77 | 209 | irq_state_set_disabled(desc); |
46999238 | 210 | desc->depth = 1; |
50f7c032 TG |
211 | if (desc->irq_data.chip->irq_shutdown) |
212 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | |
ed585a65 | 213 | else if (desc->irq_data.chip->irq_disable) |
50f7c032 TG |
214 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
215 | else | |
216 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
f8264e34 | 217 | irq_domain_deactivate_irq(&desc->irq_data); |
6e40262e | 218 | irq_state_set_masked(desc); |
46999238 TG |
219 | } |
220 | ||
87923470 TG |
221 | void irq_enable(struct irq_desc *desc) |
222 | { | |
c1594b77 | 223 | irq_state_clr_disabled(desc); |
50f7c032 TG |
224 | if (desc->irq_data.chip->irq_enable) |
225 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
226 | else | |
227 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 228 | irq_state_clr_masked(desc); |
dd87eb3a TG |
229 | } |
230 | ||
d671a605 | 231 | /** |
f788e7bf | 232 | * irq_disable - Mark interrupt disabled |
d671a605 AF |
233 | * @desc: irq descriptor which should be disabled |
234 | * | |
235 | * If the chip does not implement the irq_disable callback, we | |
236 | * use a lazy disable approach. That means we mark the interrupt | |
237 | * disabled, but leave the hardware unmasked. That's an | |
238 | * optimization because we avoid the hardware access for the | |
239 | * common case where no interrupt happens after we marked it | |
240 | * disabled. If an interrupt happens, then the interrupt flow | |
241 | * handler masks the line at the hardware level and marks it | |
242 | * pending. | |
e9849777 TG |
243 | * |
244 | * If the interrupt chip does not implement the irq_disable callback, | |
245 | * a driver can disable the lazy approach for a particular irq line by | |
246 | * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can | |
247 | * be used for devices which cannot disable the interrupt at the | |
248 | * device level under certain circumstances and have to use | |
249 | * disable_irq[_nosync] instead. | |
d671a605 | 250 | */ |
50f7c032 | 251 | void irq_disable(struct irq_desc *desc) |
89d694b9 | 252 | { |
c1594b77 | 253 | irq_state_set_disabled(desc); |
50f7c032 TG |
254 | if (desc->irq_data.chip->irq_disable) { |
255 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
a61d8258 | 256 | irq_state_set_masked(desc); |
e9849777 TG |
257 | } else if (irq_settings_disable_unlazy(desc)) { |
258 | mask_irq(desc); | |
50f7c032 | 259 | } |
89d694b9 TG |
260 | } |
261 | ||
31d9d9b6 MZ |
262 | void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu) |
263 | { | |
264 | if (desc->irq_data.chip->irq_enable) | |
265 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
266 | else | |
267 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
268 | cpumask_set_cpu(cpu, desc->percpu_enabled); | |
269 | } | |
270 | ||
271 | void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) | |
272 | { | |
273 | if (desc->irq_data.chip->irq_disable) | |
274 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
275 | else | |
276 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
277 | cpumask_clear_cpu(cpu, desc->percpu_enabled); | |
278 | } | |
279 | ||
9205e31d | 280 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 281 | { |
9205e31d TG |
282 | if (desc->irq_data.chip->irq_mask_ack) |
283 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 284 | else { |
e2c0f8ff | 285 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
286 | if (desc->irq_data.chip->irq_ack) |
287 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 288 | } |
6e40262e | 289 | irq_state_set_masked(desc); |
0b1adaa0 TG |
290 | } |
291 | ||
d4d5e089 | 292 | void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 293 | { |
e2c0f8ff TG |
294 | if (desc->irq_data.chip->irq_mask) { |
295 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 296 | irq_state_set_masked(desc); |
0b1adaa0 TG |
297 | } |
298 | } | |
299 | ||
d4d5e089 | 300 | void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 301 | { |
0eda58b7 TG |
302 | if (desc->irq_data.chip->irq_unmask) { |
303 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 304 | irq_state_clr_masked(desc); |
0b1adaa0 | 305 | } |
dd87eb3a TG |
306 | } |
307 | ||
328a4978 TG |
308 | void unmask_threaded_irq(struct irq_desc *desc) |
309 | { | |
310 | struct irq_chip *chip = desc->irq_data.chip; | |
311 | ||
312 | if (chip->flags & IRQCHIP_EOI_THREADED) | |
313 | chip->irq_eoi(&desc->irq_data); | |
314 | ||
315 | if (chip->irq_unmask) { | |
316 | chip->irq_unmask(&desc->irq_data); | |
317 | irq_state_clr_masked(desc); | |
318 | } | |
319 | } | |
320 | ||
399b5da2 TG |
321 | /* |
322 | * handle_nested_irq - Handle a nested irq from a irq thread | |
323 | * @irq: the interrupt number | |
324 | * | |
325 | * Handle interrupts which are nested into a threaded interrupt | |
326 | * handler. The handler function is called inside the calling | |
327 | * threads context. | |
328 | */ | |
329 | void handle_nested_irq(unsigned int irq) | |
330 | { | |
331 | struct irq_desc *desc = irq_to_desc(irq); | |
332 | struct irqaction *action; | |
333 | irqreturn_t action_ret; | |
334 | ||
335 | might_sleep(); | |
336 | ||
239007b8 | 337 | raw_spin_lock_irq(&desc->lock); |
399b5da2 | 338 | |
293a7a0a | 339 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
399b5da2 TG |
340 | |
341 | action = desc->action; | |
23812b9d NJ |
342 | if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) { |
343 | desc->istate |= IRQS_PENDING; | |
399b5da2 | 344 | goto out_unlock; |
23812b9d | 345 | } |
399b5da2 | 346 | |
a946e8c7 | 347 | kstat_incr_irqs_this_cpu(desc); |
32f4125e | 348 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
239007b8 | 349 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 | 350 | |
45e52022 CK |
351 | action_ret = IRQ_NONE; |
352 | for_each_action_of_desc(desc, action) | |
353 | action_ret |= action->thread_fn(action->irq, action->dev_id); | |
354 | ||
399b5da2 | 355 | if (!noirqdebug) |
0dcdbc97 | 356 | note_interrupt(desc, action_ret); |
399b5da2 | 357 | |
239007b8 | 358 | raw_spin_lock_irq(&desc->lock); |
32f4125e | 359 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
399b5da2 TG |
360 | |
361 | out_unlock: | |
239007b8 | 362 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
363 | } |
364 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
365 | ||
fe200ae4 TG |
366 | static bool irq_check_poll(struct irq_desc *desc) |
367 | { | |
6954b75b | 368 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
fe200ae4 TG |
369 | return false; |
370 | return irq_wait_for_poll(desc); | |
371 | } | |
372 | ||
c7bd3ec0 TG |
373 | static bool irq_may_run(struct irq_desc *desc) |
374 | { | |
9ce7a258 TG |
375 | unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED; |
376 | ||
377 | /* | |
378 | * If the interrupt is not in progress and is not an armed | |
379 | * wakeup interrupt, proceed. | |
380 | */ | |
381 | if (!irqd_has_set(&desc->irq_data, mask)) | |
c7bd3ec0 | 382 | return true; |
9ce7a258 TG |
383 | |
384 | /* | |
385 | * If the interrupt is an armed wakeup source, mark it pending | |
386 | * and suspended, disable it and notify the pm core about the | |
387 | * event. | |
388 | */ | |
389 | if (irq_pm_check_wakeup(desc)) | |
390 | return false; | |
391 | ||
392 | /* | |
393 | * Handle a potential concurrent poll on a different core. | |
394 | */ | |
c7bd3ec0 TG |
395 | return irq_check_poll(desc); |
396 | } | |
397 | ||
dd87eb3a TG |
398 | /** |
399 | * handle_simple_irq - Simple and software-decoded IRQs. | |
dd87eb3a | 400 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
401 | * |
402 | * Simple interrupts are either sent from a demultiplexing interrupt | |
403 | * handler or come from hardware, where no interrupt hardware control | |
404 | * is necessary. | |
405 | * | |
406 | * Note: The caller is expected to handle the ack, clear, mask and | |
407 | * unmask issues if necessary. | |
408 | */ | |
bd0b9ac4 | 409 | void handle_simple_irq(struct irq_desc *desc) |
dd87eb3a | 410 | { |
239007b8 | 411 | raw_spin_lock(&desc->lock); |
dd87eb3a | 412 | |
c7bd3ec0 TG |
413 | if (!irq_may_run(desc)) |
414 | goto out_unlock; | |
fe200ae4 | 415 | |
163ef309 | 416 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
dd87eb3a | 417 | |
23812b9d NJ |
418 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
419 | desc->istate |= IRQS_PENDING; | |
dd87eb3a | 420 | goto out_unlock; |
23812b9d | 421 | } |
dd87eb3a | 422 | |
a946e8c7 | 423 | kstat_incr_irqs_this_cpu(desc); |
107781e7 | 424 | handle_irq_event(desc); |
dd87eb3a | 425 | |
dd87eb3a | 426 | out_unlock: |
239007b8 | 427 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 428 | } |
edf76f83 | 429 | EXPORT_SYMBOL_GPL(handle_simple_irq); |
dd87eb3a | 430 | |
edd14cfe KB |
431 | /** |
432 | * handle_untracked_irq - Simple and software-decoded IRQs. | |
433 | * @desc: the interrupt description structure for this irq | |
434 | * | |
435 | * Untracked interrupts are sent from a demultiplexing interrupt | |
436 | * handler when the demultiplexer does not know which device it its | |
437 | * multiplexed irq domain generated the interrupt. IRQ's handled | |
438 | * through here are not subjected to stats tracking, randomness, or | |
439 | * spurious interrupt detection. | |
440 | * | |
441 | * Note: Like handle_simple_irq, the caller is expected to handle | |
442 | * the ack, clear, mask and unmask issues if necessary. | |
443 | */ | |
444 | void handle_untracked_irq(struct irq_desc *desc) | |
445 | { | |
446 | unsigned int flags = 0; | |
447 | ||
448 | raw_spin_lock(&desc->lock); | |
449 | ||
450 | if (!irq_may_run(desc)) | |
451 | goto out_unlock; | |
452 | ||
453 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | |
454 | ||
455 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { | |
456 | desc->istate |= IRQS_PENDING; | |
457 | goto out_unlock; | |
458 | } | |
459 | ||
460 | desc->istate &= ~IRQS_PENDING; | |
461 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
462 | raw_spin_unlock(&desc->lock); | |
463 | ||
464 | __handle_irq_event_percpu(desc, &flags); | |
465 | ||
466 | raw_spin_lock(&desc->lock); | |
467 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
468 | ||
469 | out_unlock: | |
470 | raw_spin_unlock(&desc->lock); | |
471 | } | |
472 | EXPORT_SYMBOL_GPL(handle_untracked_irq); | |
473 | ||
ac563761 TG |
474 | /* |
475 | * Called unconditionally from handle_level_irq() and only for oneshot | |
476 | * interrupts from handle_fasteoi_irq() | |
477 | */ | |
478 | static void cond_unmask_irq(struct irq_desc *desc) | |
479 | { | |
480 | /* | |
481 | * We need to unmask in the following cases: | |
482 | * - Standard level irq (IRQF_ONESHOT is not set) | |
483 | * - Oneshot irq which did not wake the thread (caused by a | |
484 | * spurious interrupt or a primary handler handling it | |
485 | * completely). | |
486 | */ | |
487 | if (!irqd_irq_disabled(&desc->irq_data) && | |
488 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) | |
489 | unmask_irq(desc); | |
490 | } | |
491 | ||
dd87eb3a TG |
492 | /** |
493 | * handle_level_irq - Level type irq handler | |
dd87eb3a | 494 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
495 | * |
496 | * Level type interrupts are active as long as the hardware line has | |
497 | * the active level. This may require to mask the interrupt and unmask | |
498 | * it after the associated handler has acknowledged the device, so the | |
499 | * interrupt line is back to inactive. | |
500 | */ | |
bd0b9ac4 | 501 | void handle_level_irq(struct irq_desc *desc) |
dd87eb3a | 502 | { |
239007b8 | 503 | raw_spin_lock(&desc->lock); |
9205e31d | 504 | mask_ack_irq(desc); |
dd87eb3a | 505 | |
c7bd3ec0 TG |
506 | if (!irq_may_run(desc)) |
507 | goto out_unlock; | |
fe200ae4 | 508 | |
163ef309 | 509 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
dd87eb3a TG |
510 | |
511 | /* | |
512 | * If its disabled or no action available | |
513 | * keep it masked and get out of here | |
514 | */ | |
d4dc0f90 TG |
515 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
516 | desc->istate |= IRQS_PENDING; | |
86998aa6 | 517 | goto out_unlock; |
d4dc0f90 | 518 | } |
dd87eb3a | 519 | |
a946e8c7 | 520 | kstat_incr_irqs_this_cpu(desc); |
1529866c | 521 | handle_irq_event(desc); |
b25c340c | 522 | |
ac563761 TG |
523 | cond_unmask_irq(desc); |
524 | ||
86998aa6 | 525 | out_unlock: |
239007b8 | 526 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 527 | } |
14819ea1 | 528 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a | 529 | |
78129576 TG |
530 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
531 | static inline void preflow_handler(struct irq_desc *desc) | |
532 | { | |
533 | if (desc->preflow_handler) | |
534 | desc->preflow_handler(&desc->irq_data); | |
535 | } | |
536 | #else | |
537 | static inline void preflow_handler(struct irq_desc *desc) { } | |
538 | #endif | |
539 | ||
328a4978 TG |
540 | static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) |
541 | { | |
542 | if (!(desc->istate & IRQS_ONESHOT)) { | |
543 | chip->irq_eoi(&desc->irq_data); | |
544 | return; | |
545 | } | |
546 | /* | |
547 | * We need to unmask in the following cases: | |
548 | * - Oneshot irq which did not wake the thread (caused by a | |
549 | * spurious interrupt or a primary handler handling it | |
550 | * completely). | |
551 | */ | |
552 | if (!irqd_irq_disabled(&desc->irq_data) && | |
553 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { | |
554 | chip->irq_eoi(&desc->irq_data); | |
555 | unmask_irq(desc); | |
556 | } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { | |
557 | chip->irq_eoi(&desc->irq_data); | |
558 | } | |
559 | } | |
560 | ||
dd87eb3a | 561 | /** |
47c2a3aa | 562 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a | 563 | * @desc: the interrupt description structure for this irq |
dd87eb3a | 564 | * |
47c2a3aa | 565 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
566 | * call when the interrupt has been serviced. This enables support |
567 | * for modern forms of interrupt handlers, which handle the flow | |
568 | * details in hardware, transparently. | |
569 | */ | |
bd0b9ac4 | 570 | void handle_fasteoi_irq(struct irq_desc *desc) |
dd87eb3a | 571 | { |
328a4978 TG |
572 | struct irq_chip *chip = desc->irq_data.chip; |
573 | ||
239007b8 | 574 | raw_spin_lock(&desc->lock); |
dd87eb3a | 575 | |
c7bd3ec0 TG |
576 | if (!irq_may_run(desc)) |
577 | goto out; | |
dd87eb3a | 578 | |
163ef309 | 579 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
dd87eb3a TG |
580 | |
581 | /* | |
582 | * If its disabled or no action available | |
76d21601 | 583 | * then mask it and get out of here: |
dd87eb3a | 584 | */ |
32f4125e | 585 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
2a0d6fb3 | 586 | desc->istate |= IRQS_PENDING; |
e2c0f8ff | 587 | mask_irq(desc); |
dd87eb3a | 588 | goto out; |
98bb244b | 589 | } |
c69e3758 | 590 | |
a946e8c7 | 591 | kstat_incr_irqs_this_cpu(desc); |
c69e3758 TG |
592 | if (desc->istate & IRQS_ONESHOT) |
593 | mask_irq(desc); | |
594 | ||
78129576 | 595 | preflow_handler(desc); |
a7ae4de5 | 596 | handle_irq_event(desc); |
77694b40 | 597 | |
328a4978 | 598 | cond_unmask_eoi_irq(desc, chip); |
ac563761 | 599 | |
239007b8 | 600 | raw_spin_unlock(&desc->lock); |
77694b40 TG |
601 | return; |
602 | out: | |
328a4978 TG |
603 | if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED)) |
604 | chip->irq_eoi(&desc->irq_data); | |
605 | raw_spin_unlock(&desc->lock); | |
dd87eb3a | 606 | } |
7cad45ee | 607 | EXPORT_SYMBOL_GPL(handle_fasteoi_irq); |
dd87eb3a TG |
608 | |
609 | /** | |
610 | * handle_edge_irq - edge type IRQ handler | |
dd87eb3a | 611 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
612 | * |
613 | * Interrupt occures on the falling and/or rising edge of a hardware | |
25985edc | 614 | * signal. The occurrence is latched into the irq controller hardware |
dd87eb3a TG |
615 | * and must be acked in order to be reenabled. After the ack another |
616 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 617 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
618 | * might be necessary to disable (mask) the interrupt depending on the |
619 | * controller hardware. This requires to reenable the interrupt inside | |
620 | * of the loop which handles the interrupts which have arrived while | |
621 | * the handler was running. If all pending interrupts are handled, the | |
622 | * loop is left. | |
623 | */ | |
bd0b9ac4 | 624 | void handle_edge_irq(struct irq_desc *desc) |
dd87eb3a | 625 | { |
239007b8 | 626 | raw_spin_lock(&desc->lock); |
dd87eb3a | 627 | |
163ef309 | 628 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
c3d7acd0 | 629 | |
c7bd3ec0 TG |
630 | if (!irq_may_run(desc)) { |
631 | desc->istate |= IRQS_PENDING; | |
632 | mask_ack_irq(desc); | |
633 | goto out_unlock; | |
dd87eb3a | 634 | } |
c3d7acd0 | 635 | |
dd87eb3a | 636 | /* |
c3d7acd0 TG |
637 | * If its disabled or no action available then mask it and get |
638 | * out of here. | |
dd87eb3a | 639 | */ |
c3d7acd0 TG |
640 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { |
641 | desc->istate |= IRQS_PENDING; | |
642 | mask_ack_irq(desc); | |
643 | goto out_unlock; | |
dd87eb3a | 644 | } |
c3d7acd0 | 645 | |
b51bf95c | 646 | kstat_incr_irqs_this_cpu(desc); |
dd87eb3a TG |
647 | |
648 | /* Start handling the irq */ | |
22a49163 | 649 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a | 650 | |
dd87eb3a | 651 | do { |
a60a5dc2 | 652 | if (unlikely(!desc->action)) { |
e2c0f8ff | 653 | mask_irq(desc); |
dd87eb3a TG |
654 | goto out_unlock; |
655 | } | |
656 | ||
657 | /* | |
658 | * When another irq arrived while we were handling | |
659 | * one, we could have masked the irq. | |
660 | * Renable it, if it was not disabled in meantime. | |
661 | */ | |
2a0d6fb3 | 662 | if (unlikely(desc->istate & IRQS_PENDING)) { |
32f4125e TG |
663 | if (!irqd_irq_disabled(&desc->irq_data) && |
664 | irqd_irq_masked(&desc->irq_data)) | |
c1594b77 | 665 | unmask_irq(desc); |
dd87eb3a TG |
666 | } |
667 | ||
a60a5dc2 | 668 | handle_irq_event(desc); |
dd87eb3a | 669 | |
2a0d6fb3 | 670 | } while ((desc->istate & IRQS_PENDING) && |
32f4125e | 671 | !irqd_irq_disabled(&desc->irq_data)); |
dd87eb3a | 672 | |
dd87eb3a | 673 | out_unlock: |
239007b8 | 674 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 675 | } |
3911ff30 | 676 | EXPORT_SYMBOL(handle_edge_irq); |
dd87eb3a | 677 | |
0521c8fb TG |
678 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER |
679 | /** | |
680 | * handle_edge_eoi_irq - edge eoi type IRQ handler | |
0521c8fb TG |
681 | * @desc: the interrupt description structure for this irq |
682 | * | |
683 | * Similar as the above handle_edge_irq, but using eoi and w/o the | |
684 | * mask/unmask logic. | |
685 | */ | |
bd0b9ac4 | 686 | void handle_edge_eoi_irq(struct irq_desc *desc) |
0521c8fb TG |
687 | { |
688 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
689 | ||
690 | raw_spin_lock(&desc->lock); | |
691 | ||
692 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | |
c3d7acd0 | 693 | |
c7bd3ec0 TG |
694 | if (!irq_may_run(desc)) { |
695 | desc->istate |= IRQS_PENDING; | |
696 | goto out_eoi; | |
0521c8fb | 697 | } |
c3d7acd0 | 698 | |
0521c8fb | 699 | /* |
c3d7acd0 TG |
700 | * If its disabled or no action available then mask it and get |
701 | * out of here. | |
0521c8fb | 702 | */ |
c3d7acd0 TG |
703 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { |
704 | desc->istate |= IRQS_PENDING; | |
705 | goto out_eoi; | |
0521c8fb | 706 | } |
c3d7acd0 | 707 | |
b51bf95c | 708 | kstat_incr_irqs_this_cpu(desc); |
0521c8fb TG |
709 | |
710 | do { | |
711 | if (unlikely(!desc->action)) | |
712 | goto out_eoi; | |
713 | ||
714 | handle_irq_event(desc); | |
715 | ||
716 | } while ((desc->istate & IRQS_PENDING) && | |
717 | !irqd_irq_disabled(&desc->irq_data)); | |
718 | ||
ac0e0447 | 719 | out_eoi: |
0521c8fb TG |
720 | chip->irq_eoi(&desc->irq_data); |
721 | raw_spin_unlock(&desc->lock); | |
722 | } | |
723 | #endif | |
724 | ||
dd87eb3a | 725 | /** |
24b26d42 | 726 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a | 727 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
728 | * |
729 | * Per CPU interrupts on SMP machines without locking requirements | |
730 | */ | |
bd0b9ac4 | 731 | void handle_percpu_irq(struct irq_desc *desc) |
dd87eb3a | 732 | { |
35e857cb | 733 | struct irq_chip *chip = irq_desc_get_chip(desc); |
dd87eb3a | 734 | |
b51bf95c | 735 | kstat_incr_irqs_this_cpu(desc); |
dd87eb3a | 736 | |
849f061c TG |
737 | if (chip->irq_ack) |
738 | chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 739 | |
71f64340 | 740 | handle_irq_event_percpu(desc); |
dd87eb3a | 741 | |
849f061c TG |
742 | if (chip->irq_eoi) |
743 | chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
744 | } |
745 | ||
31d9d9b6 MZ |
746 | /** |
747 | * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids | |
31d9d9b6 MZ |
748 | * @desc: the interrupt description structure for this irq |
749 | * | |
750 | * Per CPU interrupts on SMP machines without locking requirements. Same as | |
751 | * handle_percpu_irq() above but with the following extras: | |
752 | * | |
753 | * action->percpu_dev_id is a pointer to percpu variables which | |
754 | * contain the real device id for the cpu on which this handler is | |
755 | * called | |
756 | */ | |
bd0b9ac4 | 757 | void handle_percpu_devid_irq(struct irq_desc *desc) |
31d9d9b6 MZ |
758 | { |
759 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
760 | struct irqaction *action = desc->action; | |
bd0b9ac4 | 761 | unsigned int irq = irq_desc_get_irq(desc); |
31d9d9b6 MZ |
762 | irqreturn_t res; |
763 | ||
b51bf95c | 764 | kstat_incr_irqs_this_cpu(desc); |
31d9d9b6 MZ |
765 | |
766 | if (chip->irq_ack) | |
767 | chip->irq_ack(&desc->irq_data); | |
768 | ||
fc590c22 TG |
769 | if (likely(action)) { |
770 | trace_irq_handler_entry(irq, action); | |
771 | res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id)); | |
772 | trace_irq_handler_exit(irq, action, res); | |
773 | } else { | |
774 | unsigned int cpu = smp_processor_id(); | |
775 | bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled); | |
776 | ||
777 | if (enabled) | |
778 | irq_percpu_disable(desc, cpu); | |
779 | ||
780 | pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n", | |
781 | enabled ? " and unmasked" : "", irq, cpu); | |
782 | } | |
31d9d9b6 MZ |
783 | |
784 | if (chip->irq_eoi) | |
785 | chip->irq_eoi(&desc->irq_data); | |
786 | } | |
787 | ||
b8129a1f | 788 | static void |
3b0f95be RK |
789 | __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle, |
790 | int is_chained, const char *name) | |
dd87eb3a | 791 | { |
091738a2 | 792 | if (!handle) { |
dd87eb3a | 793 | handle = handle_bad_irq; |
091738a2 | 794 | } else { |
f86eff22 MZ |
795 | struct irq_data *irq_data = &desc->irq_data; |
796 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
797 | /* | |
798 | * With hierarchical domains we might run into a | |
799 | * situation where the outermost chip is not yet set | |
800 | * up, but the inner chips are there. Instead of | |
801 | * bailing we install the handler, but obviously we | |
802 | * cannot enable/startup the interrupt at this point. | |
803 | */ | |
804 | while (irq_data) { | |
805 | if (irq_data->chip != &no_irq_chip) | |
806 | break; | |
807 | /* | |
808 | * Bail out if the outer chip is not set up | |
809 | * and the interrrupt supposed to be started | |
810 | * right away. | |
811 | */ | |
812 | if (WARN_ON(is_chained)) | |
3b0f95be | 813 | return; |
f86eff22 MZ |
814 | /* Try the parent */ |
815 | irq_data = irq_data->parent_data; | |
816 | } | |
817 | #endif | |
818 | if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip)) | |
3b0f95be | 819 | return; |
f8b5473f | 820 | } |
dd87eb3a | 821 | |
dd87eb3a TG |
822 | /* Uninstall? */ |
823 | if (handle == handle_bad_irq) { | |
6b8ff312 | 824 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 825 | mask_ack_irq(desc); |
801a0e9a | 826 | irq_state_set_disabled(desc); |
e509bd7d MW |
827 | if (is_chained) |
828 | desc->action = NULL; | |
dd87eb3a TG |
829 | desc->depth = 1; |
830 | } | |
831 | desc->handle_irq = handle; | |
a460e745 | 832 | desc->name = name; |
dd87eb3a TG |
833 | |
834 | if (handle != handle_bad_irq && is_chained) { | |
1984e075 MZ |
835 | unsigned int type = irqd_get_trigger_type(&desc->irq_data); |
836 | ||
1e12c4a9 MZ |
837 | /* |
838 | * We're about to start this interrupt immediately, | |
839 | * hence the need to set the trigger configuration. | |
840 | * But the .set_type callback may have overridden the | |
841 | * flow handler, ignoring that we're dealing with a | |
842 | * chained interrupt. Reset it immediately because we | |
843 | * do know better. | |
844 | */ | |
1984e075 MZ |
845 | if (type != IRQ_TYPE_NONE) { |
846 | __irq_set_trigger(desc, type); | |
847 | desc->handle_irq = handle; | |
848 | } | |
1e12c4a9 | 849 | |
1ccb4e61 TG |
850 | irq_settings_set_noprobe(desc); |
851 | irq_settings_set_norequest(desc); | |
7f1b1244 | 852 | irq_settings_set_nothread(desc); |
e509bd7d | 853 | desc->action = &chained_action; |
b4bc724e | 854 | irq_startup(desc, true); |
dd87eb3a | 855 | } |
3b0f95be RK |
856 | } |
857 | ||
858 | void | |
859 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, | |
860 | const char *name) | |
861 | { | |
862 | unsigned long flags; | |
863 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); | |
864 | ||
865 | if (!desc) | |
866 | return; | |
867 | ||
868 | __irq_do_set_handler(desc, handle, is_chained, name); | |
02725e74 | 869 | irq_put_desc_busunlock(desc, flags); |
dd87eb3a | 870 | } |
3836ca08 | 871 | EXPORT_SYMBOL_GPL(__irq_set_handler); |
dd87eb3a | 872 | |
3b0f95be RK |
873 | void |
874 | irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, | |
875 | void *data) | |
876 | { | |
877 | unsigned long flags; | |
878 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); | |
879 | ||
880 | if (!desc) | |
881 | return; | |
882 | ||
af7080e0 | 883 | desc->irq_common_data.handler_data = data; |
2c4569ca | 884 | __irq_do_set_handler(desc, handle, 1, NULL); |
3b0f95be RK |
885 | |
886 | irq_put_desc_busunlock(desc, flags); | |
887 | } | |
888 | EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data); | |
889 | ||
dd87eb3a | 890 | void |
3836ca08 | 891 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 | 892 | irq_flow_handler_t handle, const char *name) |
dd87eb3a | 893 | { |
35e857cb | 894 | irq_set_chip(irq, chip); |
3836ca08 | 895 | __irq_set_handler(irq, handle, 0, name); |
dd87eb3a | 896 | } |
b3ae66f2 | 897 | EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name); |
46f4f8f6 | 898 | |
44247184 | 899 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 900 | { |
46f4f8f6 | 901 | unsigned long flags; |
31d9d9b6 | 902 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
46f4f8f6 | 903 | |
44247184 | 904 | if (!desc) |
46f4f8f6 | 905 | return; |
a005677b TG |
906 | irq_settings_clr_and_set(desc, clr, set); |
907 | ||
876dbd4c | 908 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
e1ef8241 | 909 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
a005677b TG |
910 | if (irq_settings_has_no_balance_set(desc)) |
911 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
912 | if (irq_settings_is_per_cpu(desc)) | |
913 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
e1ef8241 TG |
914 | if (irq_settings_can_move_pcntxt(desc)) |
915 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | |
0ef5ca1e TG |
916 | if (irq_settings_is_level(desc)) |
917 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
a005677b | 918 | |
876dbd4c TG |
919 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
920 | ||
02725e74 | 921 | irq_put_desc_unlock(desc, flags); |
46f4f8f6 | 922 | } |
edf76f83 | 923 | EXPORT_SYMBOL_GPL(irq_modify_status); |
0fdb4b25 DD |
924 | |
925 | /** | |
926 | * irq_cpu_online - Invoke all irq_cpu_online functions. | |
927 | * | |
928 | * Iterate through all irqs and invoke the chip.irq_cpu_online() | |
929 | * for each. | |
930 | */ | |
931 | void irq_cpu_online(void) | |
932 | { | |
933 | struct irq_desc *desc; | |
934 | struct irq_chip *chip; | |
935 | unsigned long flags; | |
936 | unsigned int irq; | |
937 | ||
938 | for_each_active_irq(irq) { | |
939 | desc = irq_to_desc(irq); | |
940 | if (!desc) | |
941 | continue; | |
942 | ||
943 | raw_spin_lock_irqsave(&desc->lock, flags); | |
944 | ||
945 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
946 | if (chip && chip->irq_cpu_online && |
947 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 948 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
949 | chip->irq_cpu_online(&desc->irq_data); |
950 | ||
951 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
952 | } | |
953 | } | |
954 | ||
955 | /** | |
956 | * irq_cpu_offline - Invoke all irq_cpu_offline functions. | |
957 | * | |
958 | * Iterate through all irqs and invoke the chip.irq_cpu_offline() | |
959 | * for each. | |
960 | */ | |
961 | void irq_cpu_offline(void) | |
962 | { | |
963 | struct irq_desc *desc; | |
964 | struct irq_chip *chip; | |
965 | unsigned long flags; | |
966 | unsigned int irq; | |
967 | ||
968 | for_each_active_irq(irq) { | |
969 | desc = irq_to_desc(irq); | |
970 | if (!desc) | |
971 | continue; | |
972 | ||
973 | raw_spin_lock_irqsave(&desc->lock, flags); | |
974 | ||
975 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
976 | if (chip && chip->irq_cpu_offline && |
977 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 978 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
979 | chip->irq_cpu_offline(&desc->irq_data); |
980 | ||
981 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
982 | } | |
983 | } | |
85f08c17 JL |
984 | |
985 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
3cfeffc2 SA |
986 | /** |
987 | * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if | |
988 | * NULL) | |
989 | * @data: Pointer to interrupt specific data | |
990 | */ | |
991 | void irq_chip_enable_parent(struct irq_data *data) | |
992 | { | |
993 | data = data->parent_data; | |
994 | if (data->chip->irq_enable) | |
995 | data->chip->irq_enable(data); | |
996 | else | |
997 | data->chip->irq_unmask(data); | |
998 | } | |
999 | ||
1000 | /** | |
1001 | * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if | |
1002 | * NULL) | |
1003 | * @data: Pointer to interrupt specific data | |
1004 | */ | |
1005 | void irq_chip_disable_parent(struct irq_data *data) | |
1006 | { | |
1007 | data = data->parent_data; | |
1008 | if (data->chip->irq_disable) | |
1009 | data->chip->irq_disable(data); | |
1010 | else | |
1011 | data->chip->irq_mask(data); | |
1012 | } | |
1013 | ||
85f08c17 JL |
1014 | /** |
1015 | * irq_chip_ack_parent - Acknowledge the parent interrupt | |
1016 | * @data: Pointer to interrupt specific data | |
1017 | */ | |
1018 | void irq_chip_ack_parent(struct irq_data *data) | |
1019 | { | |
1020 | data = data->parent_data; | |
1021 | data->chip->irq_ack(data); | |
1022 | } | |
a4289dc2 | 1023 | EXPORT_SYMBOL_GPL(irq_chip_ack_parent); |
85f08c17 | 1024 | |
56e8abab YC |
1025 | /** |
1026 | * irq_chip_mask_parent - Mask the parent interrupt | |
1027 | * @data: Pointer to interrupt specific data | |
1028 | */ | |
1029 | void irq_chip_mask_parent(struct irq_data *data) | |
1030 | { | |
1031 | data = data->parent_data; | |
1032 | data->chip->irq_mask(data); | |
1033 | } | |
52b2a05f | 1034 | EXPORT_SYMBOL_GPL(irq_chip_mask_parent); |
56e8abab YC |
1035 | |
1036 | /** | |
1037 | * irq_chip_unmask_parent - Unmask the parent interrupt | |
1038 | * @data: Pointer to interrupt specific data | |
1039 | */ | |
1040 | void irq_chip_unmask_parent(struct irq_data *data) | |
1041 | { | |
1042 | data = data->parent_data; | |
1043 | data->chip->irq_unmask(data); | |
1044 | } | |
52b2a05f | 1045 | EXPORT_SYMBOL_GPL(irq_chip_unmask_parent); |
56e8abab YC |
1046 | |
1047 | /** | |
1048 | * irq_chip_eoi_parent - Invoke EOI on the parent interrupt | |
1049 | * @data: Pointer to interrupt specific data | |
1050 | */ | |
1051 | void irq_chip_eoi_parent(struct irq_data *data) | |
1052 | { | |
1053 | data = data->parent_data; | |
1054 | data->chip->irq_eoi(data); | |
1055 | } | |
52b2a05f | 1056 | EXPORT_SYMBOL_GPL(irq_chip_eoi_parent); |
56e8abab YC |
1057 | |
1058 | /** | |
1059 | * irq_chip_set_affinity_parent - Set affinity on the parent interrupt | |
1060 | * @data: Pointer to interrupt specific data | |
1061 | * @dest: The affinity mask to set | |
1062 | * @force: Flag to enforce setting (disable online checks) | |
1063 | * | |
1064 | * Conditinal, as the underlying parent chip might not implement it. | |
1065 | */ | |
1066 | int irq_chip_set_affinity_parent(struct irq_data *data, | |
1067 | const struct cpumask *dest, bool force) | |
1068 | { | |
1069 | data = data->parent_data; | |
1070 | if (data->chip->irq_set_affinity) | |
1071 | return data->chip->irq_set_affinity(data, dest, force); | |
b7560de1 GS |
1072 | |
1073 | return -ENOSYS; | |
1074 | } | |
1075 | ||
1076 | /** | |
1077 | * irq_chip_set_type_parent - Set IRQ type on the parent interrupt | |
1078 | * @data: Pointer to interrupt specific data | |
1079 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h | |
1080 | * | |
1081 | * Conditional, as the underlying parent chip might not implement it. | |
1082 | */ | |
1083 | int irq_chip_set_type_parent(struct irq_data *data, unsigned int type) | |
1084 | { | |
1085 | data = data->parent_data; | |
1086 | ||
1087 | if (data->chip->irq_set_type) | |
1088 | return data->chip->irq_set_type(data, type); | |
56e8abab YC |
1089 | |
1090 | return -ENOSYS; | |
1091 | } | |
52b2a05f | 1092 | EXPORT_SYMBOL_GPL(irq_chip_set_type_parent); |
56e8abab | 1093 | |
85f08c17 JL |
1094 | /** |
1095 | * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware | |
1096 | * @data: Pointer to interrupt specific data | |
1097 | * | |
1098 | * Iterate through the domain hierarchy of the interrupt and check | |
1099 | * whether a hw retrigger function exists. If yes, invoke it. | |
1100 | */ | |
1101 | int irq_chip_retrigger_hierarchy(struct irq_data *data) | |
1102 | { | |
1103 | for (data = data->parent_data; data; data = data->parent_data) | |
1104 | if (data->chip && data->chip->irq_retrigger) | |
1105 | return data->chip->irq_retrigger(data); | |
1106 | ||
6d4affea | 1107 | return 0; |
85f08c17 | 1108 | } |
08b55e2a | 1109 | |
0a4377de JL |
1110 | /** |
1111 | * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt | |
1112 | * @data: Pointer to interrupt specific data | |
8505a81b | 1113 | * @vcpu_info: The vcpu affinity information |
0a4377de JL |
1114 | */ |
1115 | int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info) | |
1116 | { | |
1117 | data = data->parent_data; | |
1118 | if (data->chip->irq_set_vcpu_affinity) | |
1119 | return data->chip->irq_set_vcpu_affinity(data, vcpu_info); | |
1120 | ||
1121 | return -ENOSYS; | |
1122 | } | |
1123 | ||
08b55e2a MZ |
1124 | /** |
1125 | * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt | |
1126 | * @data: Pointer to interrupt specific data | |
1127 | * @on: Whether to set or reset the wake-up capability of this irq | |
1128 | * | |
1129 | * Conditional, as the underlying parent chip might not implement it. | |
1130 | */ | |
1131 | int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on) | |
1132 | { | |
1133 | data = data->parent_data; | |
1134 | if (data->chip->irq_set_wake) | |
1135 | return data->chip->irq_set_wake(data, on); | |
1136 | ||
1137 | return -ENOSYS; | |
1138 | } | |
85f08c17 | 1139 | #endif |
515085ef JL |
1140 | |
1141 | /** | |
1142 | * irq_chip_compose_msi_msg - Componse msi message for a irq chip | |
1143 | * @data: Pointer to interrupt specific data | |
1144 | * @msg: Pointer to the MSI message | |
1145 | * | |
1146 | * For hierarchical domains we find the first chip in the hierarchy | |
1147 | * which implements the irq_compose_msi_msg callback. For non | |
1148 | * hierarchical we use the top level chip. | |
1149 | */ | |
1150 | int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) | |
1151 | { | |
1152 | struct irq_data *pos = NULL; | |
1153 | ||
1154 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
1155 | for (; data; data = data->parent_data) | |
1156 | #endif | |
1157 | if (data->chip && data->chip->irq_compose_msi_msg) | |
1158 | pos = data; | |
1159 | if (!pos) | |
1160 | return -ENOSYS; | |
1161 | ||
1162 | pos->chip->irq_compose_msi_msg(pos, msg); | |
1163 | ||
1164 | return 0; | |
1165 | } | |
be45beb2 JH |
1166 | |
1167 | /** | |
1168 | * irq_chip_pm_get - Enable power for an IRQ chip | |
1169 | * @data: Pointer to interrupt specific data | |
1170 | * | |
1171 | * Enable the power to the IRQ chip referenced by the interrupt data | |
1172 | * structure. | |
1173 | */ | |
1174 | int irq_chip_pm_get(struct irq_data *data) | |
1175 | { | |
1176 | int retval; | |
1177 | ||
1178 | if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) { | |
1179 | retval = pm_runtime_get_sync(data->chip->parent_device); | |
1180 | if (retval < 0) { | |
1181 | pm_runtime_put_noidle(data->chip->parent_device); | |
1182 | return retval; | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | /** | |
1190 | * irq_chip_pm_put - Disable power for an IRQ chip | |
1191 | * @data: Pointer to interrupt specific data | |
1192 | * | |
1193 | * Disable the power to the IRQ chip referenced by the interrupt data | |
1194 | * structure, belongs. Note that power will only be disabled, once this | |
1195 | * function has been called for all IRQs that have called irq_chip_pm_get(). | |
1196 | */ | |
1197 | int irq_chip_pm_put(struct irq_data *data) | |
1198 | { | |
1199 | int retval = 0; | |
1200 | ||
1201 | if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) | |
1202 | retval = pm_runtime_put(data->chip->parent_device); | |
1203 | ||
1204 | return (retval < 0) ? retval : 0; | |
1205 | } |