pinctrl: at91-pio4: add missing of_node_put
[linux-2.6-block.git] / kernel / irq / chip.c
CommitLineData
52a65ff5 1// SPDX-License-Identifier: GPL-2.0
dd87eb3a 2/*
dd87eb3a
TG
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
5 *
99bfce5d
TG
6 * This file contains the core interrupt handling code, for irq-chip based
7 * architectures. Detailed information is available in
8 * Documentation/core-api/genericirq.rst
dd87eb3a
TG
9 */
10
11#include <linux/irq.h>
7fe3730d 12#include <linux/msi.h>
dd87eb3a
TG
13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/kernel_stat.h>
f8264e34 16#include <linux/irqdomain.h>
dd87eb3a 17
f069686e
SR
18#include <trace/events/irq.h>
19
dd87eb3a
TG
20#include "internals.h"
21
e509bd7d
MW
22static irqreturn_t bad_chained_irq(int irq, void *dev_id)
23{
24 WARN_ONCE(1, "Chained irq %d should not call an action\n", irq);
25 return IRQ_NONE;
26}
27
28/*
29 * Chained handlers should never call action on their IRQ. This default
30 * action will emit warning if such thing happens.
31 */
32struct irqaction chained_action = {
33 .handler = bad_chained_irq,
34};
35
dd87eb3a 36/**
a0cd9ca2 37 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
38 * @irq: irq number
39 * @chip: pointer to irq chip description structure
40 */
a0cd9ca2 41int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 42{
dd87eb3a 43 unsigned long flags;
31d9d9b6 44 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 45
02725e74 46 if (!desc)
dd87eb3a 47 return -EINVAL;
dd87eb3a
TG
48
49 if (!chip)
50 chip = &no_irq_chip;
51
6b8ff312 52 desc->irq_data.chip = chip;
02725e74 53 irq_put_desc_unlock(desc, flags);
d72274e5
DD
54 /*
55 * For !CONFIG_SPARSE_IRQ make the irq show up in
f63b6a05 56 * allocated_irqs.
d72274e5 57 */
f63b6a05 58 irq_mark_irq(irq);
dd87eb3a
TG
59 return 0;
60}
a0cd9ca2 61EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
62
63/**
a0cd9ca2 64 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 65 * @irq: irq number
0c5d1eb7 66 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 67 */
a0cd9ca2 68int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 69{
dd87eb3a 70 unsigned long flags;
31d9d9b6 71 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74 72 int ret = 0;
dd87eb3a 73
02725e74
TG
74 if (!desc)
75 return -EINVAL;
dd87eb3a 76
a1ff541a 77 ret = __irq_set_trigger(desc, type);
02725e74 78 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
79 return ret;
80}
a0cd9ca2 81EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
82
83/**
a0cd9ca2 84 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
85 * @irq: Interrupt number
86 * @data: Pointer to interrupt specific data
87 *
88 * Set the hardware irq controller data for an irq
89 */
a0cd9ca2 90int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 91{
dd87eb3a 92 unsigned long flags;
31d9d9b6 93 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 94
02725e74 95 if (!desc)
dd87eb3a 96 return -EINVAL;
af7080e0 97 desc->irq_common_data.handler_data = data;
02725e74 98 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
99 return 0;
100}
a0cd9ca2 101EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 102
5b912c10 103/**
51906e77
AG
104 * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
105 * @irq_base: Interrupt number base
106 * @irq_offset: Interrupt number offset
107 * @entry: Pointer to MSI descriptor data
5b912c10 108 *
51906e77 109 * Set the MSI descriptor entry for an irq at offset
5b912c10 110 */
51906e77
AG
111int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
112 struct msi_desc *entry)
5b912c10 113{
5b912c10 114 unsigned long flags;
51906e77 115 struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
5b912c10 116
02725e74 117 if (!desc)
5b912c10 118 return -EINVAL;
b237721c 119 desc->irq_common_data.msi_desc = entry;
51906e77
AG
120 if (entry && !irq_offset)
121 entry->irq = irq_base;
02725e74 122 irq_put_desc_unlock(desc, flags);
5b912c10
EB
123 return 0;
124}
125
51906e77
AG
126/**
127 * irq_set_msi_desc - set MSI descriptor data for an irq
128 * @irq: Interrupt number
129 * @entry: Pointer to MSI descriptor data
130 *
131 * Set the MSI descriptor entry for an irq
132 */
133int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
134{
135 return irq_set_msi_desc_off(irq, 0, entry);
136}
137
dd87eb3a 138/**
a0cd9ca2 139 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
140 * @irq: Interrupt number
141 * @data: Pointer to chip specific data
142 *
143 * Set the hardware irq chip data for an irq
144 */
a0cd9ca2 145int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 146{
dd87eb3a 147 unsigned long flags;
31d9d9b6 148 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 149
02725e74 150 if (!desc)
dd87eb3a 151 return -EINVAL;
6b8ff312 152 desc->irq_data.chip_data = data;
02725e74 153 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
154 return 0;
155}
a0cd9ca2 156EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 157
f303a6dd
TG
158struct irq_data *irq_get_irq_data(unsigned int irq)
159{
160 struct irq_desc *desc = irq_to_desc(irq);
161
162 return desc ? &desc->irq_data : NULL;
163}
164EXPORT_SYMBOL_GPL(irq_get_irq_data);
165
c1594b77
TG
166static void irq_state_clr_disabled(struct irq_desc *desc)
167{
801a0e9a 168 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
169}
170
6e40262e
TG
171static void irq_state_clr_masked(struct irq_desc *desc)
172{
32f4125e 173 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
174}
175
201d7f47
TG
176static void irq_state_clr_started(struct irq_desc *desc)
177{
178 irqd_clear(&desc->irq_data, IRQD_IRQ_STARTED);
179}
180
181static void irq_state_set_started(struct irq_desc *desc)
182{
183 irqd_set(&desc->irq_data, IRQD_IRQ_STARTED);
184}
185
761ea388
TG
186enum {
187 IRQ_STARTUP_NORMAL,
188 IRQ_STARTUP_MANAGED,
189 IRQ_STARTUP_ABORT,
190};
191
192#ifdef CONFIG_SMP
193static int
194__irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force)
195{
196 struct irq_data *d = irq_desc_get_irq_data(desc);
197
198 if (!irqd_affinity_is_managed(d))
199 return IRQ_STARTUP_NORMAL;
200
201 irqd_clr_managed_shutdown(d);
202
9cb067ef 203 if (cpumask_any_and(aff, cpu_online_mask) >= nr_cpu_ids) {
761ea388
TG
204 /*
205 * Catch code which fiddles with enable_irq() on a managed
206 * and potentially shutdown IRQ. Chained interrupt
207 * installment or irq auto probing should not happen on
c942cee4 208 * managed irqs either.
761ea388
TG
209 */
210 if (WARN_ON_ONCE(force))
c942cee4 211 return IRQ_STARTUP_ABORT;
761ea388
TG
212 /*
213 * The interrupt was requested, but there is no online CPU
214 * in it's affinity mask. Put it into managed shutdown
215 * state and let the cpu hotplug mechanism start it up once
216 * a CPU in the mask becomes available.
217 */
761ea388
TG
218 return IRQ_STARTUP_ABORT;
219 }
bb9b428a
TG
220 /*
221 * Managed interrupts have reserved resources, so this should not
222 * happen.
223 */
42e1cc2d 224 if (WARN_ON(irq_domain_activate_irq(d, false)))
bb9b428a 225 return IRQ_STARTUP_ABORT;
761ea388
TG
226 return IRQ_STARTUP_MANAGED;
227}
228#else
2372a519 229static __always_inline int
761ea388
TG
230__irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force)
231{
232 return IRQ_STARTUP_NORMAL;
233}
234#endif
235
708d174b
TG
236static int __irq_startup(struct irq_desc *desc)
237{
238 struct irq_data *d = irq_desc_get_irq_data(desc);
239 int ret = 0;
240
c942cee4
TG
241 /* Warn if this interrupt is not activated but try nevertheless */
242 WARN_ON_ONCE(!irqd_is_activated(d));
243
708d174b
TG
244 if (d->chip->irq_startup) {
245 ret = d->chip->irq_startup(d);
246 irq_state_clr_disabled(desc);
247 irq_state_clr_masked(desc);
248 } else {
249 irq_enable(desc);
250 }
251 irq_state_set_started(desc);
252 return ret;
253}
254
4cde9c6b 255int irq_startup(struct irq_desc *desc, bool resend, bool force)
46999238 256{
761ea388
TG
257 struct irq_data *d = irq_desc_get_irq_data(desc);
258 struct cpumask *aff = irq_data_get_affinity_mask(d);
b4bc724e
TG
259 int ret = 0;
260
46999238
TG
261 desc->depth = 0;
262
761ea388 263 if (irqd_is_started(d)) {
b4bc724e 264 irq_enable(desc);
201d7f47 265 } else {
761ea388
TG
266 switch (__irq_startup_managed(desc, aff, force)) {
267 case IRQ_STARTUP_NORMAL:
268 ret = __irq_startup(desc);
269 irq_setup_affinity(desc);
270 break;
271 case IRQ_STARTUP_MANAGED:
e43b3b58 272 irq_do_set_affinity(d, aff, false);
761ea388 273 ret = __irq_startup(desc);
761ea388
TG
274 break;
275 case IRQ_STARTUP_ABORT:
c942cee4 276 irqd_set_managed_shutdown(d);
761ea388
TG
277 return 0;
278 }
3aae994f 279 }
b4bc724e 280 if (resend)
0798abeb 281 check_irq_resend(desc);
201d7f47 282
b4bc724e 283 return ret;
46999238
TG
284}
285
c942cee4
TG
286int irq_activate(struct irq_desc *desc)
287{
288 struct irq_data *d = irq_desc_get_irq_data(desc);
289
290 if (!irqd_affinity_is_managed(d))
42e1cc2d 291 return irq_domain_activate_irq(d, false);
c942cee4
TG
292 return 0;
293}
294
1beaeacd 295int irq_activate_and_startup(struct irq_desc *desc, bool resend)
c942cee4
TG
296{
297 if (WARN_ON(irq_activate(desc)))
1beaeacd
TG
298 return 0;
299 return irq_startup(desc, resend, IRQ_START_FORCE);
c942cee4
TG
300}
301
201d7f47
TG
302static void __irq_disable(struct irq_desc *desc, bool mask);
303
46999238
TG
304void irq_shutdown(struct irq_desc *desc)
305{
201d7f47
TG
306 if (irqd_is_started(&desc->irq_data)) {
307 desc->depth = 1;
308 if (desc->irq_data.chip->irq_shutdown) {
309 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
310 irq_state_set_disabled(desc);
311 irq_state_set_masked(desc);
312 } else {
313 __irq_disable(desc, true);
314 }
315 irq_state_clr_started(desc);
316 }
317 /*
318 * This must be called even if the interrupt was never started up,
319 * because the activation can happen before the interrupt is
320 * available for request/startup. It has it's own state tracking so
321 * it's safe to call it unconditionally.
322 */
f8264e34 323 irq_domain_deactivate_irq(&desc->irq_data);
46999238
TG
324}
325
87923470
TG
326void irq_enable(struct irq_desc *desc)
327{
bf22ff45
JC
328 if (!irqd_irq_disabled(&desc->irq_data)) {
329 unmask_irq(desc);
330 } else {
331 irq_state_clr_disabled(desc);
332 if (desc->irq_data.chip->irq_enable) {
333 desc->irq_data.chip->irq_enable(&desc->irq_data);
334 irq_state_clr_masked(desc);
335 } else {
336 unmask_irq(desc);
337 }
338 }
dd87eb3a
TG
339}
340
201d7f47
TG
341static void __irq_disable(struct irq_desc *desc, bool mask)
342{
bf22ff45
JC
343 if (irqd_irq_disabled(&desc->irq_data)) {
344 if (mask)
345 mask_irq(desc);
346 } else {
347 irq_state_set_disabled(desc);
348 if (desc->irq_data.chip->irq_disable) {
349 desc->irq_data.chip->irq_disable(&desc->irq_data);
350 irq_state_set_masked(desc);
351 } else if (mask) {
352 mask_irq(desc);
353 }
201d7f47
TG
354 }
355}
356
d671a605 357/**
f788e7bf 358 * irq_disable - Mark interrupt disabled
d671a605
AF
359 * @desc: irq descriptor which should be disabled
360 *
361 * If the chip does not implement the irq_disable callback, we
362 * use a lazy disable approach. That means we mark the interrupt
363 * disabled, but leave the hardware unmasked. That's an
364 * optimization because we avoid the hardware access for the
365 * common case where no interrupt happens after we marked it
366 * disabled. If an interrupt happens, then the interrupt flow
367 * handler masks the line at the hardware level and marks it
368 * pending.
e9849777
TG
369 *
370 * If the interrupt chip does not implement the irq_disable callback,
371 * a driver can disable the lazy approach for a particular irq line by
372 * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can
373 * be used for devices which cannot disable the interrupt at the
374 * device level under certain circumstances and have to use
375 * disable_irq[_nosync] instead.
d671a605 376 */
50f7c032 377void irq_disable(struct irq_desc *desc)
89d694b9 378{
201d7f47 379 __irq_disable(desc, irq_settings_disable_unlazy(desc));
89d694b9
TG
380}
381
31d9d9b6
MZ
382void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
383{
384 if (desc->irq_data.chip->irq_enable)
385 desc->irq_data.chip->irq_enable(&desc->irq_data);
386 else
387 desc->irq_data.chip->irq_unmask(&desc->irq_data);
388 cpumask_set_cpu(cpu, desc->percpu_enabled);
389}
390
391void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
392{
393 if (desc->irq_data.chip->irq_disable)
394 desc->irq_data.chip->irq_disable(&desc->irq_data);
395 else
396 desc->irq_data.chip->irq_mask(&desc->irq_data);
397 cpumask_clear_cpu(cpu, desc->percpu_enabled);
398}
399
9205e31d 400static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 401{
bf22ff45 402 if (desc->irq_data.chip->irq_mask_ack) {
9205e31d 403 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
bf22ff45
JC
404 irq_state_set_masked(desc);
405 } else {
406 mask_irq(desc);
22a49163
TG
407 if (desc->irq_data.chip->irq_ack)
408 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 409 }
0b1adaa0
TG
410}
411
d4d5e089 412void mask_irq(struct irq_desc *desc)
0b1adaa0 413{
bf22ff45
JC
414 if (irqd_irq_masked(&desc->irq_data))
415 return;
416
e2c0f8ff
TG
417 if (desc->irq_data.chip->irq_mask) {
418 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 419 irq_state_set_masked(desc);
0b1adaa0
TG
420 }
421}
422
d4d5e089 423void unmask_irq(struct irq_desc *desc)
0b1adaa0 424{
bf22ff45
JC
425 if (!irqd_irq_masked(&desc->irq_data))
426 return;
427
0eda58b7
TG
428 if (desc->irq_data.chip->irq_unmask) {
429 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 430 irq_state_clr_masked(desc);
0b1adaa0 431 }
dd87eb3a
TG
432}
433
328a4978
TG
434void unmask_threaded_irq(struct irq_desc *desc)
435{
436 struct irq_chip *chip = desc->irq_data.chip;
437
438 if (chip->flags & IRQCHIP_EOI_THREADED)
439 chip->irq_eoi(&desc->irq_data);
440
bf22ff45 441 unmask_irq(desc);
328a4978
TG
442}
443
399b5da2
TG
444/*
445 * handle_nested_irq - Handle a nested irq from a irq thread
446 * @irq: the interrupt number
447 *
448 * Handle interrupts which are nested into a threaded interrupt
449 * handler. The handler function is called inside the calling
450 * threads context.
451 */
452void handle_nested_irq(unsigned int irq)
453{
454 struct irq_desc *desc = irq_to_desc(irq);
455 struct irqaction *action;
456 irqreturn_t action_ret;
457
458 might_sleep();
459
239007b8 460 raw_spin_lock_irq(&desc->lock);
399b5da2 461
293a7a0a 462 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
399b5da2
TG
463
464 action = desc->action;
23812b9d
NJ
465 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
466 desc->istate |= IRQS_PENDING;
399b5da2 467 goto out_unlock;
23812b9d 468 }
399b5da2 469
a946e8c7 470 kstat_incr_irqs_this_cpu(desc);
32f4125e 471 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 472 raw_spin_unlock_irq(&desc->lock);
399b5da2 473
45e52022
CK
474 action_ret = IRQ_NONE;
475 for_each_action_of_desc(desc, action)
476 action_ret |= action->thread_fn(action->irq, action->dev_id);
477
399b5da2 478 if (!noirqdebug)
0dcdbc97 479 note_interrupt(desc, action_ret);
399b5da2 480
239007b8 481 raw_spin_lock_irq(&desc->lock);
32f4125e 482 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
483
484out_unlock:
239007b8 485 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
486}
487EXPORT_SYMBOL_GPL(handle_nested_irq);
488
fe200ae4
TG
489static bool irq_check_poll(struct irq_desc *desc)
490{
6954b75b 491 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
492 return false;
493 return irq_wait_for_poll(desc);
494}
495
c7bd3ec0
TG
496static bool irq_may_run(struct irq_desc *desc)
497{
9ce7a258
TG
498 unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
499
500 /*
501 * If the interrupt is not in progress and is not an armed
502 * wakeup interrupt, proceed.
503 */
504 if (!irqd_has_set(&desc->irq_data, mask))
c7bd3ec0 505 return true;
9ce7a258
TG
506
507 /*
508 * If the interrupt is an armed wakeup source, mark it pending
509 * and suspended, disable it and notify the pm core about the
510 * event.
511 */
512 if (irq_pm_check_wakeup(desc))
513 return false;
514
515 /*
516 * Handle a potential concurrent poll on a different core.
517 */
c7bd3ec0
TG
518 return irq_check_poll(desc);
519}
520
dd87eb3a
TG
521/**
522 * handle_simple_irq - Simple and software-decoded IRQs.
dd87eb3a 523 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
524 *
525 * Simple interrupts are either sent from a demultiplexing interrupt
526 * handler or come from hardware, where no interrupt hardware control
527 * is necessary.
528 *
529 * Note: The caller is expected to handle the ack, clear, mask and
530 * unmask issues if necessary.
531 */
bd0b9ac4 532void handle_simple_irq(struct irq_desc *desc)
dd87eb3a 533{
239007b8 534 raw_spin_lock(&desc->lock);
dd87eb3a 535
c7bd3ec0
TG
536 if (!irq_may_run(desc))
537 goto out_unlock;
fe200ae4 538
163ef309 539 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a 540
23812b9d
NJ
541 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
542 desc->istate |= IRQS_PENDING;
dd87eb3a 543 goto out_unlock;
23812b9d 544 }
dd87eb3a 545
a946e8c7 546 kstat_incr_irqs_this_cpu(desc);
107781e7 547 handle_irq_event(desc);
dd87eb3a 548
dd87eb3a 549out_unlock:
239007b8 550 raw_spin_unlock(&desc->lock);
dd87eb3a 551}
edf76f83 552EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a 553
edd14cfe
KB
554/**
555 * handle_untracked_irq - Simple and software-decoded IRQs.
556 * @desc: the interrupt description structure for this irq
557 *
558 * Untracked interrupts are sent from a demultiplexing interrupt
559 * handler when the demultiplexer does not know which device it its
560 * multiplexed irq domain generated the interrupt. IRQ's handled
561 * through here are not subjected to stats tracking, randomness, or
562 * spurious interrupt detection.
563 *
564 * Note: Like handle_simple_irq, the caller is expected to handle
565 * the ack, clear, mask and unmask issues if necessary.
566 */
567void handle_untracked_irq(struct irq_desc *desc)
568{
569 unsigned int flags = 0;
570
571 raw_spin_lock(&desc->lock);
572
573 if (!irq_may_run(desc))
574 goto out_unlock;
575
576 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
577
578 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
579 desc->istate |= IRQS_PENDING;
580 goto out_unlock;
581 }
582
583 desc->istate &= ~IRQS_PENDING;
584 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
585 raw_spin_unlock(&desc->lock);
586
587 __handle_irq_event_percpu(desc, &flags);
588
589 raw_spin_lock(&desc->lock);
590 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
591
592out_unlock:
593 raw_spin_unlock(&desc->lock);
594}
595EXPORT_SYMBOL_GPL(handle_untracked_irq);
596
ac563761
TG
597/*
598 * Called unconditionally from handle_level_irq() and only for oneshot
599 * interrupts from handle_fasteoi_irq()
600 */
601static void cond_unmask_irq(struct irq_desc *desc)
602{
603 /*
604 * We need to unmask in the following cases:
605 * - Standard level irq (IRQF_ONESHOT is not set)
606 * - Oneshot irq which did not wake the thread (caused by a
607 * spurious interrupt or a primary handler handling it
608 * completely).
609 */
610 if (!irqd_irq_disabled(&desc->irq_data) &&
611 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
612 unmask_irq(desc);
613}
614
dd87eb3a
TG
615/**
616 * handle_level_irq - Level type irq handler
dd87eb3a 617 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
618 *
619 * Level type interrupts are active as long as the hardware line has
620 * the active level. This may require to mask the interrupt and unmask
621 * it after the associated handler has acknowledged the device, so the
622 * interrupt line is back to inactive.
623 */
bd0b9ac4 624void handle_level_irq(struct irq_desc *desc)
dd87eb3a 625{
239007b8 626 raw_spin_lock(&desc->lock);
9205e31d 627 mask_ack_irq(desc);
dd87eb3a 628
c7bd3ec0
TG
629 if (!irq_may_run(desc))
630 goto out_unlock;
fe200ae4 631
163ef309 632 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
633
634 /*
635 * If its disabled or no action available
636 * keep it masked and get out of here
637 */
d4dc0f90
TG
638 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
639 desc->istate |= IRQS_PENDING;
86998aa6 640 goto out_unlock;
d4dc0f90 641 }
dd87eb3a 642
a946e8c7 643 kstat_incr_irqs_this_cpu(desc);
1529866c 644 handle_irq_event(desc);
b25c340c 645
ac563761
TG
646 cond_unmask_irq(desc);
647
86998aa6 648out_unlock:
239007b8 649 raw_spin_unlock(&desc->lock);
dd87eb3a 650}
14819ea1 651EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 652
78129576
TG
653#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
654static inline void preflow_handler(struct irq_desc *desc)
655{
656 if (desc->preflow_handler)
657 desc->preflow_handler(&desc->irq_data);
658}
659#else
660static inline void preflow_handler(struct irq_desc *desc) { }
661#endif
662
328a4978
TG
663static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
664{
665 if (!(desc->istate & IRQS_ONESHOT)) {
666 chip->irq_eoi(&desc->irq_data);
667 return;
668 }
669 /*
670 * We need to unmask in the following cases:
671 * - Oneshot irq which did not wake the thread (caused by a
672 * spurious interrupt or a primary handler handling it
673 * completely).
674 */
675 if (!irqd_irq_disabled(&desc->irq_data) &&
676 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
677 chip->irq_eoi(&desc->irq_data);
678 unmask_irq(desc);
679 } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
680 chip->irq_eoi(&desc->irq_data);
681 }
682}
683
dd87eb3a 684/**
47c2a3aa 685 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a 686 * @desc: the interrupt description structure for this irq
dd87eb3a 687 *
47c2a3aa 688 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
689 * call when the interrupt has been serviced. This enables support
690 * for modern forms of interrupt handlers, which handle the flow
691 * details in hardware, transparently.
692 */
bd0b9ac4 693void handle_fasteoi_irq(struct irq_desc *desc)
dd87eb3a 694{
328a4978
TG
695 struct irq_chip *chip = desc->irq_data.chip;
696
239007b8 697 raw_spin_lock(&desc->lock);
dd87eb3a 698
c7bd3ec0
TG
699 if (!irq_may_run(desc))
700 goto out;
dd87eb3a 701
163ef309 702 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
703
704 /*
705 * If its disabled or no action available
76d21601 706 * then mask it and get out of here:
dd87eb3a 707 */
32f4125e 708 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 709 desc->istate |= IRQS_PENDING;
e2c0f8ff 710 mask_irq(desc);
dd87eb3a 711 goto out;
98bb244b 712 }
c69e3758 713
a946e8c7 714 kstat_incr_irqs_this_cpu(desc);
c69e3758
TG
715 if (desc->istate & IRQS_ONESHOT)
716 mask_irq(desc);
717
78129576 718 preflow_handler(desc);
a7ae4de5 719 handle_irq_event(desc);
77694b40 720
328a4978 721 cond_unmask_eoi_irq(desc, chip);
ac563761 722
239007b8 723 raw_spin_unlock(&desc->lock);
77694b40
TG
724 return;
725out:
328a4978
TG
726 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
727 chip->irq_eoi(&desc->irq_data);
728 raw_spin_unlock(&desc->lock);
dd87eb3a 729}
7cad45ee 730EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
dd87eb3a
TG
731
732/**
733 * handle_edge_irq - edge type IRQ handler
dd87eb3a 734 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
735 *
736 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 737 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
738 * and must be acked in order to be reenabled. After the ack another
739 * interrupt can happen on the same source even before the first one
dfff0615 740 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
741 * might be necessary to disable (mask) the interrupt depending on the
742 * controller hardware. This requires to reenable the interrupt inside
743 * of the loop which handles the interrupts which have arrived while
744 * the handler was running. If all pending interrupts are handled, the
745 * loop is left.
746 */
bd0b9ac4 747void handle_edge_irq(struct irq_desc *desc)
dd87eb3a 748{
239007b8 749 raw_spin_lock(&desc->lock);
dd87eb3a 750
163ef309 751 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 752
c7bd3ec0
TG
753 if (!irq_may_run(desc)) {
754 desc->istate |= IRQS_PENDING;
755 mask_ack_irq(desc);
756 goto out_unlock;
dd87eb3a 757 }
c3d7acd0 758
dd87eb3a 759 /*
c3d7acd0
TG
760 * If its disabled or no action available then mask it and get
761 * out of here.
dd87eb3a 762 */
c3d7acd0
TG
763 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
764 desc->istate |= IRQS_PENDING;
765 mask_ack_irq(desc);
766 goto out_unlock;
dd87eb3a 767 }
c3d7acd0 768
b51bf95c 769 kstat_incr_irqs_this_cpu(desc);
dd87eb3a
TG
770
771 /* Start handling the irq */
22a49163 772 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 773
dd87eb3a 774 do {
a60a5dc2 775 if (unlikely(!desc->action)) {
e2c0f8ff 776 mask_irq(desc);
dd87eb3a
TG
777 goto out_unlock;
778 }
779
780 /*
781 * When another irq arrived while we were handling
782 * one, we could have masked the irq.
783 * Renable it, if it was not disabled in meantime.
784 */
2a0d6fb3 785 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
786 if (!irqd_irq_disabled(&desc->irq_data) &&
787 irqd_irq_masked(&desc->irq_data))
c1594b77 788 unmask_irq(desc);
dd87eb3a
TG
789 }
790
a60a5dc2 791 handle_irq_event(desc);
dd87eb3a 792
2a0d6fb3 793 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 794 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 795
dd87eb3a 796out_unlock:
239007b8 797 raw_spin_unlock(&desc->lock);
dd87eb3a 798}
3911ff30 799EXPORT_SYMBOL(handle_edge_irq);
dd87eb3a 800
0521c8fb
TG
801#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
802/**
803 * handle_edge_eoi_irq - edge eoi type IRQ handler
0521c8fb
TG
804 * @desc: the interrupt description structure for this irq
805 *
806 * Similar as the above handle_edge_irq, but using eoi and w/o the
807 * mask/unmask logic.
808 */
bd0b9ac4 809void handle_edge_eoi_irq(struct irq_desc *desc)
0521c8fb
TG
810{
811 struct irq_chip *chip = irq_desc_get_chip(desc);
812
813 raw_spin_lock(&desc->lock);
814
815 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 816
c7bd3ec0
TG
817 if (!irq_may_run(desc)) {
818 desc->istate |= IRQS_PENDING;
819 goto out_eoi;
0521c8fb 820 }
c3d7acd0 821
0521c8fb 822 /*
c3d7acd0
TG
823 * If its disabled or no action available then mask it and get
824 * out of here.
0521c8fb 825 */
c3d7acd0
TG
826 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
827 desc->istate |= IRQS_PENDING;
828 goto out_eoi;
0521c8fb 829 }
c3d7acd0 830
b51bf95c 831 kstat_incr_irqs_this_cpu(desc);
0521c8fb
TG
832
833 do {
834 if (unlikely(!desc->action))
835 goto out_eoi;
836
837 handle_irq_event(desc);
838
839 } while ((desc->istate & IRQS_PENDING) &&
840 !irqd_irq_disabled(&desc->irq_data));
841
ac0e0447 842out_eoi:
0521c8fb
TG
843 chip->irq_eoi(&desc->irq_data);
844 raw_spin_unlock(&desc->lock);
845}
846#endif
847
dd87eb3a 848/**
24b26d42 849 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a 850 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
851 *
852 * Per CPU interrupts on SMP machines without locking requirements
853 */
bd0b9ac4 854void handle_percpu_irq(struct irq_desc *desc)
dd87eb3a 855{
35e857cb 856 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 857
b51bf95c 858 kstat_incr_irqs_this_cpu(desc);
dd87eb3a 859
849f061c
TG
860 if (chip->irq_ack)
861 chip->irq_ack(&desc->irq_data);
dd87eb3a 862
71f64340 863 handle_irq_event_percpu(desc);
dd87eb3a 864
849f061c
TG
865 if (chip->irq_eoi)
866 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
867}
868
31d9d9b6
MZ
869/**
870 * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
31d9d9b6
MZ
871 * @desc: the interrupt description structure for this irq
872 *
873 * Per CPU interrupts on SMP machines without locking requirements. Same as
874 * handle_percpu_irq() above but with the following extras:
875 *
876 * action->percpu_dev_id is a pointer to percpu variables which
877 * contain the real device id for the cpu on which this handler is
878 * called
879 */
bd0b9ac4 880void handle_percpu_devid_irq(struct irq_desc *desc)
31d9d9b6
MZ
881{
882 struct irq_chip *chip = irq_desc_get_chip(desc);
883 struct irqaction *action = desc->action;
bd0b9ac4 884 unsigned int irq = irq_desc_get_irq(desc);
31d9d9b6
MZ
885 irqreturn_t res;
886
b51bf95c 887 kstat_incr_irqs_this_cpu(desc);
31d9d9b6
MZ
888
889 if (chip->irq_ack)
890 chip->irq_ack(&desc->irq_data);
891
fc590c22
TG
892 if (likely(action)) {
893 trace_irq_handler_entry(irq, action);
894 res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
895 trace_irq_handler_exit(irq, action, res);
896 } else {
897 unsigned int cpu = smp_processor_id();
898 bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled);
899
900 if (enabled)
901 irq_percpu_disable(desc, cpu);
902
903 pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n",
904 enabled ? " and unmasked" : "", irq, cpu);
905 }
31d9d9b6
MZ
906
907 if (chip->irq_eoi)
908 chip->irq_eoi(&desc->irq_data);
909}
910
b8129a1f 911static void
3b0f95be
RK
912__irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
913 int is_chained, const char *name)
dd87eb3a 914{
091738a2 915 if (!handle) {
dd87eb3a 916 handle = handle_bad_irq;
091738a2 917 } else {
f86eff22
MZ
918 struct irq_data *irq_data = &desc->irq_data;
919#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
920 /*
921 * With hierarchical domains we might run into a
922 * situation where the outermost chip is not yet set
923 * up, but the inner chips are there. Instead of
924 * bailing we install the handler, but obviously we
925 * cannot enable/startup the interrupt at this point.
926 */
927 while (irq_data) {
928 if (irq_data->chip != &no_irq_chip)
929 break;
930 /*
931 * Bail out if the outer chip is not set up
932 * and the interrrupt supposed to be started
933 * right away.
934 */
935 if (WARN_ON(is_chained))
3b0f95be 936 return;
f86eff22
MZ
937 /* Try the parent */
938 irq_data = irq_data->parent_data;
939 }
940#endif
941 if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip))
3b0f95be 942 return;
f8b5473f 943 }
dd87eb3a 944
dd87eb3a
TG
945 /* Uninstall? */
946 if (handle == handle_bad_irq) {
6b8ff312 947 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 948 mask_ack_irq(desc);
801a0e9a 949 irq_state_set_disabled(desc);
e509bd7d
MW
950 if (is_chained)
951 desc->action = NULL;
dd87eb3a
TG
952 desc->depth = 1;
953 }
954 desc->handle_irq = handle;
a460e745 955 desc->name = name;
dd87eb3a
TG
956
957 if (handle != handle_bad_irq && is_chained) {
1984e075
MZ
958 unsigned int type = irqd_get_trigger_type(&desc->irq_data);
959
1e12c4a9
MZ
960 /*
961 * We're about to start this interrupt immediately,
962 * hence the need to set the trigger configuration.
963 * But the .set_type callback may have overridden the
964 * flow handler, ignoring that we're dealing with a
965 * chained interrupt. Reset it immediately because we
966 * do know better.
967 */
1984e075
MZ
968 if (type != IRQ_TYPE_NONE) {
969 __irq_set_trigger(desc, type);
970 desc->handle_irq = handle;
971 }
1e12c4a9 972
1ccb4e61
TG
973 irq_settings_set_noprobe(desc);
974 irq_settings_set_norequest(desc);
7f1b1244 975 irq_settings_set_nothread(desc);
e509bd7d 976 desc->action = &chained_action;
c942cee4 977 irq_activate_and_startup(desc, IRQ_RESEND);
dd87eb3a 978 }
3b0f95be
RK
979}
980
981void
982__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
983 const char *name)
984{
985 unsigned long flags;
986 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
987
988 if (!desc)
989 return;
990
991 __irq_do_set_handler(desc, handle, is_chained, name);
02725e74 992 irq_put_desc_busunlock(desc, flags);
dd87eb3a 993}
3836ca08 994EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a 995
3b0f95be
RK
996void
997irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
998 void *data)
999{
1000 unsigned long flags;
1001 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
1002
1003 if (!desc)
1004 return;
1005
af7080e0 1006 desc->irq_common_data.handler_data = data;
2c4569ca 1007 __irq_do_set_handler(desc, handle, 1, NULL);
3b0f95be
RK
1008
1009 irq_put_desc_busunlock(desc, flags);
1010}
1011EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data);
1012
dd87eb3a 1013void
3836ca08 1014irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 1015 irq_flow_handler_t handle, const char *name)
dd87eb3a 1016{
35e857cb 1017 irq_set_chip(irq, chip);
3836ca08 1018 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 1019}
b3ae66f2 1020EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
46f4f8f6 1021
44247184 1022void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 1023{
e8f24189 1024 unsigned long flags, trigger, tmp;
31d9d9b6 1025 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
46f4f8f6 1026
44247184 1027 if (!desc)
46f4f8f6 1028 return;
04c848d3
TG
1029
1030 /*
1031 * Warn when a driver sets the no autoenable flag on an already
1032 * active interrupt.
1033 */
1034 WARN_ON_ONCE(!desc->depth && (set & _IRQ_NOAUTOEN));
1035
a005677b
TG
1036 irq_settings_clr_and_set(desc, clr, set);
1037
e8f24189
MZ
1038 trigger = irqd_get_trigger_type(&desc->irq_data);
1039
876dbd4c 1040 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 1041 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
1042 if (irq_settings_has_no_balance_set(desc))
1043 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
1044 if (irq_settings_is_per_cpu(desc))
1045 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
1046 if (irq_settings_can_move_pcntxt(desc))
1047 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
1048 if (irq_settings_is_level(desc))
1049 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 1050
e8f24189
MZ
1051 tmp = irq_settings_get_trigger_mask(desc);
1052 if (tmp != IRQ_TYPE_NONE)
1053 trigger = tmp;
1054
1055 irqd_set(&desc->irq_data, trigger);
876dbd4c 1056
02725e74 1057 irq_put_desc_unlock(desc, flags);
46f4f8f6 1058}
edf76f83 1059EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
1060
1061/**
1062 * irq_cpu_online - Invoke all irq_cpu_online functions.
1063 *
1064 * Iterate through all irqs and invoke the chip.irq_cpu_online()
1065 * for each.
1066 */
1067void irq_cpu_online(void)
1068{
1069 struct irq_desc *desc;
1070 struct irq_chip *chip;
1071 unsigned long flags;
1072 unsigned int irq;
1073
1074 for_each_active_irq(irq) {
1075 desc = irq_to_desc(irq);
1076 if (!desc)
1077 continue;
1078
1079 raw_spin_lock_irqsave(&desc->lock, flags);
1080
1081 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
1082 if (chip && chip->irq_cpu_online &&
1083 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 1084 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
1085 chip->irq_cpu_online(&desc->irq_data);
1086
1087 raw_spin_unlock_irqrestore(&desc->lock, flags);
1088 }
1089}
1090
1091/**
1092 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
1093 *
1094 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
1095 * for each.
1096 */
1097void irq_cpu_offline(void)
1098{
1099 struct irq_desc *desc;
1100 struct irq_chip *chip;
1101 unsigned long flags;
1102 unsigned int irq;
1103
1104 for_each_active_irq(irq) {
1105 desc = irq_to_desc(irq);
1106 if (!desc)
1107 continue;
1108
1109 raw_spin_lock_irqsave(&desc->lock, flags);
1110
1111 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
1112 if (chip && chip->irq_cpu_offline &&
1113 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 1114 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
1115 chip->irq_cpu_offline(&desc->irq_data);
1116
1117 raw_spin_unlock_irqrestore(&desc->lock, flags);
1118 }
1119}
85f08c17
JL
1120
1121#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
7703b08c
DD
1122
1123#ifdef CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS
1124/**
1125 * handle_fasteoi_ack_irq - irq handler for edge hierarchy
1126 * stacked on transparent controllers
1127 *
1128 * @desc: the interrupt description structure for this irq
1129 *
1130 * Like handle_fasteoi_irq(), but for use with hierarchy where
1131 * the irq_chip also needs to have its ->irq_ack() function
1132 * called.
1133 */
1134void handle_fasteoi_ack_irq(struct irq_desc *desc)
1135{
1136 struct irq_chip *chip = desc->irq_data.chip;
1137
1138 raw_spin_lock(&desc->lock);
1139
1140 if (!irq_may_run(desc))
1141 goto out;
1142
1143 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
1144
1145 /*
1146 * If its disabled or no action available
1147 * then mask it and get out of here:
1148 */
1149 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
1150 desc->istate |= IRQS_PENDING;
1151 mask_irq(desc);
1152 goto out;
1153 }
1154
1155 kstat_incr_irqs_this_cpu(desc);
1156 if (desc->istate & IRQS_ONESHOT)
1157 mask_irq(desc);
1158
1159 /* Start handling the irq */
1160 desc->irq_data.chip->irq_ack(&desc->irq_data);
1161
1162 preflow_handler(desc);
1163 handle_irq_event(desc);
1164
1165 cond_unmask_eoi_irq(desc, chip);
1166
1167 raw_spin_unlock(&desc->lock);
1168 return;
1169out:
1170 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
1171 chip->irq_eoi(&desc->irq_data);
1172 raw_spin_unlock(&desc->lock);
1173}
1174EXPORT_SYMBOL_GPL(handle_fasteoi_ack_irq);
1175
1176/**
1177 * handle_fasteoi_mask_irq - irq handler for level hierarchy
1178 * stacked on transparent controllers
1179 *
1180 * @desc: the interrupt description structure for this irq
1181 *
1182 * Like handle_fasteoi_irq(), but for use with hierarchy where
1183 * the irq_chip also needs to have its ->irq_mask_ack() function
1184 * called.
1185 */
1186void handle_fasteoi_mask_irq(struct irq_desc *desc)
1187{
1188 struct irq_chip *chip = desc->irq_data.chip;
1189
1190 raw_spin_lock(&desc->lock);
1191 mask_ack_irq(desc);
1192
1193 if (!irq_may_run(desc))
1194 goto out;
1195
1196 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
1197
1198 /*
1199 * If its disabled or no action available
1200 * then mask it and get out of here:
1201 */
1202 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
1203 desc->istate |= IRQS_PENDING;
1204 mask_irq(desc);
1205 goto out;
1206 }
1207
1208 kstat_incr_irqs_this_cpu(desc);
1209 if (desc->istate & IRQS_ONESHOT)
1210 mask_irq(desc);
1211
1212 preflow_handler(desc);
1213 handle_irq_event(desc);
1214
1215 cond_unmask_eoi_irq(desc, chip);
1216
1217 raw_spin_unlock(&desc->lock);
1218 return;
1219out:
1220 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
1221 chip->irq_eoi(&desc->irq_data);
1222 raw_spin_unlock(&desc->lock);
1223}
1224EXPORT_SYMBOL_GPL(handle_fasteoi_mask_irq);
1225
1226#endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */
1227
3cfeffc2
SA
1228/**
1229 * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
1230 * NULL)
1231 * @data: Pointer to interrupt specific data
1232 */
1233void irq_chip_enable_parent(struct irq_data *data)
1234{
1235 data = data->parent_data;
1236 if (data->chip->irq_enable)
1237 data->chip->irq_enable(data);
1238 else
1239 data->chip->irq_unmask(data);
1240}
65efd9a4 1241EXPORT_SYMBOL_GPL(irq_chip_enable_parent);
3cfeffc2
SA
1242
1243/**
1244 * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if
1245 * NULL)
1246 * @data: Pointer to interrupt specific data
1247 */
1248void irq_chip_disable_parent(struct irq_data *data)
1249{
1250 data = data->parent_data;
1251 if (data->chip->irq_disable)
1252 data->chip->irq_disable(data);
1253 else
1254 data->chip->irq_mask(data);
1255}
65efd9a4 1256EXPORT_SYMBOL_GPL(irq_chip_disable_parent);
3cfeffc2 1257
85f08c17
JL
1258/**
1259 * irq_chip_ack_parent - Acknowledge the parent interrupt
1260 * @data: Pointer to interrupt specific data
1261 */
1262void irq_chip_ack_parent(struct irq_data *data)
1263{
1264 data = data->parent_data;
1265 data->chip->irq_ack(data);
1266}
a4289dc2 1267EXPORT_SYMBOL_GPL(irq_chip_ack_parent);
85f08c17 1268
56e8abab
YC
1269/**
1270 * irq_chip_mask_parent - Mask the parent interrupt
1271 * @data: Pointer to interrupt specific data
1272 */
1273void irq_chip_mask_parent(struct irq_data *data)
1274{
1275 data = data->parent_data;
1276 data->chip->irq_mask(data);
1277}
52b2a05f 1278EXPORT_SYMBOL_GPL(irq_chip_mask_parent);
56e8abab
YC
1279
1280/**
1281 * irq_chip_unmask_parent - Unmask the parent interrupt
1282 * @data: Pointer to interrupt specific data
1283 */
1284void irq_chip_unmask_parent(struct irq_data *data)
1285{
1286 data = data->parent_data;
1287 data->chip->irq_unmask(data);
1288}
52b2a05f 1289EXPORT_SYMBOL_GPL(irq_chip_unmask_parent);
56e8abab
YC
1290
1291/**
1292 * irq_chip_eoi_parent - Invoke EOI on the parent interrupt
1293 * @data: Pointer to interrupt specific data
1294 */
1295void irq_chip_eoi_parent(struct irq_data *data)
1296{
1297 data = data->parent_data;
1298 data->chip->irq_eoi(data);
1299}
52b2a05f 1300EXPORT_SYMBOL_GPL(irq_chip_eoi_parent);
56e8abab
YC
1301
1302/**
1303 * irq_chip_set_affinity_parent - Set affinity on the parent interrupt
1304 * @data: Pointer to interrupt specific data
1305 * @dest: The affinity mask to set
1306 * @force: Flag to enforce setting (disable online checks)
1307 *
1308 * Conditinal, as the underlying parent chip might not implement it.
1309 */
1310int irq_chip_set_affinity_parent(struct irq_data *data,
1311 const struct cpumask *dest, bool force)
1312{
1313 data = data->parent_data;
1314 if (data->chip->irq_set_affinity)
1315 return data->chip->irq_set_affinity(data, dest, force);
b7560de1
GS
1316
1317 return -ENOSYS;
1318}
65efd9a4 1319EXPORT_SYMBOL_GPL(irq_chip_set_affinity_parent);
b7560de1
GS
1320
1321/**
1322 * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
1323 * @data: Pointer to interrupt specific data
1324 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
1325 *
1326 * Conditional, as the underlying parent chip might not implement it.
1327 */
1328int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
1329{
1330 data = data->parent_data;
1331
1332 if (data->chip->irq_set_type)
1333 return data->chip->irq_set_type(data, type);
56e8abab
YC
1334
1335 return -ENOSYS;
1336}
52b2a05f 1337EXPORT_SYMBOL_GPL(irq_chip_set_type_parent);
56e8abab 1338
85f08c17
JL
1339/**
1340 * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
1341 * @data: Pointer to interrupt specific data
1342 *
1343 * Iterate through the domain hierarchy of the interrupt and check
1344 * whether a hw retrigger function exists. If yes, invoke it.
1345 */
1346int irq_chip_retrigger_hierarchy(struct irq_data *data)
1347{
1348 for (data = data->parent_data; data; data = data->parent_data)
1349 if (data->chip && data->chip->irq_retrigger)
1350 return data->chip->irq_retrigger(data);
1351
6d4affea 1352 return 0;
85f08c17 1353}
08b55e2a 1354
0a4377de
JL
1355/**
1356 * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt
1357 * @data: Pointer to interrupt specific data
8505a81b 1358 * @vcpu_info: The vcpu affinity information
0a4377de
JL
1359 */
1360int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)
1361{
1362 data = data->parent_data;
1363 if (data->chip->irq_set_vcpu_affinity)
1364 return data->chip->irq_set_vcpu_affinity(data, vcpu_info);
1365
1366 return -ENOSYS;
1367}
1368
08b55e2a
MZ
1369/**
1370 * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
1371 * @data: Pointer to interrupt specific data
1372 * @on: Whether to set or reset the wake-up capability of this irq
1373 *
1374 * Conditional, as the underlying parent chip might not implement it.
1375 */
1376int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
1377{
1378 data = data->parent_data;
1379 if (data->chip->irq_set_wake)
1380 return data->chip->irq_set_wake(data, on);
1381
1382 return -ENOSYS;
1383}
85f08c17 1384#endif
515085ef
JL
1385
1386/**
1387 * irq_chip_compose_msi_msg - Componse msi message for a irq chip
1388 * @data: Pointer to interrupt specific data
1389 * @msg: Pointer to the MSI message
1390 *
1391 * For hierarchical domains we find the first chip in the hierarchy
1392 * which implements the irq_compose_msi_msg callback. For non
1393 * hierarchical we use the top level chip.
1394 */
1395int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
1396{
1397 struct irq_data *pos = NULL;
1398
1399#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
1400 for (; data; data = data->parent_data)
1401#endif
1402 if (data->chip && data->chip->irq_compose_msi_msg)
1403 pos = data;
1404 if (!pos)
1405 return -ENOSYS;
1406
1407 pos->chip->irq_compose_msi_msg(pos, msg);
1408
1409 return 0;
1410}
be45beb2
JH
1411
1412/**
1413 * irq_chip_pm_get - Enable power for an IRQ chip
1414 * @data: Pointer to interrupt specific data
1415 *
1416 * Enable the power to the IRQ chip referenced by the interrupt data
1417 * structure.
1418 */
1419int irq_chip_pm_get(struct irq_data *data)
1420{
1421 int retval;
1422
1423 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) {
1424 retval = pm_runtime_get_sync(data->chip->parent_device);
1425 if (retval < 0) {
1426 pm_runtime_put_noidle(data->chip->parent_device);
1427 return retval;
1428 }
1429 }
1430
1431 return 0;
1432}
1433
1434/**
1435 * irq_chip_pm_put - Disable power for an IRQ chip
1436 * @data: Pointer to interrupt specific data
1437 *
1438 * Disable the power to the IRQ chip referenced by the interrupt data
1439 * structure, belongs. Note that power will only be disabled, once this
1440 * function has been called for all IRQs that have called irq_chip_pm_get().
1441 */
1442int irq_chip_pm_put(struct irq_data *data)
1443{
1444 int retval = 0;
1445
1446 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device)
1447 retval = pm_runtime_put(data->chip->parent_device);
1448
1449 return (retval < 0) ? retval : 0;
1450}