Commit | Line | Data |
---|---|---|
dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
3a16d713 EB |
21 | /** |
22 | * dynamic_irq_init - initialize a dynamically allocated irq | |
23 | * @irq: irq number to initialize | |
24 | */ | |
25 | void dynamic_irq_init(unsigned int irq) | |
26 | { | |
0b8f1efa | 27 | struct irq_desc *desc; |
3a16d713 EB |
28 | unsigned long flags; |
29 | ||
0b8f1efa | 30 | desc = irq_to_desc(irq); |
7d94f7ca | 31 | if (!desc) { |
261c40c1 | 32 | WARN(1, KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); |
3a16d713 EB |
33 | return; |
34 | } | |
35 | ||
36 | /* Ensure we don't have left over values from a previous use of this irq */ | |
3a16d713 EB |
37 | spin_lock_irqsave(&desc->lock, flags); |
38 | desc->status = IRQ_DISABLED; | |
39 | desc->chip = &no_irq_chip; | |
40 | desc->handle_irq = handle_bad_irq; | |
41 | desc->depth = 1; | |
5b912c10 | 42 | desc->msi_desc = NULL; |
3a16d713 EB |
43 | desc->handler_data = NULL; |
44 | desc->chip_data = NULL; | |
45 | desc->action = NULL; | |
46 | desc->irq_count = 0; | |
47 | desc->irqs_unhandled = 0; | |
48 | #ifdef CONFIG_SMP | |
7f7ace0c MT |
49 | cpumask_setall(desc->affinity); |
50 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
51 | cpumask_clear(desc->pending_mask); | |
52 | #endif | |
3a16d713 EB |
53 | #endif |
54 | spin_unlock_irqrestore(&desc->lock, flags); | |
55 | } | |
56 | ||
57 | /** | |
58 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq | |
59 | * @irq: irq number to initialize | |
60 | */ | |
61 | void dynamic_irq_cleanup(unsigned int irq) | |
62 | { | |
d3c60047 | 63 | struct irq_desc *desc = irq_to_desc(irq); |
3a16d713 EB |
64 | unsigned long flags; |
65 | ||
7d94f7ca | 66 | if (!desc) { |
261c40c1 | 67 | WARN(1, KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); |
3a16d713 EB |
68 | return; |
69 | } | |
70 | ||
3a16d713 | 71 | spin_lock_irqsave(&desc->lock, flags); |
1f80025e EB |
72 | if (desc->action) { |
73 | spin_unlock_irqrestore(&desc->lock, flags); | |
261c40c1 | 74 | WARN(1, KERN_ERR "Destroying IRQ%d without calling free_irq\n", |
1f80025e | 75 | irq); |
1f80025e EB |
76 | return; |
77 | } | |
5b912c10 EB |
78 | desc->msi_desc = NULL; |
79 | desc->handler_data = NULL; | |
80 | desc->chip_data = NULL; | |
3a16d713 EB |
81 | desc->handle_irq = handle_bad_irq; |
82 | desc->chip = &no_irq_chip; | |
b6f3b780 | 83 | desc->name = NULL; |
0f3c2a89 | 84 | clear_kstat_irqs(desc); |
3a16d713 EB |
85 | spin_unlock_irqrestore(&desc->lock, flags); |
86 | } | |
87 | ||
88 | ||
dd87eb3a TG |
89 | /** |
90 | * set_irq_chip - set the irq chip for an irq | |
91 | * @irq: irq number | |
92 | * @chip: pointer to irq chip description structure | |
93 | */ | |
94 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
95 | { | |
d3c60047 | 96 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
97 | unsigned long flags; |
98 | ||
7d94f7ca | 99 | if (!desc) { |
261c40c1 | 100 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
dd87eb3a TG |
101 | return -EINVAL; |
102 | } | |
103 | ||
104 | if (!chip) | |
105 | chip = &no_irq_chip; | |
106 | ||
dd87eb3a TG |
107 | spin_lock_irqsave(&desc->lock, flags); |
108 | irq_chip_set_defaults(chip); | |
109 | desc->chip = chip; | |
dd87eb3a TG |
110 | spin_unlock_irqrestore(&desc->lock, flags); |
111 | ||
112 | return 0; | |
113 | } | |
114 | EXPORT_SYMBOL(set_irq_chip); | |
115 | ||
116 | /** | |
0c5d1eb7 | 117 | * set_irq_type - set the irq trigger type for an irq |
dd87eb3a | 118 | * @irq: irq number |
0c5d1eb7 | 119 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a TG |
120 | */ |
121 | int set_irq_type(unsigned int irq, unsigned int type) | |
122 | { | |
d3c60047 | 123 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
124 | unsigned long flags; |
125 | int ret = -ENXIO; | |
126 | ||
7d94f7ca | 127 | if (!desc) { |
dd87eb3a TG |
128 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
129 | return -ENODEV; | |
130 | } | |
131 | ||
f2b662da | 132 | type &= IRQ_TYPE_SENSE_MASK; |
0c5d1eb7 DB |
133 | if (type == IRQ_TYPE_NONE) |
134 | return 0; | |
135 | ||
136 | spin_lock_irqsave(&desc->lock, flags); | |
0b3682ba | 137 | ret = __irq_set_trigger(desc, irq, type); |
0c5d1eb7 | 138 | spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
139 | return ret; |
140 | } | |
141 | EXPORT_SYMBOL(set_irq_type); | |
142 | ||
143 | /** | |
144 | * set_irq_data - set irq type data for an irq | |
145 | * @irq: Interrupt number | |
146 | * @data: Pointer to interrupt specific data | |
147 | * | |
148 | * Set the hardware irq controller data for an irq | |
149 | */ | |
150 | int set_irq_data(unsigned int irq, void *data) | |
151 | { | |
d3c60047 | 152 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
153 | unsigned long flags; |
154 | ||
7d94f7ca | 155 | if (!desc) { |
dd87eb3a TG |
156 | printk(KERN_ERR |
157 | "Trying to install controller data for IRQ%d\n", irq); | |
158 | return -EINVAL; | |
159 | } | |
160 | ||
dd87eb3a TG |
161 | spin_lock_irqsave(&desc->lock, flags); |
162 | desc->handler_data = data; | |
163 | spin_unlock_irqrestore(&desc->lock, flags); | |
164 | return 0; | |
165 | } | |
166 | EXPORT_SYMBOL(set_irq_data); | |
167 | ||
5b912c10 EB |
168 | /** |
169 | * set_irq_data - set irq type data for an irq | |
170 | * @irq: Interrupt number | |
472900b8 | 171 | * @entry: Pointer to MSI descriptor data |
5b912c10 EB |
172 | * |
173 | * Set the hardware irq controller data for an irq | |
174 | */ | |
175 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) | |
176 | { | |
d3c60047 | 177 | struct irq_desc *desc = irq_to_desc(irq); |
5b912c10 EB |
178 | unsigned long flags; |
179 | ||
7d94f7ca | 180 | if (!desc) { |
5b912c10 EB |
181 | printk(KERN_ERR |
182 | "Trying to install msi data for IRQ%d\n", irq); | |
183 | return -EINVAL; | |
184 | } | |
7d94f7ca | 185 | |
5b912c10 EB |
186 | spin_lock_irqsave(&desc->lock, flags); |
187 | desc->msi_desc = entry; | |
7fe3730d ME |
188 | if (entry) |
189 | entry->irq = irq; | |
5b912c10 EB |
190 | spin_unlock_irqrestore(&desc->lock, flags); |
191 | return 0; | |
192 | } | |
193 | ||
dd87eb3a TG |
194 | /** |
195 | * set_irq_chip_data - set irq chip data for an irq | |
196 | * @irq: Interrupt number | |
197 | * @data: Pointer to chip specific data | |
198 | * | |
199 | * Set the hardware irq chip data for an irq | |
200 | */ | |
201 | int set_irq_chip_data(unsigned int irq, void *data) | |
202 | { | |
d3c60047 | 203 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
204 | unsigned long flags; |
205 | ||
7d94f7ca YL |
206 | if (!desc) { |
207 | printk(KERN_ERR | |
208 | "Trying to install chip data for IRQ%d\n", irq); | |
209 | return -EINVAL; | |
210 | } | |
211 | ||
212 | if (!desc->chip) { | |
dd87eb3a TG |
213 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
214 | return -EINVAL; | |
215 | } | |
216 | ||
217 | spin_lock_irqsave(&desc->lock, flags); | |
218 | desc->chip_data = data; | |
219 | spin_unlock_irqrestore(&desc->lock, flags); | |
220 | ||
221 | return 0; | |
222 | } | |
223 | EXPORT_SYMBOL(set_irq_chip_data); | |
224 | ||
225 | /* | |
226 | * default enable function | |
227 | */ | |
228 | static void default_enable(unsigned int irq) | |
229 | { | |
d3c60047 | 230 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
231 | |
232 | desc->chip->unmask(irq); | |
233 | desc->status &= ~IRQ_MASKED; | |
234 | } | |
235 | ||
236 | /* | |
237 | * default disable function | |
238 | */ | |
239 | static void default_disable(unsigned int irq) | |
240 | { | |
dd87eb3a TG |
241 | } |
242 | ||
243 | /* | |
244 | * default startup function | |
245 | */ | |
246 | static unsigned int default_startup(unsigned int irq) | |
247 | { | |
d3c60047 | 248 | struct irq_desc *desc = irq_to_desc(irq); |
08678b08 | 249 | |
08678b08 | 250 | desc->chip->enable(irq); |
dd87eb3a TG |
251 | return 0; |
252 | } | |
253 | ||
89d694b9 TG |
254 | /* |
255 | * default shutdown function | |
256 | */ | |
257 | static void default_shutdown(unsigned int irq) | |
258 | { | |
d3c60047 | 259 | struct irq_desc *desc = irq_to_desc(irq); |
89d694b9 TG |
260 | |
261 | desc->chip->mask(irq); | |
262 | desc->status |= IRQ_MASKED; | |
263 | } | |
264 | ||
dd87eb3a TG |
265 | /* |
266 | * Fixup enable/disable function pointers | |
267 | */ | |
268 | void irq_chip_set_defaults(struct irq_chip *chip) | |
269 | { | |
270 | if (!chip->enable) | |
271 | chip->enable = default_enable; | |
272 | if (!chip->disable) | |
273 | chip->disable = default_disable; | |
274 | if (!chip->startup) | |
275 | chip->startup = default_startup; | |
89d694b9 TG |
276 | /* |
277 | * We use chip->disable, when the user provided its own. When | |
278 | * we have default_disable set for chip->disable, then we need | |
279 | * to use default_shutdown, otherwise the irq line is not | |
280 | * disabled on free_irq(): | |
281 | */ | |
dd87eb3a | 282 | if (!chip->shutdown) |
89d694b9 TG |
283 | chip->shutdown = chip->disable != default_disable ? |
284 | chip->disable : default_shutdown; | |
dd87eb3a TG |
285 | if (!chip->name) |
286 | chip->name = chip->typename; | |
b86432b4 ZY |
287 | if (!chip->end) |
288 | chip->end = dummy_irq_chip.end; | |
dd87eb3a TG |
289 | } |
290 | ||
291 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) | |
292 | { | |
293 | if (desc->chip->mask_ack) | |
294 | desc->chip->mask_ack(irq); | |
295 | else { | |
296 | desc->chip->mask(irq); | |
efdc64f0 WC |
297 | if (desc->chip->ack) |
298 | desc->chip->ack(irq); | |
dd87eb3a TG |
299 | } |
300 | } | |
301 | ||
302 | /** | |
303 | * handle_simple_irq - Simple and software-decoded IRQs. | |
304 | * @irq: the interrupt number | |
305 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
306 | * |
307 | * Simple interrupts are either sent from a demultiplexing interrupt | |
308 | * handler or come from hardware, where no interrupt hardware control | |
309 | * is necessary. | |
310 | * | |
311 | * Note: The caller is expected to handle the ack, clear, mask and | |
312 | * unmask issues if necessary. | |
313 | */ | |
7ad5b3a5 | 314 | void |
7d12e780 | 315 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
316 | { |
317 | struct irqaction *action; | |
318 | irqreturn_t action_ret; | |
dd87eb3a TG |
319 | |
320 | spin_lock(&desc->lock); | |
321 | ||
322 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
323 | goto out_unlock; | |
971e5b35 | 324 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 325 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
326 | |
327 | action = desc->action; | |
971e5b35 | 328 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
dd87eb3a TG |
329 | goto out_unlock; |
330 | ||
331 | desc->status |= IRQ_INPROGRESS; | |
332 | spin_unlock(&desc->lock); | |
333 | ||
7d12e780 | 334 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 335 | if (!noirqdebug) |
7d12e780 | 336 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
337 | |
338 | spin_lock(&desc->lock); | |
339 | desc->status &= ~IRQ_INPROGRESS; | |
340 | out_unlock: | |
341 | spin_unlock(&desc->lock); | |
342 | } | |
343 | ||
344 | /** | |
345 | * handle_level_irq - Level type irq handler | |
346 | * @irq: the interrupt number | |
347 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
348 | * |
349 | * Level type interrupts are active as long as the hardware line has | |
350 | * the active level. This may require to mask the interrupt and unmask | |
351 | * it after the associated handler has acknowledged the device, so the | |
352 | * interrupt line is back to inactive. | |
353 | */ | |
7ad5b3a5 | 354 | void |
7d12e780 | 355 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 356 | { |
dd87eb3a TG |
357 | struct irqaction *action; |
358 | irqreturn_t action_ret; | |
359 | ||
360 | spin_lock(&desc->lock); | |
361 | mask_ack_irq(desc, irq); | |
362 | ||
363 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
86998aa6 | 364 | goto out_unlock; |
dd87eb3a | 365 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 366 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
367 | |
368 | /* | |
369 | * If its disabled or no action available | |
370 | * keep it masked and get out of here | |
371 | */ | |
372 | action = desc->action; | |
49663421 | 373 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
86998aa6 | 374 | goto out_unlock; |
dd87eb3a TG |
375 | |
376 | desc->status |= IRQ_INPROGRESS; | |
377 | spin_unlock(&desc->lock); | |
378 | ||
7d12e780 | 379 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 380 | if (!noirqdebug) |
7d12e780 | 381 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
382 | |
383 | spin_lock(&desc->lock); | |
384 | desc->status &= ~IRQ_INPROGRESS; | |
dd87eb3a TG |
385 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) |
386 | desc->chip->unmask(irq); | |
86998aa6 | 387 | out_unlock: |
dd87eb3a TG |
388 | spin_unlock(&desc->lock); |
389 | } | |
14819ea1 | 390 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a TG |
391 | |
392 | /** | |
47c2a3aa | 393 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
394 | * @irq: the interrupt number |
395 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 396 | * |
47c2a3aa | 397 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
398 | * call when the interrupt has been serviced. This enables support |
399 | * for modern forms of interrupt handlers, which handle the flow | |
400 | * details in hardware, transparently. | |
401 | */ | |
7ad5b3a5 | 402 | void |
7d12e780 | 403 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 404 | { |
dd87eb3a TG |
405 | struct irqaction *action; |
406 | irqreturn_t action_ret; | |
407 | ||
408 | spin_lock(&desc->lock); | |
409 | ||
410 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
411 | goto out; | |
412 | ||
413 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
d6c88a50 | 414 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
415 | |
416 | /* | |
417 | * If its disabled or no action available | |
76d21601 | 418 | * then mask it and get out of here: |
dd87eb3a TG |
419 | */ |
420 | action = desc->action; | |
98bb244b BH |
421 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
422 | desc->status |= IRQ_PENDING; | |
76d21601 IM |
423 | if (desc->chip->mask) |
424 | desc->chip->mask(irq); | |
dd87eb3a | 425 | goto out; |
98bb244b | 426 | } |
dd87eb3a TG |
427 | |
428 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 429 | desc->status &= ~IRQ_PENDING; |
dd87eb3a TG |
430 | spin_unlock(&desc->lock); |
431 | ||
7d12e780 | 432 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 433 | if (!noirqdebug) |
7d12e780 | 434 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
435 | |
436 | spin_lock(&desc->lock); | |
437 | desc->status &= ~IRQ_INPROGRESS; | |
438 | out: | |
47c2a3aa | 439 | desc->chip->eoi(irq); |
dd87eb3a TG |
440 | |
441 | spin_unlock(&desc->lock); | |
442 | } | |
443 | ||
444 | /** | |
445 | * handle_edge_irq - edge type IRQ handler | |
446 | * @irq: the interrupt number | |
447 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
448 | * |
449 | * Interrupt occures on the falling and/or rising edge of a hardware | |
450 | * signal. The occurence is latched into the irq controller hardware | |
451 | * and must be acked in order to be reenabled. After the ack another | |
452 | * interrupt can happen on the same source even before the first one | |
453 | * is handled by the assosiacted event handler. If this happens it | |
454 | * might be necessary to disable (mask) the interrupt depending on the | |
455 | * controller hardware. This requires to reenable the interrupt inside | |
456 | * of the loop which handles the interrupts which have arrived while | |
457 | * the handler was running. If all pending interrupts are handled, the | |
458 | * loop is left. | |
459 | */ | |
7ad5b3a5 | 460 | void |
7d12e780 | 461 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 462 | { |
dd87eb3a TG |
463 | spin_lock(&desc->lock); |
464 | ||
465 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
466 | ||
467 | /* | |
468 | * If we're currently running this IRQ, or its disabled, | |
469 | * we shouldn't process the IRQ. Mark it pending, handle | |
470 | * the necessary masking and go out | |
471 | */ | |
472 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
473 | !desc->action)) { | |
474 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
475 | mask_ack_irq(desc, irq); | |
476 | goto out_unlock; | |
477 | } | |
d6c88a50 | 478 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
479 | |
480 | /* Start handling the irq */ | |
efdc64f0 WC |
481 | if (desc->chip->ack) |
482 | desc->chip->ack(irq); | |
dd87eb3a TG |
483 | |
484 | /* Mark the IRQ currently in progress.*/ | |
485 | desc->status |= IRQ_INPROGRESS; | |
486 | ||
487 | do { | |
488 | struct irqaction *action = desc->action; | |
489 | irqreturn_t action_ret; | |
490 | ||
491 | if (unlikely(!action)) { | |
492 | desc->chip->mask(irq); | |
493 | goto out_unlock; | |
494 | } | |
495 | ||
496 | /* | |
497 | * When another irq arrived while we were handling | |
498 | * one, we could have masked the irq. | |
499 | * Renable it, if it was not disabled in meantime. | |
500 | */ | |
501 | if (unlikely((desc->status & | |
502 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
503 | (IRQ_PENDING | IRQ_MASKED))) { | |
504 | desc->chip->unmask(irq); | |
505 | desc->status &= ~IRQ_MASKED; | |
506 | } | |
507 | ||
508 | desc->status &= ~IRQ_PENDING; | |
509 | spin_unlock(&desc->lock); | |
7d12e780 | 510 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 511 | if (!noirqdebug) |
7d12e780 | 512 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
513 | spin_lock(&desc->lock); |
514 | ||
515 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
516 | ||
517 | desc->status &= ~IRQ_INPROGRESS; | |
518 | out_unlock: | |
519 | spin_unlock(&desc->lock); | |
520 | } | |
521 | ||
dd87eb3a TG |
522 | /** |
523 | * handle_percpu_IRQ - Per CPU local irq handler | |
524 | * @irq: the interrupt number | |
525 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
526 | * |
527 | * Per CPU interrupts on SMP machines without locking requirements | |
528 | */ | |
7ad5b3a5 | 529 | void |
7d12e780 | 530 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
531 | { |
532 | irqreturn_t action_ret; | |
533 | ||
d6c88a50 | 534 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
535 | |
536 | if (desc->chip->ack) | |
537 | desc->chip->ack(irq); | |
538 | ||
7d12e780 | 539 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 540 | if (!noirqdebug) |
7d12e780 | 541 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 542 | |
fcef5911 | 543 | if (desc->chip->eoi) |
dd87eb3a TG |
544 | desc->chip->eoi(irq); |
545 | } | |
546 | ||
dd87eb3a | 547 | void |
a460e745 IM |
548 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
549 | const char *name) | |
dd87eb3a | 550 | { |
d3c60047 | 551 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
552 | unsigned long flags; |
553 | ||
7d94f7ca | 554 | if (!desc) { |
dd87eb3a TG |
555 | printk(KERN_ERR |
556 | "Trying to install type control for IRQ%d\n", irq); | |
557 | return; | |
558 | } | |
559 | ||
dd87eb3a TG |
560 | if (!handle) |
561 | handle = handle_bad_irq; | |
9d7ac8be | 562 | else if (desc->chip == &no_irq_chip) { |
f8b5473f | 563 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 564 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
565 | /* |
566 | * Some ARM implementations install a handler for really dumb | |
567 | * interrupt hardware without setting an irq_chip. This worked | |
568 | * with the ARM no_irq_chip but the check in setup_irq would | |
569 | * prevent us to setup the interrupt at all. Switch it to | |
570 | * dummy_irq_chip for easy transition. | |
571 | */ | |
572 | desc->chip = &dummy_irq_chip; | |
573 | } | |
dd87eb3a TG |
574 | |
575 | spin_lock_irqsave(&desc->lock, flags); | |
576 | ||
577 | /* Uninstall? */ | |
578 | if (handle == handle_bad_irq) { | |
fcef5911 | 579 | if (desc->chip != &no_irq_chip) |
5575ddf7 | 580 | mask_ack_irq(desc, irq); |
dd87eb3a TG |
581 | desc->status |= IRQ_DISABLED; |
582 | desc->depth = 1; | |
583 | } | |
584 | desc->handle_irq = handle; | |
a460e745 | 585 | desc->name = name; |
dd87eb3a TG |
586 | |
587 | if (handle != handle_bad_irq && is_chained) { | |
588 | desc->status &= ~IRQ_DISABLED; | |
589 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | |
590 | desc->depth = 0; | |
7e6e178a | 591 | desc->chip->startup(irq); |
dd87eb3a TG |
592 | } |
593 | spin_unlock_irqrestore(&desc->lock, flags); | |
594 | } | |
14819ea1 | 595 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
dd87eb3a TG |
596 | |
597 | void | |
598 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 599 | irq_flow_handler_t handle) |
dd87eb3a TG |
600 | { |
601 | set_irq_chip(irq, chip); | |
a460e745 | 602 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
603 | } |
604 | ||
a460e745 IM |
605 | void |
606 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
607 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 608 | { |
a460e745 IM |
609 | set_irq_chip(irq, chip); |
610 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 611 | } |
46f4f8f6 RB |
612 | |
613 | void __init set_irq_noprobe(unsigned int irq) | |
614 | { | |
d3c60047 | 615 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
616 | unsigned long flags; |
617 | ||
7d94f7ca | 618 | if (!desc) { |
46f4f8f6 | 619 | printk(KERN_ERR "Trying to mark IRQ%d non-probeable\n", irq); |
46f4f8f6 RB |
620 | return; |
621 | } | |
622 | ||
46f4f8f6 RB |
623 | spin_lock_irqsave(&desc->lock, flags); |
624 | desc->status |= IRQ_NOPROBE; | |
625 | spin_unlock_irqrestore(&desc->lock, flags); | |
626 | } | |
627 | ||
628 | void __init set_irq_probe(unsigned int irq) | |
629 | { | |
d3c60047 | 630 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
631 | unsigned long flags; |
632 | ||
7d94f7ca | 633 | if (!desc) { |
46f4f8f6 | 634 | printk(KERN_ERR "Trying to mark IRQ%d probeable\n", irq); |
46f4f8f6 RB |
635 | return; |
636 | } | |
637 | ||
46f4f8f6 RB |
638 | spin_lock_irqsave(&desc->lock, flags); |
639 | desc->status &= ~IRQ_NOPROBE; | |
640 | spin_unlock_irqrestore(&desc->lock, flags); | |
641 | } |