[linux-block.git] / include / video / omapdss.h

/*
 * Copyright (C) 2008 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __OMAP_OMAPDSS_H
#define __OMAP_OMAPDSS_H

#include <linux/list.h>
#include <linux/kobject.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <asm/atomic.h>

#define DISPC_IRQ_FRAMEDONE		(1 << 0)
#define DISPC_IRQ_VSYNC			(1 << 1)
#define DISPC_IRQ_EVSYNC_EVEN		(1 << 2)
#define DISPC_IRQ_EVSYNC_ODD		(1 << 3)
#define DISPC_IRQ_ACBIAS_COUNT_STAT	(1 << 4)
#define DISPC_IRQ_PROG_LINE_NUM		(1 << 5)
#define DISPC_IRQ_GFX_FIFO_UNDERFLOW	(1 << 6)
#define DISPC_IRQ_GFX_END_WIN		(1 << 7)
#define DISPC_IRQ_PAL_GAMMA_MASK	(1 << 8)
#define DISPC_IRQ_OCP_ERR		(1 << 9)
#define DISPC_IRQ_VID1_FIFO_UNDERFLOW	(1 << 10)
#define DISPC_IRQ_VID1_END_WIN		(1 << 11)
#define DISPC_IRQ_VID2_FIFO_UNDERFLOW	(1 << 12)
#define DISPC_IRQ_VID2_END_WIN		(1 << 13)
#define DISPC_IRQ_SYNC_LOST		(1 << 14)
#define DISPC_IRQ_SYNC_LOST_DIGIT	(1 << 15)
#define DISPC_IRQ_WAKEUP		(1 << 16)
#define DISPC_IRQ_SYNC_LOST2		(1 << 17)
#define DISPC_IRQ_VSYNC2		(1 << 18)
#define DISPC_IRQ_ACBIAS_COUNT_STAT2	(1 << 21)
#define DISPC_IRQ_FRAMEDONE2		(1 << 22)

struct omap_dss_device;
struct omap_overlay_manager;

enum omap_display_type {
	OMAP_DISPLAY_TYPE_NONE		= 0,
	OMAP_DISPLAY_TYPE_DPI		= 1 << 0,
	OMAP_DISPLAY_TYPE_DBI		= 1 << 1,
	OMAP_DISPLAY_TYPE_SDI		= 1 << 2,
	OMAP_DISPLAY_TYPE_DSI		= 1 << 3,
	OMAP_DISPLAY_TYPE_VENC		= 1 << 4,
	OMAP_DISPLAY_TYPE_HDMI		= 1 << 5,
};

enum omap_plane {
	OMAP_DSS_GFX	= 0,
	OMAP_DSS_VIDEO1	= 1,
	OMAP_DSS_VIDEO2	= 2
};

enum omap_channel {
	OMAP_DSS_CHANNEL_LCD	= 0,
	OMAP_DSS_CHANNEL_DIGIT	= 1,
	OMAP_DSS_CHANNEL_LCD2	= 2,
};

enum omap_color_mode {
	OMAP_DSS_COLOR_CLUT1	= 1 << 0,  /* BITMAP 1 */
	OMAP_DSS_COLOR_CLUT2	= 1 << 1,  /* BITMAP 2 */
	OMAP_DSS_COLOR_CLUT4	= 1 << 2,  /* BITMAP 4 */
	OMAP_DSS_COLOR_CLUT8	= 1 << 3,  /* BITMAP 8 */
	OMAP_DSS_COLOR_RGB12U	= 1 << 4,  /* RGB12, 16-bit container */
	OMAP_DSS_COLOR_ARGB16	= 1 << 5,  /* ARGB16 */
	OMAP_DSS_COLOR_RGB16	= 1 << 6,  /* RGB16 */
	OMAP_DSS_COLOR_RGB24U	= 1 << 7,  /* RGB24, 32-bit container */
	OMAP_DSS_COLOR_RGB24P	= 1 << 8,  /* RGB24, 24-bit container */
	OMAP_DSS_COLOR_YUV2	= 1 << 9,  /* YUV2 4:2:2 co-sited */
	OMAP_DSS_COLOR_UYVY	= 1 << 10, /* UYVY 4:2:2 co-sited */
	OMAP_DSS_COLOR_ARGB32	= 1 << 11, /* ARGB32 */
	OMAP_DSS_COLOR_RGBA32	= 1 << 12, /* RGBA32 */
	OMAP_DSS_COLOR_RGBX32	= 1 << 13, /* RGBx32 */
	OMAP_DSS_COLOR_NV12		= 1 << 14, /* NV12 format: YUV 4:2:0 */
	OMAP_DSS_COLOR_RGBA16		= 1 << 15, /* RGBA16 - 4444 */
	OMAP_DSS_COLOR_RGBX16		= 1 << 16, /* RGBx16 - 4444 */
	OMAP_DSS_COLOR_ARGB16_1555	= 1 << 17, /* ARGB16 - 1555 */
	OMAP_DSS_COLOR_XRGB16_1555	= 1 << 18, /* xRGB16 - 1555 */
};

enum omap_lcd_display_type {
	OMAP_DSS_LCD_DISPLAY_STN,
	OMAP_DSS_LCD_DISPLAY_TFT,
};

enum omap_dss_load_mode {
	OMAP_DSS_LOAD_CLUT_AND_FRAME	= 0,
	OMAP_DSS_LOAD_CLUT_ONLY		= 1,
	OMAP_DSS_LOAD_FRAME_ONLY	= 2,
	OMAP_DSS_LOAD_CLUT_ONCE_FRAME	= 3,
};

enum omap_dss_trans_key_type {
	OMAP_DSS_COLOR_KEY_GFX_DST = 0,
	OMAP_DSS_COLOR_KEY_VID_SRC = 1,
};

enum omap_rfbi_te_mode {
	OMAP_DSS_RFBI_TE_MODE_1 = 1,
	OMAP_DSS_RFBI_TE_MODE_2 = 2,
};

enum omap_panel_config {
	OMAP_DSS_LCD_IVS		= 1<<0,
	OMAP_DSS_LCD_IHS		= 1<<1,
	OMAP_DSS_LCD_IPC		= 1<<2,
	OMAP_DSS_LCD_IEO		= 1<<3,
	OMAP_DSS_LCD_RF			= 1<<4,
	OMAP_DSS_LCD_ONOFF		= 1<<5,

	OMAP_DSS_LCD_TFT		= 1<<20,
};

enum omap_dss_venc_type {
	OMAP_DSS_VENC_TYPE_COMPOSITE,
	OMAP_DSS_VENC_TYPE_SVIDEO,
};

enum omap_display_caps {
	OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE	= 1 << 0,
	OMAP_DSS_DISPLAY_CAP_TEAR_ELIM		= 1 << 1,
};

enum omap_dss_update_mode {
	OMAP_DSS_UPDATE_DISABLED = 0,
	OMAP_DSS_UPDATE_AUTO,
	OMAP_DSS_UPDATE_MANUAL,
};

enum omap_dss_display_state {
	OMAP_DSS_DISPLAY_DISABLED = 0,
	OMAP_DSS_DISPLAY_ACTIVE,
	OMAP_DSS_DISPLAY_SUSPENDED,
};

/* XXX perhaps this should be removed */
enum omap_dss_overlay_managers {
	OMAP_DSS_OVL_MGR_LCD,
	OMAP_DSS_OVL_MGR_TV,
	OMAP_DSS_OVL_MGR_LCD2,
};

enum omap_dss_rotation_type {
	OMAP_DSS_ROT_DMA = 0,
	OMAP_DSS_ROT_VRFB = 1,
};

/* clockwise rotation angle */
enum omap_dss_rotation_angle {
	OMAP_DSS_ROT_0   = 0,
	OMAP_DSS_ROT_90  = 1,
	OMAP_DSS_ROT_180 = 2,
	OMAP_DSS_ROT_270 = 3,
};

enum omap_overlay_caps {
	OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
	OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
};

enum omap_overlay_manager_caps {
	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
};

enum omap_dss_clk_source {
	OMAP_DSS_CLK_SRC_FCK = 0,		/* OMAP2/3: DSS1_ALWON_FCLK
						 * OMAP4: DSS_FCLK */
	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,	/* OMAP3: DSI1_PLL_FCLK
						 * OMAP4: PLL1_CLK1 */
	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,	/* OMAP3: DSI2_PLL_FCLK
						 * OMAP4: PLL1_CLK2 */
	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,	/* OMAP4: PLL2_CLK1 */
	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,	/* OMAP4: PLL2_CLK2 */
};

/* RFBI */

struct rfbi_timings {
	int cs_on_time;
	int cs_off_time;
	int we_on_time;
	int we_off_time;
	int re_on_time;
	int re_off_time;
	int we_cycle_time;
	int re_cycle_time;
	int cs_pulse_width;
	int access_time;

	int clk_div;

	u32 tim[5];             /* set by rfbi_convert_timings() */

	int converted;
};

void omap_rfbi_write_command(const void *buf, u32 len);
void omap_rfbi_read_data(void *buf, u32 len);
void omap_rfbi_write_data(const void *buf, u32 len);
void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
		u16 x, u16 y,
		u16 w, u16 h);
int omap_rfbi_enable_te(bool enable, unsigned line);
int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
			     unsigned hs_pulse_time, unsigned vs_pulse_time,
			     int hs_pol_inv, int vs_pol_inv, int extif_div);
void rfbi_bus_lock(void);
void rfbi_bus_unlock(void);

/* DSI */
void dsi_bus_lock(struct omap_dss_device *dssdev);
void dsi_bus_unlock(struct omap_dss_device *dssdev);
int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
		int len);
int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
		u8 dcs_cmd);
int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 param);
int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
		u8 *data, int len);
int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *buf, int buflen);
int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *data);
int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *data1, u8 *data2);
int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
		u16 len);
int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);

/* Board specific data */
struct omap_dss_board_info {
	int (*get_last_off_on_transaction_id)(struct device *dev);
	int num_devices;
	struct omap_dss_device **devices;
	struct omap_dss_device *default_device;
	void (*dsi_mux_pads)(bool enable);
};

#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
/* Init with the board info */
extern int omap_display_init(struct omap_dss_board_info *board_data);
#else
static inline int omap_display_init(struct omap_dss_board_info *board_data)
{
	return 0;
}
#endif

struct omap_display_platform_data {
	struct omap_dss_board_info *board_data;
	/* TODO: Additional members to be added when PM is considered */

	bool (*opt_clock_available)(const char *clk_role);
};

struct omap_video_timings {
	/* Unit: pixels */
	u16 x_res;
	/* Unit: pixels */
	u16 y_res;
	/* Unit: KHz */
	u32 pixel_clock;
	/* Unit: pixel clocks */
	u16 hsw;	/* Horizontal synchronization pulse width */
	/* Unit: pixel clocks */
	u16 hfp;	/* Horizontal front porch */
	/* Unit: pixel clocks */
	u16 hbp;	/* Horizontal back porch */
	/* Unit: line clocks */
	u16 vsw;	/* Vertical synchronization pulse width */
	/* Unit: line clocks */
	u16 vfp;	/* Vertical front porch */
	/* Unit: line clocks */
	u16 vbp;	/* Vertical back porch */
};

#ifdef CONFIG_OMAP2_DSS_VENC
/* Hardcoded timings for tv modes. Venc only uses these to
 * identify the mode, and does not actually use the configs
 * itself. However, the configs should be something that
 * a normal monitor can also show */
extern const struct omap_video_timings omap_dss_pal_timings;
extern const struct omap_video_timings omap_dss_ntsc_timings;
#endif

struct omap_overlay_info {
	bool enabled;

	u32 paddr;
	void __iomem *vaddr;
	u16 screen_width;
	u16 width;
	u16 height;
	enum omap_color_mode color_mode;
	u8 rotation;
	enum omap_dss_rotation_type rotation_type;
	bool mirror;

	u16 pos_x;
	u16 pos_y;
	u16 out_width;	/* if 0, out_width == width */
	u16 out_height;	/* if 0, out_height == height */
	u8 global_alpha;
	u8 pre_mult_alpha;
};

struct omap_overlay {
	struct kobject kobj;
	struct list_head list;

	/* static fields */
	const char *name;
	int id;
	enum omap_color_mode supported_modes;
	enum omap_overlay_caps caps;

	/* dynamic fields */
	struct omap_overlay_manager *manager;
	struct omap_overlay_info info;

	/* if true, info has been changed, but not applied() yet */
	bool info_dirty;

	int (*set_manager)(struct omap_overlay *ovl,
		struct omap_overlay_manager *mgr);
	int (*unset_manager)(struct omap_overlay *ovl);

	int (*set_overlay_info)(struct omap_overlay *ovl,
			struct omap_overlay_info *info);
	void (*get_overlay_info)(struct omap_overlay *ovl,
			struct omap_overlay_info *info);

	int (*wait_for_go)(struct omap_overlay *ovl);
};

struct omap_overlay_manager_info {
	u32 default_color;

	enum omap_dss_trans_key_type trans_key_type;
	u32 trans_key;
	bool trans_enabled;

	bool alpha_enabled;
};

struct omap_overlay_manager {
	struct kobject kobj;
	struct list_head list;

	/* static fields */
	const char *name;
	int id;
	enum omap_overlay_manager_caps caps;
	int num_overlays;
	struct omap_overlay **overlays;
	enum omap_display_type supported_displays;

	/* dynamic fields */
	struct omap_dss_device *device;
	struct omap_overlay_manager_info info;

	bool device_changed;
	/* if true, info has been changed but not applied() yet */
	bool info_dirty;

	int (*set_device)(struct omap_overlay_manager *mgr,
		struct omap_dss_device *dssdev);
	int (*unset_device)(struct omap_overlay_manager *mgr);

	int (*set_manager_info)(struct omap_overlay_manager *mgr,
			struct omap_overlay_manager_info *info);
	void (*get_manager_info)(struct omap_overlay_manager *mgr,
			struct omap_overlay_manager_info *info);

	int (*apply)(struct omap_overlay_manager *mgr);
	int (*wait_for_go)(struct omap_overlay_manager *mgr);
	int (*wait_for_vsync)(struct omap_overlay_manager *mgr);

	int (*enable)(struct omap_overlay_manager *mgr);
	int (*disable)(struct omap_overlay_manager *mgr);
};

struct omap_dss_device {
	struct device dev;

	enum omap_display_type type;

	enum omap_channel channel;

	union {
		struct {
			u8 data_lines;
		} dpi;

		struct {
			u8 channel;
			u8 data_lines;
		} rfbi;

		struct {
			u8 datapairs;
		} sdi;

		struct {
			u8 clk_lane;
			u8 clk_pol;
			u8 data1_lane;
			u8 data1_pol;
			u8 data2_lane;
			u8 data2_pol;
			u8 data3_lane;
			u8 data3_pol;
			u8 data4_lane;
			u8 data4_pol;

			int module;

			bool ext_te;
			u8 ext_te_gpio;
		} dsi;

		struct {
			enum omap_dss_venc_type type;
			bool invert_polarity;
		} venc;
	} phy;

	struct {
		struct {
			struct {
				u16 lck_div;
				u16 pck_div;
				enum omap_dss_clk_source lcd_clk_src;
			} channel;

			enum omap_dss_clk_source dispc_fclk_src;
		} dispc;

		struct {
			u16 regn;
			u16 regm;
			u16 regm_dispc;
			u16 regm_dsi;

			u16 lp_clk_div;
			enum omap_dss_clk_source dsi_fclk_src;
		} dsi;

		struct {
			u16 regn;
			u16 regm2;
		} hdmi;
	} clocks;

	struct {
		struct omap_video_timings timings;

		int acbi;	/* ac-bias pin transitions per interrupt */
		/* Unit: line clocks */
		int acb;	/* ac-bias pin frequency */

		enum omap_panel_config config;
	} panel;

	struct {
		u8 pixel_size;
		struct rfbi_timings rfbi_timings;
	} ctrl;

	int reset_gpio;

	int max_backlight_level;

	const char *name;

	/* used to match device to driver */
	const char *driver_name;

	void *data;

	struct omap_dss_driver *driver;

	/* helper variable for driver suspend/resume */
	bool activate_after_resume;

	enum omap_display_caps caps;

	struct omap_overlay_manager *manager;

	enum omap_dss_display_state state;

	/* platform specific  */
	int (*platform_enable)(struct omap_dss_device *dssdev);
	void (*platform_disable)(struct omap_dss_device *dssdev);
	int (*set_backlight)(struct omap_dss_device *dssdev, int level);
	int (*get_backlight)(struct omap_dss_device *dssdev);
};

struct omap_dss_driver {
	struct device_driver driver;

	int (*probe)(struct omap_dss_device *);
	void (*remove)(struct omap_dss_device *);

	int (*enable)(struct omap_dss_device *display);
	void (*disable)(struct omap_dss_device *display);
	int (*suspend)(struct omap_dss_device *display);
	int (*resume)(struct omap_dss_device *display);
	int (*run_test)(struct omap_dss_device *display, int test);

	int (*set_update_mode)(struct omap_dss_device *dssdev,
			enum omap_dss_update_mode);
	enum omap_dss_update_mode (*get_update_mode)(
			struct omap_dss_device *dssdev);

	int (*update)(struct omap_dss_device *dssdev,
			       u16 x, u16 y, u16 w, u16 h);
	int (*sync)(struct omap_dss_device *dssdev);

	int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
	int (*get_te)(struct omap_dss_device *dssdev);

	u8 (*get_rotate)(struct omap_dss_device *dssdev);
	int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);

	bool (*get_mirror)(struct omap_dss_device *dssdev);
	int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);

	int (*memory_read)(struct omap_dss_device *dssdev,
			void *buf, size_t size,
			u16 x, u16 y, u16 w, u16 h);

	void (*get_resolution)(struct omap_dss_device *dssdev,
			u16 *xres, u16 *yres);
	void (*get_dimensions)(struct omap_dss_device *dssdev,
			u32 *width, u32 *height);
	int (*get_recommended_bpp)(struct omap_dss_device *dssdev);

	int (*check_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
	void (*set_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
	void (*get_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);

	int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
	u32 (*get_wss)(struct omap_dss_device *dssdev);
};

int omap_dss_register_driver(struct omap_dss_driver *);
void omap_dss_unregister_driver(struct omap_dss_driver *);

void omap_dss_get_device(struct omap_dss_device *dssdev);
void omap_dss_put_device(struct omap_dss_device *dssdev);
#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
struct omap_dss_device *omap_dss_find_device(void *data,
		int (*match)(struct omap_dss_device *dssdev, void *data));

int omap_dss_start_device(struct omap_dss_device *dssdev);
void omap_dss_stop_device(struct omap_dss_device *dssdev);

int omap_dss_get_num_overlay_managers(void);
struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);

int omap_dss_get_num_overlays(void);
struct omap_overlay *omap_dss_get_overlay(int num);

void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
		u16 *xres, u16 *yres);
int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);

typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);

int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
		unsigned long timeout);

#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)

void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
		bool enable);
int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);

int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
				    u16 *x, u16 *y, u16 *w, u16 *h,
				    bool enlarge_update_area);
int omap_dsi_update(struct omap_dss_device *dssdev,
		int channel,
		u16 x, u16 y, u16 w, u16 h,
		void (*callback)(int, void *), void *data);
int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);

int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
		bool disconnect_lanes, bool enter_ulps);

int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
void dpi_set_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
int dpi_check_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);

int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);

int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
		u16 *x, u16 *y, u16 *w, u16 *h);
int omap_rfbi_update(struct omap_dss_device *dssdev,
		u16 x, u16 y, u16 w, u16 h,
		void (*callback)(void *), void *data);
int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
		int data_lines);

#endif
Commit	Line	Data
559d6701	1	/*
559d6701 TV	2	* Copyright (C) 2008 Nokia Corporation
	3	* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
a0b38cc4 TV	18	#ifndef __OMAP_OMAPDSS_H
a0b38cc4 TV	19	#define __OMAP_OMAPDSS_H
559d6701 TV	20
	21	#include <linux/list.h>
	22	#include <linux/kobject.h>
	23	#include <linux/device.h>
b7ee79ab	24	#include <linux/platform_device.h>
559d6701 TV	25	#include <asm/atomic.h>
	26
	27	#define DISPC_IRQ_FRAMEDONE (1 << 0)
	28	#define DISPC_IRQ_VSYNC (1 << 1)
	29	#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
	30	#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
	31	#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
	32	#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
	33	#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
	34	#define DISPC_IRQ_GFX_END_WIN (1 << 7)
	35	#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
	36	#define DISPC_IRQ_OCP_ERR (1 << 9)
	37	#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
	38	#define DISPC_IRQ_VID1_END_WIN (1 << 11)
	39	#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
	40	#define DISPC_IRQ_VID2_END_WIN (1 << 13)
	41	#define DISPC_IRQ_SYNC_LOST (1 << 14)
	42	#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
	43	#define DISPC_IRQ_WAKEUP (1 << 16)
2a205f34 SS	44	#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
	45	#define DISPC_IRQ_VSYNC2 (1 << 18)
	46	#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
	47	#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
559d6701 TV	48
	49	struct omap_dss_device;
	50	struct omap_overlay_manager;
	51
	52	enum omap_display_type {
	53	OMAP_DISPLAY_TYPE_NONE = 0,
	54	OMAP_DISPLAY_TYPE_DPI = 1 << 0,
	55	OMAP_DISPLAY_TYPE_DBI = 1 << 1,
	56	OMAP_DISPLAY_TYPE_SDI = 1 << 2,
	57	OMAP_DISPLAY_TYPE_DSI = 1 << 3,
	58	OMAP_DISPLAY_TYPE_VENC = 1 << 4,
b119601d	59	OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
559d6701 TV	60	};
	61
	62	enum omap_plane {
	63	OMAP_DSS_GFX = 0,
	64	OMAP_DSS_VIDEO1 = 1,
	65	OMAP_DSS_VIDEO2 = 2
	66	};
	67
	68	enum omap_channel {
	69	OMAP_DSS_CHANNEL_LCD = 0,
	70	OMAP_DSS_CHANNEL_DIGIT = 1,
8613b000	71	OMAP_DSS_CHANNEL_LCD2 = 2,
559d6701 TV	72	};
	73
	74	enum omap_color_mode {
	75	OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
	76	OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
	77	OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
	78	OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
	79	OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
	80	OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
	81	OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
	82	OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
	83	OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
	84	OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
	85	OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
	86	OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
	87	OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
	88	OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
f20e4220 AJ	89	OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
	90	OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
	91	OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
	92	OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
	93	OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
559d6701 TV	94	};
	95
	96	enum omap_lcd_display_type {
	97	OMAP_DSS_LCD_DISPLAY_STN,
	98	OMAP_DSS_LCD_DISPLAY_TFT,
	99	};
	100
	101	enum omap_dss_load_mode {
	102	OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
	103	OMAP_DSS_LOAD_CLUT_ONLY = 1,
	104	OMAP_DSS_LOAD_FRAME_ONLY = 2,
	105	OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
	106	};
	107
	108	enum omap_dss_trans_key_type {
	109	OMAP_DSS_COLOR_KEY_GFX_DST = 0,
	110	OMAP_DSS_COLOR_KEY_VID_SRC = 1,
	111	};
	112
	113	enum omap_rfbi_te_mode {
	114	OMAP_DSS_RFBI_TE_MODE_1 = 1,
	115	OMAP_DSS_RFBI_TE_MODE_2 = 2,
	116	};
	117
	118	enum omap_panel_config {
	119	OMAP_DSS_LCD_IVS = 1<<0,
	120	OMAP_DSS_LCD_IHS = 1<<1,
	121	OMAP_DSS_LCD_IPC = 1<<2,
	122	OMAP_DSS_LCD_IEO = 1<<3,
	123	OMAP_DSS_LCD_RF = 1<<4,
	124	OMAP_DSS_LCD_ONOFF = 1<<5,
	125
	126	OMAP_DSS_LCD_TFT = 1<<20,
	127	};
	128
	129	enum omap_dss_venc_type {
	130	OMAP_DSS_VENC_TYPE_COMPOSITE,
	131	OMAP_DSS_VENC_TYPE_SVIDEO,
	132	};
	133
	134	enum omap_display_caps {
	135	OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
	136	OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
	137	};
	138
	139	enum omap_dss_update_mode {
	140	OMAP_DSS_UPDATE_DISABLED = 0,
	141	OMAP_DSS_UPDATE_AUTO,
	142	OMAP_DSS_UPDATE_MANUAL,
	143	};
	144
	145	enum omap_dss_display_state {
	146	OMAP_DSS_DISPLAY_DISABLED = 0,
	147	OMAP_DSS_DISPLAY_ACTIVE,
	148	OMAP_DSS_DISPLAY_SUSPENDED,
	149	};
	150
	151	/* XXX perhaps this should be removed */
	152	enum omap_dss_overlay_managers {
	153	OMAP_DSS_OVL_MGR_LCD,
	154	OMAP_DSS_OVL_MGR_TV,
8613b000	155	OMAP_DSS_OVL_MGR_LCD2,
559d6701 TV	156	};
	157
	158	enum omap_dss_rotation_type {
	159	OMAP_DSS_ROT_DMA = 0,
	160	OMAP_DSS_ROT_VRFB = 1,
	161	};
	162
	163	/* clockwise rotation angle */
	164	enum omap_dss_rotation_angle {
	165	OMAP_DSS_ROT_0 = 0,
	166	OMAP_DSS_ROT_90 = 1,
	167	OMAP_DSS_ROT_180 = 2,
	168	OMAP_DSS_ROT_270 = 3,
	169	};
	170
	171	enum omap_overlay_caps {
	172	OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
	173	OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
	174	};
	175
	176	enum omap_overlay_manager_caps {
	177	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
	178	};
	179
89a35e51 AT	180	enum omap_dss_clk_source {
	181	OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
	182	* OMAP4: DSS_FCLK */
	183	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
	184	* OMAP4: PLL1_CLK1 */
	185	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
	186	* OMAP4: PLL1_CLK2 */
5a8b572d AT	187	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
5a8b572d AT	188	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
89a35e51 AT	189	};
89a35e51 AT	190
559d6701 TV	191	/* RFBI */
	192
	193	struct rfbi_timings {
	194	int cs_on_time;
	195	int cs_off_time;
	196	int we_on_time;
	197	int we_off_time;
	198	int re_on_time;
	199	int re_off_time;
	200	int we_cycle_time;
	201	int re_cycle_time;
	202	int cs_pulse_width;
	203	int access_time;
	204
	205	int clk_div;
	206
	207	u32 tim[5]; /* set by rfbi_convert_timings() */
	208
	209	int converted;
	210	};
	211
	212	void omap_rfbi_write_command(const void *buf, u32 len);
	213	void omap_rfbi_read_data(void *buf, u32 len);
	214	void omap_rfbi_write_data(const void *buf, u32 len);
	215	void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
	216	u16 x, u16 y,
	217	u16 w, u16 h);
	218	int omap_rfbi_enable_te(bool enable, unsigned line);
	219	int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
	220	unsigned hs_pulse_time, unsigned vs_pulse_time,
	221	int hs_pol_inv, int vs_pol_inv, int extif_div);
773139f1 TV	222	void rfbi_bus_lock(void);
773139f1 TV	223	void rfbi_bus_unlock(void);
559d6701 TV	224
559d6701 TV	225	/* DSI */
1ffefe75 AT	226	void dsi_bus_lock(struct omap_dss_device *dssdev);
	227	void dsi_bus_unlock(struct omap_dss_device *dssdev);
	228	int dsi_vc_dcs_write(struct omap_dss_device dssdev, int channel, u8 data,
	229	int len);
	230	int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
	231	u8 dcs_cmd);
	232	int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	233	u8 param);
	234	int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
	235	u8 *data, int len);
	236	int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	237	u8 *buf, int buflen);
	238	int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	239	u8 *data);
	240	int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	241	u8 data1, u8 data2);
	242	int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
	243	u16 len);
	244	int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
	245	int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
559d6701 TV	246
	247	/* Board specific data */
	248	struct omap_dss_board_info {
	249	int (get_last_off_on_transaction_id)(struct device dev);
	250	int num_devices;
	251	struct omap_dss_device **devices;
	252	struct omap_dss_device *default_device;
d1f5857e	253	void (*dsi_mux_pads)(bool enable);
559d6701 TV	254	};
559d6701 TV	255
b7ee79ab SS	256	#if defined(CONFIG_OMAP2_DSS_MODULE) \|\| defined(CONFIG_OMAP2_DSS)
	257	/* Init with the board info */
	258	extern int omap_display_init(struct omap_dss_board_info *board_data);
	259	#else
	260	static inline int omap_display_init(struct omap_dss_board_info *board_data)
	261	{
	262	return 0;
	263	}
	264	#endif
	265
cf07f531 SG	266	struct omap_display_platform_data {
	267	struct omap_dss_board_info *board_data;
	268	/* TODO: Additional members to be added when PM is considered */
fd4b34f6 SS	269
fd4b34f6 SS	270	bool (opt_clock_available)(const char clk_role);
cf07f531 SG	271	};
cf07f531 SG	272
559d6701 TV	273	struct omap_video_timings {
	274	/* Unit: pixels */
	275	u16 x_res;
	276	/* Unit: pixels */
	277	u16 y_res;
	278	/* Unit: KHz */
	279	u32 pixel_clock;
	280	/* Unit: pixel clocks */
	281	u16 hsw; /* Horizontal synchronization pulse width */
	282	/* Unit: pixel clocks */
	283	u16 hfp; /* Horizontal front porch */
	284	/* Unit: pixel clocks */
	285	u16 hbp; /* Horizontal back porch */
	286	/* Unit: line clocks */
	287	u16 vsw; /* Vertical synchronization pulse width */
	288	/* Unit: line clocks */
	289	u16 vfp; /* Vertical front porch */
	290	/* Unit: line clocks */
	291	u16 vbp; /* Vertical back porch */
	292	};
	293
	294	#ifdef CONFIG_OMAP2_DSS_VENC
	295	/* Hardcoded timings for tv modes. Venc only uses these to
	296	* identify the mode, and does not actually use the configs
	297	* itself. However, the configs should be something that
	298	* a normal monitor can also show */
5a1819e3 TK	299	extern const struct omap_video_timings omap_dss_pal_timings;
5a1819e3 TK	300	extern const struct omap_video_timings omap_dss_ntsc_timings;
559d6701 TV	301	#endif
	302
	303	struct omap_overlay_info {
	304	bool enabled;
	305
	306	u32 paddr;
	307	void __iomem *vaddr;
	308	u16 screen_width;
	309	u16 width;
	310	u16 height;
	311	enum omap_color_mode color_mode;
	312	u8 rotation;
	313	enum omap_dss_rotation_type rotation_type;
	314	bool mirror;
	315
	316	u16 pos_x;
	317	u16 pos_y;
	318	u16 out_width; /* if 0, out_width == width */
	319	u16 out_height; /* if 0, out_height == height */
	320	u8 global_alpha;
fd28a390	321	u8 pre_mult_alpha;
559d6701 TV	322	};
	323
	324	struct omap_overlay {
	325	struct kobject kobj;
	326	struct list_head list;
	327
	328	/* static fields */
	329	const char *name;
	330	int id;
	331	enum omap_color_mode supported_modes;
	332	enum omap_overlay_caps caps;
	333
	334	/* dynamic fields */
	335	struct omap_overlay_manager *manager;
	336	struct omap_overlay_info info;
	337
	338	/* if true, info has been changed, but not applied() yet */
	339	bool info_dirty;
	340
	341	int (set_manager)(struct omap_overlay ovl,
	342	struct omap_overlay_manager *mgr);
	343	int (unset_manager)(struct omap_overlay ovl);
	344
	345	int (set_overlay_info)(struct omap_overlay ovl,
	346	struct omap_overlay_info *info);
	347	void (get_overlay_info)(struct omap_overlay ovl,
	348	struct omap_overlay_info *info);
	349
	350	int (wait_for_go)(struct omap_overlay ovl);
	351	};
	352
	353	struct omap_overlay_manager_info {
	354	u32 default_color;
	355
	356	enum omap_dss_trans_key_type trans_key_type;
	357	u32 trans_key;
	358	bool trans_enabled;
	359
	360	bool alpha_enabled;
	361	};
	362
	363	struct omap_overlay_manager {
	364	struct kobject kobj;
	365	struct list_head list;
	366
	367	/* static fields */
	368	const char *name;
	369	int id;
	370	enum omap_overlay_manager_caps caps;
	371	int num_overlays;
	372	struct omap_overlay **overlays;
	373	enum omap_display_type supported_displays;
	374
	375	/* dynamic fields */
	376	struct omap_dss_device *device;
	377	struct omap_overlay_manager_info info;
	378
	379	bool device_changed;
	380	/* if true, info has been changed but not applied() yet */
	381	bool info_dirty;
	382
	383	int (set_device)(struct omap_overlay_manager mgr,
	384	struct omap_dss_device *dssdev);
	385	int (unset_device)(struct omap_overlay_manager mgr);
386
387	int (set_manager_info)(struct omap_overlay_manager mgr,
388	struct omap_overlay_manager_info *info);
389	void (get_manager_info)(struct omap_overlay_manager mgr,
390	struct omap_overlay_manager_info *info);
391
392	int (apply)(struct omap_overlay_manager mgr);
393	int (wait_for_go)(struct omap_overlay_manager mgr);
3f71cbe7	394	int (wait_for_vsync)(struct omap_overlay_manager mgr);
a2faee84 TV	395
	396	int (enable)(struct omap_overlay_manager mgr);
	397	int (disable)(struct omap_overlay_manager mgr);
559d6701 TV	398	};
	399
	400	struct omap_dss_device {
	401	struct device dev;
	402
	403	enum omap_display_type type;
	404
18faa1b6 SS	405	enum omap_channel channel;
18faa1b6 SS	406
559d6701 TV	407	union {
	408	struct {
	409	u8 data_lines;
	410	} dpi;
	411
	412	struct {
	413	u8 channel;
	414	u8 data_lines;
	415	} rfbi;
	416
	417	struct {
	418	u8 datapairs;
	419	} sdi;
	420
	421	struct {
	422	u8 clk_lane;
	423	u8 clk_pol;
	424	u8 data1_lane;
	425	u8 data1_pol;
	426	u8 data2_lane;
	427	u8 data2_pol;
75d7247c AT	428	u8 data3_lane;
	429	u8 data3_pol;
	430	u8 data4_lane;
	431	u8 data4_pol;
559d6701	432
a72b64b9 AT	433	int module;
a72b64b9 AT	434
559d6701 TV	435	bool ext_te;
	436	u8 ext_te_gpio;
	437	} dsi;
	438
	439	struct {
	440	enum omap_dss_venc_type type;
	441	bool invert_polarity;
	442	} venc;
	443	} phy;
	444
c6940a3d TV	445	struct {
c6940a3d TV	446	struct {
e8881662 AT	447	struct {
	448	u16 lck_div;
	449	u16 pck_div;
	450	enum omap_dss_clk_source lcd_clk_src;
	451	} channel;
	452
	453	enum omap_dss_clk_source dispc_fclk_src;
c6940a3d TV	454	} dispc;
	455
	456	struct {
	457	u16 regn;
	458	u16 regm;
	459	u16 regm_dispc;
	460	u16 regm_dsi;
	461
	462	u16 lp_clk_div;
e8881662	463	enum omap_dss_clk_source dsi_fclk_src;
c6940a3d	464	} dsi;
6cb07b25 AT	465
	466	struct {
	467	u16 regn;
	468	u16 regm2;
	469	} hdmi;
c6940a3d TV	470	} clocks;
c6940a3d TV	471
559d6701 TV	472	struct {
	473	struct omap_video_timings timings;
	474
	475	int acbi; /* ac-bias pin transitions per interrupt */
	476	/* Unit: line clocks */
	477	int acb; /* ac-bias pin frequency */
	478
	479	enum omap_panel_config config;
559d6701 TV	480	} panel;
	481
	482	struct {
	483	u8 pixel_size;
	484	struct rfbi_timings rfbi_timings;
559d6701 TV	485	} ctrl;
	486
	487	int reset_gpio;
	488
	489	int max_backlight_level;
	490
	491	const char *name;
	492
	493	/* used to match device to driver */
	494	const char *driver_name;
	495
	496	void *data;
	497
	498	struct omap_dss_driver *driver;
	499
	500	/* helper variable for driver suspend/resume */
	501	bool activate_after_resume;
	502
	503	enum omap_display_caps caps;
	504
	505	struct omap_overlay_manager *manager;
	506
	507	enum omap_dss_display_state state;
	508
559d6701 TV	509	/* platform specific */
	510	int (platform_enable)(struct omap_dss_device dssdev);
	511	void (platform_disable)(struct omap_dss_device dssdev);
	512	int (set_backlight)(struct omap_dss_device dssdev, int level);
	513	int (get_backlight)(struct omap_dss_device dssdev);
	514	};
	515
	516	struct omap_dss_driver {
	517	struct device_driver driver;
	518
	519	int (probe)(struct omap_dss_device );
	520	void (remove)(struct omap_dss_device );
	521
	522	int (enable)(struct omap_dss_device display);
	523	void (disable)(struct omap_dss_device display);
	524	int (suspend)(struct omap_dss_device display);
	525	int (resume)(struct omap_dss_device display);
	526	int (run_test)(struct omap_dss_device display, int test);
	527
446f7bff TV	528	int (set_update_mode)(struct omap_dss_device dssdev,
	529	enum omap_dss_update_mode);
	530	enum omap_dss_update_mode (*get_update_mode)(
	531	struct omap_dss_device *dssdev);
559d6701	532
18946f62 TV	533	int (update)(struct omap_dss_device dssdev,
	534	u16 x, u16 y, u16 w, u16 h);
	535	int (sync)(struct omap_dss_device dssdev);
	536
559d6701	537	int (enable_te)(struct omap_dss_device dssdev, bool enable);
225b650d	538	int (get_te)(struct omap_dss_device dssdev);
559d6701 TV	539
	540	u8 (get_rotate)(struct omap_dss_device dssdev);
	541	int (set_rotate)(struct omap_dss_device dssdev, u8 rotate);
	542
	543	bool (get_mirror)(struct omap_dss_device dssdev);
	544	int (set_mirror)(struct omap_dss_device dssdev, bool enable);
	545
	546	int (memory_read)(struct omap_dss_device dssdev,
	547	void *buf, size_t size,
	548	u16 x, u16 y, u16 w, u16 h);
96adcece TV	549
	550	void (get_resolution)(struct omap_dss_device dssdev,
	551	u16 xres, u16 yres);
7a0987bf JN	552	void (get_dimensions)(struct omap_dss_device dssdev,
7a0987bf JN	553	u32 width, u32 height);
a2699504	554	int (get_recommended_bpp)(struct omap_dss_device dssdev);
36511312	555
69b2048f TV	556	int (check_timings)(struct omap_dss_device dssdev,
	557	struct omap_video_timings *timings);
	558	void (set_timings)(struct omap_dss_device dssdev,
	559	struct omap_video_timings *timings);
	560	void (get_timings)(struct omap_dss_device dssdev,
	561	struct omap_video_timings *timings);
	562
36511312 TV	563	int (set_wss)(struct omap_dss_device dssdev, u32 wss);
36511312 TV	564	u32 (get_wss)(struct omap_dss_device dssdev);
559d6701 TV	565	};
	566
	567	int omap_dss_register_driver(struct omap_dss_driver *);
	568	void omap_dss_unregister_driver(struct omap_dss_driver *);
	569
559d6701 TV	570	void omap_dss_get_device(struct omap_dss_device *dssdev);
	571	void omap_dss_put_device(struct omap_dss_device *dssdev);
	572	#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
	573	struct omap_dss_device omap_dss_get_next_device(struct omap_dss_device from);
	574	struct omap_dss_device omap_dss_find_device(void data,
	575	int (match)(struct omap_dss_device dssdev, void *data));
	576
	577	int omap_dss_start_device(struct omap_dss_device *dssdev);
	578	void omap_dss_stop_device(struct omap_dss_device *dssdev);
	579
	580	int omap_dss_get_num_overlay_managers(void);
	581	struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
	582
	583	int omap_dss_get_num_overlays(void);
	584	struct omap_overlay *omap_dss_get_overlay(int num);
	585
96adcece TV	586	void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
96adcece TV	587	u16 xres, u16 yres);
a2699504 TV	588	int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
a2699504 TV	589
559d6701 TV	590	typedef void (omap_dispc_isr_t) (void arg, u32 mask);
	591	int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
	592	int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
	593
	594	int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
	595	int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
	596	unsigned long timeout);
	597
	598	#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
	599	#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
	600
1ffefe75 AT	601	void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
1ffefe75 AT	602	bool enable);
225b650d	603	int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
61140c9a	604
18946f62	605	int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
26a8c250 TV	606	u16 x, u16 y, u16 w, u16 h,
26a8c250 TV	607	bool enlarge_update_area);
18946f62 TV	608	int omap_dsi_update(struct omap_dss_device *dssdev,
	609	int channel,
	610	u16 x, u16 y, u16 w, u16 h,
	611	void (callback)(int, void ), void *data);
5ee3c144 AT	612	int omap_dsi_request_vc(struct omap_dss_device dssdev, int channel);
	613	int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
	614	void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
18946f62	615
37ac60e4	616	int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
2a89dc15	617	void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
22d6d676	618	bool disconnect_lanes, bool enter_ulps);
37ac60e4 TV	619
	620	int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
	621	void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
69b2048f TV	622	void dpi_set_timings(struct omap_dss_device *dssdev,
	623	struct omap_video_timings *timings);
	624	int dpi_check_timings(struct omap_dss_device *dssdev,
	625	struct omap_video_timings *timings);
37ac60e4 TV	626
	627	int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
	628	void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
	629
	630	int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
	631	void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
18946f62 TV	632	int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
	633	u16 x, u16 y, u16 w, u16 h);
	634	int omap_rfbi_update(struct omap_dss_device *dssdev,
	635	u16 x, u16 y, u16 w, u16 h,
	636	void (callback)(void ), void *data);
1d5952a8 TV	637	int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
1d5952a8 TV	638	int data_lines);
18946f62	639
559d6701	640	#endif