video/omap: fix build dependencies
[linux-2.6-block.git] / include / video / omapdss.h
CommitLineData
559d6701 1/*
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2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
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18#ifndef __OMAP_OMAPDSS_H
19#define __OMAP_OMAPDSS_H
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20
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
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24
25#define DISPC_IRQ_FRAMEDONE (1 << 0)
26#define DISPC_IRQ_VSYNC (1 << 1)
27#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
28#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
29#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
30#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
31#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
32#define DISPC_IRQ_GFX_END_WIN (1 << 7)
33#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
34#define DISPC_IRQ_OCP_ERR (1 << 9)
35#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
36#define DISPC_IRQ_VID1_END_WIN (1 << 11)
37#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
38#define DISPC_IRQ_VID2_END_WIN (1 << 13)
39#define DISPC_IRQ_SYNC_LOST (1 << 14)
40#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
41#define DISPC_IRQ_WAKEUP (1 << 16)
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42#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
43#define DISPC_IRQ_VSYNC2 (1 << 18)
44#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
45#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
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46#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
47#define DISPC_IRQ_FRAMEDONETV (1 << 24)
48#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
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49
50struct omap_dss_device;
51struct omap_overlay_manager;
52
53enum omap_display_type {
54 OMAP_DISPLAY_TYPE_NONE = 0,
55 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
56 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
57 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
58 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
59 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
b119601d 60 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
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61};
62
63enum omap_plane {
64 OMAP_DSS_GFX = 0,
65 OMAP_DSS_VIDEO1 = 1,
66 OMAP_DSS_VIDEO2 = 2
67};
68
69enum omap_channel {
70 OMAP_DSS_CHANNEL_LCD = 0,
71 OMAP_DSS_CHANNEL_DIGIT = 1,
8613b000 72 OMAP_DSS_CHANNEL_LCD2 = 2,
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73};
74
75enum omap_color_mode {
76 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
77 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
78 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
79 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
80 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
81 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
82 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
83 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
84 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
85 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
86 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
87 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
88 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
89 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
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90 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
91 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
92 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
93 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
94 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
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95};
96
97enum omap_lcd_display_type {
98 OMAP_DSS_LCD_DISPLAY_STN,
99 OMAP_DSS_LCD_DISPLAY_TFT,
100};
101
102enum omap_dss_load_mode {
103 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
104 OMAP_DSS_LOAD_CLUT_ONLY = 1,
105 OMAP_DSS_LOAD_FRAME_ONLY = 2,
106 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
107};
108
109enum omap_dss_trans_key_type {
110 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
111 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
112};
113
114enum omap_rfbi_te_mode {
115 OMAP_DSS_RFBI_TE_MODE_1 = 1,
116 OMAP_DSS_RFBI_TE_MODE_2 = 2,
117};
118
119enum omap_panel_config {
120 OMAP_DSS_LCD_IVS = 1<<0,
121 OMAP_DSS_LCD_IHS = 1<<1,
122 OMAP_DSS_LCD_IPC = 1<<2,
123 OMAP_DSS_LCD_IEO = 1<<3,
124 OMAP_DSS_LCD_RF = 1<<4,
125 OMAP_DSS_LCD_ONOFF = 1<<5,
126
127 OMAP_DSS_LCD_TFT = 1<<20,
128};
129
130enum omap_dss_venc_type {
131 OMAP_DSS_VENC_TYPE_COMPOSITE,
132 OMAP_DSS_VENC_TYPE_SVIDEO,
133};
134
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135enum omap_dss_dsi_pixel_format {
136 OMAP_DSS_DSI_FMT_RGB888,
137 OMAP_DSS_DSI_FMT_RGB666,
138 OMAP_DSS_DSI_FMT_RGB666_PACKED,
139 OMAP_DSS_DSI_FMT_RGB565,
140};
141
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142enum omap_dss_dsi_mode {
143 OMAP_DSS_DSI_CMD_MODE = 0,
144 OMAP_DSS_DSI_VIDEO_MODE,
145};
146
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147enum omap_display_caps {
148 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
149 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
150};
151
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152enum omap_dss_display_state {
153 OMAP_DSS_DISPLAY_DISABLED = 0,
154 OMAP_DSS_DISPLAY_ACTIVE,
155 OMAP_DSS_DISPLAY_SUSPENDED,
156};
157
158/* XXX perhaps this should be removed */
159enum omap_dss_overlay_managers {
160 OMAP_DSS_OVL_MGR_LCD,
161 OMAP_DSS_OVL_MGR_TV,
8613b000 162 OMAP_DSS_OVL_MGR_LCD2,
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163};
164
165enum omap_dss_rotation_type {
166 OMAP_DSS_ROT_DMA = 0,
167 OMAP_DSS_ROT_VRFB = 1,
168};
169
170/* clockwise rotation angle */
171enum omap_dss_rotation_angle {
172 OMAP_DSS_ROT_0 = 0,
173 OMAP_DSS_ROT_90 = 1,
174 OMAP_DSS_ROT_180 = 2,
175 OMAP_DSS_ROT_270 = 3,
176};
177
178enum omap_overlay_caps {
179 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
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180 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
181 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
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182};
183
184enum omap_overlay_manager_caps {
4a9e78ab 185 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
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186};
187
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188enum omap_dss_clk_source {
189 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
190 * OMAP4: DSS_FCLK */
191 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
192 * OMAP4: PLL1_CLK1 */
193 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
194 * OMAP4: PLL1_CLK2 */
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195 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
196 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
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197};
198
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199/* RFBI */
200
201struct rfbi_timings {
202 int cs_on_time;
203 int cs_off_time;
204 int we_on_time;
205 int we_off_time;
206 int re_on_time;
207 int re_off_time;
208 int we_cycle_time;
209 int re_cycle_time;
210 int cs_pulse_width;
211 int access_time;
212
213 int clk_div;
214
215 u32 tim[5]; /* set by rfbi_convert_timings() */
216
217 int converted;
218};
219
220void omap_rfbi_write_command(const void *buf, u32 len);
221void omap_rfbi_read_data(void *buf, u32 len);
222void omap_rfbi_write_data(const void *buf, u32 len);
223void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
224 u16 x, u16 y,
225 u16 w, u16 h);
226int omap_rfbi_enable_te(bool enable, unsigned line);
227int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
228 unsigned hs_pulse_time, unsigned vs_pulse_time,
229 int hs_pol_inv, int vs_pol_inv, int extif_div);
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230void rfbi_bus_lock(void);
231void rfbi_bus_unlock(void);
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232
233/* DSI */
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234
235struct omap_dss_dsi_videomode_data {
236 /* DSI video mode blanking data */
237 /* Unit: byte clock cycles */
238 u16 hsa;
239 u16 hfp;
240 u16 hbp;
241 /* Unit: line clocks */
242 u16 vsa;
243 u16 vfp;
244 u16 vbp;
245
246 /* DSI blanking modes */
247 int blanking_mode;
248 int hsa_blanking_mode;
249 int hbp_blanking_mode;
250 int hfp_blanking_mode;
251
252 /* Video port sync events */
253 int vp_de_pol;
254 int vp_hsync_pol;
255 int vp_vsync_pol;
256 bool vp_vsync_end;
257 bool vp_hsync_end;
258
259 bool ddr_clk_always_on;
260 int window_sync;
261};
262
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263void dsi_bus_lock(struct omap_dss_device *dssdev);
264void dsi_bus_unlock(struct omap_dss_device *dssdev);
265int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
266 int len);
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267int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
268 int len);
269int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
270int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
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271int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
272 u8 param);
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273int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
274 u8 param);
275int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
276 u8 param1, u8 param2);
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277int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
278 u8 *data, int len);
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279int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
280 u8 *data, int len);
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281int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
282 u8 *buf, int buflen);
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283int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
284 int buflen);
285int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
286 u8 *buf, int buflen);
287int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
288 u8 param1, u8 param2, u8 *buf, int buflen);
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289int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
290 u16 len);
291int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
292int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
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293int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel);
294void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel);
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295
296/* Board specific data */
297struct omap_dss_board_info {
aac927c9 298 int (*get_context_loss_count)(struct device *dev);
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299 int num_devices;
300 struct omap_dss_device **devices;
301 struct omap_dss_device *default_device;
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302 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
303 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
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304};
305
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306#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
307/* Init with the board info */
308extern int omap_display_init(struct omap_dss_board_info *board_data);
309#else
310static inline int omap_display_init(struct omap_dss_board_info *board_data)
311{
312 return 0;
313}
314#endif
315
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316struct omap_display_platform_data {
317 struct omap_dss_board_info *board_data;
318 /* TODO: Additional members to be added when PM is considered */
319};
320
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321struct omap_video_timings {
322 /* Unit: pixels */
323 u16 x_res;
324 /* Unit: pixels */
325 u16 y_res;
326 /* Unit: KHz */
327 u32 pixel_clock;
328 /* Unit: pixel clocks */
329 u16 hsw; /* Horizontal synchronization pulse width */
330 /* Unit: pixel clocks */
331 u16 hfp; /* Horizontal front porch */
332 /* Unit: pixel clocks */
333 u16 hbp; /* Horizontal back porch */
334 /* Unit: line clocks */
335 u16 vsw; /* Vertical synchronization pulse width */
336 /* Unit: line clocks */
337 u16 vfp; /* Vertical front porch */
338 /* Unit: line clocks */
339 u16 vbp; /* Vertical back porch */
340};
341
342#ifdef CONFIG_OMAP2_DSS_VENC
343/* Hardcoded timings for tv modes. Venc only uses these to
344 * identify the mode, and does not actually use the configs
345 * itself. However, the configs should be something that
346 * a normal monitor can also show */
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347extern const struct omap_video_timings omap_dss_pal_timings;
348extern const struct omap_video_timings omap_dss_ntsc_timings;
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349#endif
350
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351struct omap_dss_cpr_coefs {
352 s16 rr, rg, rb;
353 s16 gr, gg, gb;
354 s16 br, bg, bb;
355};
356
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357struct omap_overlay_info {
358 bool enabled;
359
360 u32 paddr;
0d66cbb5 361 u32 p_uv_addr; /* for NV12 format */
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362 u16 screen_width;
363 u16 width;
364 u16 height;
365 enum omap_color_mode color_mode;
366 u8 rotation;
367 enum omap_dss_rotation_type rotation_type;
368 bool mirror;
369
370 u16 pos_x;
371 u16 pos_y;
372 u16 out_width; /* if 0, out_width == width */
373 u16 out_height; /* if 0, out_height == height */
374 u8 global_alpha;
fd28a390 375 u8 pre_mult_alpha;
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376};
377
378struct omap_overlay {
379 struct kobject kobj;
380 struct list_head list;
381
382 /* static fields */
383 const char *name;
4a9e78ab 384 enum omap_plane id;
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385 enum omap_color_mode supported_modes;
386 enum omap_overlay_caps caps;
387
388 /* dynamic fields */
389 struct omap_overlay_manager *manager;
390 struct omap_overlay_info info;
391
8fa8031c 392 bool manager_changed;
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393 /* if true, info has been changed, but not applied() yet */
394 bool info_dirty;
395
396 int (*set_manager)(struct omap_overlay *ovl,
397 struct omap_overlay_manager *mgr);
398 int (*unset_manager)(struct omap_overlay *ovl);
399
400 int (*set_overlay_info)(struct omap_overlay *ovl,
401 struct omap_overlay_info *info);
402 void (*get_overlay_info)(struct omap_overlay *ovl,
403 struct omap_overlay_info *info);
404
405 int (*wait_for_go)(struct omap_overlay *ovl);
406};
407
408struct omap_overlay_manager_info {
409 u32 default_color;
410
411 enum omap_dss_trans_key_type trans_key_type;
412 u32 trans_key;
413 bool trans_enabled;
414
415 bool alpha_enabled;
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416
417 bool cpr_enable;
418 struct omap_dss_cpr_coefs cpr_coefs;
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419};
420
421struct omap_overlay_manager {
422 struct kobject kobj;
423 struct list_head list;
424
425 /* static fields */
426 const char *name;
4a9e78ab 427 enum omap_channel id;
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428 enum omap_overlay_manager_caps caps;
429 int num_overlays;
430 struct omap_overlay **overlays;
431 enum omap_display_type supported_displays;
432
433 /* dynamic fields */
434 struct omap_dss_device *device;
435 struct omap_overlay_manager_info info;
436
437 bool device_changed;
438 /* if true, info has been changed but not applied() yet */
439 bool info_dirty;
440
441 int (*set_device)(struct omap_overlay_manager *mgr,
442 struct omap_dss_device *dssdev);
443 int (*unset_device)(struct omap_overlay_manager *mgr);
444
445 int (*set_manager_info)(struct omap_overlay_manager *mgr,
446 struct omap_overlay_manager_info *info);
447 void (*get_manager_info)(struct omap_overlay_manager *mgr,
448 struct omap_overlay_manager_info *info);
449
450 int (*apply)(struct omap_overlay_manager *mgr);
451 int (*wait_for_go)(struct omap_overlay_manager *mgr);
3f71cbe7 452 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
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453
454 int (*enable)(struct omap_overlay_manager *mgr);
455 int (*disable)(struct omap_overlay_manager *mgr);
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456};
457
458struct omap_dss_device {
459 struct device dev;
460
461 enum omap_display_type type;
462
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463 enum omap_channel channel;
464
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465 union {
466 struct {
467 u8 data_lines;
468 } dpi;
469
470 struct {
471 u8 channel;
472 u8 data_lines;
473 } rfbi;
474
475 struct {
476 u8 datapairs;
477 } sdi;
478
479 struct {
480 u8 clk_lane;
481 u8 clk_pol;
482 u8 data1_lane;
483 u8 data1_pol;
484 u8 data2_lane;
485 u8 data2_pol;
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486 u8 data3_lane;
487 u8 data3_pol;
488 u8 data4_lane;
489 u8 data4_pol;
559d6701 490
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491 int module;
492
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493 bool ext_te;
494 u8 ext_te_gpio;
495 } dsi;
496
497 struct {
498 enum omap_dss_venc_type type;
499 bool invert_polarity;
500 } venc;
501 } phy;
502
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503 struct {
504 struct {
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505 struct {
506 u16 lck_div;
507 u16 pck_div;
508 enum omap_dss_clk_source lcd_clk_src;
509 } channel;
510
511 enum omap_dss_clk_source dispc_fclk_src;
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512 } dispc;
513
514 struct {
c90a78ec 515 /* regn is one greater than TRM's REGN value */
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516 u16 regn;
517 u16 regm;
518 u16 regm_dispc;
519 u16 regm_dsi;
520
521 u16 lp_clk_div;
e8881662 522 enum omap_dss_clk_source dsi_fclk_src;
c6940a3d 523 } dsi;
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524
525 struct {
b44e4582 526 /* regn is one greater than TRM's REGN value */
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527 u16 regn;
528 u16 regm2;
529 } hdmi;
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530 } clocks;
531
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532 struct {
533 struct omap_video_timings timings;
534
535 int acbi; /* ac-bias pin transitions per interrupt */
536 /* Unit: line clocks */
537 int acb; /* ac-bias pin frequency */
538
539 enum omap_panel_config config;
7e951ee9 540
a3b3cc2b 541 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
7e951ee9 542 enum omap_dss_dsi_mode dsi_mode;
8af6ff01 543 struct omap_dss_dsi_videomode_data dsi_vm_data;
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544 } panel;
545
546 struct {
547 u8 pixel_size;
548 struct rfbi_timings rfbi_timings;
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549 } ctrl;
550
551 int reset_gpio;
552
553 int max_backlight_level;
554
555 const char *name;
556
557 /* used to match device to driver */
558 const char *driver_name;
559
560 void *data;
561
562 struct omap_dss_driver *driver;
563
564 /* helper variable for driver suspend/resume */
565 bool activate_after_resume;
566
567 enum omap_display_caps caps;
568
569 struct omap_overlay_manager *manager;
570
571 enum omap_dss_display_state state;
572
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573 /* platform specific */
574 int (*platform_enable)(struct omap_dss_device *dssdev);
575 void (*platform_disable)(struct omap_dss_device *dssdev);
576 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
577 int (*get_backlight)(struct omap_dss_device *dssdev);
578};
579
580struct omap_dss_driver {
581 struct device_driver driver;
582
583 int (*probe)(struct omap_dss_device *);
584 void (*remove)(struct omap_dss_device *);
585
586 int (*enable)(struct omap_dss_device *display);
587 void (*disable)(struct omap_dss_device *display);
588 int (*suspend)(struct omap_dss_device *display);
589 int (*resume)(struct omap_dss_device *display);
590 int (*run_test)(struct omap_dss_device *display, int test);
591
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592 int (*update)(struct omap_dss_device *dssdev,
593 u16 x, u16 y, u16 w, u16 h);
594 int (*sync)(struct omap_dss_device *dssdev);
595
559d6701 596 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
225b650d 597 int (*get_te)(struct omap_dss_device *dssdev);
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598
599 u8 (*get_rotate)(struct omap_dss_device *dssdev);
600 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
601
602 bool (*get_mirror)(struct omap_dss_device *dssdev);
603 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
604
605 int (*memory_read)(struct omap_dss_device *dssdev,
606 void *buf, size_t size,
607 u16 x, u16 y, u16 w, u16 h);
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608
609 void (*get_resolution)(struct omap_dss_device *dssdev,
610 u16 *xres, u16 *yres);
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611 void (*get_dimensions)(struct omap_dss_device *dssdev,
612 u32 *width, u32 *height);
a2699504 613 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
36511312 614
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615 int (*check_timings)(struct omap_dss_device *dssdev,
616 struct omap_video_timings *timings);
617 void (*set_timings)(struct omap_dss_device *dssdev,
618 struct omap_video_timings *timings);
619 void (*get_timings)(struct omap_dss_device *dssdev,
620 struct omap_video_timings *timings);
621
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622 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
623 u32 (*get_wss)(struct omap_dss_device *dssdev);
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624
625 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
df4769c9 626 bool (*detect)(struct omap_dss_device *dssdev);
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627};
628
629int omap_dss_register_driver(struct omap_dss_driver *);
630void omap_dss_unregister_driver(struct omap_dss_driver *);
631
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632void omap_dss_get_device(struct omap_dss_device *dssdev);
633void omap_dss_put_device(struct omap_dss_device *dssdev);
634#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
635struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
636struct omap_dss_device *omap_dss_find_device(void *data,
637 int (*match)(struct omap_dss_device *dssdev, void *data));
638
639int omap_dss_start_device(struct omap_dss_device *dssdev);
640void omap_dss_stop_device(struct omap_dss_device *dssdev);
641
642int omap_dss_get_num_overlay_managers(void);
643struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
644
645int omap_dss_get_num_overlays(void);
646struct omap_overlay *omap_dss_get_overlay(int num);
647
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648void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
649 u16 *xres, u16 *yres);
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650int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
651
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652typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
653int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
654int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
655
656int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
657int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
658 unsigned long timeout);
659
660#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
661#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
662
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663void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
664 bool enable);
225b650d 665int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
61140c9a 666
18946f62 667int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
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668 u16 *x, u16 *y, u16 *w, u16 *h,
669 bool enlarge_update_area);
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670int omap_dsi_update(struct omap_dss_device *dssdev,
671 int channel,
672 u16 x, u16 y, u16 w, u16 h,
673 void (*callback)(int, void *), void *data);
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674int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
675int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
676void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
18946f62 677
37ac60e4 678int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
2a89dc15 679void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
22d6d676 680 bool disconnect_lanes, bool enter_ulps);
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681
682int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
683void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
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684void dpi_set_timings(struct omap_dss_device *dssdev,
685 struct omap_video_timings *timings);
686int dpi_check_timings(struct omap_dss_device *dssdev,
687 struct omap_video_timings *timings);
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688
689int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
690void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
691
692int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
693void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
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694int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
695 u16 *x, u16 *y, u16 *w, u16 *h);
696int omap_rfbi_update(struct omap_dss_device *dssdev,
697 u16 x, u16 y, u16 w, u16 h,
698 void (*callback)(void *), void *data);
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699int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
700 int data_lines);
18946f62 701
559d6701 702#endif