Commit | Line | Data |
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aecfbdb1 SH |
1 | /* |
2 | * Copyright 2005-2009 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU Lesser General | |
5 | * Public License. You may obtain a copy of the GNU Lesser General | |
6 | * Public License Version 2.1 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/lgpl-license.html | |
9 | * http://www.gnu.org/copyleft/lgpl.html | |
10 | */ | |
11 | ||
12 | #ifndef __DRM_IPU_H__ | |
13 | #define __DRM_IPU_H__ | |
14 | ||
15 | #include <linux/types.h> | |
16 | #include <linux/videodev2.h> | |
17 | #include <linux/bitmap.h> | |
18 | #include <linux/fb.h> | |
310944d1 | 19 | #include <linux/of.h> |
2ffd48f2 | 20 | #include <media/v4l2-mediabus.h> |
6541d710 | 21 | #include <video/videomode.h> |
aecfbdb1 SH |
22 | |
23 | struct ipu_soc; | |
24 | ||
25 | enum ipuv3_type { | |
26 | IPUV3EX, | |
27 | IPUV3M, | |
28 | IPUV3H, | |
29 | }; | |
30 | ||
7f4392aa PZ |
31 | #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3') |
32 | ||
aecfbdb1 SH |
33 | /* |
34 | * Bitfield of Display Interface signal polarities. | |
35 | */ | |
36 | struct ipu_di_signal_cfg { | |
aecfbdb1 SH |
37 | unsigned data_pol:1; /* true = inverted */ |
38 | unsigned clk_pol:1; /* true = rising edge */ | |
39 | unsigned enable_pol:1; | |
aecfbdb1 | 40 | |
b6835a71 SL |
41 | struct videomode mode; |
42 | ||
2872c807 | 43 | u32 bus_format; |
aecfbdb1 | 44 | u32 v_to_h_sync; |
b6835a71 | 45 | |
aecfbdb1 SH |
46 | #define IPU_DI_CLKMODE_SYNC (1 << 0) |
47 | #define IPU_DI_CLKMODE_EXT (1 << 1) | |
48 | unsigned long clkflags; | |
2ea42608 PZ |
49 | |
50 | u8 hsync_pin; | |
51 | u8 vsync_pin; | |
aecfbdb1 SH |
52 | }; |
53 | ||
2ffd48f2 SL |
54 | /* |
55 | * Enumeration of CSI destinations | |
56 | */ | |
57 | enum ipu_csi_dest { | |
58 | IPU_CSI_DEST_IDMAC, /* to memory via SMFC */ | |
59 | IPU_CSI_DEST_IC, /* to Image Converter */ | |
60 | IPU_CSI_DEST_VDIC, /* to VDIC */ | |
61 | }; | |
62 | ||
1aa8ea0d SL |
63 | /* |
64 | * Enumeration of IPU rotation modes | |
65 | */ | |
8b9c3d50 SL |
66 | #define IPU_ROT_BIT_VFLIP (1 << 0) |
67 | #define IPU_ROT_BIT_HFLIP (1 << 1) | |
68 | #define IPU_ROT_BIT_90 (1 << 2) | |
69 | ||
1aa8ea0d SL |
70 | enum ipu_rotate_mode { |
71 | IPU_ROTATE_NONE = 0, | |
8b9c3d50 SL |
72 | IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP, |
73 | IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP, | |
74 | IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP), | |
75 | IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90, | |
76 | IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP), | |
77 | IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP), | |
78 | IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 | | |
79 | IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP), | |
1aa8ea0d SL |
80 | }; |
81 | ||
8b9c3d50 SL |
82 | /* 90-degree rotations require the IRT unit */ |
83 | #define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0) | |
84 | ||
aecfbdb1 SH |
85 | enum ipu_color_space { |
86 | IPUV3_COLORSPACE_RGB, | |
87 | IPUV3_COLORSPACE_YUV, | |
88 | IPUV3_COLORSPACE_UNKNOWN, | |
89 | }; | |
90 | ||
2d2ead45 SL |
91 | /* |
92 | * Enumeration of VDI MOTION select | |
93 | */ | |
94 | enum ipu_motion_sel { | |
95 | MOTION_NONE = 0, | |
96 | LOW_MOTION, | |
97 | MED_MOTION, | |
98 | HIGH_MOTION, | |
99 | }; | |
100 | ||
aecfbdb1 SH |
101 | struct ipuv3_channel; |
102 | ||
103 | enum ipu_channel_irq { | |
104 | IPU_IRQ_EOF = 0, | |
105 | IPU_IRQ_NFACK = 64, | |
106 | IPU_IRQ_NFB4EOF = 128, | |
107 | IPU_IRQ_EOS = 192, | |
108 | }; | |
109 | ||
a4cd8f22 SL |
110 | /* |
111 | * Enumeration of IDMAC channels | |
112 | */ | |
113 | #define IPUV3_CHANNEL_CSI0 0 | |
114 | #define IPUV3_CHANNEL_CSI1 1 | |
115 | #define IPUV3_CHANNEL_CSI2 2 | |
116 | #define IPUV3_CHANNEL_CSI3 3 | |
117 | #define IPUV3_CHANNEL_VDI_MEM_IC_VF 5 | |
ac4708fa SL |
118 | /* |
119 | * NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels, | |
120 | * but the direct CSI->VDI linking is handled the same way as IDMAC | |
121 | * channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so | |
122 | * these channel names are used to support the direct CSI->VDI link. | |
123 | */ | |
124 | #define IPUV3_CHANNEL_CSI_DIRECT 6 | |
125 | #define IPUV3_CHANNEL_CSI_VDI_PREV 7 | |
97afc25c SL |
126 | #define IPUV3_CHANNEL_MEM_VDI_PREV 8 |
127 | #define IPUV3_CHANNEL_MEM_VDI_CUR 9 | |
128 | #define IPUV3_CHANNEL_MEM_VDI_NEXT 10 | |
a4cd8f22 SL |
129 | #define IPUV3_CHANNEL_MEM_IC_PP 11 |
130 | #define IPUV3_CHANNEL_MEM_IC_PRP_VF 12 | |
bc0a3387 | 131 | #define IPUV3_CHANNEL_VDI_MEM_RECENT 13 |
a4cd8f22 SL |
132 | #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14 |
133 | #define IPUV3_CHANNEL_G_MEM_IC_PP 15 | |
bc0a3387 PZ |
134 | #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17 |
135 | #define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18 | |
136 | #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19 | |
a4cd8f22 SL |
137 | #define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20 |
138 | #define IPUV3_CHANNEL_IC_PRP_VF_MEM 21 | |
139 | #define IPUV3_CHANNEL_IC_PP_MEM 22 | |
140 | #define IPUV3_CHANNEL_MEM_BG_SYNC 23 | |
141 | #define IPUV3_CHANNEL_MEM_BG_ASYNC 24 | |
bc0a3387 PZ |
142 | #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25 |
143 | #define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26 | |
a4cd8f22 SL |
144 | #define IPUV3_CHANNEL_MEM_FG_SYNC 27 |
145 | #define IPUV3_CHANNEL_MEM_DC_SYNC 28 | |
146 | #define IPUV3_CHANNEL_MEM_FG_ASYNC 29 | |
147 | #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31 | |
bc0a3387 PZ |
148 | #define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33 |
149 | #define IPUV3_CHANNEL_DC_MEM_READ 40 | |
a4cd8f22 | 150 | #define IPUV3_CHANNEL_MEM_DC_ASYNC 41 |
bc0a3387 PZ |
151 | #define IPUV3_CHANNEL_MEM_DC_COMMAND 42 |
152 | #define IPUV3_CHANNEL_MEM_DC_COMMAND2 43 | |
153 | #define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44 | |
a4cd8f22 SL |
154 | #define IPUV3_CHANNEL_MEM_ROT_ENC 45 |
155 | #define IPUV3_CHANNEL_MEM_ROT_VF 46 | |
156 | #define IPUV3_CHANNEL_MEM_ROT_PP 47 | |
157 | #define IPUV3_CHANNEL_ROT_ENC_MEM 48 | |
158 | #define IPUV3_CHANNEL_ROT_VF_MEM 49 | |
159 | #define IPUV3_CHANNEL_ROT_PP_MEM 50 | |
160 | #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51 | |
bc0a3387 | 161 | #define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52 |
ac4708fa | 162 | #define IPUV3_NUM_CHANNELS 64 |
a4cd8f22 | 163 | |
e72db3b1 PZ |
164 | static inline int ipu_channel_alpha_channel(int ch_num) |
165 | { | |
166 | switch (ch_num) { | |
167 | case IPUV3_CHANNEL_G_MEM_IC_PRP_VF: | |
168 | return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA; | |
169 | case IPUV3_CHANNEL_G_MEM_IC_PP: | |
170 | return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA; | |
171 | case IPUV3_CHANNEL_MEM_FG_SYNC: | |
172 | return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA; | |
173 | case IPUV3_CHANNEL_MEM_FG_ASYNC: | |
174 | return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA; | |
175 | case IPUV3_CHANNEL_MEM_BG_SYNC: | |
176 | return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA; | |
177 | case IPUV3_CHANNEL_MEM_BG_ASYNC: | |
178 | return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA; | |
179 | case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB: | |
180 | return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA; | |
181 | default: | |
182 | return -EINVAL; | |
183 | } | |
184 | } | |
185 | ||
861a50c1 | 186 | int ipu_map_irq(struct ipu_soc *ipu, int irq); |
aecfbdb1 SH |
187 | int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, |
188 | enum ipu_channel_irq irq); | |
189 | ||
190 | #define IPU_IRQ_DP_SF_START (448 + 2) | |
191 | #define IPU_IRQ_DP_SF_END (448 + 3) | |
192 | #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END, | |
193 | #define IPU_IRQ_DC_FC_0 (448 + 8) | |
194 | #define IPU_IRQ_DC_FC_1 (448 + 9) | |
195 | #define IPU_IRQ_DC_FC_2 (448 + 10) | |
196 | #define IPU_IRQ_DC_FC_3 (448 + 11) | |
197 | #define IPU_IRQ_DC_FC_4 (448 + 12) | |
198 | #define IPU_IRQ_DC_FC_6 (448 + 13) | |
199 | #define IPU_IRQ_VSYNC_PRE_0 (448 + 14) | |
200 | #define IPU_IRQ_VSYNC_PRE_1 (448 + 15) | |
201 | ||
ba07975f SL |
202 | /* |
203 | * IPU Common functions | |
204 | */ | |
572a7615 | 205 | int ipu_get_num(struct ipu_soc *ipu); |
ba07975f SL |
206 | void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2); |
207 | void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi); | |
3feb049f | 208 | void ipu_dump(struct ipu_soc *ipu); |
ba07975f | 209 | |
aecfbdb1 SH |
210 | /* |
211 | * IPU Image DMA Controller (idmac) functions | |
212 | */ | |
213 | struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel); | |
214 | void ipu_idmac_put(struct ipuv3_channel *); | |
215 | ||
216 | int ipu_idmac_enable_channel(struct ipuv3_channel *channel); | |
217 | int ipu_idmac_disable_channel(struct ipuv3_channel *channel); | |
2bcf577e | 218 | void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable); |
4fd1a07a | 219 | int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts); |
fb822a39 | 220 | int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms); |
aecfbdb1 SH |
221 | |
222 | void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, | |
223 | bool doublebuffer); | |
e9046097 | 224 | int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel); |
aa52f578 | 225 | bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num); |
aecfbdb1 | 226 | void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num); |
bce6f087 | 227 | void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num); |
ac4708fa SL |
228 | int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch); |
229 | int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch); | |
230 | int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink); | |
231 | int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink); | |
aecfbdb1 | 232 | |
7d2691da SL |
233 | /* |
234 | * IPU Channel Parameter Memory (cpmem) functions | |
235 | */ | |
236 | struct ipu_rgb { | |
237 | struct fb_bitfield red; | |
238 | struct fb_bitfield green; | |
239 | struct fb_bitfield blue; | |
240 | struct fb_bitfield transp; | |
241 | int bits_per_pixel; | |
242 | }; | |
243 | ||
244 | struct ipu_image { | |
245 | struct v4l2_pix_format pix; | |
246 | struct v4l2_rect rect; | |
2094b603 SL |
247 | dma_addr_t phys0; |
248 | dma_addr_t phys1; | |
dec408fd SL |
249 | /* chroma plane offset overrides */ |
250 | u32 u_offset; | |
251 | u32 v_offset; | |
7d2691da SL |
252 | }; |
253 | ||
254 | void ipu_cpmem_zero(struct ipuv3_channel *ch); | |
255 | void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres); | |
e1e9733c | 256 | void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch); |
7d2691da SL |
257 | void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride); |
258 | void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch); | |
259 | void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf); | |
e5e8690f | 260 | void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off); |
9b5c8d5f SL |
261 | void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride, |
262 | u32 pixelformat); | |
555f0e66 | 263 | void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id); |
03085911 | 264 | int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch); |
7d2691da | 265 | void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize); |
9b9da0be | 266 | void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch); |
c42d37ca SL |
267 | void ipu_cpmem_set_rotation(struct ipuv3_channel *ch, |
268 | enum ipu_rotate_mode rot); | |
7d2691da SL |
269 | int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch, |
270 | const struct ipu_rgb *rgb); | |
271 | int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width); | |
272 | void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format); | |
273 | void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, | |
90195c36 PZ |
274 | unsigned int uv_stride, |
275 | unsigned int u_offset, | |
276 | unsigned int v_offset); | |
7d2691da SL |
277 | int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc); |
278 | int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image); | |
60c04456 | 279 | void ipu_cpmem_dump(struct ipuv3_channel *ch); |
7d2691da | 280 | |
aecfbdb1 SH |
281 | /* |
282 | * IPU Display Controller (dc) functions | |
283 | */ | |
284 | struct ipu_dc; | |
285 | struct ipu_di; | |
286 | struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel); | |
287 | void ipu_dc_put(struct ipu_dc *dc); | |
288 | int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, | |
289 | u32 pixel_fmt, u32 width); | |
1e6d486b | 290 | void ipu_dc_enable(struct ipu_soc *ipu); |
aecfbdb1 SH |
291 | void ipu_dc_enable_channel(struct ipu_dc *dc); |
292 | void ipu_dc_disable_channel(struct ipu_dc *dc); | |
1e6d486b | 293 | void ipu_dc_disable(struct ipu_soc *ipu); |
aecfbdb1 SH |
294 | |
295 | /* | |
296 | * IPU Display Interface (di) functions | |
297 | */ | |
298 | struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp); | |
299 | void ipu_di_put(struct ipu_di *); | |
300 | int ipu_di_disable(struct ipu_di *); | |
301 | int ipu_di_enable(struct ipu_di *); | |
302 | int ipu_di_get_num(struct ipu_di *); | |
6541d710 | 303 | int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode); |
aecfbdb1 SH |
304 | int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig); |
305 | ||
306 | /* | |
307 | * IPU Display Multi FIFO Controller (dmfc) functions | |
308 | */ | |
309 | struct dmfc_channel; | |
310 | int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc); | |
311 | void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc); | |
27630c20 | 312 | void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width); |
aecfbdb1 SH |
313 | struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel); |
314 | void ipu_dmfc_put(struct dmfc_channel *dmfc); | |
315 | ||
316 | /* | |
317 | * IPU Display Processor (dp) functions | |
318 | */ | |
319 | #define IPU_DP_FLOW_SYNC_BG 0 | |
320 | #define IPU_DP_FLOW_SYNC_FG 1 | |
321 | #define IPU_DP_FLOW_ASYNC0_BG 2 | |
322 | #define IPU_DP_FLOW_ASYNC0_FG 3 | |
323 | #define IPU_DP_FLOW_ASYNC1_BG 4 | |
324 | #define IPU_DP_FLOW_ASYNC1_FG 5 | |
325 | ||
326 | struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow); | |
327 | void ipu_dp_put(struct ipu_dp *); | |
285bbb01 | 328 | int ipu_dp_enable(struct ipu_soc *ipu); |
aecfbdb1 | 329 | int ipu_dp_enable_channel(struct ipu_dp *dp); |
f9bb7acb | 330 | void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync); |
285bbb01 | 331 | void ipu_dp_disable(struct ipu_soc *ipu); |
aecfbdb1 SH |
332 | int ipu_dp_setup_channel(struct ipu_dp *dp, |
333 | enum ipu_color_space in, enum ipu_color_space out); | |
334 | int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos); | |
335 | int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha, | |
336 | bool bg_chan); | |
337 | ||
ea9c2605 LS |
338 | /* |
339 | * IPU Prefetch Resolve Gasket (prg) functions | |
340 | */ | |
341 | int ipu_prg_max_active_channels(void); | |
342 | bool ipu_prg_present(struct ipu_soc *ipu); | |
343 | bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format, | |
344 | uint64_t modifier); | |
345 | int ipu_prg_enable(struct ipu_soc *ipu); | |
346 | void ipu_prg_disable(struct ipu_soc *ipu); | |
347 | void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan); | |
348 | int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan, | |
349 | unsigned int axi_id, unsigned int width, | |
350 | unsigned int height, unsigned int stride, | |
a2ceec52 | 351 | u32 format, uint64_t modifier, unsigned long *eba); |
4bfbd561 | 352 | bool ipu_prg_channel_configure_pending(struct ipuv3_channel *ipu_chan); |
ea9c2605 | 353 | |
3f5a8a94 PZ |
354 | /* |
355 | * IPU CMOS Sensor Interface (csi) functions | |
356 | */ | |
2ffd48f2 SL |
357 | struct ipu_csi; |
358 | int ipu_csi_init_interface(struct ipu_csi *csi, | |
fc8c7238 SL |
359 | const struct v4l2_mbus_config *mbus_cfg, |
360 | const struct v4l2_mbus_framefmt *infmt, | |
361 | const struct v4l2_mbus_framefmt *outfmt); | |
2ffd48f2 SL |
362 | bool ipu_csi_is_interlaced(struct ipu_csi *csi); |
363 | void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w); | |
364 | void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w); | |
867341b9 | 365 | void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert); |
2ffd48f2 SL |
366 | void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active, |
367 | u32 r_value, u32 g_value, u32 b_value, | |
368 | u32 pix_clk); | |
369 | int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc, | |
370 | struct v4l2_mbus_framefmt *mbus_fmt); | |
371 | int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip, | |
372 | u32 max_ratio, u32 id); | |
373 | int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest); | |
374 | int ipu_csi_enable(struct ipu_csi *csi); | |
375 | int ipu_csi_disable(struct ipu_csi *csi); | |
376 | struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id); | |
377 | void ipu_csi_put(struct ipu_csi *csi); | |
378 | void ipu_csi_dump(struct ipu_csi *csi); | |
3f5a8a94 | 379 | |
1aa8ea0d SL |
380 | /* |
381 | * IPU Image Converter (ic) functions | |
382 | */ | |
383 | enum ipu_ic_task { | |
384 | IC_TASK_ENCODER, | |
385 | IC_TASK_VIEWFINDER, | |
386 | IC_TASK_POST_PROCESSOR, | |
387 | IC_NUM_TASKS, | |
388 | }; | |
389 | ||
f208b26e SL |
390 | /* |
391 | * The parameters that describe a colorspace according to the | |
392 | * Image Converter: | |
393 | * - Y'CbCr encoding | |
394 | * - quantization | |
395 | * - "colorspace" (RGB or YUV). | |
396 | */ | |
397 | struct ipu_ic_colorspace { | |
398 | enum v4l2_ycbcr_encoding enc; | |
399 | enum v4l2_quantization quant; | |
400 | enum ipu_color_space cs; | |
401 | }; | |
402 | ||
403 | static inline void | |
404 | ipu_ic_fill_colorspace(struct ipu_ic_colorspace *ic_cs, | |
405 | enum v4l2_ycbcr_encoding enc, | |
406 | enum v4l2_quantization quant, | |
407 | enum ipu_color_space cs) | |
408 | { | |
409 | ic_cs->enc = enc; | |
410 | ic_cs->quant = quant; | |
411 | ic_cs->cs = cs; | |
412 | } | |
413 | ||
414 | struct ipu_ic_csc_params { | |
415 | s16 coeff[3][3]; /* signed 9-bit integer coefficients */ | |
416 | s16 offset[3]; /* signed 11+2-bit fixed point offset */ | |
417 | u8 scale:2; /* scale coefficients * 2^(scale-1) */ | |
418 | bool sat:1; /* saturate to (16, 235(Y) / 240(U, V)) */ | |
419 | }; | |
420 | ||
421 | struct ipu_ic_csc { | |
422 | struct ipu_ic_colorspace in_cs; | |
423 | struct ipu_ic_colorspace out_cs; | |
424 | struct ipu_ic_csc_params params; | |
425 | }; | |
426 | ||
1aa8ea0d | 427 | struct ipu_ic; |
f208b26e SL |
428 | |
429 | int __ipu_ic_calc_csc(struct ipu_ic_csc *csc); | |
430 | int ipu_ic_calc_csc(struct ipu_ic_csc *csc, | |
431 | enum v4l2_ycbcr_encoding in_enc, | |
432 | enum v4l2_quantization in_quant, | |
433 | enum ipu_color_space in_cs, | |
434 | enum v4l2_ycbcr_encoding out_enc, | |
435 | enum v4l2_quantization out_quant, | |
436 | enum ipu_color_space out_cs); | |
1aa8ea0d | 437 | int ipu_ic_task_init(struct ipu_ic *ic, |
f208b26e | 438 | const struct ipu_ic_csc *csc, |
1aa8ea0d | 439 | int in_width, int in_height, |
f208b26e | 440 | int out_width, int out_height); |
d0cbc93a | 441 | int ipu_ic_task_init_rsc(struct ipu_ic *ic, |
f208b26e | 442 | const struct ipu_ic_csc *csc, |
d0cbc93a PZ |
443 | int in_width, int in_height, |
444 | int out_width, int out_height, | |
d0cbc93a | 445 | u32 rsc); |
1aa8ea0d | 446 | int ipu_ic_task_graphics_init(struct ipu_ic *ic, |
f208b26e | 447 | const struct ipu_ic_colorspace *g_in_cs, |
1aa8ea0d SL |
448 | bool galpha_en, u32 galpha, |
449 | bool colorkey_en, u32 colorkey); | |
450 | void ipu_ic_task_enable(struct ipu_ic *ic); | |
451 | void ipu_ic_task_disable(struct ipu_ic *ic); | |
452 | int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel, | |
453 | u32 width, u32 height, int burst_size, | |
454 | enum ipu_rotate_mode rot); | |
455 | int ipu_ic_enable(struct ipu_ic *ic); | |
456 | int ipu_ic_disable(struct ipu_ic *ic); | |
457 | struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task); | |
458 | void ipu_ic_put(struct ipu_ic *ic); | |
459 | void ipu_ic_dump(struct ipu_ic *ic); | |
460 | ||
2d2ead45 SL |
461 | /* |
462 | * IPU Video De-Interlacer (vdi) functions | |
463 | */ | |
464 | struct ipu_vdi; | |
465 | void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field); | |
466 | void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel); | |
467 | void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres); | |
468 | void ipu_vdi_unsetup(struct ipu_vdi *vdi); | |
469 | int ipu_vdi_enable(struct ipu_vdi *vdi); | |
470 | int ipu_vdi_disable(struct ipu_vdi *vdi); | |
471 | struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu); | |
472 | void ipu_vdi_put(struct ipu_vdi *vdi); | |
473 | ||
35de925f PZ |
474 | /* |
475 | * IPU Sensor Multiple FIFO Controller (SMFC) functions | |
476 | */ | |
7fafa8f0 SL |
477 | struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno); |
478 | void ipu_smfc_put(struct ipu_smfc *smfc); | |
479 | int ipu_smfc_enable(struct ipu_smfc *smfc); | |
480 | int ipu_smfc_disable(struct ipu_smfc *smfc); | |
481 | int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id); | |
482 | int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize); | |
a2be35e3 | 483 | int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level); |
35de925f | 484 | |
7cb17797 | 485 | enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc); |
aecfbdb1 | 486 | enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat); |
ae0e9708 | 487 | enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code); |
6930afdc | 488 | int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat); |
4cea940d | 489 | bool ipu_pixelformat_is_planar(u32 pixelformat); |
f835f386 SL |
490 | int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees, |
491 | bool hflip, bool vflip); | |
492 | int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode, | |
493 | bool hflip, bool vflip); | |
aecfbdb1 | 494 | |
aecfbdb1 | 495 | struct ipu_client_platformdata { |
d6ca8ca7 | 496 | int csi; |
aecfbdb1 SH |
497 | int di; |
498 | int dc; | |
499 | int dp; | |
aecfbdb1 | 500 | int dma[2]; |
310944d1 | 501 | struct device_node *of_node; |
aecfbdb1 SH |
502 | }; |
503 | ||
504 | #endif /* __DRM_IPU_H__ */ |