[linux-block.git] / include / ufs / ufshci.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Universal Flash Storage Host controller driver
 * Copyright (C) 2011-2013 Samsung India Software Operations
 *
 * Authors:
 *	Santosh Yaraganavi <santosh.sy@samsung.com>
 *	Vinayak Holikatti <h.vinayak@samsung.com>
 */

#ifndef _UFSHCI_H
#define _UFSHCI_H

#include <scsi/scsi_host.h>

enum {
	TASK_REQ_UPIU_SIZE_DWORDS	= 8,
	TASK_RSP_UPIU_SIZE_DWORDS	= 8,
	ALIGNED_UPIU_SIZE		= 512,
};

/* UFSHCI Registers */
enum {
	REG_CONTROLLER_CAPABILITIES		= 0x00,
	REG_UFS_VERSION				= 0x08,
	REG_CONTROLLER_DEV_ID			= 0x10,
	REG_CONTROLLER_PROD_ID			= 0x14,
	REG_AUTO_HIBERNATE_IDLE_TIMER		= 0x18,
	REG_INTERRUPT_STATUS			= 0x20,
	REG_INTERRUPT_ENABLE			= 0x24,
	REG_CONTROLLER_STATUS			= 0x30,
	REG_CONTROLLER_ENABLE			= 0x34,
	REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER	= 0x38,
	REG_UIC_ERROR_CODE_DATA_LINK_LAYER	= 0x3C,
	REG_UIC_ERROR_CODE_NETWORK_LAYER	= 0x40,
	REG_UIC_ERROR_CODE_TRANSPORT_LAYER	= 0x44,
	REG_UIC_ERROR_CODE_DME			= 0x48,
	REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL	= 0x4C,
	REG_UTP_TRANSFER_REQ_LIST_BASE_L	= 0x50,
	REG_UTP_TRANSFER_REQ_LIST_BASE_H	= 0x54,
	REG_UTP_TRANSFER_REQ_DOOR_BELL		= 0x58,
	REG_UTP_TRANSFER_REQ_LIST_CLEAR		= 0x5C,
	REG_UTP_TRANSFER_REQ_LIST_RUN_STOP	= 0x60,
	REG_UTP_TASK_REQ_LIST_BASE_L		= 0x70,
	REG_UTP_TASK_REQ_LIST_BASE_H		= 0x74,
	REG_UTP_TASK_REQ_DOOR_BELL		= 0x78,
	REG_UTP_TASK_REQ_LIST_CLEAR		= 0x7C,
	REG_UTP_TASK_REQ_LIST_RUN_STOP		= 0x80,
	REG_UIC_COMMAND				= 0x90,
	REG_UIC_COMMAND_ARG_1			= 0x94,
	REG_UIC_COMMAND_ARG_2			= 0x98,
	REG_UIC_COMMAND_ARG_3			= 0x9C,

	UFSHCI_REG_SPACE_SIZE			= 0xA0,

	REG_UFS_CCAP				= 0x100,
	REG_UFS_CRYPTOCAP			= 0x104,

	UFSHCI_CRYPTO_REG_SPACE_SIZE		= 0x400,
};

/* Controller capability masks */
enum {
	MASK_TRANSFER_REQUESTS_SLOTS		= 0x0000001F,
	MASK_TASK_MANAGEMENT_REQUEST_SLOTS	= 0x00070000,
	MASK_AUTO_HIBERN8_SUPPORT		= 0x00800000,
	MASK_64_ADDRESSING_SUPPORT		= 0x01000000,
	MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT	= 0x02000000,
	MASK_UIC_DME_TEST_MODE_SUPPORT		= 0x04000000,
	MASK_CRYPTO_SUPPORT			= 0x10000000,
};

#define UFS_MASK(mask, offset)		((mask) << (offset))

/* UFS Version 08h */
#define MINOR_VERSION_NUM_MASK		UFS_MASK(0xFFFF, 0)
#define MAJOR_VERSION_NUM_MASK		UFS_MASK(0xFFFF, 16)

/*
 * Controller UFSHCI version
 * - 2.x and newer use the following scheme:
 *   major << 8 + minor << 4
 * - 1.x has been converted to match this in
 *   ufshcd_get_ufs_version()
 */
static inline u32 ufshci_version(u32 major, u32 minor)
{
	return (major << 8) + (minor << 4);
}

/*
 * HCDDID - Host Controller Identification Descriptor
 *	  - Device ID and Device Class 10h
 */
#define DEVICE_CLASS	UFS_MASK(0xFFFF, 0)
#define DEVICE_ID	UFS_MASK(0xFF, 24)

/*
 * HCPMID - Host Controller Identification Descriptor
 *	  - Product/Manufacturer ID  14h
 */
#define MANUFACTURE_ID_MASK	UFS_MASK(0xFFFF, 0)
#define PRODUCT_ID_MASK		UFS_MASK(0xFFFF, 16)

/* AHIT - Auto-Hibernate Idle Timer */
#define UFSHCI_AHIBERN8_TIMER_MASK		GENMASK(9, 0)
#define UFSHCI_AHIBERN8_SCALE_MASK		GENMASK(12, 10)
#define UFSHCI_AHIBERN8_SCALE_FACTOR		10
#define UFSHCI_AHIBERN8_MAX			(1023 * 100000)

/*
 * IS - Interrupt Status - 20h
 */
#define UTP_TRANSFER_REQ_COMPL			0x1
#define UIC_DME_END_PT_RESET			0x2
#define UIC_ERROR				0x4
#define UIC_TEST_MODE				0x8
#define UIC_POWER_MODE				0x10
#define UIC_HIBERNATE_EXIT			0x20
#define UIC_HIBERNATE_ENTER			0x40
#define UIC_LINK_LOST				0x80
#define UIC_LINK_STARTUP			0x100
#define UTP_TASK_REQ_COMPL			0x200
#define UIC_COMMAND_COMPL			0x400
#define DEVICE_FATAL_ERROR			0x800
#define CONTROLLER_FATAL_ERROR			0x10000
#define SYSTEM_BUS_FATAL_ERROR			0x20000
#define CRYPTO_ENGINE_FATAL_ERROR		0x40000

#define UFSHCD_UIC_HIBERN8_MASK	(UIC_HIBERNATE_ENTER |\
				UIC_HIBERNATE_EXIT)

#define UFSHCD_UIC_PWR_MASK	(UFSHCD_UIC_HIBERN8_MASK |\
				UIC_POWER_MODE)

#define UFSHCD_UIC_MASK		(UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)

#define UFSHCD_ERROR_MASK	(UIC_ERROR |\
				DEVICE_FATAL_ERROR |\
				CONTROLLER_FATAL_ERROR |\
				SYSTEM_BUS_FATAL_ERROR |\
				CRYPTO_ENGINE_FATAL_ERROR)

#define INT_FATAL_ERRORS	(DEVICE_FATAL_ERROR |\
				CONTROLLER_FATAL_ERROR |\
				SYSTEM_BUS_FATAL_ERROR |\
				CRYPTO_ENGINE_FATAL_ERROR |\
				UIC_LINK_LOST)

/* HCS - Host Controller Status 30h */
#define DEVICE_PRESENT				0x1
#define UTP_TRANSFER_REQ_LIST_READY		0x2
#define UTP_TASK_REQ_LIST_READY			0x4
#define UIC_COMMAND_READY			0x8
#define HOST_ERROR_INDICATOR			0x10
#define DEVICE_ERROR_INDICATOR			0x20
#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK	UFS_MASK(0x7, 8)

#define UFSHCD_STATUS_READY	(UTP_TRANSFER_REQ_LIST_READY |\
				UTP_TASK_REQ_LIST_READY |\
				UIC_COMMAND_READY)

enum {
	PWR_OK		= 0x0,
	PWR_LOCAL	= 0x01,
	PWR_REMOTE	= 0x02,
	PWR_BUSY	= 0x03,
	PWR_ERROR_CAP	= 0x04,
	PWR_FATAL_ERROR	= 0x05,
};

/* HCE - Host Controller Enable 34h */
#define CONTROLLER_ENABLE	0x1
#define CONTROLLER_DISABLE	0x0
#define CRYPTO_GENERAL_ENABLE	0x2

/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
#define UIC_PHY_ADAPTER_LAYER_ERROR			0x80000000
#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK		0x1F
#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK		0xF
#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR		0x10

/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
#define UIC_DATA_LINK_LAYER_ERROR		0x80000000
#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK	0xFFFF
#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP	0x2
#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP	0x4
#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP	0x8
#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF	0x20
#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT	0x2000
#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED	0x0001
#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002

/* UECN - Host UIC Error Code Network Layer 40h */
#define UIC_NETWORK_LAYER_ERROR			0x80000000
#define UIC_NETWORK_LAYER_ERROR_CODE_MASK	0x7
#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE	0x1
#define UIC_NETWORK_BAD_DEVICEID_ENC		0x2
#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING	0x4

/* UECT - Host UIC Error Code Transport Layer 44h */
#define UIC_TRANSPORT_LAYER_ERROR		0x80000000
#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK	0x7F
#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE	0x1
#define UIC_TRANSPORT_UNKNOWN_CPORTID		0x2
#define UIC_TRANSPORT_NO_CONNECTION_RX		0x4
#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING	0x8
#define UIC_TRANSPORT_BAD_TC			0x10
#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW	0x20
#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING	0x40

/* UECDME - Host UIC Error Code DME 48h */
#define UIC_DME_ERROR			0x80000000
#define UIC_DME_ERROR_CODE_MASK		0x1

/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
#define INT_AGGR_TIMEOUT_VAL_MASK		0xFF
#define INT_AGGR_COUNTER_THRESHOLD_MASK		UFS_MASK(0x1F, 8)
#define INT_AGGR_COUNTER_AND_TIMER_RESET	0x10000
#define INT_AGGR_STATUS_BIT			0x100000
#define INT_AGGR_PARAM_WRITE			0x1000000
#define INT_AGGR_ENABLE				0x80000000

/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT	0x1

/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
#define UTP_TASK_REQ_LIST_RUN_STOP_BIT		0x1

/* UICCMD - UIC Command */
#define COMMAND_OPCODE_MASK		0xFF
#define GEN_SELECTOR_INDEX_MASK		0xFFFF

#define MIB_ATTRIBUTE_MASK		UFS_MASK(0xFFFF, 16)
#define RESET_LEVEL			0xFF

#define ATTR_SET_TYPE_MASK		UFS_MASK(0xFF, 16)
#define CONFIG_RESULT_CODE_MASK		0xFF
#define GENERIC_ERROR_CODE_MASK		0xFF

/* GenSelectorIndex calculation macros for M-PHY attributes */
#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))

#define UIC_ARG_MIB_SEL(attr, sel)	((((attr) & 0xFFFF) << 16) |\
					 ((sel) & 0xFFFF))
#define UIC_ARG_MIB(attr)		UIC_ARG_MIB_SEL(attr, 0)
#define UIC_ARG_ATTR_TYPE(t)		(((t) & 0xFF) << 16)
#define UIC_GET_ATTR_ID(v)		(((v) >> 16) & 0xFFFF)

/* Link Status*/
enum link_status {
	UFSHCD_LINK_IS_DOWN	= 1,
	UFSHCD_LINK_IS_UP	= 2,
};

/* UIC Commands */
enum uic_cmd_dme {
	UIC_CMD_DME_GET			= 0x01,
	UIC_CMD_DME_SET			= 0x02,
	UIC_CMD_DME_PEER_GET		= 0x03,
	UIC_CMD_DME_PEER_SET		= 0x04,
	UIC_CMD_DME_POWERON		= 0x10,
	UIC_CMD_DME_POWEROFF		= 0x11,
	UIC_CMD_DME_ENABLE		= 0x12,
	UIC_CMD_DME_RESET		= 0x14,
	UIC_CMD_DME_END_PT_RST		= 0x15,
	UIC_CMD_DME_LINK_STARTUP	= 0x16,
	UIC_CMD_DME_HIBER_ENTER		= 0x17,
	UIC_CMD_DME_HIBER_EXIT		= 0x18,
	UIC_CMD_DME_TEST_MODE		= 0x1A,
};

/* UIC Config result code / Generic error code */
enum {
	UIC_CMD_RESULT_SUCCESS			= 0x00,
	UIC_CMD_RESULT_INVALID_ATTR		= 0x01,
	UIC_CMD_RESULT_FAILURE			= 0x01,
	UIC_CMD_RESULT_INVALID_ATTR_VALUE	= 0x02,
	UIC_CMD_RESULT_READ_ONLY_ATTR		= 0x03,
	UIC_CMD_RESULT_WRITE_ONLY_ATTR		= 0x04,
	UIC_CMD_RESULT_BAD_INDEX		= 0x05,
	UIC_CMD_RESULT_LOCKED_ATTR		= 0x06,
	UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX	= 0x07,
	UIC_CMD_RESULT_PEER_COMM_FAILURE	= 0x08,
	UIC_CMD_RESULT_BUSY			= 0x09,
	UIC_CMD_RESULT_DME_FAILURE		= 0x0A,
};

#define MASK_UIC_COMMAND_RESULT			0xFF

#define INT_AGGR_COUNTER_THLD_VAL(c)	(((c) & 0x1F) << 8)
#define INT_AGGR_TIMEOUT_VAL(t)		(((t) & 0xFF) << 0)

/* Interrupt disable masks */
enum {
	/* Interrupt disable mask for UFSHCI v1.0 */
	INTERRUPT_MASK_ALL_VER_10	= 0x30FFF,
	INTERRUPT_MASK_RW_VER_10	= 0x30000,

	/* Interrupt disable mask for UFSHCI v1.1 */
	INTERRUPT_MASK_ALL_VER_11	= 0x31FFF,

	/* Interrupt disable mask for UFSHCI v2.1 */
	INTERRUPT_MASK_ALL_VER_21	= 0x71FFF,
};

/* CCAP - Crypto Capability 100h */
union ufs_crypto_capabilities {
	__le32 reg_val;
	struct {
		u8 num_crypto_cap;
		u8 config_count;
		u8 reserved;
		u8 config_array_ptr;
	};
};

enum ufs_crypto_key_size {
	UFS_CRYPTO_KEY_SIZE_INVALID	= 0x0,
	UFS_CRYPTO_KEY_SIZE_128		= 0x1,
	UFS_CRYPTO_KEY_SIZE_192		= 0x2,
	UFS_CRYPTO_KEY_SIZE_256		= 0x3,
	UFS_CRYPTO_KEY_SIZE_512		= 0x4,
};

enum ufs_crypto_alg {
	UFS_CRYPTO_ALG_AES_XTS			= 0x0,
	UFS_CRYPTO_ALG_BITLOCKER_AES_CBC	= 0x1,
	UFS_CRYPTO_ALG_AES_ECB			= 0x2,
	UFS_CRYPTO_ALG_ESSIV_AES_CBC		= 0x3,
};

/* x-CRYPTOCAP - Crypto Capability X */
union ufs_crypto_cap_entry {
	__le32 reg_val;
	struct {
		u8 algorithm_id;
		u8 sdus_mask; /* Supported data unit size mask */
		u8 key_size;
		u8 reserved;
	};
};

#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
#define UFS_CRYPTO_KEY_MAX_SIZE 64
/* x-CRYPTOCFG - Crypto Configuration X */
union ufs_crypto_cfg_entry {
	__le32 reg_val[32];
	struct {
		u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
		u8 data_unit_size;
		u8 crypto_cap_idx;
		u8 reserved_1;
		u8 config_enable;
		u8 reserved_multi_host;
		u8 reserved_2;
		u8 vsb[2];
		u8 reserved_3[56];
	};
};

/*
 * Request Descriptor Definitions
 */

/* Transfer request command type */
enum {
	UTP_CMD_TYPE_SCSI		= 0x0,
	UTP_CMD_TYPE_UFS		= 0x1,
	UTP_CMD_TYPE_DEV_MANAGE		= 0x2,
};

/* To accommodate UFS2.0 required Command type */
enum {
	UTP_CMD_TYPE_UFS_STORAGE	= 0x1,
};

enum {
	UTP_SCSI_COMMAND		= 0x00000000,
	UTP_NATIVE_UFS_COMMAND		= 0x10000000,
	UTP_DEVICE_MANAGEMENT_FUNCTION	= 0x20000000,
	UTP_REQ_DESC_INT_CMD		= 0x01000000,
	UTP_REQ_DESC_CRYPTO_ENABLE_CMD	= 0x00800000,
};

/* UTP Transfer Request Data Direction (DD) */
enum {
	UTP_NO_DATA_TRANSFER	= 0x00000000,
	UTP_HOST_TO_DEVICE	= 0x02000000,
	UTP_DEVICE_TO_HOST	= 0x04000000,
};

/* Overall command status values */
enum utp_ocs {
	OCS_SUCCESS			= 0x0,
	OCS_INVALID_CMD_TABLE_ATTR	= 0x1,
	OCS_INVALID_PRDT_ATTR		= 0x2,
	OCS_MISMATCH_DATA_BUF_SIZE	= 0x3,
	OCS_MISMATCH_RESP_UPIU_SIZE	= 0x4,
	OCS_PEER_COMM_FAILURE		= 0x5,
	OCS_ABORTED			= 0x6,
	OCS_FATAL_ERROR			= 0x7,
	OCS_DEVICE_FATAL_ERROR		= 0x8,
	OCS_INVALID_CRYPTO_CONFIG	= 0x9,
	OCS_GENERAL_CRYPTO_ERROR	= 0xA,
	OCS_INVALID_COMMAND_STATUS	= 0x0F,
};

enum {
	MASK_OCS			= 0x0F,
};

/* The maximum length of the data byte count field in the PRDT is 256KB */
#define PRDT_DATA_BYTE_COUNT_MAX	(256 * 1024)
/* The granularity of the data byte count field in the PRDT is 32-bit */
#define PRDT_DATA_BYTE_COUNT_PAD	4

/**
 * struct ufshcd_sg_entry - UFSHCI PRD Entry
 * @addr: Physical address; DW-0 and DW-1.
 * @reserved: Reserved for future use DW-2
 * @size: size of physical segment DW-3
 */
struct ufshcd_sg_entry {
	__le64    addr;
	__le32    reserved;
	__le32    size;
};

/**
 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
 * @command_upiu: Command UPIU Frame address
 * @response_upiu: Response UPIU Frame address
 * @prd_table: Physical Region Descriptor
 */
struct utp_transfer_cmd_desc {
	u8 command_upiu[ALIGNED_UPIU_SIZE];
	u8 response_upiu[ALIGNED_UPIU_SIZE];
	struct ufshcd_sg_entry    prd_table[SG_ALL];
};

/**
 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
 * @dword0: Descriptor Header DW0
 * @dword1: Descriptor Header DW1
 * @dword2: Descriptor Header DW2
 * @dword3: Descriptor Header DW3
 */
struct request_desc_header {
	__le32 dword_0;
	__le32 dword_1;
	__le32 dword_2;
	__le32 dword_3;
};

/**
 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
 * @header: UTRD header DW-0 to DW-3
 * @command_desc_base_addr_lo: UCD base address low DW-4
 * @command_desc_base_addr_hi: UCD base address high DW-5
 * @response_upiu_length: response UPIU length DW-6
 * @response_upiu_offset: response UPIU offset DW-6
 * @prd_table_length: Physical region descriptor length DW-7
 * @prd_table_offset: Physical region descriptor offset DW-7
 */
struct utp_transfer_req_desc {

	/* DW 0-3 */
	struct request_desc_header header;

	/* DW 4-5*/
	__le32  command_desc_base_addr_lo;
	__le32  command_desc_base_addr_hi;

	/* DW 6 */
	__le16  response_upiu_length;
	__le16  response_upiu_offset;

	/* DW 7 */
	__le16  prd_table_length;
	__le16  prd_table_offset;
};

/*
 * UTMRD structure.
 */
struct utp_task_req_desc {
	/* DW 0-3 */
	struct request_desc_header header;

	/* DW 4-11 - Task request UPIU structure */
	struct {
		struct utp_upiu_header	req_header;
		__be32			input_param1;
		__be32			input_param2;
		__be32			input_param3;
		__be32			__reserved1[2];
	} upiu_req;

	/* DW 12-19 - Task Management Response UPIU structure */
	struct {
		struct utp_upiu_header	rsp_header;
		__be32			output_param1;
		__be32			output_param2;
		__be32			__reserved2[3];
	} upiu_rsp;
};

#endif /* End of Header */
Commit	Line	Data
67351119	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
7a3e97b0 SY	2	/*
7a3e97b0 SY	3	* Universal Flash Storage Host controller driver
3b1d0580	4	* Copyright (C) 2011-2013 Samsung India Software Operations
7a3e97b0	5	*
3b1d0580 VH	6	* Authors:
	7	* Santosh Yaraganavi <santosh.sy@samsung.com>
	8	* Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0 SY	9	*/
	10
	11	#ifndef _UFSHCI_H
	12	#define _UFSHCI_H
	13
3f06f780 BVA	14	#include <scsi/scsi_host.h>
3f06f780 BVA	15
7a3e97b0 SY	16	enum {
	17	TASK_REQ_UPIU_SIZE_DWORDS = 8,
	18	TASK_RSP_UPIU_SIZE_DWORDS = 8,
68078d5c	19	ALIGNED_UPIU_SIZE = 512,
7a3e97b0 SY	20	};
	21
	22	/* UFSHCI Registers */
	23	enum {
	24	REG_CONTROLLER_CAPABILITIES = 0x00,
	25	REG_UFS_VERSION = 0x08,
	26	REG_CONTROLLER_DEV_ID = 0x10,
	27	REG_CONTROLLER_PROD_ID = 0x14,
f6b25451	28	REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
7a3e97b0 SY	29	REG_INTERRUPT_STATUS = 0x20,
	30	REG_INTERRUPT_ENABLE = 0x24,
	31	REG_CONTROLLER_STATUS = 0x30,
	32	REG_CONTROLLER_ENABLE = 0x34,
	33	REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
	34	REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
	35	REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
	36	REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
	37	REG_UIC_ERROR_CODE_DME = 0x48,
	38	REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
	39	REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
	40	REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
	41	REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
	42	REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
	43	REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
	44	REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
	45	REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
	46	REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
	47	REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
	48	REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
	49	REG_UIC_COMMAND = 0x90,
	50	REG_UIC_COMMAND_ARG_1 = 0x94,
	51	REG_UIC_COMMAND_ARG_2 = 0x98,
	52	REG_UIC_COMMAND_ARG_3 = 0x9C,
66cc820f DR	53
	54	UFSHCI_REG_SPACE_SIZE = 0xA0,
	55
c01848c6 YG	56	REG_UFS_CCAP = 0x100,
	57	REG_UFS_CRYPTOCAP = 0x104,
	58
	59	UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
7a3e97b0 SY	60	};
	61
	62	/* Controller capability masks */
	63	enum {
	64	MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
	65	MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
ad448378	66	MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
7a3e97b0 SY	67	MASK_64_ADDRESSING_SUPPORT = 0x01000000,
	68	MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
	69	MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
5e7341e1	70	MASK_CRYPTO_SUPPORT = 0x10000000,
7a3e97b0 SY	71	};
7a3e97b0 SY	72
679882ae S	73	#define UFS_MASK(mask, offset) ((mask) << (offset))
679882ae S	74
7a3e97b0 SY	75	/* UFS Version 08h */
	76	#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
	77	#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
	78
51428818 CC	79	/*
	80	* Controller UFSHCI version
	81	* - 2.x and newer use the following scheme:
	82	* major << 8 + minor << 4
	83	* - 1.x has been converted to match this in
	84	* ufshcd_get_ufs_version()
	85	*/
	86	static inline u32 ufshci_version(u32 major, u32 minor)
	87	{
	88	return (major << 8) + (minor << 4);
	89	}
7a3e97b0 SY	90
	91	/*
	92	* HCDDID - Host Controller Identification Descriptor
	93	* - Device ID and Device Class 10h
	94	*/
	95	#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
	96	#define DEVICE_ID UFS_MASK(0xFF, 24)
	97
	98	/*
	99	* HCPMID - Host Controller Identification Descriptor
	100	* - Product/Manufacturer ID 14h
	101	*/
	102	#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
	103	#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
	104
ad448378 AH	105	/* AHIT - Auto-Hibernate Idle Timer */
	106	#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
	107	#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
	108	#define UFSHCI_AHIBERN8_SCALE_FACTOR 10
	109	#define UFSHCI_AHIBERN8_MAX (1023 * 100000)
	110
cc81641a AA	111	/*
	112	* IS - Interrupt Status - 20h
	113	*/
	114	#define UTP_TRANSFER_REQ_COMPL 0x1
	115	#define UIC_DME_END_PT_RESET 0x2
	116	#define UIC_ERROR 0x4
	117	#define UIC_TEST_MODE 0x8
	118	#define UIC_POWER_MODE 0x10
	119	#define UIC_HIBERNATE_EXIT 0x20
	120	#define UIC_HIBERNATE_ENTER 0x40
	121	#define UIC_LINK_LOST 0x80
	122	#define UIC_LINK_STARTUP 0x100
	123	#define UTP_TASK_REQ_COMPL 0x200
	124	#define UIC_COMMAND_COMPL 0x400
	125	#define DEVICE_FATAL_ERROR 0x800
	126	#define CONTROLLER_FATAL_ERROR 0x10000
	127	#define SYSTEM_BUS_FATAL_ERROR 0x20000
5e7341e1	128	#define CRYPTO_ENGINE_FATAL_ERROR 0x40000
7a3e97b0	129
82174440 SC	130	#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER \|\
	131	UIC_HIBERNATE_EXIT)
	132
	133	#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK \|\
57d104c1 SJ	134	UIC_POWER_MODE)
	135
	136	#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL \| UFSHCD_UIC_PWR_MASK)
53b3d9c3	137
7a3e97b0 SY	138	#define UFSHCD_ERROR_MASK (UIC_ERROR \|\
	139	DEVICE_FATAL_ERROR \|\
	140	CONTROLLER_FATAL_ERROR \|\
5e7341e1 ST	141	SYSTEM_BUS_FATAL_ERROR \|\
5e7341e1 ST	142	CRYPTO_ENGINE_FATAL_ERROR)
7a3e97b0 SY	143
	144	#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR \|\
	145	CONTROLLER_FATAL_ERROR \|\
5e7341e1	146	SYSTEM_BUS_FATAL_ERROR \|\
c99b9b23 KK	147	CRYPTO_ENGINE_FATAL_ERROR \|\
c99b9b23 KK	148	UIC_LINK_LOST)
7a3e97b0 SY	149
7a3e97b0 SY	150	/* HCS - Host Controller Status 30h */
cc81641a AA	151	#define DEVICE_PRESENT 0x1
	152	#define UTP_TRANSFER_REQ_LIST_READY 0x2
	153	#define UTP_TASK_REQ_LIST_READY 0x4
	154	#define UIC_COMMAND_READY 0x8
cffe3ff3	155	#define HOST_ERROR_INDICATOR 0x10
cffe3ff3	156	#define DEVICE_ERROR_INDICATOR 0x20
7a3e97b0 SY	157	#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
7a3e97b0 SY	158
6cf16115 TK	159	#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY \|\
	160	UTP_TASK_REQ_LIST_READY \|\
	161	UIC_COMMAND_READY)
	162
53b3d9c3 SJ	163	enum {
	164	PWR_OK = 0x0,
	165	PWR_LOCAL = 0x01,
	166	PWR_REMOTE = 0x02,
	167	PWR_BUSY = 0x03,
	168	PWR_ERROR_CAP = 0x04,
	169	PWR_FATAL_ERROR = 0x05,
	170	};
	171
7a3e97b0	172	/* HCE - Host Controller Enable 34h */
cc81641a	173	#define CONTROLLER_ENABLE 0x1
7a3e97b0	174	#define CONTROLLER_DISABLE 0x0
cc81641a	175	#define CRYPTO_GENERAL_ENABLE 0x2
7a3e97b0 SY	176
7a3e97b0 SY	177	/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
cc81641a	178	#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
7a3e97b0	179	#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
fb7b45f0	180	#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
2355b66e	181	#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
7a3e97b0 SY	182
7a3e97b0 SY	183	/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
cc81641a	184	#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
9333d775	185	#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
cffe3ff3	186	#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
	187	#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
	188	#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
	189	#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
7a3e97b0	190	#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
583fa62d YG	191	#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
583fa62d YG	192	#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
7a3e97b0 SY	193
7a3e97b0 SY	194	/* UECN - Host UIC Error Code Network Layer 40h */
cc81641a	195	#define UIC_NETWORK_LAYER_ERROR 0x80000000
7a3e97b0	196	#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
cffe3ff3	197	#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
	198	#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
	199	#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
7a3e97b0 SY	200
7a3e97b0 SY	201	/* UECT - Host UIC Error Code Transport Layer 44h */
cc81641a	202	#define UIC_TRANSPORT_LAYER_ERROR 0x80000000
7a3e97b0	203	#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
cffe3ff3	204	#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
	205	#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
	206	#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
	207	#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
	208	#define UIC_TRANSPORT_BAD_TC 0x10
	209	#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
	210	#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
7a3e97b0 SY	211
7a3e97b0 SY	212	/* UECDME - Host UIC Error Code DME 48h */
cc81641a	213	#define UIC_DME_ERROR 0x80000000
7a3e97b0 SY	214	#define UIC_DME_ERROR_CODE_MASK 0x1
7a3e97b0 SY	215
cc81641a	216	/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
7a3e97b0 SY	217	#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
7a3e97b0 SY	218	#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
cc81641a AA	219	#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
	220	#define INT_AGGR_STATUS_BIT 0x100000
	221	#define INT_AGGR_PARAM_WRITE 0x1000000
	222	#define INT_AGGR_ENABLE 0x80000000
7a3e97b0 SY	223
7a3e97b0 SY	224	/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
cc81641a	225	#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
7a3e97b0 SY	226
7a3e97b0 SY	227	/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
cc81641a	228	#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
7a3e97b0 SY	229
	230	/* UICCMD - UIC Command */
	231	#define COMMAND_OPCODE_MASK 0xFF
	232	#define GEN_SELECTOR_INDEX_MASK 0xFFFF
	233
	234	#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
	235	#define RESET_LEVEL 0xFF
	236
	237	#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
	238	#define CONFIG_RESULT_CODE_MASK 0xFF
	239	#define GENERIC_ERROR_CODE_MASK 0xFF
	240
7ca38cf3 YG	241	/* GenSelectorIndex calculation macros for M-PHY attributes */
7ca38cf3 YG	242	#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
37113106	243	#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
7ca38cf3	244
12b4fdb4 SJ	245	#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) \|\
	246	((sel) & 0xFFFF))
	247	#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
	248	#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
	249	#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
	250
79fcc033 JP	251	/* Link Status*/
	252	enum link_status {
	253	UFSHCD_LINK_IS_DOWN = 1,
	254	UFSHCD_LINK_IS_UP = 2,
	255	};
	256
7a3e97b0	257	/* UIC Commands */
57d104c1	258	enum uic_cmd_dme {
7a3e97b0 SY	259	UIC_CMD_DME_GET = 0x01,
	260	UIC_CMD_DME_SET = 0x02,
	261	UIC_CMD_DME_PEER_GET = 0x03,
	262	UIC_CMD_DME_PEER_SET = 0x04,
	263	UIC_CMD_DME_POWERON = 0x10,
	264	UIC_CMD_DME_POWEROFF = 0x11,
	265	UIC_CMD_DME_ENABLE = 0x12,
	266	UIC_CMD_DME_RESET = 0x14,
	267	UIC_CMD_DME_END_PT_RST = 0x15,
	268	UIC_CMD_DME_LINK_STARTUP = 0x16,
	269	UIC_CMD_DME_HIBER_ENTER = 0x17,
	270	UIC_CMD_DME_HIBER_EXIT = 0x18,
	271	UIC_CMD_DME_TEST_MODE = 0x1A,
	272	};
	273
	274	/* UIC Config result code / Generic error code */
	275	enum {
	276	UIC_CMD_RESULT_SUCCESS = 0x00,
	277	UIC_CMD_RESULT_INVALID_ATTR = 0x01,
	278	UIC_CMD_RESULT_FAILURE = 0x01,
	279	UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
	280	UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
	281	UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
	282	UIC_CMD_RESULT_BAD_INDEX = 0x05,
	283	UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
	284	UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
	285	UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
	286	UIC_CMD_RESULT_BUSY = 0x09,
	287	UIC_CMD_RESULT_DME_FAILURE = 0x0A,
	288	};
	289
	290	#define MASK_UIC_COMMAND_RESULT 0xFF
	291
7d568652 SJ	292	#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
7d568652 SJ	293	#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
7a3e97b0 SY	294
	295	/* Interrupt disable masks */
	296	enum {
	297	/* Interrupt disable mask for UFSHCI v1.0 */
2fbd009b SJ	298	INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
2fbd009b SJ	299	INTERRUPT_MASK_RW_VER_10 = 0x30000,
7a3e97b0 SY	300
7a3e97b0 SY	301	/* Interrupt disable mask for UFSHCI v1.1 */
2fbd009b	302	INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
c01848c6 YG	303
	304	/* Interrupt disable mask for UFSHCI v2.1 */
	305	INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
7a3e97b0 SY	306	};
7a3e97b0 SY	307
5e7341e1 ST	308	/* CCAP - Crypto Capability 100h */
	309	union ufs_crypto_capabilities {
	310	__le32 reg_val;
	311	struct {
	312	u8 num_crypto_cap;
	313	u8 config_count;
	314	u8 reserved;
	315	u8 config_array_ptr;
	316	};
	317	};
	318
	319	enum ufs_crypto_key_size {
	320	UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
	321	UFS_CRYPTO_KEY_SIZE_128 = 0x1,
	322	UFS_CRYPTO_KEY_SIZE_192 = 0x2,
	323	UFS_CRYPTO_KEY_SIZE_256 = 0x3,
	324	UFS_CRYPTO_KEY_SIZE_512 = 0x4,
	325	};
	326
	327	enum ufs_crypto_alg {
	328	UFS_CRYPTO_ALG_AES_XTS = 0x0,
	329	UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
	330	UFS_CRYPTO_ALG_AES_ECB = 0x2,
	331	UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
	332	};
	333
	334	/* x-CRYPTOCAP - Crypto Capability X */
	335	union ufs_crypto_cap_entry {
	336	__le32 reg_val;
	337	struct {
	338	u8 algorithm_id;
	339	u8 sdus_mask; /* Supported data unit size mask */
	340	u8 key_size;
	341	u8 reserved;
	342	};
	343	};
	344
	345	#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
	346	#define UFS_CRYPTO_KEY_MAX_SIZE 64
	347	/* x-CRYPTOCFG - Crypto Configuration X */
	348	union ufs_crypto_cfg_entry {
	349	__le32 reg_val[32];
	350	struct {
	351	u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
	352	u8 data_unit_size;
	353	u8 crypto_cap_idx;
	354	u8 reserved_1;
	355	u8 config_enable;
	356	u8 reserved_multi_host;
	357	u8 reserved_2;
	358	u8 vsb[2];
	359	u8 reserved_3[56];
	360	};
	361	};
	362
7a3e97b0 SY	363	/*
	364	* Request Descriptor Definitions
	365	*/
	366
	367	/* Transfer request command type */
	368	enum {
	369	UTP_CMD_TYPE_SCSI = 0x0,
	370	UTP_CMD_TYPE_UFS = 0x1,
	371	UTP_CMD_TYPE_DEV_MANAGE = 0x2,
	372	};
	373
300bb13f JP	374	/* To accommodate UFS2.0 required Command type */
	375	enum {
	376	UTP_CMD_TYPE_UFS_STORAGE = 0x1,
	377	};
	378
7a3e97b0 SY	379	enum {
	380	UTP_SCSI_COMMAND = 0x00000000,
	381	UTP_NATIVE_UFS_COMMAND = 0x10000000,
	382	UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
	383	UTP_REQ_DESC_INT_CMD = 0x01000000,
5e7341e1	384	UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000,
7a3e97b0 SY	385	};
	386
	387	/* UTP Transfer Request Data Direction (DD) */
	388	enum {
	389	UTP_NO_DATA_TRANSFER = 0x00000000,
	390	UTP_HOST_TO_DEVICE = 0x02000000,
	391	UTP_DEVICE_TO_HOST = 0x04000000,
	392	};
	393
	394	/* Overall command status values */
957d63e7	395	enum utp_ocs {
7a3e97b0 SY	396	OCS_SUCCESS = 0x0,
	397	OCS_INVALID_CMD_TABLE_ATTR = 0x1,
	398	OCS_INVALID_PRDT_ATTR = 0x2,
	399	OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
	400	OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
	401	OCS_PEER_COMM_FAILURE = 0x5,
	402	OCS_ABORTED = 0x6,
	403	OCS_FATAL_ERROR = 0x7,
5e7341e1 ST	404	OCS_DEVICE_FATAL_ERROR = 0x8,
	405	OCS_INVALID_CRYPTO_CONFIG = 0x9,
	406	OCS_GENERAL_CRYPTO_ERROR = 0xA,
7a3e97b0	407	OCS_INVALID_COMMAND_STATUS = 0x0F,
957d63e7 BVA	408	};
	409
	410	enum {
7a3e97b0 SY	411	MASK_OCS = 0x0F,
	412	};
	413
eeda4749 AM	414	/* The maximum length of the data byte count field in the PRDT is 256KB */
	415	#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
	416	/* The granularity of the data byte count field in the PRDT is 32-bit */
	417	#define PRDT_DATA_BYTE_COUNT_PAD 4
	418
7a3e97b0 SY	419	/**
7a3e97b0 SY	420	* struct ufshcd_sg_entry - UFSHCI PRD Entry
1ea7d802	421	* @addr: Physical address; DW-0 and DW-1.
7a3e97b0 SY	422	* @reserved: Reserved for future use DW-2
	423	* @size: size of physical segment DW-3
	424	*/
	425	struct ufshcd_sg_entry {
1ea7d802	426	__le64 addr;
e8c8e82a SRT	427	__le32 reserved;
e8c8e82a SRT	428	__le32 size;
7a3e97b0 SY	429	};
	430
	431	/**
91bb765c	432	* struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
7a3e97b0 SY	433	* @command_upiu: Command UPIU Frame address
	434	* @response_upiu: Response UPIU Frame address
	435	* @prd_table: Physical Region Descriptor
	436	*/
	437	struct utp_transfer_cmd_desc {
	438	u8 command_upiu[ALIGNED_UPIU_SIZE];
	439	u8 response_upiu[ALIGNED_UPIU_SIZE];
	440	struct ufshcd_sg_entry prd_table[SG_ALL];
	441	};
	442
	443	/**
	444	* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
	445	* @dword0: Descriptor Header DW0
	446	* @dword1: Descriptor Header DW1
	447	* @dword2: Descriptor Header DW2
	448	* @dword3: Descriptor Header DW3
	449	*/
	450	struct request_desc_header {
e8c8e82a SRT	451	__le32 dword_0;
	452	__le32 dword_1;
	453	__le32 dword_2;
	454	__le32 dword_3;
7a3e97b0 SY	455	};
	456
	457	/**
91bb765c	458	* struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
7a3e97b0 SY	459	* @header: UTRD header DW-0 to DW-3
	460	* @command_desc_base_addr_lo: UCD base address low DW-4
	461	* @command_desc_base_addr_hi: UCD base address high DW-5
	462	* @response_upiu_length: response UPIU length DW-6
	463	* @response_upiu_offset: response UPIU offset DW-6
	464	* @prd_table_length: Physical region descriptor length DW-7
	465	* @prd_table_offset: Physical region descriptor offset DW-7
	466	*/
	467	struct utp_transfer_req_desc {
	468
	469	/* DW 0-3 */
	470	struct request_desc_header header;
	471
	472	/* DW 4-5*/
e8c8e82a SRT	473	__le32 command_desc_base_addr_lo;
e8c8e82a SRT	474	__le32 command_desc_base_addr_hi;
7a3e97b0 SY	475
7a3e97b0 SY	476	/* DW 6 */
e8c8e82a SRT	477	__le16 response_upiu_length;
e8c8e82a SRT	478	__le16 response_upiu_offset;
7a3e97b0 SY	479
7a3e97b0 SY	480	/* DW 7 */
e8c8e82a SRT	481	__le16 prd_table_length;
e8c8e82a SRT	482	__le16 prd_table_offset;
7a3e97b0 SY	483	};
7a3e97b0 SY	484
391e388f CH	485	/*
391e388f CH	486	* UTMRD structure.
7a3e97b0 SY	487	*/
7a3e97b0 SY	488	struct utp_task_req_desc {
7a3e97b0 SY	489	/* DW 0-3 */
	490	struct request_desc_header header;
	491
391e388f	492	/* DW 4-11 - Task request UPIU structure */
1352eec8 GS	493	struct {
	494	struct utp_upiu_header req_header;
	495	__be32 input_param1;
	496	__be32 input_param2;
	497	__be32 input_param3;
	498	__be32 __reserved1[2];
	499	} upiu_req;
391e388f CH	500
391e388f CH	501	/* DW 12-19 - Task Management Response UPIU structure */
1352eec8 GS	502	struct {
	503	struct utp_upiu_header rsp_header;
	504	__be32 output_param1;
	505	__be32 output_param2;
	506	__be32 __reserved2[3];
	507	} upiu_rsp;
7a3e97b0 SY	508	};
	509
	510	#endif /* End of Header */