[linux-block.git] / include / ufs / ufshci.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Universal Flash Storage Host controller driver
 * Copyright (C) 2011-2013 Samsung India Software Operations
 *
 * Authors:
 *	Santosh Yaraganavi <santosh.sy@samsung.com>
 *	Vinayak Holikatti <h.vinayak@samsung.com>
 */

#ifndef _UFSHCI_H
#define _UFSHCI_H

#include <scsi/scsi_host.h>

enum {
	TASK_REQ_UPIU_SIZE_DWORDS	= 8,
	TASK_RSP_UPIU_SIZE_DWORDS	= 8,
	ALIGNED_UPIU_SIZE		= 512,
};

/* UFSHCI Registers */
enum {
	REG_CONTROLLER_CAPABILITIES		= 0x00,
	REG_MCQCAP				= 0x04,
	REG_UFS_VERSION				= 0x08,
	REG_CONTROLLER_DEV_ID			= 0x10,
	REG_CONTROLLER_PROD_ID			= 0x14,
	REG_AUTO_HIBERNATE_IDLE_TIMER		= 0x18,
	REG_INTERRUPT_STATUS			= 0x20,
	REG_INTERRUPT_ENABLE			= 0x24,
	REG_CONTROLLER_STATUS			= 0x30,
	REG_CONTROLLER_ENABLE			= 0x34,
	REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER	= 0x38,
	REG_UIC_ERROR_CODE_DATA_LINK_LAYER	= 0x3C,
	REG_UIC_ERROR_CODE_NETWORK_LAYER	= 0x40,
	REG_UIC_ERROR_CODE_TRANSPORT_LAYER	= 0x44,
	REG_UIC_ERROR_CODE_DME			= 0x48,
	REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL	= 0x4C,
	REG_UTP_TRANSFER_REQ_LIST_BASE_L	= 0x50,
	REG_UTP_TRANSFER_REQ_LIST_BASE_H	= 0x54,
	REG_UTP_TRANSFER_REQ_DOOR_BELL		= 0x58,
	REG_UTP_TRANSFER_REQ_LIST_CLEAR		= 0x5C,
	REG_UTP_TRANSFER_REQ_LIST_RUN_STOP	= 0x60,
	REG_UTP_TASK_REQ_LIST_BASE_L		= 0x70,
	REG_UTP_TASK_REQ_LIST_BASE_H		= 0x74,
	REG_UTP_TASK_REQ_DOOR_BELL		= 0x78,
	REG_UTP_TASK_REQ_LIST_CLEAR		= 0x7C,
	REG_UTP_TASK_REQ_LIST_RUN_STOP		= 0x80,
	REG_UIC_COMMAND				= 0x90,
	REG_UIC_COMMAND_ARG_1			= 0x94,
	REG_UIC_COMMAND_ARG_2			= 0x98,
	REG_UIC_COMMAND_ARG_3			= 0x9C,

	UFSHCI_REG_SPACE_SIZE			= 0xA0,

	REG_UFS_CCAP				= 0x100,
	REG_UFS_CRYPTOCAP			= 0x104,

	REG_UFS_MEM_CFG				= 0x300,
	REG_UFS_MCQ_CFG				= 0x380,
	REG_UFS_ESILBA				= 0x384,
	REG_UFS_ESIUBA				= 0x388,
	UFSHCI_CRYPTO_REG_SPACE_SIZE		= 0x400,
};

/* Controller capability masks */
enum {
	MASK_TRANSFER_REQUESTS_SLOTS		= 0x0000001F,
	MASK_TASK_MANAGEMENT_REQUEST_SLOTS	= 0x00070000,
	MASK_EHSLUTRD_SUPPORTED			= 0x00400000,
	MASK_AUTO_HIBERN8_SUPPORT		= 0x00800000,
	MASK_64_ADDRESSING_SUPPORT		= 0x01000000,
	MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT	= 0x02000000,
	MASK_UIC_DME_TEST_MODE_SUPPORT		= 0x04000000,
	MASK_CRYPTO_SUPPORT			= 0x10000000,
	MASK_MCQ_SUPPORT			= 0x40000000,
};

/* MCQ capability mask */
enum {
	MASK_EXT_IID_SUPPORT = 0x00000400,
};

enum {
	REG_SQATTR		= 0x0,
	REG_SQLBA		= 0x4,
	REG_SQUBA		= 0x8,
	REG_SQDAO		= 0xC,
	REG_SQISAO		= 0x10,

	REG_CQATTR		= 0x20,
	REG_CQLBA		= 0x24,
	REG_CQUBA		= 0x28,
	REG_CQDAO		= 0x2C,
	REG_CQISAO		= 0x30,
};

enum {
	REG_SQHP		= 0x0,
	REG_SQTP		= 0x4,
};

enum {
	REG_CQHP		= 0x0,
	REG_CQTP		= 0x4,
};

enum {
	REG_CQIS		= 0x0,
	REG_CQIE		= 0x4,
};

#define UFS_MASK(mask, offset)		((mask) << (offset))

/* UFS Version 08h */
#define MINOR_VERSION_NUM_MASK		UFS_MASK(0xFFFF, 0)
#define MAJOR_VERSION_NUM_MASK		UFS_MASK(0xFFFF, 16)

/*
 * Controller UFSHCI version
 * - 2.x and newer use the following scheme:
 *   major << 8 + minor << 4
 * - 1.x has been converted to match this in
 *   ufshcd_get_ufs_version()
 */
static inline u32 ufshci_version(u32 major, u32 minor)
{
	return (major << 8) + (minor << 4);
}

/*
 * HCDDID - Host Controller Identification Descriptor
 *	  - Device ID and Device Class 10h
 */
#define DEVICE_CLASS	UFS_MASK(0xFFFF, 0)
#define DEVICE_ID	UFS_MASK(0xFF, 24)

/*
 * HCPMID - Host Controller Identification Descriptor
 *	  - Product/Manufacturer ID  14h
 */
#define MANUFACTURE_ID_MASK	UFS_MASK(0xFFFF, 0)
#define PRODUCT_ID_MASK		UFS_MASK(0xFFFF, 16)

/* AHIT - Auto-Hibernate Idle Timer */
#define UFSHCI_AHIBERN8_TIMER_MASK		GENMASK(9, 0)
#define UFSHCI_AHIBERN8_SCALE_MASK		GENMASK(12, 10)
#define UFSHCI_AHIBERN8_SCALE_FACTOR		10
#define UFSHCI_AHIBERN8_MAX			(1023 * 100000)

/*
 * IS - Interrupt Status - 20h
 */
#define UTP_TRANSFER_REQ_COMPL			0x1
#define UIC_DME_END_PT_RESET			0x2
#define UIC_ERROR				0x4
#define UIC_TEST_MODE				0x8
#define UIC_POWER_MODE				0x10
#define UIC_HIBERNATE_EXIT			0x20
#define UIC_HIBERNATE_ENTER			0x40
#define UIC_LINK_LOST				0x80
#define UIC_LINK_STARTUP			0x100
#define UTP_TASK_REQ_COMPL			0x200
#define UIC_COMMAND_COMPL			0x400
#define DEVICE_FATAL_ERROR			0x800
#define CONTROLLER_FATAL_ERROR			0x10000
#define SYSTEM_BUS_FATAL_ERROR			0x20000
#define CRYPTO_ENGINE_FATAL_ERROR		0x40000
#define MCQ_CQ_EVENT_STATUS			0x100000

#define UFSHCD_UIC_HIBERN8_MASK	(UIC_HIBERNATE_ENTER |\
				UIC_HIBERNATE_EXIT)

#define UFSHCD_UIC_PWR_MASK	(UFSHCD_UIC_HIBERN8_MASK |\
				UIC_POWER_MODE)

#define UFSHCD_UIC_MASK		(UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)

#define UFSHCD_ERROR_MASK	(UIC_ERROR | INT_FATAL_ERRORS)

#define INT_FATAL_ERRORS	(DEVICE_FATAL_ERROR |\
				CONTROLLER_FATAL_ERROR |\
				SYSTEM_BUS_FATAL_ERROR |\
				CRYPTO_ENGINE_FATAL_ERROR |\
				UIC_LINK_LOST)

/* HCS - Host Controller Status 30h */
#define DEVICE_PRESENT				0x1
#define UTP_TRANSFER_REQ_LIST_READY		0x2
#define UTP_TASK_REQ_LIST_READY			0x4
#define UIC_COMMAND_READY			0x8
#define HOST_ERROR_INDICATOR			0x10
#define DEVICE_ERROR_INDICATOR			0x20
#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK	UFS_MASK(0x7, 8)

#define UFSHCD_STATUS_READY	(UTP_TRANSFER_REQ_LIST_READY |\
				UTP_TASK_REQ_LIST_READY |\
				UIC_COMMAND_READY)

enum {
	PWR_OK		= 0x0,
	PWR_LOCAL	= 0x01,
	PWR_REMOTE	= 0x02,
	PWR_BUSY	= 0x03,
	PWR_ERROR_CAP	= 0x04,
	PWR_FATAL_ERROR	= 0x05,
};

/* HCE - Host Controller Enable 34h */
#define CONTROLLER_ENABLE	0x1
#define CONTROLLER_DISABLE	0x0
#define CRYPTO_GENERAL_ENABLE	0x2

/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
#define UIC_PHY_ADAPTER_LAYER_ERROR			0x80000000
#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK		0x1F
#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK		0xF
#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR		0x10

/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
#define UIC_DATA_LINK_LAYER_ERROR		0x80000000
#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK	0xFFFF
#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP	0x2
#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP	0x4
#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP	0x8
#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF	0x20
#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT	0x2000
#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED	0x0001
#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002

/* UECN - Host UIC Error Code Network Layer 40h */
#define UIC_NETWORK_LAYER_ERROR			0x80000000
#define UIC_NETWORK_LAYER_ERROR_CODE_MASK	0x7
#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE	0x1
#define UIC_NETWORK_BAD_DEVICEID_ENC		0x2
#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING	0x4

/* UECT - Host UIC Error Code Transport Layer 44h */
#define UIC_TRANSPORT_LAYER_ERROR		0x80000000
#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK	0x7F
#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE	0x1
#define UIC_TRANSPORT_UNKNOWN_CPORTID		0x2
#define UIC_TRANSPORT_NO_CONNECTION_RX		0x4
#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING	0x8
#define UIC_TRANSPORT_BAD_TC			0x10
#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW	0x20
#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING	0x40

/* UECDME - Host UIC Error Code DME 48h */
#define UIC_DME_ERROR			0x80000000
#define UIC_DME_ERROR_CODE_MASK		0x1

/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
#define INT_AGGR_TIMEOUT_VAL_MASK		0xFF
#define INT_AGGR_COUNTER_THRESHOLD_MASK		UFS_MASK(0x1F, 8)
#define INT_AGGR_COUNTER_AND_TIMER_RESET	0x10000
#define INT_AGGR_STATUS_BIT			0x100000
#define INT_AGGR_PARAM_WRITE			0x1000000
#define INT_AGGR_ENABLE				0x80000000

/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT	0x1

/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
#define UTP_TASK_REQ_LIST_RUN_STOP_BIT		0x1

/* CQISy - CQ y Interrupt Status Register  */
#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS	0x1

/* UICCMD - UIC Command */
#define COMMAND_OPCODE_MASK		0xFF
#define GEN_SELECTOR_INDEX_MASK		0xFFFF

#define MIB_ATTRIBUTE_MASK		UFS_MASK(0xFFFF, 16)
#define RESET_LEVEL			0xFF

#define ATTR_SET_TYPE_MASK		UFS_MASK(0xFF, 16)
#define CONFIG_RESULT_CODE_MASK		0xFF
#define GENERIC_ERROR_CODE_MASK		0xFF

/* GenSelectorIndex calculation macros for M-PHY attributes */
#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))

#define UIC_ARG_MIB_SEL(attr, sel)	((((attr) & 0xFFFF) << 16) |\
					 ((sel) & 0xFFFF))
#define UIC_ARG_MIB(attr)		UIC_ARG_MIB_SEL(attr, 0)
#define UIC_ARG_ATTR_TYPE(t)		(((t) & 0xFF) << 16)
#define UIC_GET_ATTR_ID(v)		(((v) >> 16) & 0xFFFF)

/* Link Status*/
enum link_status {
	UFSHCD_LINK_IS_DOWN	= 1,
	UFSHCD_LINK_IS_UP	= 2,
};

/* UIC Commands */
enum uic_cmd_dme {
	UIC_CMD_DME_GET			= 0x01,
	UIC_CMD_DME_SET			= 0x02,
	UIC_CMD_DME_PEER_GET		= 0x03,
	UIC_CMD_DME_PEER_SET		= 0x04,
	UIC_CMD_DME_POWERON		= 0x10,
	UIC_CMD_DME_POWEROFF		= 0x11,
	UIC_CMD_DME_ENABLE		= 0x12,
	UIC_CMD_DME_RESET		= 0x14,
	UIC_CMD_DME_END_PT_RST		= 0x15,
	UIC_CMD_DME_LINK_STARTUP	= 0x16,
	UIC_CMD_DME_HIBER_ENTER		= 0x17,
	UIC_CMD_DME_HIBER_EXIT		= 0x18,
	UIC_CMD_DME_TEST_MODE		= 0x1A,
};

/* UIC Config result code / Generic error code */
enum {
	UIC_CMD_RESULT_SUCCESS			= 0x00,
	UIC_CMD_RESULT_INVALID_ATTR		= 0x01,
	UIC_CMD_RESULT_FAILURE			= 0x01,
	UIC_CMD_RESULT_INVALID_ATTR_VALUE	= 0x02,
	UIC_CMD_RESULT_READ_ONLY_ATTR		= 0x03,
	UIC_CMD_RESULT_WRITE_ONLY_ATTR		= 0x04,
	UIC_CMD_RESULT_BAD_INDEX		= 0x05,
	UIC_CMD_RESULT_LOCKED_ATTR		= 0x06,
	UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX	= 0x07,
	UIC_CMD_RESULT_PEER_COMM_FAILURE	= 0x08,
	UIC_CMD_RESULT_BUSY			= 0x09,
	UIC_CMD_RESULT_DME_FAILURE		= 0x0A,
};

#define MASK_UIC_COMMAND_RESULT			0xFF

#define INT_AGGR_COUNTER_THLD_VAL(c)	(((c) & 0x1F) << 8)
#define INT_AGGR_TIMEOUT_VAL(t)		(((t) & 0xFF) << 0)

/* Interrupt disable masks */
enum {
	/* Interrupt disable mask for UFSHCI v1.0 */
	INTERRUPT_MASK_ALL_VER_10	= 0x30FFF,
	INTERRUPT_MASK_RW_VER_10	= 0x30000,

	/* Interrupt disable mask for UFSHCI v1.1 */
	INTERRUPT_MASK_ALL_VER_11	= 0x31FFF,

	/* Interrupt disable mask for UFSHCI v2.1 */
	INTERRUPT_MASK_ALL_VER_21	= 0x71FFF,
};

/* CCAP - Crypto Capability 100h */
union ufs_crypto_capabilities {
	__le32 reg_val;
	struct {
		u8 num_crypto_cap;
		u8 config_count;
		u8 reserved;
		u8 config_array_ptr;
	};
};

enum ufs_crypto_key_size {
	UFS_CRYPTO_KEY_SIZE_INVALID	= 0x0,
	UFS_CRYPTO_KEY_SIZE_128		= 0x1,
	UFS_CRYPTO_KEY_SIZE_192		= 0x2,
	UFS_CRYPTO_KEY_SIZE_256		= 0x3,
	UFS_CRYPTO_KEY_SIZE_512		= 0x4,
};

enum ufs_crypto_alg {
	UFS_CRYPTO_ALG_AES_XTS			= 0x0,
	UFS_CRYPTO_ALG_BITLOCKER_AES_CBC	= 0x1,
	UFS_CRYPTO_ALG_AES_ECB			= 0x2,
	UFS_CRYPTO_ALG_ESSIV_AES_CBC		= 0x3,
};

/* x-CRYPTOCAP - Crypto Capability X */
union ufs_crypto_cap_entry {
	__le32 reg_val;
	struct {
		u8 algorithm_id;
		u8 sdus_mask; /* Supported data unit size mask */
		u8 key_size;
		u8 reserved;
	};
};

#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
#define UFS_CRYPTO_KEY_MAX_SIZE 64
/* x-CRYPTOCFG - Crypto Configuration X */
union ufs_crypto_cfg_entry {
	__le32 reg_val[32];
	struct {
		u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
		u8 data_unit_size;
		u8 crypto_cap_idx;
		u8 reserved_1;
		u8 config_enable;
		u8 reserved_multi_host;
		u8 reserved_2;
		u8 vsb[2];
		u8 reserved_3[56];
	};
};

/*
 * Request Descriptor Definitions
 */

/* Transfer request command type */
enum {
	UTP_CMD_TYPE_SCSI		= 0x0,
	UTP_CMD_TYPE_UFS		= 0x1,
	UTP_CMD_TYPE_DEV_MANAGE		= 0x2,
};

/* To accommodate UFS2.0 required Command type */
enum {
	UTP_CMD_TYPE_UFS_STORAGE	= 0x1,
};

enum {
	UTP_SCSI_COMMAND		= 0x00000000,
	UTP_NATIVE_UFS_COMMAND		= 0x10000000,
	UTP_DEVICE_MANAGEMENT_FUNCTION	= 0x20000000,
	UTP_REQ_DESC_INT_CMD		= 0x01000000,
	UTP_REQ_DESC_CRYPTO_ENABLE_CMD	= 0x00800000,
};

/* UTP Transfer Request Data Direction (DD) */
enum {
	UTP_NO_DATA_TRANSFER	= 0x00000000,
	UTP_HOST_TO_DEVICE	= 0x02000000,
	UTP_DEVICE_TO_HOST	= 0x04000000,
};

/* Overall command status values */
enum utp_ocs {
	OCS_SUCCESS			= 0x0,
	OCS_INVALID_CMD_TABLE_ATTR	= 0x1,
	OCS_INVALID_PRDT_ATTR		= 0x2,
	OCS_MISMATCH_DATA_BUF_SIZE	= 0x3,
	OCS_MISMATCH_RESP_UPIU_SIZE	= 0x4,
	OCS_PEER_COMM_FAILURE		= 0x5,
	OCS_ABORTED			= 0x6,
	OCS_FATAL_ERROR			= 0x7,
	OCS_DEVICE_FATAL_ERROR		= 0x8,
	OCS_INVALID_CRYPTO_CONFIG	= 0x9,
	OCS_GENERAL_CRYPTO_ERROR	= 0xA,
	OCS_INVALID_COMMAND_STATUS	= 0x0F,
};

enum {
	MASK_OCS			= 0x0F,
};

/* The maximum length of the data byte count field in the PRDT is 256KB */
#define PRDT_DATA_BYTE_COUNT_MAX	(256 * 1024)
/* The granularity of the data byte count field in the PRDT is 32-bit */
#define PRDT_DATA_BYTE_COUNT_PAD	4

/**
 * struct ufshcd_sg_entry - UFSHCI PRD Entry
 * @addr: Physical address; DW-0 and DW-1.
 * @reserved: Reserved for future use DW-2
 * @size: size of physical segment DW-3
 */
struct ufshcd_sg_entry {
	__le64    addr;
	__le32    reserved;
	__le32    size;
	/*
	 * followed by variant-specific fields if
	 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined.
	 */
};

/**
 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
 * @command_upiu: Command UPIU Frame address
 * @response_upiu: Response UPIU Frame address
 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct
 *	ufshcd_sg_entry's.  Variant-specific fields may be present after each.
 */
struct utp_transfer_cmd_desc {
	u8 command_upiu[ALIGNED_UPIU_SIZE];
	u8 response_upiu[ALIGNED_UPIU_SIZE];
	u8 prd_table[];
};

/**
 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
 * @dword0: Descriptor Header DW0
 * @dword1: Descriptor Header DW1
 * @dword2: Descriptor Header DW2
 * @dword3: Descriptor Header DW3
 */
struct request_desc_header {
	__le32 dword_0;
	__le32 dword_1;
	__le32 dword_2;
	__le32 dword_3;
};

/**
 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
 * @header: UTRD header DW-0 to DW-3
 * @command_desc_base_addr_lo: UCD base address low DW-4
 * @command_desc_base_addr_hi: UCD base address high DW-5
 * @response_upiu_length: response UPIU length DW-6
 * @response_upiu_offset: response UPIU offset DW-6
 * @prd_table_length: Physical region descriptor length DW-7
 * @prd_table_offset: Physical region descriptor offset DW-7
 */
struct utp_transfer_req_desc {

	/* DW 0-3 */
	struct request_desc_header header;

	/* DW 4-5*/
	__le32  command_desc_base_addr_lo;
	__le32  command_desc_base_addr_hi;

	/* DW 6 */
	__le16  response_upiu_length;
	__le16  response_upiu_offset;

	/* DW 7 */
	__le16  prd_table_length;
	__le16  prd_table_offset;
};

/* MCQ Completion Queue Entry */
struct cq_entry {
	/* DW 0-1 */
	__le64 command_desc_base_addr;

	/* DW 2 */
	__le16  response_upiu_length;
	__le16  response_upiu_offset;

	/* DW 3 */
	__le16  prd_table_length;
	__le16  prd_table_offset;

	/* DW 4 */
	__le32 status;

	/* DW 5-7 */
	__le32 reserved[3];
};

static_assert(sizeof(struct cq_entry) == 32);

/*
 * UTMRD structure.
 */
struct utp_task_req_desc {
	/* DW 0-3 */
	struct request_desc_header header;

	/* DW 4-11 - Task request UPIU structure */
	struct {
		struct utp_upiu_header	req_header;
		__be32			input_param1;
		__be32			input_param2;
		__be32			input_param3;
		__be32			__reserved1[2];
	} upiu_req;

	/* DW 12-19 - Task Management Response UPIU structure */
	struct {
		struct utp_upiu_header	rsp_header;
		__be32			output_param1;
		__be32			output_param2;
		__be32			__reserved2[3];
	} upiu_rsp;
};

#endif /* End of Header */
Commit	Line	Data
67351119	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
7a3e97b0 SY	2	/*
7a3e97b0 SY	3	* Universal Flash Storage Host controller driver
3b1d0580	4	* Copyright (C) 2011-2013 Samsung India Software Operations
7a3e97b0	5	*
3b1d0580 VH	6	* Authors:
	7	* Santosh Yaraganavi <santosh.sy@samsung.com>
	8	* Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0 SY	9	*/
	10
	11	#ifndef _UFSHCI_H
	12	#define _UFSHCI_H
	13
3f06f780 BVA	14	#include <scsi/scsi_host.h>
3f06f780 BVA	15
7a3e97b0 SY	16	enum {
	17	TASK_REQ_UPIU_SIZE_DWORDS = 8,
	18	TASK_RSP_UPIU_SIZE_DWORDS = 8,
68078d5c	19	ALIGNED_UPIU_SIZE = 512,
7a3e97b0 SY	20	};
	21
	22	/* UFSHCI Registers */
	23	enum {
	24	REG_CONTROLLER_CAPABILITIES = 0x00,
6e1d850a	25	REG_MCQCAP = 0x04,
7a3e97b0 SY	26	REG_UFS_VERSION = 0x08,
	27	REG_CONTROLLER_DEV_ID = 0x10,
	28	REG_CONTROLLER_PROD_ID = 0x14,
f6b25451	29	REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
7a3e97b0 SY	30	REG_INTERRUPT_STATUS = 0x20,
	31	REG_INTERRUPT_ENABLE = 0x24,
	32	REG_CONTROLLER_STATUS = 0x30,
	33	REG_CONTROLLER_ENABLE = 0x34,
	34	REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
	35	REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
	36	REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
	37	REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
	38	REG_UIC_ERROR_CODE_DME = 0x48,
	39	REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
	40	REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
	41	REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
	42	REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
	43	REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
	44	REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
	45	REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
	46	REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
	47	REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
	48	REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
	49	REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
	50	REG_UIC_COMMAND = 0x90,
	51	REG_UIC_COMMAND_ARG_1 = 0x94,
	52	REG_UIC_COMMAND_ARG_2 = 0x98,
	53	REG_UIC_COMMAND_ARG_3 = 0x9C,
66cc820f DR	54
	55	UFSHCI_REG_SPACE_SIZE = 0xA0,
	56
c01848c6 YG	57	REG_UFS_CCAP = 0x100,
	58	REG_UFS_CRYPTOCAP = 0x104,
	59
2468da61	60	REG_UFS_MEM_CFG = 0x300,
7224c806	61	REG_UFS_MCQ_CFG = 0x380,
e02288e0 CG	62	REG_UFS_ESILBA = 0x384,
e02288e0 CG	63	REG_UFS_ESIUBA = 0x388,
c01848c6	64	UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
7a3e97b0 SY	65	};
	66
	67	/* Controller capability masks */
	68	enum {
	69	MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
	70	MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
6ff265fc	71	MASK_EHSLUTRD_SUPPORTED = 0x00400000,
ad448378	72	MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
7a3e97b0 SY	73	MASK_64_ADDRESSING_SUPPORT = 0x01000000,
	74	MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
	75	MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
5e7341e1	76	MASK_CRYPTO_SUPPORT = 0x10000000,
6e1d850a AD	77	MASK_MCQ_SUPPORT = 0x40000000,
	78	};
	79
	80	/* MCQ capability mask */
	81	enum {
	82	MASK_EXT_IID_SUPPORT = 0x00000400,
7a3e97b0 SY	83	};
7a3e97b0 SY	84
2468da61 AD	85	enum {
	86	REG_SQATTR = 0x0,
	87	REG_SQLBA = 0x4,
	88	REG_SQUBA = 0x8,
	89	REG_SQDAO = 0xC,
	90	REG_SQISAO = 0x10,
	91
	92	REG_CQATTR = 0x20,
	93	REG_CQLBA = 0x24,
	94	REG_CQUBA = 0x28,
	95	REG_CQDAO = 0x2C,
	96	REG_CQISAO = 0x30,
	97	};
	98
	99	enum {
	100	REG_SQHP = 0x0,
	101	REG_SQTP = 0x4,
	102	};
	103
	104	enum {
	105	REG_CQHP = 0x0,
	106	REG_CQTP = 0x4,
	107	};
	108
	109	enum {
	110	REG_CQIS = 0x0,
	111	REG_CQIE = 0x4,
	112	};
	113
679882ae S	114	#define UFS_MASK(mask, offset) ((mask) << (offset))
679882ae S	115
7a3e97b0 SY	116	/* UFS Version 08h */
	117	#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
	118	#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
	119
51428818 CC	120	/*
	121	* Controller UFSHCI version
	122	* - 2.x and newer use the following scheme:
	123	* major << 8 + minor << 4
	124	* - 1.x has been converted to match this in
	125	* ufshcd_get_ufs_version()
	126	*/
	127	static inline u32 ufshci_version(u32 major, u32 minor)
	128	{
	129	return (major << 8) + (minor << 4);
	130	}
7a3e97b0 SY	131
	132	/*
	133	* HCDDID - Host Controller Identification Descriptor
	134	* - Device ID and Device Class 10h
	135	*/
	136	#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
	137	#define DEVICE_ID UFS_MASK(0xFF, 24)
	138
	139	/*
	140	* HCPMID - Host Controller Identification Descriptor
	141	* - Product/Manufacturer ID 14h
	142	*/
	143	#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
	144	#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
	145
ad448378 AH	146	/* AHIT - Auto-Hibernate Idle Timer */
	147	#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
	148	#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
	149	#define UFSHCI_AHIBERN8_SCALE_FACTOR 10
	150	#define UFSHCI_AHIBERN8_MAX (1023 * 100000)
	151
cc81641a AA	152	/*
	153	* IS - Interrupt Status - 20h
	154	*/
	155	#define UTP_TRANSFER_REQ_COMPL 0x1
	156	#define UIC_DME_END_PT_RESET 0x2
	157	#define UIC_ERROR 0x4
	158	#define UIC_TEST_MODE 0x8
	159	#define UIC_POWER_MODE 0x10
	160	#define UIC_HIBERNATE_EXIT 0x20
	161	#define UIC_HIBERNATE_ENTER 0x40
	162	#define UIC_LINK_LOST 0x80
	163	#define UIC_LINK_STARTUP 0x100
	164	#define UTP_TASK_REQ_COMPL 0x200
	165	#define UIC_COMMAND_COMPL 0x400
	166	#define DEVICE_FATAL_ERROR 0x800
	167	#define CONTROLLER_FATAL_ERROR 0x10000
	168	#define SYSTEM_BUS_FATAL_ERROR 0x20000
5e7341e1	169	#define CRYPTO_ENGINE_FATAL_ERROR 0x40000
2468da61	170	#define MCQ_CQ_EVENT_STATUS 0x100000
7a3e97b0	171
82174440 SC	172	#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER \|\
	173	UIC_HIBERNATE_EXIT)
	174
	175	#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK \|\
57d104c1 SJ	176	UIC_POWER_MODE)
	177
	178	#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL \| UFSHCD_UIC_PWR_MASK)
53b3d9c3	179
6d17a112	180	#define UFSHCD_ERROR_MASK (UIC_ERROR \| INT_FATAL_ERRORS)
7a3e97b0 SY	181
	182	#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR \|\
	183	CONTROLLER_FATAL_ERROR \|\
5e7341e1	184	SYSTEM_BUS_FATAL_ERROR \|\
c99b9b23 KK	185	CRYPTO_ENGINE_FATAL_ERROR \|\
c99b9b23 KK	186	UIC_LINK_LOST)
7a3e97b0 SY	187
7a3e97b0 SY	188	/* HCS - Host Controller Status 30h */
cc81641a AA	189	#define DEVICE_PRESENT 0x1
	190	#define UTP_TRANSFER_REQ_LIST_READY 0x2
	191	#define UTP_TASK_REQ_LIST_READY 0x4
	192	#define UIC_COMMAND_READY 0x8
cffe3ff3	193	#define HOST_ERROR_INDICATOR 0x10
cffe3ff3	194	#define DEVICE_ERROR_INDICATOR 0x20
7a3e97b0 SY	195	#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
7a3e97b0 SY	196
6cf16115 TK	197	#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY \|\
	198	UTP_TASK_REQ_LIST_READY \|\
	199	UIC_COMMAND_READY)
	200
53b3d9c3 SJ	201	enum {
	202	PWR_OK = 0x0,
	203	PWR_LOCAL = 0x01,
	204	PWR_REMOTE = 0x02,
	205	PWR_BUSY = 0x03,
	206	PWR_ERROR_CAP = 0x04,
	207	PWR_FATAL_ERROR = 0x05,
	208	};
	209
7a3e97b0	210	/* HCE - Host Controller Enable 34h */
cc81641a	211	#define CONTROLLER_ENABLE 0x1
7a3e97b0	212	#define CONTROLLER_DISABLE 0x0
cc81641a	213	#define CRYPTO_GENERAL_ENABLE 0x2
7a3e97b0 SY	214
7a3e97b0 SY	215	/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
cc81641a	216	#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
7a3e97b0	217	#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
fb7b45f0	218	#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
2355b66e	219	#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
7a3e97b0 SY	220
7a3e97b0 SY	221	/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
cc81641a	222	#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
9333d775	223	#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
cffe3ff3	224	#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
	225	#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
	226	#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
	227	#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
7a3e97b0	228	#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
583fa62d YG	229	#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
583fa62d YG	230	#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
7a3e97b0 SY	231
7a3e97b0 SY	232	/* UECN - Host UIC Error Code Network Layer 40h */
cc81641a	233	#define UIC_NETWORK_LAYER_ERROR 0x80000000
7a3e97b0	234	#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
cffe3ff3	235	#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
	236	#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
	237	#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
7a3e97b0 SY	238
7a3e97b0 SY	239	/* UECT - Host UIC Error Code Transport Layer 44h */
cc81641a	240	#define UIC_TRANSPORT_LAYER_ERROR 0x80000000
7a3e97b0	241	#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
cffe3ff3	242	#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
	243	#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
	244	#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
	245	#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
	246	#define UIC_TRANSPORT_BAD_TC 0x10
	247	#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
	248	#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
7a3e97b0 SY	249
7a3e97b0 SY	250	/* UECDME - Host UIC Error Code DME 48h */
cc81641a	251	#define UIC_DME_ERROR 0x80000000
7a3e97b0 SY	252	#define UIC_DME_ERROR_CODE_MASK 0x1
7a3e97b0 SY	253
cc81641a	254	/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
7a3e97b0 SY	255	#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
7a3e97b0 SY	256	#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
cc81641a AA	257	#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
	258	#define INT_AGGR_STATUS_BIT 0x100000
	259	#define INT_AGGR_PARAM_WRITE 0x1000000
	260	#define INT_AGGR_ENABLE 0x80000000
7a3e97b0 SY	261
7a3e97b0 SY	262	/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
cc81641a	263	#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
7a3e97b0 SY	264
7a3e97b0 SY	265	/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
cc81641a	266	#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
7a3e97b0	267
f87b2c41 AD	268	/* CQISy - CQ y Interrupt Status Register */
	269	#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1
	270
7a3e97b0 SY	271	/* UICCMD - UIC Command */
	272	#define COMMAND_OPCODE_MASK 0xFF
	273	#define GEN_SELECTOR_INDEX_MASK 0xFFFF
	274
	275	#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
	276	#define RESET_LEVEL 0xFF
	277
	278	#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
	279	#define CONFIG_RESULT_CODE_MASK 0xFF
	280	#define GENERIC_ERROR_CODE_MASK 0xFF
	281
7ca38cf3 YG	282	/* GenSelectorIndex calculation macros for M-PHY attributes */
7ca38cf3 YG	283	#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
37113106	284	#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
7ca38cf3	285
12b4fdb4 SJ	286	#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) \|\
	287	((sel) & 0xFFFF))
	288	#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
	289	#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
	290	#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
	291
79fcc033 JP	292	/* Link Status*/
	293	enum link_status {
	294	UFSHCD_LINK_IS_DOWN = 1,
	295	UFSHCD_LINK_IS_UP = 2,
	296	};
	297
7a3e97b0	298	/* UIC Commands */
57d104c1	299	enum uic_cmd_dme {
7a3e97b0 SY	300	UIC_CMD_DME_GET = 0x01,
	301	UIC_CMD_DME_SET = 0x02,
	302	UIC_CMD_DME_PEER_GET = 0x03,
	303	UIC_CMD_DME_PEER_SET = 0x04,
	304	UIC_CMD_DME_POWERON = 0x10,
	305	UIC_CMD_DME_POWEROFF = 0x11,
	306	UIC_CMD_DME_ENABLE = 0x12,
	307	UIC_CMD_DME_RESET = 0x14,
	308	UIC_CMD_DME_END_PT_RST = 0x15,
	309	UIC_CMD_DME_LINK_STARTUP = 0x16,
	310	UIC_CMD_DME_HIBER_ENTER = 0x17,
	311	UIC_CMD_DME_HIBER_EXIT = 0x18,
	312	UIC_CMD_DME_TEST_MODE = 0x1A,
	313	};
	314
	315	/* UIC Config result code / Generic error code */
	316	enum {
	317	UIC_CMD_RESULT_SUCCESS = 0x00,
	318	UIC_CMD_RESULT_INVALID_ATTR = 0x01,
	319	UIC_CMD_RESULT_FAILURE = 0x01,
	320	UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
	321	UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
	322	UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
	323	UIC_CMD_RESULT_BAD_INDEX = 0x05,
	324	UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
	325	UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
	326	UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
	327	UIC_CMD_RESULT_BUSY = 0x09,
	328	UIC_CMD_RESULT_DME_FAILURE = 0x0A,
	329	};
	330
	331	#define MASK_UIC_COMMAND_RESULT 0xFF
	332
7d568652 SJ	333	#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
7d568652 SJ	334	#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
7a3e97b0 SY	335
	336	/* Interrupt disable masks */
	337	enum {
	338	/* Interrupt disable mask for UFSHCI v1.0 */
2fbd009b SJ	339	INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
2fbd009b SJ	340	INTERRUPT_MASK_RW_VER_10 = 0x30000,
7a3e97b0 SY	341
7a3e97b0 SY	342	/* Interrupt disable mask for UFSHCI v1.1 */
2fbd009b	343	INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
c01848c6 YG	344
	345	/* Interrupt disable mask for UFSHCI v2.1 */
	346	INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
7a3e97b0 SY	347	};
7a3e97b0 SY	348
5e7341e1 ST	349	/* CCAP - Crypto Capability 100h */
	350	union ufs_crypto_capabilities {
	351	__le32 reg_val;
	352	struct {
	353	u8 num_crypto_cap;
	354	u8 config_count;
	355	u8 reserved;
	356	u8 config_array_ptr;
	357	};
	358	};
	359
	360	enum ufs_crypto_key_size {
	361	UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
	362	UFS_CRYPTO_KEY_SIZE_128 = 0x1,
	363	UFS_CRYPTO_KEY_SIZE_192 = 0x2,
	364	UFS_CRYPTO_KEY_SIZE_256 = 0x3,
	365	UFS_CRYPTO_KEY_SIZE_512 = 0x4,
	366	};
	367
	368	enum ufs_crypto_alg {
	369	UFS_CRYPTO_ALG_AES_XTS = 0x0,
	370	UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
	371	UFS_CRYPTO_ALG_AES_ECB = 0x2,
	372	UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
	373	};
	374
	375	/* x-CRYPTOCAP - Crypto Capability X */
	376	union ufs_crypto_cap_entry {
	377	__le32 reg_val;
	378	struct {
	379	u8 algorithm_id;
	380	u8 sdus_mask; /* Supported data unit size mask */
	381	u8 key_size;
	382	u8 reserved;
	383	};
	384	};
	385
	386	#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
	387	#define UFS_CRYPTO_KEY_MAX_SIZE 64
	388	/* x-CRYPTOCFG - Crypto Configuration X */
	389	union ufs_crypto_cfg_entry {
	390	__le32 reg_val[32];
	391	struct {
	392	u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
	393	u8 data_unit_size;
	394	u8 crypto_cap_idx;
	395	u8 reserved_1;
	396	u8 config_enable;
	397	u8 reserved_multi_host;
	398	u8 reserved_2;
	399	u8 vsb[2];
	400	u8 reserved_3[56];
	401	};
	402	};
	403
7a3e97b0 SY	404	/*
	405	* Request Descriptor Definitions
	406	*/
	407
	408	/* Transfer request command type */
	409	enum {
	410	UTP_CMD_TYPE_SCSI = 0x0,
	411	UTP_CMD_TYPE_UFS = 0x1,
	412	UTP_CMD_TYPE_DEV_MANAGE = 0x2,
	413	};
	414
300bb13f JP	415	/* To accommodate UFS2.0 required Command type */
	416	enum {
	417	UTP_CMD_TYPE_UFS_STORAGE = 0x1,
	418	};
	419
7a3e97b0 SY	420	enum {
	421	UTP_SCSI_COMMAND = 0x00000000,
	422	UTP_NATIVE_UFS_COMMAND = 0x10000000,
	423	UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
	424	UTP_REQ_DESC_INT_CMD = 0x01000000,
5e7341e1	425	UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000,
7a3e97b0 SY	426	};
	427
	428	/* UTP Transfer Request Data Direction (DD) */
	429	enum {
	430	UTP_NO_DATA_TRANSFER = 0x00000000,
	431	UTP_HOST_TO_DEVICE = 0x02000000,
	432	UTP_DEVICE_TO_HOST = 0x04000000,
	433	};
	434
	435	/* Overall command status values */
957d63e7	436	enum utp_ocs {
7a3e97b0 SY	437	OCS_SUCCESS = 0x0,
	438	OCS_INVALID_CMD_TABLE_ATTR = 0x1,
	439	OCS_INVALID_PRDT_ATTR = 0x2,
	440	OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
	441	OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
	442	OCS_PEER_COMM_FAILURE = 0x5,
	443	OCS_ABORTED = 0x6,
	444	OCS_FATAL_ERROR = 0x7,
5e7341e1 ST	445	OCS_DEVICE_FATAL_ERROR = 0x8,
	446	OCS_INVALID_CRYPTO_CONFIG = 0x9,
	447	OCS_GENERAL_CRYPTO_ERROR = 0xA,
7a3e97b0	448	OCS_INVALID_COMMAND_STATUS = 0x0F,
957d63e7 BVA	449	};
	450
	451	enum {
7a3e97b0 SY	452	MASK_OCS = 0x0F,
	453	};
	454
eeda4749 AM	455	/* The maximum length of the data byte count field in the PRDT is 256KB */
	456	#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
	457	/* The granularity of the data byte count field in the PRDT is 32-bit */
	458	#define PRDT_DATA_BYTE_COUNT_PAD 4
	459
7a3e97b0 SY	460	/**
7a3e97b0 SY	461	* struct ufshcd_sg_entry - UFSHCI PRD Entry
1ea7d802	462	* @addr: Physical address; DW-0 and DW-1.
7a3e97b0 SY	463	* @reserved: Reserved for future use DW-2
	464	* @size: size of physical segment DW-3
	465	*/
	466	struct ufshcd_sg_entry {
1ea7d802	467	__le64 addr;
e8c8e82a SRT	468	__le32 reserved;
e8c8e82a SRT	469	__le32 size;
ada1e653 EB	470	/*
	471	* followed by variant-specific fields if
	472	* CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined.
	473	*/
7a3e97b0 SY	474	};
	475
	476	/**
91bb765c	477	* struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
7a3e97b0 SY	478	* @command_upiu: Command UPIU Frame address
7a3e97b0 SY	479	* @response_upiu: Response UPIU Frame address
ada1e653 EB	480	* @prd_table: Physical Region Descriptor: an array of SG_ALL struct
ada1e653 EB	481	* ufshcd_sg_entry's. Variant-specific fields may be present after each.
7a3e97b0 SY	482	*/
	483	struct utp_transfer_cmd_desc {
	484	u8 command_upiu[ALIGNED_UPIU_SIZE];
	485	u8 response_upiu[ALIGNED_UPIU_SIZE];
ada1e653	486	u8 prd_table[];
7a3e97b0 SY	487	};
	488
	489	/**
	490	* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
	491	* @dword0: Descriptor Header DW0
	492	* @dword1: Descriptor Header DW1
	493	* @dword2: Descriptor Header DW2
	494	* @dword3: Descriptor Header DW3
	495	*/
	496	struct request_desc_header {
e8c8e82a SRT	497	__le32 dword_0;
	498	__le32 dword_1;
	499	__le32 dword_2;
	500	__le32 dword_3;
7a3e97b0 SY	501	};
	502
	503	/**
91bb765c	504	* struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
7a3e97b0 SY	505	* @header: UTRD header DW-0 to DW-3
	506	* @command_desc_base_addr_lo: UCD base address low DW-4
	507	* @command_desc_base_addr_hi: UCD base address high DW-5
	508	* @response_upiu_length: response UPIU length DW-6
	509	* @response_upiu_offset: response UPIU offset DW-6
	510	* @prd_table_length: Physical region descriptor length DW-7
	511	* @prd_table_offset: Physical region descriptor offset DW-7
	512	*/
	513	struct utp_transfer_req_desc {
	514
	515	/* DW 0-3 */
	516	struct request_desc_header header;
	517
	518	/* DW 4-5*/
e8c8e82a SRT	519	__le32 command_desc_base_addr_lo;
e8c8e82a SRT	520	__le32 command_desc_base_addr_hi;
7a3e97b0 SY	521
7a3e97b0 SY	522	/* DW 6 */
e8c8e82a SRT	523	__le16 response_upiu_length;
e8c8e82a SRT	524	__le16 response_upiu_offset;
7a3e97b0 SY	525
7a3e97b0 SY	526	/* DW 7 */
e8c8e82a SRT	527	__le16 prd_table_length;
e8c8e82a SRT	528	__le16 prd_table_offset;
7a3e97b0 SY	529	};
7a3e97b0 SY	530
4682abfa AD	531	/* MCQ Completion Queue Entry */
	532	struct cq_entry {
	533	/* DW 0-1 */
	534	__le64 command_desc_base_addr;
	535
	536	/* DW 2 */
	537	__le16 response_upiu_length;
	538	__le16 response_upiu_offset;
	539
	540	/* DW 3 */
	541	__le16 prd_table_length;
	542	__le16 prd_table_offset;
	543
	544	/* DW 4 */
	545	__le32 status;
	546
	547	/* DW 5-7 */
	548	__le32 reserved[3];
	549	};
	550
	551	static_assert(sizeof(struct cq_entry) == 32);
	552
391e388f CH	553	/*
391e388f CH	554	* UTMRD structure.
7a3e97b0 SY	555	*/
7a3e97b0 SY	556	struct utp_task_req_desc {
7a3e97b0 SY	557	/* DW 0-3 */
	558	struct request_desc_header header;
	559
391e388f	560	/* DW 4-11 - Task request UPIU structure */
1352eec8 GS	561	struct {
	562	struct utp_upiu_header req_header;
	563	__be32 input_param1;
	564	__be32 input_param2;
	565	__be32 input_param3;
	566	__be32 __reserved1[2];
	567	} upiu_req;
391e388f CH	568
391e388f CH	569	/* DW 12-19 - Task Management Response UPIU structure */
1352eec8 GS	570	struct {
	571	struct utp_upiu_header rsp_header;
	572	__be32 output_param1;
	573	__be32 output_param2;
	574	__be32 __reserved2[3];
	575	} upiu_rsp;
7a3e97b0 SY	576	};
	577
	578	#endif /* End of Header */