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67351119 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
e0eca63e VH |
2 | /* |
3 | * Universal Flash Storage Host controller driver | |
e0eca63e | 4 | * Copyright (C) 2011-2013 Samsung India Software Operations |
dc3c8d3a | 5 | * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
e0eca63e VH |
6 | * |
7 | * Authors: | |
8 | * Santosh Yaraganavi <santosh.sy@samsung.com> | |
9 | * Vinayak Holikatti <h.vinayak@samsung.com> | |
e0eca63e VH |
10 | */ |
11 | ||
12 | #ifndef _UFSHCD_H | |
13 | #define _UFSHCD_H | |
14 | ||
5a244e0e | 15 | #include <linux/bitfield.h> |
1e8d44bd | 16 | #include <linux/blk-crypto-profile.h> |
3f06f780 BVA |
17 | #include <linux/blk-mq.h> |
18 | #include <linux/devfreq.h> | |
045da307 | 19 | #include <linux/fault-inject.h> |
e02288e0 | 20 | #include <linux/msi.h> |
3f06f780 | 21 | #include <linux/pm_runtime.h> |
f3e57da5 | 22 | #include <linux/dma-direction.h> |
3f06f780 | 23 | #include <scsi/scsi_device.h> |
cce9fd60 | 24 | #include <scsi/scsi_host.h> |
dd11376b BVA |
25 | #include <ufs/unipro.h> |
26 | #include <ufs/ufs.h> | |
27 | #include <ufs/ufs_quirks.h> | |
28 | #include <ufs/ufshci.h> | |
e0eca63e VH |
29 | |
30 | #define UFSHCD "ufshcd" | |
e0eca63e | 31 | |
858231bd | 32 | struct scsi_device; |
5c0c28a8 SRT |
33 | struct ufs_hba; |
34 | ||
5a0b0cb9 SRT |
35 | enum dev_cmd_type { |
36 | DEV_CMD_TYPE_NOP = 0x0, | |
68078d5c | 37 | DEV_CMD_TYPE_QUERY = 0x1, |
6ff265fc | 38 | DEV_CMD_TYPE_RPMB = 0x2, |
5a0b0cb9 SRT |
39 | }; |
40 | ||
e965e5e0 SC |
41 | enum ufs_event_type { |
42 | /* uic specific errors */ | |
43 | UFS_EVT_PA_ERR = 0, | |
44 | UFS_EVT_DL_ERR, | |
45 | UFS_EVT_NL_ERR, | |
46 | UFS_EVT_TL_ERR, | |
47 | UFS_EVT_DME_ERR, | |
48 | ||
49 | /* fatal errors */ | |
50 | UFS_EVT_AUTO_HIBERN8_ERR, | |
51 | UFS_EVT_FATAL_ERR, | |
52 | UFS_EVT_LINK_STARTUP_FAIL, | |
53 | UFS_EVT_RESUME_ERR, | |
54 | UFS_EVT_SUSPEND_ERR, | |
b294ff3e AD |
55 | UFS_EVT_WL_SUSP_ERR, |
56 | UFS_EVT_WL_RES_ERR, | |
e965e5e0 SC |
57 | |
58 | /* abnormal events */ | |
59 | UFS_EVT_DEV_RESET, | |
60 | UFS_EVT_HOST_RESET, | |
61 | UFS_EVT_ABORT, | |
62 | ||
63 | UFS_EVT_CNT, | |
64 | }; | |
65 | ||
e0eca63e VH |
66 | /** |
67 | * struct uic_command - UIC command structure | |
68 | * @command: UIC command | |
69 | * @argument1: UIC command argument 1 | |
70 | * @argument2: UIC command argument 2 | |
71 | * @argument3: UIC command argument 3 | |
0f52fcb9 | 72 | * @cmd_active: Indicate if UIC command is outstanding |
6ccf44fe | 73 | * @done: UIC command completion |
e0eca63e VH |
74 | */ |
75 | struct uic_command { | |
76 | u32 command; | |
77 | u32 argument1; | |
78 | u32 argument2; | |
79 | u32 argument3; | |
0f52fcb9 | 80 | int cmd_active; |
6ccf44fe | 81 | struct completion done; |
e0eca63e VH |
82 | }; |
83 | ||
57d104c1 SJ |
84 | /* Used to differentiate the power management options */ |
85 | enum ufs_pm_op { | |
86 | UFS_RUNTIME_PM, | |
87 | UFS_SYSTEM_PM, | |
88 | UFS_SHUTDOWN_PM, | |
89 | }; | |
90 | ||
57d104c1 SJ |
91 | /* Host <-> Device UniPro Link state */ |
92 | enum uic_link_state { | |
93 | UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ | |
94 | UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ | |
95 | UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ | |
4db7a236 | 96 | UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ |
57d104c1 SJ |
97 | }; |
98 | ||
99 | #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) | |
100 | #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ | |
101 | UIC_LINK_ACTIVE_STATE) | |
102 | #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ | |
103 | UIC_LINK_HIBERN8_STATE) | |
4db7a236 CG |
104 | #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ |
105 | UIC_LINK_BROKEN_STATE) | |
57d104c1 SJ |
106 | #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) |
107 | #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ | |
108 | UIC_LINK_ACTIVE_STATE) | |
109 | #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ | |
110 | UIC_LINK_HIBERN8_STATE) | |
4db7a236 CG |
111 | #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ |
112 | UIC_LINK_BROKEN_STATE) | |
57d104c1 | 113 | |
1764fa2a SC |
114 | #define ufshcd_set_ufs_dev_active(h) \ |
115 | ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) | |
116 | #define ufshcd_set_ufs_dev_sleep(h) \ | |
117 | ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) | |
118 | #define ufshcd_set_ufs_dev_poweroff(h) \ | |
119 | ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) | |
fe1d4c2e AH |
120 | #define ufshcd_set_ufs_dev_deepsleep(h) \ |
121 | ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) | |
1764fa2a SC |
122 | #define ufshcd_is_ufs_dev_active(h) \ |
123 | ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) | |
124 | #define ufshcd_is_ufs_dev_sleep(h) \ | |
125 | ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) | |
126 | #define ufshcd_is_ufs_dev_poweroff(h) \ | |
127 | ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) | |
fe1d4c2e AH |
128 | #define ufshcd_is_ufs_dev_deepsleep(h) \ |
129 | ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) | |
1764fa2a | 130 | |
57d104c1 SJ |
131 | /* |
132 | * UFS Power management levels. | |
fe1d4c2e AH |
133 | * Each level is in increasing order of power savings, except DeepSleep |
134 | * which is lower than PowerDown with power on but not PowerDown with | |
135 | * power off. | |
57d104c1 SJ |
136 | */ |
137 | enum ufs_pm_level { | |
e2ac7ab2 BVA |
138 | UFS_PM_LVL_0, |
139 | UFS_PM_LVL_1, | |
140 | UFS_PM_LVL_2, | |
141 | UFS_PM_LVL_3, | |
142 | UFS_PM_LVL_4, | |
143 | UFS_PM_LVL_5, | |
144 | UFS_PM_LVL_6, | |
57d104c1 SJ |
145 | UFS_PM_LVL_MAX |
146 | }; | |
147 | ||
148 | struct ufs_pm_lvl_states { | |
149 | enum ufs_dev_pwr_mode dev_state; | |
150 | enum uic_link_state link_state; | |
151 | }; | |
152 | ||
e0eca63e VH |
153 | /** |
154 | * struct ufshcd_lrb - local reference block | |
155 | * @utr_descriptor_ptr: UTRD address of the command | |
5a0b0cb9 | 156 | * @ucd_req_ptr: UCD address of the command |
e0eca63e VH |
157 | * @ucd_rsp_ptr: Response UPIU address for this command |
158 | * @ucd_prdt_ptr: PRDT address of the command | |
ff8e20c6 DR |
159 | * @utrd_dma_addr: UTRD dma address for debug |
160 | * @ucd_prdt_dma_addr: PRDT dma address for debug | |
161 | * @ucd_rsp_dma_addr: UPIU response dma address for debug | |
162 | * @ucd_req_dma_addr: UPIU request dma address for debug | |
e0eca63e | 163 | * @cmd: pointer to SCSI command |
e0eca63e VH |
164 | * @scsi_status: SCSI status of the command |
165 | * @command_type: SCSI, UFS, Query. | |
166 | * @task_tag: Task tag of the command | |
167 | * @lun: LUN of the command | |
5a0b0cb9 | 168 | * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) |
0f85e747 DL |
169 | * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) |
170 | * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) | |
171 | * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) | |
172 | * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) | |
df043c74 ST |
173 | * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) |
174 | * @data_unit_num: the data unit number for the first block for inline crypto | |
e0b299e3 | 175 | * @req_abort_skip: skip request abort task flag |
e0eca63e VH |
176 | */ |
177 | struct ufshcd_lrb { | |
178 | struct utp_transfer_req_desc *utr_descriptor_ptr; | |
5a0b0cb9 | 179 | struct utp_upiu_req *ucd_req_ptr; |
e0eca63e VH |
180 | struct utp_upiu_rsp *ucd_rsp_ptr; |
181 | struct ufshcd_sg_entry *ucd_prdt_ptr; | |
182 | ||
ff8e20c6 DR |
183 | dma_addr_t utrd_dma_addr; |
184 | dma_addr_t ucd_req_dma_addr; | |
185 | dma_addr_t ucd_rsp_dma_addr; | |
186 | dma_addr_t ucd_prdt_dma_addr; | |
187 | ||
e0eca63e | 188 | struct scsi_cmnd *cmd; |
e0eca63e VH |
189 | int scsi_status; |
190 | ||
191 | int command_type; | |
192 | int task_tag; | |
0ce147d4 | 193 | u8 lun; /* UPIU LUN id field is only 8-bit wide */ |
5a0b0cb9 | 194 | bool intr_cmd; |
ff8e20c6 | 195 | ktime_t issue_time_stamp; |
0f85e747 | 196 | u64 issue_time_stamp_local_clock; |
09017188 | 197 | ktime_t compl_time_stamp; |
0f85e747 | 198 | u64 compl_time_stamp_local_clock; |
df043c74 ST |
199 | #ifdef CONFIG_SCSI_UFS_CRYPTO |
200 | int crypto_key_slot; | |
201 | u64 data_unit_num; | |
202 | #endif | |
e0b299e3 GB |
203 | |
204 | bool req_abort_skip; | |
e0eca63e VH |
205 | }; |
206 | ||
e2566e0b BVA |
207 | /** |
208 | * struct ufs_query_req - parameters for building a query request | |
209 | * @query_func: UPIU header query function | |
210 | * @upiu_req: the query request data | |
211 | */ | |
212 | struct ufs_query_req { | |
213 | u8 query_func; | |
214 | struct utp_upiu_query upiu_req; | |
215 | }; | |
216 | ||
217 | /** | |
218 | * struct ufs_query_resp - UPIU QUERY | |
219 | * @response: device response code | |
220 | * @upiu_res: query response data | |
221 | */ | |
222 | struct ufs_query_res { | |
223 | struct utp_upiu_query upiu_res; | |
224 | }; | |
225 | ||
68078d5c | 226 | /** |
a230c2f6 | 227 | * struct ufs_query - holds relevant data structures for query request |
68078d5c DR |
228 | * @request: request upiu and function |
229 | * @descriptor: buffer for sending/receiving descriptor | |
230 | * @response: response upiu and response | |
231 | */ | |
232 | struct ufs_query { | |
233 | struct ufs_query_req request; | |
234 | u8 *descriptor; | |
235 | struct ufs_query_res response; | |
236 | }; | |
237 | ||
5a0b0cb9 SRT |
238 | /** |
239 | * struct ufs_dev_cmd - all assosiated fields with device management commands | |
240 | * @type: device management command type - Query, NOP OUT | |
241 | * @lock: lock to allow one command at a time | |
242 | * @complete: internal commands completion | |
cff91daf | 243 | * @query: Device management query information |
5a0b0cb9 SRT |
244 | */ |
245 | struct ufs_dev_cmd { | |
246 | enum dev_cmd_type type; | |
247 | struct mutex lock; | |
248 | struct completion *complete; | |
68078d5c | 249 | struct ufs_query query; |
5a0b0cb9 | 250 | }; |
e0eca63e | 251 | |
c6e79dac SRT |
252 | /** |
253 | * struct ufs_clk_info - UFS clock related info | |
254 | * @list: list headed by hba->clk_list_head | |
255 | * @clk: clock node | |
256 | * @name: clock name | |
257 | * @max_freq: maximum frequency supported by the clock | |
4cff6d99 | 258 | * @min_freq: min frequency that can be used for clock scaling |
856b3483 | 259 | * @curr_freq: indicates the current frequency that it is set to |
81309c24 | 260 | * @keep_link_active: indicates that the clk should not be disabled if |
cff91daf | 261 | * link is active |
c6e79dac SRT |
262 | * @enabled: variable to check against multiple enable/disable |
263 | */ | |
264 | struct ufs_clk_info { | |
265 | struct list_head list; | |
266 | struct clk *clk; | |
267 | const char *name; | |
268 | u32 max_freq; | |
4cff6d99 | 269 | u32 min_freq; |
856b3483 | 270 | u32 curr_freq; |
81309c24 | 271 | bool keep_link_active; |
c6e79dac SRT |
272 | bool enabled; |
273 | }; | |
274 | ||
f06fcc71 YG |
275 | enum ufs_notify_change_status { |
276 | PRE_CHANGE, | |
277 | POST_CHANGE, | |
278 | }; | |
7eb584db DR |
279 | |
280 | struct ufs_pa_layer_attr { | |
281 | u32 gear_rx; | |
282 | u32 gear_tx; | |
283 | u32 lane_rx; | |
284 | u32 lane_tx; | |
285 | u32 pwr_rx; | |
286 | u32 pwr_tx; | |
287 | u32 hs_rate; | |
288 | }; | |
289 | ||
290 | struct ufs_pwr_mode_info { | |
291 | bool is_valid; | |
292 | struct ufs_pa_layer_attr info; | |
293 | }; | |
294 | ||
5c0c28a8 SRT |
295 | /** |
296 | * struct ufs_hba_variant_ops - variant specific callbacks | |
297 | * @name: variant name | |
298 | * @init: called when the driver is initialized | |
299 | * @exit: called to cleanup everything done in init | |
9949e702 | 300 | * @get_ufs_hci_version: called to get UFS HCI version |
856b3483 | 301 | * @clk_scale_notify: notifies that clks are scaled up/down |
5c0c28a8 | 302 | * @setup_clocks: called before touching any of the controller registers |
5c0c28a8 SRT |
303 | * @hce_enable_notify: called before and after HCE enable bit is set to allow |
304 | * variant specific Uni-Pro initialization. | |
305 | * @link_startup_notify: called before and after Link startup is carried out | |
306 | * to allow variant specific Uni-Pro initialization. | |
7eb584db DR |
307 | * @pwr_change_notify: called before and after a power mode change |
308 | * is carried out to allow vendor spesific capabilities | |
309 | * to be set. | |
0e675efa KK |
310 | * @setup_xfer_req: called before any transfer request is issued |
311 | * to set some things | |
d2877be4 KK |
312 | * @setup_task_mgmt: called before any task management request is issued |
313 | * to set some things | |
ee32c909 | 314 | * @hibern8_notify: called around hibern8 enter/exit |
56d4a186 | 315 | * @apply_dev_quirks: called to apply device specific quirks |
cff91daf | 316 | * @fixup_dev_quirks: called to modify device specific quirks |
57d104c1 SJ |
317 | * @suspend: called during host controller PM callback |
318 | * @resume: called during host controller PM callback | |
6e3fd44d | 319 | * @dbg_register_dump: used to dump controller debug information |
4b9ffb5a | 320 | * @phy_initialization: used to initialize phys |
d8d9f793 | 321 | * @device_reset: called to issue a reset pulse on the UFS device |
cff91daf | 322 | * @config_scaling_param: called to configure clock scaling parameters |
1bc726e2 | 323 | * @program_key: program or evict an inline encryption key |
172614a9 | 324 | * @event_notify: called to notify important events |
c2c38c57 | 325 | * @reinit_notify: called to notify reinit of UFSHCD during max gear switch |
c263b4ef | 326 | * @mcq_config_resource: called to configure MCQ platform resources |
7224c806 | 327 | * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode |
2468da61 | 328 | * @op_runtime_config: called to config Operation and runtime regs Pointers |
f87b2c41 | 329 | * @get_outstanding_cqs: called to get outstanding completion queues |
edb0db05 | 330 | * @config_esi: called to config Event Specific Interrupt |
db06ae7c | 331 | * @config_scsi_dev: called to configure SCSI device parameters |
5c0c28a8 SRT |
332 | */ |
333 | struct ufs_hba_variant_ops { | |
334 | const char *name; | |
335 | int (*init)(struct ufs_hba *); | |
336 | void (*exit)(struct ufs_hba *); | |
9949e702 | 337 | u32 (*get_ufs_hci_version)(struct ufs_hba *); |
f06fcc71 YG |
338 | int (*clk_scale_notify)(struct ufs_hba *, bool, |
339 | enum ufs_notify_change_status); | |
1e879e8f SJ |
340 | int (*setup_clocks)(struct ufs_hba *, bool, |
341 | enum ufs_notify_change_status); | |
f06fcc71 YG |
342 | int (*hce_enable_notify)(struct ufs_hba *, |
343 | enum ufs_notify_change_status); | |
344 | int (*link_startup_notify)(struct ufs_hba *, | |
345 | enum ufs_notify_change_status); | |
7eb584db | 346 | int (*pwr_change_notify)(struct ufs_hba *, |
f06fcc71 YG |
347 | enum ufs_notify_change_status status, |
348 | struct ufs_pa_layer_attr *, | |
7eb584db | 349 | struct ufs_pa_layer_attr *); |
b427609e BVA |
350 | void (*setup_xfer_req)(struct ufs_hba *hba, int tag, |
351 | bool is_scsi_cmd); | |
d2877be4 | 352 | void (*setup_task_mgmt)(struct ufs_hba *, int, u8); |
ee32c909 | 353 | void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, |
56d4a186 | 354 | enum ufs_notify_change_status); |
09750066 | 355 | int (*apply_dev_quirks)(struct ufs_hba *hba); |
c28c00ba | 356 | void (*fixup_dev_quirks)(struct ufs_hba *hba); |
9561f584 PW |
357 | int (*suspend)(struct ufs_hba *, enum ufs_pm_op, |
358 | enum ufs_notify_change_status); | |
57d104c1 | 359 | int (*resume)(struct ufs_hba *, enum ufs_pm_op); |
6e3fd44d | 360 | void (*dbg_register_dump)(struct ufs_hba *hba); |
4b9ffb5a | 361 | int (*phy_initialization)(struct ufs_hba *); |
151f1b66 | 362 | int (*device_reset)(struct ufs_hba *hba); |
2c75f9a5 | 363 | void (*config_scaling_param)(struct ufs_hba *hba, |
c906e832 BVA |
364 | struct devfreq_dev_profile *profile, |
365 | struct devfreq_simple_ondemand_data *data); | |
1bc726e2 EB |
366 | int (*program_key)(struct ufs_hba *hba, |
367 | const union ufs_crypto_cfg_entry *cfg, int slot); | |
172614a9 SC |
368 | void (*event_notify)(struct ufs_hba *hba, |
369 | enum ufs_event_type evt, void *data); | |
c2c38c57 | 370 | void (*reinit_notify)(struct ufs_hba *); |
c263b4ef | 371 | int (*mcq_config_resource)(struct ufs_hba *hba); |
7224c806 | 372 | int (*get_hba_mac)(struct ufs_hba *hba); |
2468da61 | 373 | int (*op_runtime_config)(struct ufs_hba *hba); |
f87b2c41 AD |
374 | int (*get_outstanding_cqs)(struct ufs_hba *hba, |
375 | unsigned long *ocqs); | |
edb0db05 | 376 | int (*config_esi)(struct ufs_hba *hba); |
858231bd | 377 | void (*config_scsi_dev)(struct scsi_device *sdev); |
5c0c28a8 SRT |
378 | }; |
379 | ||
1ab27c9c ST |
380 | /* clock gating state */ |
381 | enum clk_gating_state { | |
382 | CLKS_OFF, | |
383 | CLKS_ON, | |
384 | REQ_CLKS_OFF, | |
385 | REQ_CLKS_ON, | |
386 | }; | |
387 | ||
388 | /** | |
389 | * struct ufs_clk_gating - UFS clock gating related info | |
390 | * @gate_work: worker to turn off clocks after some delay as specified in | |
391 | * delay_ms | |
392 | * @ungate_work: worker to turn on clocks that will be used in case of | |
393 | * interrupt context | |
394 | * @state: the current clocks state | |
395 | * @delay_ms: gating delay in ms | |
396 | * @is_suspended: clk gating is suspended when set to 1 which can be used | |
397 | * during suspend/resume | |
398 | * @delay_attr: sysfs attribute to control delay_attr | |
b427411a ST |
399 | * @enable_attr: sysfs attribute to enable/disable clock gating |
400 | * @is_enabled: Indicates the current status of clock gating | |
4543d9d7 | 401 | * @is_initialized: Indicates whether clock gating is initialized or not |
1ab27c9c ST |
402 | * @active_reqs: number of requests that are pending and should be waited for |
403 | * completion before gating clocks. | |
cff91daf | 404 | * @clk_gating_workq: workqueue for clock gating work. |
1ab27c9c ST |
405 | */ |
406 | struct ufs_clk_gating { | |
407 | struct delayed_work gate_work; | |
408 | struct work_struct ungate_work; | |
409 | enum clk_gating_state state; | |
410 | unsigned long delay_ms; | |
411 | bool is_suspended; | |
412 | struct device_attribute delay_attr; | |
b427411a ST |
413 | struct device_attribute enable_attr; |
414 | bool is_enabled; | |
4543d9d7 | 415 | bool is_initialized; |
1ab27c9c | 416 | int active_reqs; |
10e5e375 | 417 | struct workqueue_struct *clk_gating_workq; |
1ab27c9c ST |
418 | }; |
419 | ||
401f1e44 | 420 | /** |
421 | * struct ufs_clk_scaling - UFS clock scaling related data | |
422 | * @active_reqs: number of requests that are pending. If this is zero when | |
423 | * devfreq ->target() function is called then schedule "suspend_work" to | |
424 | * suspend devfreq. | |
425 | * @tot_busy_t: Total busy time in current polling window | |
426 | * @window_start_t: Start time (in jiffies) of the current polling window | |
427 | * @busy_start_t: Start time of current busy period | |
428 | * @enable_attr: sysfs attribute to enable/disable clock scaling | |
429 | * @saved_pwr_info: UFS power mode may also be changed during scaling and this | |
430 | * one keeps track of previous power mode. | |
431 | * @workq: workqueue to schedule devfreq suspend/resume work | |
432 | * @suspend_work: worker to suspend devfreq | |
433 | * @resume_work: worker to resume devfreq | |
930bd77e | 434 | * @target_freq: frequency requested by devfreq framework |
29b87e92 | 435 | * @min_gear: lowest HS gear to scale down to |
0e9d4ca4 | 436 | * @is_enabled: tracks if scaling is currently enabled or not, controlled by |
cff91daf | 437 | * clkscale_enable sysfs node |
0e9d4ca4 | 438 | * @is_allowed: tracks if scaling is currently allowed or not, used to block |
cff91daf | 439 | * clock scaling which is not invoked from devfreq governor |
4543d9d7 | 440 | * @is_initialized: Indicates whether clock scaling is initialized or not |
401f1e44 | 441 | * @is_busy_started: tracks if busy period has started or not |
442 | * @is_suspended: tracks if devfreq is suspended or not | |
443 | */ | |
856b3483 | 444 | struct ufs_clk_scaling { |
401f1e44 | 445 | int active_reqs; |
446 | unsigned long tot_busy_t; | |
b1bf66d1 | 447 | ktime_t window_start_t; |
401f1e44 | 448 | ktime_t busy_start_t; |
fcb0c4b0 | 449 | struct device_attribute enable_attr; |
543a827b | 450 | struct ufs_pa_layer_attr saved_pwr_info; |
401f1e44 | 451 | struct workqueue_struct *workq; |
452 | struct work_struct suspend_work; | |
453 | struct work_struct resume_work; | |
930bd77e | 454 | unsigned long target_freq; |
29b87e92 | 455 | u32 min_gear; |
0e9d4ca4 | 456 | bool is_enabled; |
401f1e44 | 457 | bool is_allowed; |
4543d9d7 | 458 | bool is_initialized; |
401f1e44 | 459 | bool is_busy_started; |
460 | bool is_suspended; | |
856b3483 ST |
461 | }; |
462 | ||
e965e5e0 | 463 | #define UFS_EVENT_HIST_LENGTH 8 |
ff8e20c6 | 464 | /** |
e965e5e0 | 465 | * struct ufs_event_hist - keeps history of errors |
ff8e20c6 | 466 | * @pos: index to indicate cyclic buffer position |
cff91daf | 467 | * @val: cyclic buffer for registers value |
ff8e20c6 | 468 | * @tstamp: cyclic buffer for time stamp |
b6cacaf2 | 469 | * @cnt: error counter |
ff8e20c6 | 470 | */ |
e965e5e0 | 471 | struct ufs_event_hist { |
ff8e20c6 | 472 | int pos; |
e965e5e0 | 473 | u32 val[UFS_EVENT_HIST_LENGTH]; |
0f85e747 | 474 | u64 tstamp[UFS_EVENT_HIST_LENGTH]; |
b6cacaf2 | 475 | unsigned long long cnt; |
ff8e20c6 DR |
476 | }; |
477 | ||
478 | /** | |
479 | * struct ufs_stats - keeps usage/err statistics | |
3f8af604 CG |
480 | * @last_intr_status: record the last interrupt status. |
481 | * @last_intr_ts: record the last interrupt timestamp. | |
ff8e20c6 DR |
482 | * @hibern8_exit_cnt: Counter to keep track of number of exits, |
483 | * reset this after link-startup. | |
484 | * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. | |
485 | * Clear after the first successful command completion. | |
cff91daf | 486 | * @event: array with event history. |
ff8e20c6 DR |
487 | */ |
488 | struct ufs_stats { | |
3f8af604 | 489 | u32 last_intr_status; |
0f85e747 | 490 | u64 last_intr_ts; |
3f8af604 | 491 | |
ff8e20c6 | 492 | u32 hibern8_exit_cnt; |
0f85e747 | 493 | u64 last_hibern8_exit_tstamp; |
e965e5e0 | 494 | struct ufs_event_hist event[UFS_EVT_CNT]; |
ff8e20c6 DR |
495 | }; |
496 | ||
9c202090 BVA |
497 | /** |
498 | * enum ufshcd_state - UFS host controller state | |
499 | * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command | |
500 | * processing. | |
501 | * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process | |
502 | * SCSI commands. | |
503 | * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. | |
504 | * SCSI commands may be submitted to the controller. | |
505 | * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail | |
506 | * newly submitted SCSI commands with error code DID_BAD_TARGET. | |
507 | * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery | |
508 | * failed. Fail all SCSI commands with error code DID_ERROR. | |
509 | */ | |
510 | enum ufshcd_state { | |
511 | UFSHCD_STATE_RESET, | |
512 | UFSHCD_STATE_OPERATIONAL, | |
513 | UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, | |
514 | UFSHCD_STATE_EH_SCHEDULED_FATAL, | |
515 | UFSHCD_STATE_ERROR, | |
516 | }; | |
517 | ||
c3f7d1fc CH |
518 | enum ufshcd_quirks { |
519 | /* Interrupt aggregation support is broken */ | |
520 | UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, | |
521 | ||
522 | /* | |
523 | * delay before each dme command is required as the unipro | |
524 | * layer has shown instabilities | |
525 | */ | |
526 | UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, | |
527 | ||
528 | /* | |
529 | * If UFS host controller is having issue in processing LCC (Line | |
530 | * Control Command) coming from device then enable this quirk. | |
531 | * When this quirk is enabled, host controller driver should disable | |
532 | * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE | |
533 | * attribute of device to 0). | |
534 | */ | |
535 | UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, | |
536 | ||
537 | /* | |
538 | * The attribute PA_RXHSUNTERMCAP specifies whether or not the | |
539 | * inbound Link supports unterminated line in HS mode. Setting this | |
540 | * attribute to 1 fixes moving to HS gear. | |
541 | */ | |
542 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, | |
543 | ||
544 | /* | |
545 | * This quirk needs to be enabled if the host controller only allows | |
546 | * accessing the peer dme attributes in AUTO mode (FAST AUTO or | |
547 | * SLOW AUTO). | |
548 | */ | |
549 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, | |
550 | ||
551 | /* | |
552 | * This quirk needs to be enabled if the host controller doesn't | |
553 | * advertise the correct version in UFS_VER register. If this quirk | |
554 | * is enabled, standard UFS host driver will call the vendor specific | |
555 | * ops (get_ufs_hci_version) to get the correct version. | |
556 | */ | |
557 | UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, | |
87183841 AA |
558 | |
559 | /* | |
560 | * Clear handling for transfer/task request list is just opposite. | |
561 | */ | |
562 | UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, | |
b638b5eb AA |
563 | |
564 | /* | |
565 | * This quirk needs to be enabled if host controller doesn't allow | |
566 | * that the interrupt aggregation timer and counter are reset by s/w. | |
567 | */ | |
568 | UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, | |
39bf2d83 AA |
569 | |
570 | /* | |
571 | * This quirks needs to be enabled if host controller cannot be | |
572 | * enabled via HCE register. | |
573 | */ | |
574 | UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, | |
26f968d7 AA |
575 | |
576 | /* | |
577 | * This quirk needs to be enabled if the host controller regards | |
578 | * resolution of the values of PRDTO and PRDTL in UTRD as byte. | |
579 | */ | |
580 | UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, | |
d779a6e9 KK |
581 | |
582 | /* | |
583 | * This quirk needs to be enabled if the host controller reports | |
584 | * OCS FATAL ERROR with device error through sense data | |
585 | */ | |
586 | UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, | |
5df6f2de | 587 | |
8da76f71 AH |
588 | /* |
589 | * This quirk needs to be enabled if the host controller has | |
590 | * auto-hibernate capability but it doesn't work. | |
591 | */ | |
592 | UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, | |
02f74150 | 593 | |
5df6f2de KK |
594 | /* |
595 | * This quirk needs to disable manual flush for write booster | |
596 | */ | |
02f74150 MP |
597 | UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, |
598 | ||
b1d0d2eb KK |
599 | /* |
600 | * This quirk needs to disable unipro timeout values | |
601 | * before power mode change | |
602 | */ | |
603 | UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, | |
604 | ||
a22bcfdb | 605 | /* |
606 | * This quirk needs to be enabled if the host controller does not | |
607 | * support UIC command | |
608 | */ | |
609 | UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, | |
10fb4f87 | 610 | |
611 | /* | |
612 | * This quirk needs to be enabled if the host controller cannot | |
613 | * support physical host configuration. | |
614 | */ | |
615 | UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, | |
6554400d YS |
616 | |
617 | /* | |
618 | * This quirk needs to be enabled if the host controller has | |
619 | * 64-bit addressing supported capability but it doesn't work. | |
620 | */ | |
621 | UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, | |
2f11bbc2 YS |
622 | |
623 | /* | |
624 | * This quirk needs to be enabled if the host controller has | |
625 | * auto-hibernate capability but it's FASTAUTO only. | |
626 | */ | |
627 | UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, | |
96a7141d MS |
628 | |
629 | /* | |
630 | * This quirk needs to be enabled if the host controller needs | |
631 | * to reinit the device after switching to maximum gear. | |
632 | */ | |
633 | UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, | |
c4ad4f2e PWK |
634 | |
635 | /* | |
636 | * Some host raises interrupt (per queue) in addition to | |
637 | * CQES (traditional) when ESI is disabled. | |
638 | * Enable this quirk will disable CQES and use per queue interrupt. | |
639 | */ | |
640 | UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20, | |
aa9d5d00 PWK |
641 | |
642 | /* | |
643 | * Some host does not implement SQ Run Time Command (SQRTC) register | |
644 | * thus need this quirk to skip related flow. | |
645 | */ | |
646 | UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21, | |
c3f7d1fc CH |
647 | }; |
648 | ||
c2014682 SC |
649 | enum ufshcd_caps { |
650 | /* Allow dynamic clk gating */ | |
651 | UFSHCD_CAP_CLK_GATING = 1 << 0, | |
652 | ||
653 | /* Allow hiberb8 with clk gating */ | |
654 | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, | |
655 | ||
656 | /* Allow dynamic clk scaling */ | |
657 | UFSHCD_CAP_CLK_SCALING = 1 << 2, | |
658 | ||
659 | /* Allow auto bkops to enabled during runtime suspend */ | |
660 | UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, | |
661 | ||
662 | /* | |
663 | * This capability allows host controller driver to use the UFS HCI's | |
664 | * interrupt aggregation capability. | |
665 | * CAUTION: Enabling this might reduce overall UFS throughput. | |
666 | */ | |
667 | UFSHCD_CAP_INTR_AGGR = 1 << 4, | |
668 | ||
669 | /* | |
670 | * This capability allows the device auto-bkops to be always enabled | |
671 | * except during suspend (both runtime and suspend). | |
672 | * Enabling this capability means that device will always be allowed | |
673 | * to do background operation when it's active but it might degrade | |
674 | * the performance of ongoing read/write operations. | |
675 | */ | |
676 | UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, | |
677 | ||
678 | /* | |
679 | * This capability allows host controller driver to automatically | |
680 | * enable runtime power management by itself instead of waiting | |
681 | * for userspace to control the power management. | |
682 | */ | |
683 | UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, | |
3d17b9b5 AD |
684 | |
685 | /* | |
686 | * This capability allows the host controller driver to turn-on | |
687 | * WriteBooster, if the underlying device supports it and is | |
688 | * provisioned to be used. This would increase the write performance. | |
689 | */ | |
690 | UFSHCD_CAP_WB_EN = 1 << 7, | |
5e7341e1 ST |
691 | |
692 | /* | |
693 | * This capability allows the host controller driver to use the | |
694 | * inline crypto engine, if it is present | |
695 | */ | |
696 | UFSHCD_CAP_CRYPTO = 1 << 8, | |
dd7143e2 CG |
697 | |
698 | /* | |
699 | * This capability allows the controller regulators to be put into | |
700 | * lpm mode aggressively during clock gating. | |
701 | * This would increase power savings. | |
702 | */ | |
703 | UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, | |
fe1d4c2e AH |
704 | |
705 | /* | |
706 | * This capability allows the host controller driver to use DeepSleep, | |
707 | * if it is supported by the UFS device. The host controller driver must | |
708 | * support device hardware reset via the hba->device_reset() callback, | |
709 | * in order to exit DeepSleep state. | |
710 | */ | |
711 | UFSHCD_CAP_DEEPSLEEP = 1 << 10, | |
e88e2d32 AA |
712 | |
713 | /* | |
714 | * This capability allows the host controller driver to use temperature | |
715 | * notification if it is supported by the UFS device. | |
716 | */ | |
717 | UFSHCD_CAP_TEMP_NOTIF = 1 << 11, | |
87bd0501 PW |
718 | |
719 | /* | |
720 | * Enable WriteBooster when scaling up the clock and disable | |
721 | * WriteBooster when scaling the clock down. | |
722 | */ | |
723 | UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, | |
c2014682 SC |
724 | }; |
725 | ||
90b8491c SC |
726 | struct ufs_hba_variant_params { |
727 | struct devfreq_dev_profile devfreq_profile; | |
728 | struct devfreq_simple_ondemand_data ondemand_data; | |
729 | u16 hba_enable_delay_us; | |
d14734ae | 730 | u32 wb_flush_threshold; |
90b8491c SC |
731 | }; |
732 | ||
1d8613a2 CG |
733 | struct ufs_hba_monitor { |
734 | unsigned long chunk_size; | |
735 | ||
736 | unsigned long nr_sec_rw[2]; | |
737 | ktime_t total_busy[2]; | |
738 | ||
739 | unsigned long nr_req[2]; | |
740 | /* latencies*/ | |
741 | ktime_t lat_sum[2]; | |
742 | ktime_t lat_max[2]; | |
743 | ktime_t lat_min[2]; | |
744 | ||
745 | u32 nr_queued[2]; | |
746 | ktime_t busy_start_ts[2]; | |
747 | ||
748 | ktime_t enabled_ts; | |
749 | bool enabled; | |
750 | }; | |
751 | ||
c263b4ef AD |
752 | /** |
753 | * struct ufshcd_res_info_t - MCQ related resource regions | |
754 | * | |
755 | * @name: resource name | |
756 | * @resource: pointer to resource region | |
757 | * @base: register base address | |
758 | */ | |
759 | struct ufshcd_res_info { | |
760 | const char *name; | |
761 | struct resource *resource; | |
762 | void __iomem *base; | |
763 | }; | |
764 | ||
765 | enum ufshcd_res { | |
766 | RES_UFS, | |
767 | RES_MCQ, | |
768 | RES_MCQ_SQD, | |
769 | RES_MCQ_SQIS, | |
770 | RES_MCQ_CQD, | |
771 | RES_MCQ_CQIS, | |
772 | RES_MCQ_VS, | |
773 | RES_MAX, | |
774 | }; | |
775 | ||
2468da61 AD |
776 | /** |
777 | * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers | |
778 | * | |
779 | * @offset: Doorbell Address Offset | |
780 | * @stride: Steps proportional to queue [0...31] | |
781 | * @base: base address | |
782 | */ | |
783 | struct ufshcd_mcq_opr_info_t { | |
784 | unsigned long offset; | |
785 | unsigned long stride; | |
786 | void __iomem *base; | |
787 | }; | |
788 | ||
789 | enum ufshcd_mcq_opr { | |
790 | OPR_SQD, | |
791 | OPR_SQIS, | |
792 | OPR_CQD, | |
793 | OPR_CQIS, | |
794 | OPR_MAX, | |
795 | }; | |
796 | ||
e0eca63e VH |
797 | /** |
798 | * struct ufs_hba - per adapter private structure | |
799 | * @mmio_base: UFSHCI base register address | |
800 | * @ucdl_base_addr: UFS Command Descriptor base address | |
801 | * @utrdl_base_addr: UTP Transfer Request Descriptor base address | |
802 | * @utmrdl_base_addr: UTP Task Management Descriptor base address | |
803 | * @ucdl_dma_addr: UFS Command Descriptor DMA address | |
804 | * @utrdl_dma_addr: UTRDL DMA address | |
805 | * @utmrdl_dma_addr: UTMRDL DMA address | |
806 | * @host: Scsi_Host instance of the driver | |
807 | * @dev: device handle | |
e2106584 | 808 | * @ufs_device_wlun: WLUN that controls the entire UFS device. |
cff91daf BVA |
809 | * @hwmon_device: device instance registered with the hwmon core. |
810 | * @curr_dev_pwr_mode: active UFS device power mode. | |
811 | * @uic_link_state: active state of the link to the UFS device. | |
812 | * @rpm_lvl: desired UFS power management level during runtime PM. | |
813 | * @spm_lvl: desired UFS power management level during system PM. | |
814 | * @pm_op_in_progress: whether or not a PM operation is in progress. | |
815 | * @ahit: value of Auto-Hibernate Idle Timer register. | |
e0eca63e VH |
816 | * @lrb: local reference block |
817 | * @outstanding_tasks: Bits representing outstanding task requests | |
169f5eb2 | 818 | * @outstanding_lock: Protects @outstanding_reqs. |
e0eca63e VH |
819 | * @outstanding_reqs: Bits representing outstanding transfer requests |
820 | * @capabilities: UFS Controller Capabilities | |
6e1d850a | 821 | * @mcq_capabilities: UFS Multi Circular Queue capabilities |
e0eca63e VH |
822 | * @nutrs: Transfer Request Queue depth supported by controller |
823 | * @nutmrs: Task Management Queue depth supported by controller | |
945c3cca | 824 | * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. |
e0eca63e | 825 | * @ufs_version: UFS Version to which controller complies |
5c0c28a8 | 826 | * @vops: pointer to variant specific operations |
cff91daf | 827 | * @vps: pointer to variant specific parameters |
5c0c28a8 | 828 | * @priv: pointer to variant specific private data |
ada1e653 | 829 | * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) |
e0eca63e | 830 | * @irq: Irq number of the controller |
cff91daf BVA |
831 | * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. |
832 | * @dev_ref_clk_freq: reference clock frequency | |
833 | * @quirks: bitmask with information about deviations from the UFSHCI standard. | |
834 | * @dev_quirks: bitmask with information about deviations from the UFS standard. | |
69a6c269 BVA |
835 | * @tmf_tag_set: TMF tag set. |
836 | * @tmf_queue: Used to allocate TMF tags. | |
cff91daf BVA |
837 | * @tmf_rqs: array with pointers to TMF requests while these are in progress. |
838 | * @active_uic_cmd: handle of active UIC command | |
839 | * @uic_cmd_mutex: mutex for UIC command | |
840 | * @uic_async_done: completion used during UIC processing | |
9c202090 | 841 | * @ufshcd_state: UFSHCD state |
3441da7d | 842 | * @eh_flags: Error handling flags |
2fbd009b | 843 | * @intr_mask: Interrupt Mask Bits |
66ec6d59 | 844 | * @ee_ctrl_mask: Exception event control mask |
cff91daf BVA |
845 | * @ee_drv_mask: Exception event mask for driver |
846 | * @ee_usr_mask: Exception event mask for user (set via debugfs) | |
847 | * @ee_ctrl_mutex: Used to serialize exception event information. | |
1d337ec2 | 848 | * @is_powered: flag to check if HBA is powered |
9cd20d3f CG |
849 | * @shutting_down: flag to check if shutdown has been invoked |
850 | * @host_sem: semaphore used to serialize concurrent contexts | |
88b09900 AH |
851 | * @eh_wq: Workqueue that eh_work works on |
852 | * @eh_work: Worker to handle UFS errors that require s/w attention | |
66ec6d59 | 853 | * @eeh_work: Worker to handle exception events |
e0eca63e | 854 | * @errors: HBA errors |
e8e7f271 SRT |
855 | * @uic_error: UFS interconnect layer error status |
856 | * @saved_err: sticky error mask | |
857 | * @saved_uic_err: sticky UIC error mask | |
cff91daf | 858 | * @ufs_stats: various error counters |
4db7a236 | 859 | * @force_reset: flag to force eh_work perform a full reset |
2355b66e | 860 | * @force_pmc: flag to force a power mode change |
2df74b69 | 861 | * @silence_err_logs: flag to silence error logs |
5a0b0cb9 | 862 | * @dev_cmd: ufs device management command information |
cad2e03d | 863 | * @last_dme_cmd_tstamp: time stamp of the last completed DME command |
cff91daf BVA |
864 | * @nop_out_timeout: NOP OUT timeout value |
865 | * @dev_info: information about the UFS device | |
66ec6d59 | 866 | * @auto_bkops_enabled: to track whether bkops is enabled in device |
aa497613 | 867 | * @vreg_info: UFS device voltage regulator information |
c6e79dac | 868 | * @clk_list_head: UFS host controller clocks list node head |
930bd77e | 869 | * @use_pm_opp: Indicates whether OPP based scaling is used or not |
cff91daf BVA |
870 | * @req_abort_count: number of times ufshcd_abort() has been called |
871 | * @lanes_per_direction: number of lanes per data direction between the UFS | |
872 | * controller and the UFS device. | |
7eb584db DR |
873 | * @pwr_info: holds current power mode |
874 | * @max_pwr_info: keeps the device max valid pwm | |
cff91daf BVA |
875 | * @clk_gating: information related to clock gating |
876 | * @caps: bitmask with information about UFS controller capabilities | |
877 | * @devfreq: frequency scaling information owned by the devfreq core | |
878 | * @clk_scaling: frequency scaling information owned by the UFS driver | |
1a547cbc BVA |
879 | * @system_suspending: system suspend has been started and system resume has |
880 | * not yet finished. | |
881 | * @is_sys_suspended: UFS device has been suspended because of system suspend | |
afdfff59 YG |
882 | * @urgent_bkops_lvl: keeps track of urgent bkops level for device |
883 | * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for | |
884 | * device is known or not. | |
ba810437 | 885 | * @wb_mutex: used to serialize devfreq and sysfs write booster toggling |
cff91daf BVA |
886 | * @clk_scaling_lock: used to serialize device commands and clock scaling |
887 | * @desc_size: descriptor sizes reported by device | |
38135535 | 888 | * @scsi_block_reqs_cnt: reference counting for scsi block requests |
cff91daf BVA |
889 | * @bsg_dev: struct device associated with the BSG queue |
890 | * @bsg_queue: BSG queue associated with the UFS controller | |
891 | * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power | |
892 | * management) after the UFS device has finished a WriteBooster buffer | |
893 | * flush or auto BKOP. | |
cff91daf | 894 | * @monitor: statistics about UFS commands |
70297a8a ST |
895 | * @crypto_capabilities: Content of crypto capabilities register (0x100) |
896 | * @crypto_cap_array: Array of crypto capabilities | |
897 | * @crypto_cfg_register: Start of the crypto cfg array | |
cb77cb5a | 898 | * @crypto_profile: the crypto profile of this hba (if applicable) |
cff91daf BVA |
899 | * @debugfs_root: UFS controller debugfs root directory |
900 | * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay | |
901 | * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore | |
902 | * ee_ctrl_mask | |
903 | * @luns_avail: number of regular and well known LUNs supported by the UFS | |
904 | * device | |
57b1c0ef AD |
905 | * @nr_hw_queues: number of hardware queues configured |
906 | * @nr_queues: number of Queues of different queue types | |
cff91daf BVA |
907 | * @complete_put: whether or not to call ufshcd_rpm_put() from inside |
908 | * ufshcd_resume_complete() | |
6e1d850a | 909 | * @ext_iid_sup: is EXT_IID is supported by UFSHC |
305a357d | 910 | * @mcq_sup: is mcq supported by UFSHC |
2468da61 | 911 | * @mcq_enabled: is mcq ready to accept requests |
c263b4ef AD |
912 | * @res: array of resource info of MCQ registers |
913 | * @mcq_base: Multi circular queue registers base address | |
4682abfa AD |
914 | * @uhq: array of supported hardware queues |
915 | * @dev_cmd_queue: Queue for issuing device management commands | |
6bf999e0 BH |
916 | * @mcq_opr: MCQ operation and runtime registers |
917 | * @ufs_rtc_update_work: A work for UFS RTC periodic update | |
2777e73f MN |
918 | * @pm_qos_req: PM QoS request handle |
919 | * @pm_qos_enabled: flag to check if pm qos is enabled | |
e0eca63e VH |
920 | */ |
921 | struct ufs_hba { | |
922 | void __iomem *mmio_base; | |
923 | ||
924 | /* Virtual memory reference */ | |
925 | struct utp_transfer_cmd_desc *ucdl_base_addr; | |
926 | struct utp_transfer_req_desc *utrdl_base_addr; | |
927 | struct utp_task_req_desc *utmrdl_base_addr; | |
928 | ||
929 | /* DMA memory reference */ | |
930 | dma_addr_t ucdl_dma_addr; | |
931 | dma_addr_t utrdl_dma_addr; | |
932 | dma_addr_t utmrdl_dma_addr; | |
933 | ||
934 | struct Scsi_Host *host; | |
935 | struct device *dev; | |
e2106584 | 936 | struct scsi_device *ufs_device_wlun; |
e0eca63e | 937 | |
e88e2d32 AA |
938 | #ifdef CONFIG_SCSI_UFS_HWMON |
939 | struct device *hwmon_device; | |
940 | #endif | |
941 | ||
57d104c1 SJ |
942 | enum ufs_dev_pwr_mode curr_dev_pwr_mode; |
943 | enum uic_link_state uic_link_state; | |
944 | /* Desired UFS power management level during runtime PM */ | |
945 | enum ufs_pm_level rpm_lvl; | |
946 | /* Desired UFS power management level during system PM */ | |
947 | enum ufs_pm_level spm_lvl; | |
948 | int pm_op_in_progress; | |
949 | ||
ad448378 AH |
950 | /* Auto-Hibernate Idle Timer register value */ |
951 | u32 ahit; | |
952 | ||
e0eca63e VH |
953 | struct ufshcd_lrb *lrb; |
954 | ||
955 | unsigned long outstanding_tasks; | |
169f5eb2 | 956 | spinlock_t outstanding_lock; |
e0eca63e VH |
957 | unsigned long outstanding_reqs; |
958 | ||
959 | u32 capabilities; | |
960 | int nutrs; | |
6e1d850a | 961 | u32 mcq_capabilities; |
e0eca63e | 962 | int nutmrs; |
945c3cca | 963 | u32 reserved_slot; |
e0eca63e | 964 | u32 ufs_version; |
176eb927 | 965 | const struct ufs_hba_variant_ops *vops; |
90b8491c | 966 | struct ufs_hba_variant_params *vps; |
5c0c28a8 | 967 | void *priv; |
ada1e653 EB |
968 | #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE |
969 | size_t sg_entry_size; | |
970 | #endif | |
e0eca63e | 971 | unsigned int irq; |
57d104c1 | 972 | bool is_irq_enabled; |
9e1e8a75 | 973 | enum ufs_ref_clk_freq dev_ref_clk_freq; |
e0eca63e | 974 | |
cad2e03d | 975 | unsigned int quirks; /* Deviations from standard UFSHCI spec. */ |
6ccf44fe | 976 | |
c58ab7aa YG |
977 | /* Device deviations from standard UFS device spec. */ |
978 | unsigned int dev_quirks; | |
979 | ||
69a6c269 BVA |
980 | struct blk_mq_tag_set tmf_tag_set; |
981 | struct request_queue *tmf_queue; | |
f5ef336f | 982 | struct request **tmf_rqs; |
e0eca63e | 983 | |
57d104c1 SJ |
984 | struct uic_command *active_uic_cmd; |
985 | struct mutex uic_cmd_mutex; | |
986 | struct completion *uic_async_done; | |
53b3d9c3 | 987 | |
9c202090 | 988 | enum ufshcd_state ufshcd_state; |
3441da7d | 989 | u32 eh_flags; |
2fbd009b | 990 | u32 intr_mask; |
cff91daf BVA |
991 | u16 ee_ctrl_mask; |
992 | u16 ee_drv_mask; | |
993 | u16 ee_usr_mask; | |
cd469475 | 994 | struct mutex ee_ctrl_mutex; |
1d337ec2 | 995 | bool is_powered; |
9cd20d3f CG |
996 | bool shutting_down; |
997 | struct semaphore host_sem; | |
e0eca63e VH |
998 | |
999 | /* Work Queues */ | |
88b09900 AH |
1000 | struct workqueue_struct *eh_wq; |
1001 | struct work_struct eh_work; | |
66ec6d59 | 1002 | struct work_struct eeh_work; |
e0eca63e VH |
1003 | |
1004 | /* HBA Errors */ | |
1005 | u32 errors; | |
e8e7f271 SRT |
1006 | u32 uic_error; |
1007 | u32 saved_err; | |
1008 | u32 saved_uic_err; | |
ff8e20c6 | 1009 | struct ufs_stats ufs_stats; |
4db7a236 | 1010 | bool force_reset; |
2355b66e | 1011 | bool force_pmc; |
2df74b69 | 1012 | bool silence_err_logs; |
5a0b0cb9 SRT |
1013 | |
1014 | /* Device management request data */ | |
1015 | struct ufs_dev_cmd dev_cmd; | |
cad2e03d | 1016 | ktime_t last_dme_cmd_tstamp; |
1cbc9ad3 | 1017 | int nop_out_timeout; |
66ec6d59 | 1018 | |
57d104c1 SJ |
1019 | /* Keeps information of the UFS device connected to this host */ |
1020 | struct ufs_dev_info dev_info; | |
66ec6d59 | 1021 | bool auto_bkops_enabled; |
aa497613 | 1022 | struct ufs_vreg_info vreg_info; |
c6e79dac | 1023 | struct list_head clk_list_head; |
930bd77e | 1024 | bool use_pm_opp; |
57d104c1 | 1025 | |
7fabb77b GB |
1026 | /* Number of requests aborts */ |
1027 | int req_abort_count; | |
1028 | ||
54b879b7 YG |
1029 | /* Number of lanes available (1 or 2) for Rx/Tx */ |
1030 | u32 lanes_per_direction; | |
7eb584db DR |
1031 | struct ufs_pa_layer_attr pwr_info; |
1032 | struct ufs_pwr_mode_info max_pwr_info; | |
1ab27c9c ST |
1033 | |
1034 | struct ufs_clk_gating clk_gating; | |
1035 | /* Control to enable/disable host capabilities */ | |
1036 | u32 caps; | |
856b3483 ST |
1037 | |
1038 | struct devfreq *devfreq; | |
1039 | struct ufs_clk_scaling clk_scaling; | |
1a547cbc | 1040 | bool system_suspending; |
e785060e | 1041 | bool is_sys_suspended; |
afdfff59 YG |
1042 | |
1043 | enum bkops_status urgent_bkops_lvl; | |
1044 | bool is_urgent_bkops_lvl_checked; | |
a3cd5ec5 | 1045 | |
ba810437 | 1046 | struct mutex wb_mutex; |
a3cd5ec5 | 1047 | struct rw_semaphore clk_scaling_lock; |
38135535 | 1048 | atomic_t scsi_block_reqs_cnt; |
df032bf2 AA |
1049 | |
1050 | struct device bsg_dev; | |
1051 | struct request_queue *bsg_queue; | |
51dd905b | 1052 | struct delayed_work rpm_dev_flush_recheck_work; |
70297a8a | 1053 | |
1d8613a2 CG |
1054 | struct ufs_hba_monitor monitor; |
1055 | ||
70297a8a ST |
1056 | #ifdef CONFIG_SCSI_UFS_CRYPTO |
1057 | union ufs_crypto_capabilities crypto_capabilities; | |
1058 | union ufs_crypto_cap_entry *crypto_cap_array; | |
1059 | u32 crypto_cfg_register; | |
cb77cb5a | 1060 | struct blk_crypto_profile crypto_profile; |
70297a8a | 1061 | #endif |
b6cacaf2 AH |
1062 | #ifdef CONFIG_DEBUG_FS |
1063 | struct dentry *debugfs_root; | |
7deedfda AH |
1064 | struct delayed_work debugfs_ee_work; |
1065 | u32 debugfs_ee_rate_limit_ms; | |
045da307 AM |
1066 | #endif |
1067 | #ifdef CONFIG_SCSI_UFS_FAULT_INJECTION | |
1068 | struct fault_attr trigger_eh_attr; | |
1069 | struct fault_attr timeout_attr; | |
b6cacaf2 | 1070 | #endif |
b294ff3e | 1071 | u32 luns_avail; |
57b1c0ef AD |
1072 | unsigned int nr_hw_queues; |
1073 | unsigned int nr_queues[HCTX_MAX_TYPES]; | |
b294ff3e | 1074 | bool complete_put; |
6e1d850a | 1075 | bool ext_iid_sup; |
0cab4023 | 1076 | bool scsi_host_added; |
305a357d | 1077 | bool mcq_sup; |
2468da61 | 1078 | bool mcq_enabled; |
c263b4ef AD |
1079 | struct ufshcd_res_info res[RES_MAX]; |
1080 | void __iomem *mcq_base; | |
4682abfa AD |
1081 | struct ufs_hw_queue *uhq; |
1082 | struct ufs_hw_queue *dev_cmd_queue; | |
2468da61 | 1083 | struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX]; |
6bf999e0 BH |
1084 | |
1085 | struct delayed_work ufs_rtc_update_work; | |
2777e73f MN |
1086 | struct pm_qos_request pm_qos_req; |
1087 | bool pm_qos_enabled; | |
4682abfa AD |
1088 | }; |
1089 | ||
1090 | /** | |
1091 | * struct ufs_hw_queue - per hardware queue structure | |
2468da61 AD |
1092 | * @mcq_sq_head: base address of submission queue head pointer |
1093 | * @mcq_sq_tail: base address of submission queue tail pointer | |
1094 | * @mcq_cq_head: base address of completion queue head pointer | |
1095 | * @mcq_cq_tail: base address of completion queue tail pointer | |
4682abfa AD |
1096 | * @sqe_base_addr: submission queue entry base address |
1097 | * @sqe_dma_addr: submission queue dma address | |
1098 | * @cqe_base_addr: completion queue base address | |
1099 | * @cqe_dma_addr: completion queue dma address | |
1100 | * @max_entries: max number of slots in this hardware queue | |
2468da61 | 1101 | * @id: hardware queue ID |
22a2d563 AD |
1102 | * @sq_tp_slot: current slot to which SQ tail pointer is pointing |
1103 | * @sq_lock: serialize submission queue access | |
f87b2c41 AD |
1104 | * @cq_tail_slot: current slot to which CQ tail pointer is pointing |
1105 | * @cq_head_slot: current slot to which CQ head pointer is pointing | |
ed975065 | 1106 | * @cq_lock: Synchronize between multiple polling instances |
8d729034 | 1107 | * @sq_mutex: prevent submission queue concurrent access |
4682abfa AD |
1108 | */ |
1109 | struct ufs_hw_queue { | |
2468da61 AD |
1110 | void __iomem *mcq_sq_head; |
1111 | void __iomem *mcq_sq_tail; | |
1112 | void __iomem *mcq_cq_head; | |
1113 | void __iomem *mcq_cq_tail; | |
1114 | ||
3c85f087 | 1115 | struct utp_transfer_req_desc *sqe_base_addr; |
4682abfa AD |
1116 | dma_addr_t sqe_dma_addr; |
1117 | struct cq_entry *cqe_base_addr; | |
1118 | dma_addr_t cqe_dma_addr; | |
1119 | u32 max_entries; | |
2468da61 | 1120 | u32 id; |
22a2d563 AD |
1121 | u32 sq_tail_slot; |
1122 | spinlock_t sq_lock; | |
f87b2c41 AD |
1123 | u32 cq_tail_slot; |
1124 | u32 cq_head_slot; | |
ed975065 | 1125 | spinlock_t cq_lock; |
8d729034 BN |
1126 | /* prevent concurrent access to submission queue */ |
1127 | struct mutex sq_mutex; | |
e0eca63e VH |
1128 | }; |
1129 | ||
2468da61 AD |
1130 | static inline bool is_mcq_enabled(struct ufs_hba *hba) |
1131 | { | |
1132 | return hba->mcq_enabled; | |
1133 | } | |
1134 | ||
ada1e653 EB |
1135 | #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE |
1136 | static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) | |
1137 | { | |
1138 | return hba->sg_entry_size; | |
1139 | } | |
1140 | ||
1141 | static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) | |
1142 | { | |
1143 | WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); | |
1144 | hba->sg_entry_size = sg_entry_size; | |
1145 | } | |
1146 | #else | |
1147 | static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) | |
1148 | { | |
1149 | return sizeof(struct ufshcd_sg_entry); | |
1150 | } | |
1151 | ||
1152 | #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ | |
1153 | ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) | |
1154 | #endif | |
1155 | ||
06caeb53 | 1156 | static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba) |
ada1e653 EB |
1157 | { |
1158 | return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); | |
1159 | } | |
1160 | ||
1ab27c9c ST |
1161 | /* Returns true if clocks can be gated. Otherwise false */ |
1162 | static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) | |
1163 | { | |
1164 | return hba->caps & UFSHCD_CAP_CLK_GATING; | |
1165 | } | |
1166 | static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) | |
1167 | { | |
1168 | return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; | |
1169 | } | |
fcb0c4b0 | 1170 | static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) |
856b3483 ST |
1171 | { |
1172 | return hba->caps & UFSHCD_CAP_CLK_SCALING; | |
1173 | } | |
374a246e SJ |
1174 | static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) |
1175 | { | |
1176 | return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; | |
1177 | } | |
49615ba1 SC |
1178 | static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) |
1179 | { | |
1180 | return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; | |
1181 | } | |
374a246e | 1182 | |
b852190e YG |
1183 | static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) |
1184 | { | |
1c0810e7 KP |
1185 | return (hba->caps & UFSHCD_CAP_INTR_AGGR) && |
1186 | !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); | |
b852190e YG |
1187 | } |
1188 | ||
dd7143e2 CG |
1189 | static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) |
1190 | { | |
1191 | return !!(ufshcd_is_link_hibern8(hba) && | |
1192 | (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); | |
1193 | } | |
1194 | ||
ee5f1042 SC |
1195 | static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) |
1196 | { | |
8da76f71 AH |
1197 | return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && |
1198 | !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); | |
ee5f1042 SC |
1199 | } |
1200 | ||
5a244e0e SC |
1201 | static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) |
1202 | { | |
51d1628f | 1203 | return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); |
5a244e0e SC |
1204 | } |
1205 | ||
3d17b9b5 AD |
1206 | static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) |
1207 | { | |
1208 | return hba->caps & UFSHCD_CAP_WB_EN; | |
1209 | } | |
1210 | ||
87bd0501 PW |
1211 | static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) |
1212 | { | |
1213 | return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; | |
1214 | } | |
1215 | ||
2468da61 AD |
1216 | #define ufsmcq_writel(hba, val, reg) \ |
1217 | writel((val), (hba)->mcq_base + (reg)) | |
1218 | #define ufsmcq_readl(hba, reg) \ | |
1219 | readl((hba)->mcq_base + (reg)) | |
1220 | ||
1221 | #define ufsmcq_writelx(hba, val, reg) \ | |
1222 | writel_relaxed((val), (hba)->mcq_base + (reg)) | |
1223 | #define ufsmcq_readlx(hba, reg) \ | |
1224 | readl_relaxed((hba)->mcq_base + (reg)) | |
1225 | ||
b873a275 SJ |
1226 | #define ufshcd_writel(hba, val, reg) \ |
1227 | writel((val), (hba)->mmio_base + (reg)) | |
1228 | #define ufshcd_readl(hba, reg) \ | |
1229 | readl((hba)->mmio_base + (reg)) | |
1230 | ||
e785060e | 1231 | /** |
cff91daf BVA |
1232 | * ufshcd_rmwl - perform read/modify/write for a controller register |
1233 | * @hba: per adapter instance | |
1234 | * @mask: mask to apply on read value | |
1235 | * @val: actual value to write | |
1236 | * @reg: register address | |
e785060e DR |
1237 | */ |
1238 | static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) | |
1239 | { | |
1240 | u32 tmp; | |
1241 | ||
1242 | tmp = ufshcd_readl(hba, reg); | |
1243 | tmp &= ~mask; | |
1244 | tmp |= (val & mask); | |
1245 | ufshcd_writel(hba, tmp, reg); | |
1246 | } | |
1247 | ||
0ae7a027 MS |
1248 | void ufshcd_enable_irq(struct ufs_hba *hba); |
1249 | void ufshcd_disable_irq(struct ufs_hba *hba); | |
5c0c28a8 | 1250 | int ufshcd_alloc_host(struct device *, struct ufs_hba **); |
47555a5c | 1251 | void ufshcd_dealloc_host(struct ufs_hba *); |
9d19bf7a | 1252 | int ufshcd_hba_enable(struct ufs_hba *hba); |
ecd7beb3 | 1253 | int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); |
087c5efa | 1254 | int ufshcd_link_recovery(struct ufs_hba *hba); |
9d19bf7a | 1255 | int ufshcd_make_hba_operational(struct ufs_hba *hba); |
e0eca63e | 1256 | void ufshcd_remove(struct ufs_hba *); |
525943a5 | 1257 | int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); |
9d19bf7a | 1258 | int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); |
5c955c10 | 1259 | void ufshcd_delay_us(unsigned long us, unsigned long tolerance); |
9e1e8a75 | 1260 | void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); |
e965e5e0 | 1261 | void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); |
3a95f5b3 | 1262 | void ufshcd_hba_stop(struct ufs_hba *hba); |
267a59f6 | 1263 | void ufshcd_schedule_eh_work(struct ufs_hba *hba); |
11afb65c PWK |
1264 | void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); |
1265 | u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); | |
e02288e0 | 1266 | void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); |
57d6ef46 | 1267 | unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, |
e02288e0 | 1268 | struct ufs_hw_queue *hwq); |
11afb65c | 1269 | void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); |
e02288e0 | 1270 | void ufshcd_mcq_enable_esi(struct ufs_hba *hba); |
ab3e6c4e | 1271 | void ufshcd_mcq_enable(struct ufs_hba *hba); |
e02288e0 | 1272 | void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); |
e0eca63e | 1273 | |
72208ebe MS |
1274 | int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, |
1275 | struct dev_pm_opp *opp, void *data, | |
1276 | bool scaling_down); | |
1ce5898a YG |
1277 | /** |
1278 | * ufshcd_set_variant - set variant specific data to the hba | |
cff91daf BVA |
1279 | * @hba: per adapter instance |
1280 | * @variant: pointer to variant specific data | |
1ce5898a YG |
1281 | */ |
1282 | static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) | |
1283 | { | |
1284 | BUG_ON(!hba); | |
1285 | hba->priv = variant; | |
1286 | } | |
1287 | ||
1288 | /** | |
1289 | * ufshcd_get_variant - get variant specific data from the hba | |
cff91daf | 1290 | * @hba: per adapter instance |
1ce5898a YG |
1291 | */ |
1292 | static inline void *ufshcd_get_variant(struct ufs_hba *hba) | |
1293 | { | |
1294 | BUG_ON(!hba); | |
1295 | return hba->priv; | |
1296 | } | |
e88e2d32 | 1297 | |
9bb25e5d | 1298 | #ifdef CONFIG_PM |
f1ecbe1e BVA |
1299 | extern int ufshcd_runtime_suspend(struct device *dev); |
1300 | extern int ufshcd_runtime_resume(struct device *dev); | |
9bb25e5d BVA |
1301 | #endif |
1302 | #ifdef CONFIG_PM_SLEEP | |
f1ecbe1e BVA |
1303 | extern int ufshcd_system_suspend(struct device *dev); |
1304 | extern int ufshcd_system_resume(struct device *dev); | |
88441a8d AH |
1305 | extern int ufshcd_system_freeze(struct device *dev); |
1306 | extern int ufshcd_system_thaw(struct device *dev); | |
1307 | extern int ufshcd_system_restore(struct device *dev); | |
9bb25e5d | 1308 | #endif |
88441a8d | 1309 | |
fc85a74e SC |
1310 | extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, |
1311 | int agreed_gear, | |
1312 | int adapt_val); | |
12b4fdb4 SJ |
1313 | extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, |
1314 | u8 attr_set, u32 mib_val, u8 peer); | |
1315 | extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, | |
1316 | u32 *mib_val, u8 peer); | |
0d846e70 AA |
1317 | extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, |
1318 | struct ufs_pa_layer_attr *desired_pwr_mode); | |
fc53683b | 1319 | extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); |
12b4fdb4 SJ |
1320 | |
1321 | /* UIC command interfaces for DME primitives */ | |
1322 | #define DME_LOCAL 0 | |
1323 | #define DME_PEER 1 | |
1324 | #define ATTR_SET_NOR 0 /* NORMAL */ | |
1325 | #define ATTR_SET_ST 1 /* STATIC */ | |
1326 | ||
1327 | static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, | |
1328 | u32 mib_val) | |
1329 | { | |
1330 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, | |
1331 | mib_val, DME_LOCAL); | |
1332 | } | |
1333 | ||
1334 | static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, | |
1335 | u32 mib_val) | |
1336 | { | |
1337 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, | |
1338 | mib_val, DME_LOCAL); | |
1339 | } | |
1340 | ||
1341 | static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, | |
1342 | u32 mib_val) | |
1343 | { | |
1344 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, | |
1345 | mib_val, DME_PEER); | |
1346 | } | |
1347 | ||
1348 | static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, | |
1349 | u32 mib_val) | |
1350 | { | |
1351 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, | |
1352 | mib_val, DME_PEER); | |
1353 | } | |
1354 | ||
1355 | static inline int ufshcd_dme_get(struct ufs_hba *hba, | |
1356 | u32 attr_sel, u32 *mib_val) | |
1357 | { | |
1358 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); | |
1359 | } | |
1360 | ||
1361 | static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, | |
1362 | u32 attr_sel, u32 *mib_val) | |
1363 | { | |
1364 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); | |
1365 | } | |
1366 | ||
f37aabcf YG |
1367 | static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) |
1368 | { | |
1369 | return (pwr_info->pwr_rx == FAST_MODE || | |
1370 | pwr_info->pwr_rx == FASTAUTO_MODE) && | |
1371 | (pwr_info->pwr_tx == FAST_MODE || | |
1372 | pwr_info->pwr_tx == FASTAUTO_MODE); | |
1373 | } | |
1374 | ||
984eaac1 SC |
1375 | static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) |
1376 | { | |
1377 | return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); | |
1378 | } | |
1379 | ||
ba7af5ec | 1380 | void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); |
aead21f3 BVA |
1381 | void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, |
1382 | const struct ufs_dev_quirk *fixups); | |
4b828fe1 TW |
1383 | #define SD_ASCII_STD true |
1384 | #define SD_RAW false | |
1385 | int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, | |
1386 | u8 **buf, bool ascii); | |
2238d31c | 1387 | |
078f4f4b | 1388 | void ufshcd_hold(struct ufs_hba *hba); |
1ab27c9c | 1389 | void ufshcd_release(struct ufs_hba *hba); |
a4b0e8a4 | 1390 | |
ad8a647e BVA |
1391 | void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); |
1392 | ||
37113106 | 1393 | u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); |
0263bcd0 | 1394 | |
1d6f9dec SC |
1395 | int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); |
1396 | ||
e77044c5 AA |
1397 | int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); |
1398 | ||
6ff265fc BH |
1399 | int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, |
1400 | struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, | |
1401 | struct ufs_ehs *ehs_rsp, int sg_cnt, | |
1402 | struct scatterlist *sg_list, enum dma_data_direction dir); | |
3b5f3c0d | 1403 | int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); |
6c4148ce | 1404 | int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); |
b294ff3e | 1405 | int ufshcd_suspend_prepare(struct device *dev); |
ddba1cf7 | 1406 | int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); |
b294ff3e | 1407 | void ufshcd_resume_complete(struct device *dev); |
548fdf77 | 1408 | bool ufshcd_is_hba_active(struct ufs_hba *hba); |
2777e73f MN |
1409 | void ufshcd_pm_qos_init(struct ufs_hba *hba); |
1410 | void ufshcd_pm_qos_exit(struct ufs_hba *hba); | |
8e834ca5 | 1411 | |
0263bcd0 | 1412 | /* Wrapper functions for safely calling variant operations */ |
0263bcd0 YG |
1413 | static inline int ufshcd_vops_init(struct ufs_hba *hba) |
1414 | { | |
1415 | if (hba->vops && hba->vops->init) | |
1416 | return hba->vops->init(hba); | |
1417 | ||
1418 | return 0; | |
1419 | } | |
1420 | ||
92bcebe4 SC |
1421 | static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) |
1422 | { | |
1423 | if (hba->vops && hba->vops->phy_initialization) | |
1424 | return hba->vops->phy_initialization(hba); | |
1425 | ||
1426 | return 0; | |
1427 | } | |
1428 | ||
35d11ec2 | 1429 | extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; |
cbb6813e | 1430 | |
ba80917d TW |
1431 | int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, |
1432 | const char *prefix); | |
1433 | ||
7deedfda AH |
1434 | int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); |
1435 | int ufshcd_write_ee_control(struct ufs_hba *hba); | |
35d11ec2 KK |
1436 | int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, |
1437 | const u16 *other_mask, u16 set, u16 clr); | |
cd469475 | 1438 | |
e0eca63e | 1439 | #endif /* End of Header */ |