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67351119 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
e0eca63e VH |
2 | /* |
3 | * Universal Flash Storage Host controller driver | |
e0eca63e | 4 | * Copyright (C) 2011-2013 Samsung India Software Operations |
dc3c8d3a | 5 | * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
e0eca63e VH |
6 | * |
7 | * Authors: | |
8 | * Santosh Yaraganavi <santosh.sy@samsung.com> | |
9 | * Vinayak Holikatti <h.vinayak@samsung.com> | |
e0eca63e VH |
10 | */ |
11 | ||
12 | #ifndef _UFSHCD_H | |
13 | #define _UFSHCD_H | |
14 | ||
5a244e0e | 15 | #include <linux/bitfield.h> |
1e8d44bd | 16 | #include <linux/blk-crypto-profile.h> |
3f06f780 BVA |
17 | #include <linux/blk-mq.h> |
18 | #include <linux/devfreq.h> | |
19 | #include <linux/pm_runtime.h> | |
f3e57da5 | 20 | #include <linux/dma-direction.h> |
3f06f780 | 21 | #include <scsi/scsi_device.h> |
dd11376b BVA |
22 | #include <ufs/unipro.h> |
23 | #include <ufs/ufs.h> | |
24 | #include <ufs/ufs_quirks.h> | |
25 | #include <ufs/ufshci.h> | |
e0eca63e VH |
26 | |
27 | #define UFSHCD "ufshcd" | |
e0eca63e | 28 | |
5c0c28a8 SRT |
29 | struct ufs_hba; |
30 | ||
5a0b0cb9 SRT |
31 | enum dev_cmd_type { |
32 | DEV_CMD_TYPE_NOP = 0x0, | |
68078d5c | 33 | DEV_CMD_TYPE_QUERY = 0x1, |
6ff265fc | 34 | DEV_CMD_TYPE_RPMB = 0x2, |
5a0b0cb9 SRT |
35 | }; |
36 | ||
e965e5e0 SC |
37 | enum ufs_event_type { |
38 | /* uic specific errors */ | |
39 | UFS_EVT_PA_ERR = 0, | |
40 | UFS_EVT_DL_ERR, | |
41 | UFS_EVT_NL_ERR, | |
42 | UFS_EVT_TL_ERR, | |
43 | UFS_EVT_DME_ERR, | |
44 | ||
45 | /* fatal errors */ | |
46 | UFS_EVT_AUTO_HIBERN8_ERR, | |
47 | UFS_EVT_FATAL_ERR, | |
48 | UFS_EVT_LINK_STARTUP_FAIL, | |
49 | UFS_EVT_RESUME_ERR, | |
50 | UFS_EVT_SUSPEND_ERR, | |
b294ff3e AD |
51 | UFS_EVT_WL_SUSP_ERR, |
52 | UFS_EVT_WL_RES_ERR, | |
e965e5e0 SC |
53 | |
54 | /* abnormal events */ | |
55 | UFS_EVT_DEV_RESET, | |
56 | UFS_EVT_HOST_RESET, | |
57 | UFS_EVT_ABORT, | |
58 | ||
59 | UFS_EVT_CNT, | |
60 | }; | |
61 | ||
e0eca63e VH |
62 | /** |
63 | * struct uic_command - UIC command structure | |
64 | * @command: UIC command | |
65 | * @argument1: UIC command argument 1 | |
66 | * @argument2: UIC command argument 2 | |
67 | * @argument3: UIC command argument 3 | |
0f52fcb9 | 68 | * @cmd_active: Indicate if UIC command is outstanding |
6ccf44fe | 69 | * @done: UIC command completion |
e0eca63e VH |
70 | */ |
71 | struct uic_command { | |
72 | u32 command; | |
73 | u32 argument1; | |
74 | u32 argument2; | |
75 | u32 argument3; | |
0f52fcb9 | 76 | int cmd_active; |
6ccf44fe | 77 | struct completion done; |
e0eca63e VH |
78 | }; |
79 | ||
57d104c1 SJ |
80 | /* Used to differentiate the power management options */ |
81 | enum ufs_pm_op { | |
82 | UFS_RUNTIME_PM, | |
83 | UFS_SYSTEM_PM, | |
84 | UFS_SHUTDOWN_PM, | |
85 | }; | |
86 | ||
57d104c1 SJ |
87 | /* Host <-> Device UniPro Link state */ |
88 | enum uic_link_state { | |
89 | UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ | |
90 | UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ | |
91 | UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ | |
4db7a236 | 92 | UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ |
57d104c1 SJ |
93 | }; |
94 | ||
95 | #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) | |
96 | #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ | |
97 | UIC_LINK_ACTIVE_STATE) | |
98 | #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ | |
99 | UIC_LINK_HIBERN8_STATE) | |
4db7a236 CG |
100 | #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ |
101 | UIC_LINK_BROKEN_STATE) | |
57d104c1 SJ |
102 | #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) |
103 | #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ | |
104 | UIC_LINK_ACTIVE_STATE) | |
105 | #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ | |
106 | UIC_LINK_HIBERN8_STATE) | |
4db7a236 CG |
107 | #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ |
108 | UIC_LINK_BROKEN_STATE) | |
57d104c1 | 109 | |
1764fa2a SC |
110 | #define ufshcd_set_ufs_dev_active(h) \ |
111 | ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) | |
112 | #define ufshcd_set_ufs_dev_sleep(h) \ | |
113 | ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) | |
114 | #define ufshcd_set_ufs_dev_poweroff(h) \ | |
115 | ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) | |
fe1d4c2e AH |
116 | #define ufshcd_set_ufs_dev_deepsleep(h) \ |
117 | ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) | |
1764fa2a SC |
118 | #define ufshcd_is_ufs_dev_active(h) \ |
119 | ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) | |
120 | #define ufshcd_is_ufs_dev_sleep(h) \ | |
121 | ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) | |
122 | #define ufshcd_is_ufs_dev_poweroff(h) \ | |
123 | ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) | |
fe1d4c2e AH |
124 | #define ufshcd_is_ufs_dev_deepsleep(h) \ |
125 | ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) | |
1764fa2a | 126 | |
57d104c1 SJ |
127 | /* |
128 | * UFS Power management levels. | |
fe1d4c2e AH |
129 | * Each level is in increasing order of power savings, except DeepSleep |
130 | * which is lower than PowerDown with power on but not PowerDown with | |
131 | * power off. | |
57d104c1 SJ |
132 | */ |
133 | enum ufs_pm_level { | |
e2ac7ab2 BVA |
134 | UFS_PM_LVL_0, |
135 | UFS_PM_LVL_1, | |
136 | UFS_PM_LVL_2, | |
137 | UFS_PM_LVL_3, | |
138 | UFS_PM_LVL_4, | |
139 | UFS_PM_LVL_5, | |
140 | UFS_PM_LVL_6, | |
57d104c1 SJ |
141 | UFS_PM_LVL_MAX |
142 | }; | |
143 | ||
144 | struct ufs_pm_lvl_states { | |
145 | enum ufs_dev_pwr_mode dev_state; | |
146 | enum uic_link_state link_state; | |
147 | }; | |
148 | ||
e0eca63e VH |
149 | /** |
150 | * struct ufshcd_lrb - local reference block | |
151 | * @utr_descriptor_ptr: UTRD address of the command | |
5a0b0cb9 | 152 | * @ucd_req_ptr: UCD address of the command |
e0eca63e VH |
153 | * @ucd_rsp_ptr: Response UPIU address for this command |
154 | * @ucd_prdt_ptr: PRDT address of the command | |
ff8e20c6 DR |
155 | * @utrd_dma_addr: UTRD dma address for debug |
156 | * @ucd_prdt_dma_addr: PRDT dma address for debug | |
157 | * @ucd_rsp_dma_addr: UPIU response dma address for debug | |
158 | * @ucd_req_dma_addr: UPIU request dma address for debug | |
e0eca63e | 159 | * @cmd: pointer to SCSI command |
e0eca63e VH |
160 | * @scsi_status: SCSI status of the command |
161 | * @command_type: SCSI, UFS, Query. | |
162 | * @task_tag: Task tag of the command | |
163 | * @lun: LUN of the command | |
5a0b0cb9 | 164 | * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) |
0f85e747 DL |
165 | * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) |
166 | * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) | |
167 | * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) | |
168 | * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) | |
df043c74 ST |
169 | * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) |
170 | * @data_unit_num: the data unit number for the first block for inline crypto | |
e0b299e3 | 171 | * @req_abort_skip: skip request abort task flag |
e0eca63e VH |
172 | */ |
173 | struct ufshcd_lrb { | |
174 | struct utp_transfer_req_desc *utr_descriptor_ptr; | |
5a0b0cb9 | 175 | struct utp_upiu_req *ucd_req_ptr; |
e0eca63e VH |
176 | struct utp_upiu_rsp *ucd_rsp_ptr; |
177 | struct ufshcd_sg_entry *ucd_prdt_ptr; | |
178 | ||
ff8e20c6 DR |
179 | dma_addr_t utrd_dma_addr; |
180 | dma_addr_t ucd_req_dma_addr; | |
181 | dma_addr_t ucd_rsp_dma_addr; | |
182 | dma_addr_t ucd_prdt_dma_addr; | |
183 | ||
e0eca63e | 184 | struct scsi_cmnd *cmd; |
e0eca63e VH |
185 | int scsi_status; |
186 | ||
187 | int command_type; | |
188 | int task_tag; | |
0ce147d4 | 189 | u8 lun; /* UPIU LUN id field is only 8-bit wide */ |
5a0b0cb9 | 190 | bool intr_cmd; |
ff8e20c6 | 191 | ktime_t issue_time_stamp; |
0f85e747 | 192 | u64 issue_time_stamp_local_clock; |
09017188 | 193 | ktime_t compl_time_stamp; |
0f85e747 | 194 | u64 compl_time_stamp_local_clock; |
df043c74 ST |
195 | #ifdef CONFIG_SCSI_UFS_CRYPTO |
196 | int crypto_key_slot; | |
197 | u64 data_unit_num; | |
198 | #endif | |
e0b299e3 GB |
199 | |
200 | bool req_abort_skip; | |
e0eca63e VH |
201 | }; |
202 | ||
68078d5c | 203 | /** |
a230c2f6 | 204 | * struct ufs_query - holds relevant data structures for query request |
68078d5c DR |
205 | * @request: request upiu and function |
206 | * @descriptor: buffer for sending/receiving descriptor | |
207 | * @response: response upiu and response | |
208 | */ | |
209 | struct ufs_query { | |
210 | struct ufs_query_req request; | |
211 | u8 *descriptor; | |
212 | struct ufs_query_res response; | |
213 | }; | |
214 | ||
5a0b0cb9 SRT |
215 | /** |
216 | * struct ufs_dev_cmd - all assosiated fields with device management commands | |
217 | * @type: device management command type - Query, NOP OUT | |
218 | * @lock: lock to allow one command at a time | |
219 | * @complete: internal commands completion | |
cff91daf | 220 | * @query: Device management query information |
5a0b0cb9 SRT |
221 | */ |
222 | struct ufs_dev_cmd { | |
223 | enum dev_cmd_type type; | |
224 | struct mutex lock; | |
225 | struct completion *complete; | |
68078d5c | 226 | struct ufs_query query; |
5a0b0cb9 | 227 | }; |
e0eca63e | 228 | |
c6e79dac SRT |
229 | /** |
230 | * struct ufs_clk_info - UFS clock related info | |
231 | * @list: list headed by hba->clk_list_head | |
232 | * @clk: clock node | |
233 | * @name: clock name | |
234 | * @max_freq: maximum frequency supported by the clock | |
4cff6d99 | 235 | * @min_freq: min frequency that can be used for clock scaling |
856b3483 | 236 | * @curr_freq: indicates the current frequency that it is set to |
81309c24 | 237 | * @keep_link_active: indicates that the clk should not be disabled if |
cff91daf | 238 | * link is active |
c6e79dac SRT |
239 | * @enabled: variable to check against multiple enable/disable |
240 | */ | |
241 | struct ufs_clk_info { | |
242 | struct list_head list; | |
243 | struct clk *clk; | |
244 | const char *name; | |
245 | u32 max_freq; | |
4cff6d99 | 246 | u32 min_freq; |
856b3483 | 247 | u32 curr_freq; |
81309c24 | 248 | bool keep_link_active; |
c6e79dac SRT |
249 | bool enabled; |
250 | }; | |
251 | ||
f06fcc71 YG |
252 | enum ufs_notify_change_status { |
253 | PRE_CHANGE, | |
254 | POST_CHANGE, | |
255 | }; | |
7eb584db DR |
256 | |
257 | struct ufs_pa_layer_attr { | |
258 | u32 gear_rx; | |
259 | u32 gear_tx; | |
260 | u32 lane_rx; | |
261 | u32 lane_tx; | |
262 | u32 pwr_rx; | |
263 | u32 pwr_tx; | |
264 | u32 hs_rate; | |
265 | }; | |
266 | ||
267 | struct ufs_pwr_mode_info { | |
268 | bool is_valid; | |
269 | struct ufs_pa_layer_attr info; | |
270 | }; | |
271 | ||
5c0c28a8 SRT |
272 | /** |
273 | * struct ufs_hba_variant_ops - variant specific callbacks | |
274 | * @name: variant name | |
275 | * @init: called when the driver is initialized | |
276 | * @exit: called to cleanup everything done in init | |
9949e702 | 277 | * @get_ufs_hci_version: called to get UFS HCI version |
856b3483 | 278 | * @clk_scale_notify: notifies that clks are scaled up/down |
5c0c28a8 | 279 | * @setup_clocks: called before touching any of the controller registers |
5c0c28a8 SRT |
280 | * @hce_enable_notify: called before and after HCE enable bit is set to allow |
281 | * variant specific Uni-Pro initialization. | |
282 | * @link_startup_notify: called before and after Link startup is carried out | |
283 | * to allow variant specific Uni-Pro initialization. | |
7eb584db DR |
284 | * @pwr_change_notify: called before and after a power mode change |
285 | * is carried out to allow vendor spesific capabilities | |
286 | * to be set. | |
0e675efa KK |
287 | * @setup_xfer_req: called before any transfer request is issued |
288 | * to set some things | |
d2877be4 KK |
289 | * @setup_task_mgmt: called before any task management request is issued |
290 | * to set some things | |
ee32c909 | 291 | * @hibern8_notify: called around hibern8 enter/exit |
56d4a186 | 292 | * @apply_dev_quirks: called to apply device specific quirks |
cff91daf | 293 | * @fixup_dev_quirks: called to modify device specific quirks |
57d104c1 SJ |
294 | * @suspend: called during host controller PM callback |
295 | * @resume: called during host controller PM callback | |
6e3fd44d | 296 | * @dbg_register_dump: used to dump controller debug information |
4b9ffb5a | 297 | * @phy_initialization: used to initialize phys |
d8d9f793 | 298 | * @device_reset: called to issue a reset pulse on the UFS device |
cff91daf | 299 | * @config_scaling_param: called to configure clock scaling parameters |
1bc726e2 | 300 | * @program_key: program or evict an inline encryption key |
172614a9 | 301 | * @event_notify: called to notify important events |
c2c38c57 | 302 | * @reinit_notify: called to notify reinit of UFSHCD during max gear switch |
c263b4ef | 303 | * @mcq_config_resource: called to configure MCQ platform resources |
7224c806 | 304 | * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode |
2468da61 | 305 | * @op_runtime_config: called to config Operation and runtime regs Pointers |
5c0c28a8 SRT |
306 | */ |
307 | struct ufs_hba_variant_ops { | |
308 | const char *name; | |
309 | int (*init)(struct ufs_hba *); | |
310 | void (*exit)(struct ufs_hba *); | |
9949e702 | 311 | u32 (*get_ufs_hci_version)(struct ufs_hba *); |
f06fcc71 YG |
312 | int (*clk_scale_notify)(struct ufs_hba *, bool, |
313 | enum ufs_notify_change_status); | |
1e879e8f SJ |
314 | int (*setup_clocks)(struct ufs_hba *, bool, |
315 | enum ufs_notify_change_status); | |
f06fcc71 YG |
316 | int (*hce_enable_notify)(struct ufs_hba *, |
317 | enum ufs_notify_change_status); | |
318 | int (*link_startup_notify)(struct ufs_hba *, | |
319 | enum ufs_notify_change_status); | |
7eb584db | 320 | int (*pwr_change_notify)(struct ufs_hba *, |
f06fcc71 YG |
321 | enum ufs_notify_change_status status, |
322 | struct ufs_pa_layer_attr *, | |
7eb584db | 323 | struct ufs_pa_layer_attr *); |
b427609e BVA |
324 | void (*setup_xfer_req)(struct ufs_hba *hba, int tag, |
325 | bool is_scsi_cmd); | |
d2877be4 | 326 | void (*setup_task_mgmt)(struct ufs_hba *, int, u8); |
ee32c909 | 327 | void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, |
56d4a186 | 328 | enum ufs_notify_change_status); |
09750066 | 329 | int (*apply_dev_quirks)(struct ufs_hba *hba); |
c28c00ba | 330 | void (*fixup_dev_quirks)(struct ufs_hba *hba); |
9561f584 PW |
331 | int (*suspend)(struct ufs_hba *, enum ufs_pm_op, |
332 | enum ufs_notify_change_status); | |
57d104c1 | 333 | int (*resume)(struct ufs_hba *, enum ufs_pm_op); |
6e3fd44d | 334 | void (*dbg_register_dump)(struct ufs_hba *hba); |
4b9ffb5a | 335 | int (*phy_initialization)(struct ufs_hba *); |
151f1b66 | 336 | int (*device_reset)(struct ufs_hba *hba); |
2c75f9a5 | 337 | void (*config_scaling_param)(struct ufs_hba *hba, |
c906e832 BVA |
338 | struct devfreq_dev_profile *profile, |
339 | struct devfreq_simple_ondemand_data *data); | |
1bc726e2 EB |
340 | int (*program_key)(struct ufs_hba *hba, |
341 | const union ufs_crypto_cfg_entry *cfg, int slot); | |
172614a9 SC |
342 | void (*event_notify)(struct ufs_hba *hba, |
343 | enum ufs_event_type evt, void *data); | |
c2c38c57 | 344 | void (*reinit_notify)(struct ufs_hba *); |
c263b4ef | 345 | int (*mcq_config_resource)(struct ufs_hba *hba); |
7224c806 | 346 | int (*get_hba_mac)(struct ufs_hba *hba); |
2468da61 | 347 | int (*op_runtime_config)(struct ufs_hba *hba); |
5c0c28a8 SRT |
348 | }; |
349 | ||
1ab27c9c ST |
350 | /* clock gating state */ |
351 | enum clk_gating_state { | |
352 | CLKS_OFF, | |
353 | CLKS_ON, | |
354 | REQ_CLKS_OFF, | |
355 | REQ_CLKS_ON, | |
356 | }; | |
357 | ||
358 | /** | |
359 | * struct ufs_clk_gating - UFS clock gating related info | |
360 | * @gate_work: worker to turn off clocks after some delay as specified in | |
361 | * delay_ms | |
362 | * @ungate_work: worker to turn on clocks that will be used in case of | |
363 | * interrupt context | |
364 | * @state: the current clocks state | |
365 | * @delay_ms: gating delay in ms | |
366 | * @is_suspended: clk gating is suspended when set to 1 which can be used | |
367 | * during suspend/resume | |
368 | * @delay_attr: sysfs attribute to control delay_attr | |
b427411a ST |
369 | * @enable_attr: sysfs attribute to enable/disable clock gating |
370 | * @is_enabled: Indicates the current status of clock gating | |
4543d9d7 | 371 | * @is_initialized: Indicates whether clock gating is initialized or not |
1ab27c9c ST |
372 | * @active_reqs: number of requests that are pending and should be waited for |
373 | * completion before gating clocks. | |
cff91daf | 374 | * @clk_gating_workq: workqueue for clock gating work. |
1ab27c9c ST |
375 | */ |
376 | struct ufs_clk_gating { | |
377 | struct delayed_work gate_work; | |
378 | struct work_struct ungate_work; | |
379 | enum clk_gating_state state; | |
380 | unsigned long delay_ms; | |
381 | bool is_suspended; | |
382 | struct device_attribute delay_attr; | |
b427411a ST |
383 | struct device_attribute enable_attr; |
384 | bool is_enabled; | |
4543d9d7 | 385 | bool is_initialized; |
1ab27c9c | 386 | int active_reqs; |
10e5e375 | 387 | struct workqueue_struct *clk_gating_workq; |
1ab27c9c ST |
388 | }; |
389 | ||
a3cd5ec5 | 390 | struct ufs_saved_pwr_info { |
391 | struct ufs_pa_layer_attr info; | |
392 | bool is_valid; | |
393 | }; | |
394 | ||
401f1e44 | 395 | /** |
396 | * struct ufs_clk_scaling - UFS clock scaling related data | |
397 | * @active_reqs: number of requests that are pending. If this is zero when | |
398 | * devfreq ->target() function is called then schedule "suspend_work" to | |
399 | * suspend devfreq. | |
400 | * @tot_busy_t: Total busy time in current polling window | |
401 | * @window_start_t: Start time (in jiffies) of the current polling window | |
402 | * @busy_start_t: Start time of current busy period | |
403 | * @enable_attr: sysfs attribute to enable/disable clock scaling | |
404 | * @saved_pwr_info: UFS power mode may also be changed during scaling and this | |
405 | * one keeps track of previous power mode. | |
406 | * @workq: workqueue to schedule devfreq suspend/resume work | |
407 | * @suspend_work: worker to suspend devfreq | |
408 | * @resume_work: worker to resume devfreq | |
29b87e92 | 409 | * @min_gear: lowest HS gear to scale down to |
0e9d4ca4 | 410 | * @is_enabled: tracks if scaling is currently enabled or not, controlled by |
cff91daf | 411 | * clkscale_enable sysfs node |
0e9d4ca4 | 412 | * @is_allowed: tracks if scaling is currently allowed or not, used to block |
cff91daf | 413 | * clock scaling which is not invoked from devfreq governor |
4543d9d7 | 414 | * @is_initialized: Indicates whether clock scaling is initialized or not |
401f1e44 | 415 | * @is_busy_started: tracks if busy period has started or not |
416 | * @is_suspended: tracks if devfreq is suspended or not | |
417 | */ | |
856b3483 | 418 | struct ufs_clk_scaling { |
401f1e44 | 419 | int active_reqs; |
420 | unsigned long tot_busy_t; | |
b1bf66d1 | 421 | ktime_t window_start_t; |
401f1e44 | 422 | ktime_t busy_start_t; |
fcb0c4b0 | 423 | struct device_attribute enable_attr; |
a3cd5ec5 | 424 | struct ufs_saved_pwr_info saved_pwr_info; |
401f1e44 | 425 | struct workqueue_struct *workq; |
426 | struct work_struct suspend_work; | |
427 | struct work_struct resume_work; | |
29b87e92 | 428 | u32 min_gear; |
0e9d4ca4 | 429 | bool is_enabled; |
401f1e44 | 430 | bool is_allowed; |
4543d9d7 | 431 | bool is_initialized; |
401f1e44 | 432 | bool is_busy_started; |
433 | bool is_suspended; | |
856b3483 ST |
434 | }; |
435 | ||
e965e5e0 | 436 | #define UFS_EVENT_HIST_LENGTH 8 |
ff8e20c6 | 437 | /** |
e965e5e0 | 438 | * struct ufs_event_hist - keeps history of errors |
ff8e20c6 | 439 | * @pos: index to indicate cyclic buffer position |
cff91daf | 440 | * @val: cyclic buffer for registers value |
ff8e20c6 | 441 | * @tstamp: cyclic buffer for time stamp |
b6cacaf2 | 442 | * @cnt: error counter |
ff8e20c6 | 443 | */ |
e965e5e0 | 444 | struct ufs_event_hist { |
ff8e20c6 | 445 | int pos; |
e965e5e0 | 446 | u32 val[UFS_EVENT_HIST_LENGTH]; |
0f85e747 | 447 | u64 tstamp[UFS_EVENT_HIST_LENGTH]; |
b6cacaf2 | 448 | unsigned long long cnt; |
ff8e20c6 DR |
449 | }; |
450 | ||
451 | /** | |
452 | * struct ufs_stats - keeps usage/err statistics | |
3f8af604 CG |
453 | * @last_intr_status: record the last interrupt status. |
454 | * @last_intr_ts: record the last interrupt timestamp. | |
ff8e20c6 DR |
455 | * @hibern8_exit_cnt: Counter to keep track of number of exits, |
456 | * reset this after link-startup. | |
457 | * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. | |
458 | * Clear after the first successful command completion. | |
cff91daf | 459 | * @event: array with event history. |
ff8e20c6 DR |
460 | */ |
461 | struct ufs_stats { | |
3f8af604 | 462 | u32 last_intr_status; |
0f85e747 | 463 | u64 last_intr_ts; |
3f8af604 | 464 | |
ff8e20c6 | 465 | u32 hibern8_exit_cnt; |
0f85e747 | 466 | u64 last_hibern8_exit_tstamp; |
e965e5e0 | 467 | struct ufs_event_hist event[UFS_EVT_CNT]; |
ff8e20c6 DR |
468 | }; |
469 | ||
9c202090 BVA |
470 | /** |
471 | * enum ufshcd_state - UFS host controller state | |
472 | * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command | |
473 | * processing. | |
474 | * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process | |
475 | * SCSI commands. | |
476 | * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. | |
477 | * SCSI commands may be submitted to the controller. | |
478 | * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail | |
479 | * newly submitted SCSI commands with error code DID_BAD_TARGET. | |
480 | * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery | |
481 | * failed. Fail all SCSI commands with error code DID_ERROR. | |
482 | */ | |
483 | enum ufshcd_state { | |
484 | UFSHCD_STATE_RESET, | |
485 | UFSHCD_STATE_OPERATIONAL, | |
486 | UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, | |
487 | UFSHCD_STATE_EH_SCHEDULED_FATAL, | |
488 | UFSHCD_STATE_ERROR, | |
489 | }; | |
490 | ||
c3f7d1fc CH |
491 | enum ufshcd_quirks { |
492 | /* Interrupt aggregation support is broken */ | |
493 | UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, | |
494 | ||
495 | /* | |
496 | * delay before each dme command is required as the unipro | |
497 | * layer has shown instabilities | |
498 | */ | |
499 | UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, | |
500 | ||
501 | /* | |
502 | * If UFS host controller is having issue in processing LCC (Line | |
503 | * Control Command) coming from device then enable this quirk. | |
504 | * When this quirk is enabled, host controller driver should disable | |
505 | * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE | |
506 | * attribute of device to 0). | |
507 | */ | |
508 | UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, | |
509 | ||
510 | /* | |
511 | * The attribute PA_RXHSUNTERMCAP specifies whether or not the | |
512 | * inbound Link supports unterminated line in HS mode. Setting this | |
513 | * attribute to 1 fixes moving to HS gear. | |
514 | */ | |
515 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, | |
516 | ||
517 | /* | |
518 | * This quirk needs to be enabled if the host controller only allows | |
519 | * accessing the peer dme attributes in AUTO mode (FAST AUTO or | |
520 | * SLOW AUTO). | |
521 | */ | |
522 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, | |
523 | ||
524 | /* | |
525 | * This quirk needs to be enabled if the host controller doesn't | |
526 | * advertise the correct version in UFS_VER register. If this quirk | |
527 | * is enabled, standard UFS host driver will call the vendor specific | |
528 | * ops (get_ufs_hci_version) to get the correct version. | |
529 | */ | |
530 | UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, | |
87183841 AA |
531 | |
532 | /* | |
533 | * Clear handling for transfer/task request list is just opposite. | |
534 | */ | |
535 | UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, | |
b638b5eb AA |
536 | |
537 | /* | |
538 | * This quirk needs to be enabled if host controller doesn't allow | |
539 | * that the interrupt aggregation timer and counter are reset by s/w. | |
540 | */ | |
541 | UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, | |
39bf2d83 AA |
542 | |
543 | /* | |
544 | * This quirks needs to be enabled if host controller cannot be | |
545 | * enabled via HCE register. | |
546 | */ | |
547 | UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, | |
26f968d7 AA |
548 | |
549 | /* | |
550 | * This quirk needs to be enabled if the host controller regards | |
551 | * resolution of the values of PRDTO and PRDTL in UTRD as byte. | |
552 | */ | |
553 | UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, | |
d779a6e9 KK |
554 | |
555 | /* | |
556 | * This quirk needs to be enabled if the host controller reports | |
557 | * OCS FATAL ERROR with device error through sense data | |
558 | */ | |
559 | UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, | |
5df6f2de | 560 | |
8da76f71 AH |
561 | /* |
562 | * This quirk needs to be enabled if the host controller has | |
563 | * auto-hibernate capability but it doesn't work. | |
564 | */ | |
565 | UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, | |
02f74150 | 566 | |
5df6f2de KK |
567 | /* |
568 | * This quirk needs to disable manual flush for write booster | |
569 | */ | |
02f74150 MP |
570 | UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, |
571 | ||
b1d0d2eb KK |
572 | /* |
573 | * This quirk needs to disable unipro timeout values | |
574 | * before power mode change | |
575 | */ | |
576 | UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, | |
577 | ||
2b2bfc8a KK |
578 | /* |
579 | * This quirk allows only sg entries aligned with page size. | |
580 | */ | |
9599a1cf | 581 | UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 14, |
a22bcfdb | 582 | |
583 | /* | |
584 | * This quirk needs to be enabled if the host controller does not | |
585 | * support UIC command | |
586 | */ | |
587 | UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, | |
10fb4f87 | 588 | |
589 | /* | |
590 | * This quirk needs to be enabled if the host controller cannot | |
591 | * support physical host configuration. | |
592 | */ | |
593 | UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, | |
6554400d YS |
594 | |
595 | /* | |
596 | * This quirk needs to be enabled if the host controller has | |
597 | * 64-bit addressing supported capability but it doesn't work. | |
598 | */ | |
599 | UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, | |
2f11bbc2 YS |
600 | |
601 | /* | |
602 | * This quirk needs to be enabled if the host controller has | |
603 | * auto-hibernate capability but it's FASTAUTO only. | |
604 | */ | |
605 | UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, | |
96a7141d MS |
606 | |
607 | /* | |
608 | * This quirk needs to be enabled if the host controller needs | |
609 | * to reinit the device after switching to maximum gear. | |
610 | */ | |
611 | UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, | |
c3f7d1fc CH |
612 | }; |
613 | ||
c2014682 SC |
614 | enum ufshcd_caps { |
615 | /* Allow dynamic clk gating */ | |
616 | UFSHCD_CAP_CLK_GATING = 1 << 0, | |
617 | ||
618 | /* Allow hiberb8 with clk gating */ | |
619 | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, | |
620 | ||
621 | /* Allow dynamic clk scaling */ | |
622 | UFSHCD_CAP_CLK_SCALING = 1 << 2, | |
623 | ||
624 | /* Allow auto bkops to enabled during runtime suspend */ | |
625 | UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, | |
626 | ||
627 | /* | |
628 | * This capability allows host controller driver to use the UFS HCI's | |
629 | * interrupt aggregation capability. | |
630 | * CAUTION: Enabling this might reduce overall UFS throughput. | |
631 | */ | |
632 | UFSHCD_CAP_INTR_AGGR = 1 << 4, | |
633 | ||
634 | /* | |
635 | * This capability allows the device auto-bkops to be always enabled | |
636 | * except during suspend (both runtime and suspend). | |
637 | * Enabling this capability means that device will always be allowed | |
638 | * to do background operation when it's active but it might degrade | |
639 | * the performance of ongoing read/write operations. | |
640 | */ | |
641 | UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, | |
642 | ||
643 | /* | |
644 | * This capability allows host controller driver to automatically | |
645 | * enable runtime power management by itself instead of waiting | |
646 | * for userspace to control the power management. | |
647 | */ | |
648 | UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, | |
3d17b9b5 AD |
649 | |
650 | /* | |
651 | * This capability allows the host controller driver to turn-on | |
652 | * WriteBooster, if the underlying device supports it and is | |
653 | * provisioned to be used. This would increase the write performance. | |
654 | */ | |
655 | UFSHCD_CAP_WB_EN = 1 << 7, | |
5e7341e1 ST |
656 | |
657 | /* | |
658 | * This capability allows the host controller driver to use the | |
659 | * inline crypto engine, if it is present | |
660 | */ | |
661 | UFSHCD_CAP_CRYPTO = 1 << 8, | |
dd7143e2 CG |
662 | |
663 | /* | |
664 | * This capability allows the controller regulators to be put into | |
665 | * lpm mode aggressively during clock gating. | |
666 | * This would increase power savings. | |
667 | */ | |
668 | UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, | |
fe1d4c2e AH |
669 | |
670 | /* | |
671 | * This capability allows the host controller driver to use DeepSleep, | |
672 | * if it is supported by the UFS device. The host controller driver must | |
673 | * support device hardware reset via the hba->device_reset() callback, | |
674 | * in order to exit DeepSleep state. | |
675 | */ | |
676 | UFSHCD_CAP_DEEPSLEEP = 1 << 10, | |
e88e2d32 AA |
677 | |
678 | /* | |
679 | * This capability allows the host controller driver to use temperature | |
680 | * notification if it is supported by the UFS device. | |
681 | */ | |
682 | UFSHCD_CAP_TEMP_NOTIF = 1 << 11, | |
87bd0501 PW |
683 | |
684 | /* | |
685 | * Enable WriteBooster when scaling up the clock and disable | |
686 | * WriteBooster when scaling the clock down. | |
687 | */ | |
688 | UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, | |
c2014682 SC |
689 | }; |
690 | ||
90b8491c SC |
691 | struct ufs_hba_variant_params { |
692 | struct devfreq_dev_profile devfreq_profile; | |
693 | struct devfreq_simple_ondemand_data ondemand_data; | |
694 | u16 hba_enable_delay_us; | |
d14734ae | 695 | u32 wb_flush_threshold; |
90b8491c SC |
696 | }; |
697 | ||
f02bc975 DP |
698 | #ifdef CONFIG_SCSI_UFS_HPB |
699 | /** | |
700 | * struct ufshpb_dev_info - UFSHPB device related info | |
701 | * @num_lu: the number of user logical unit to check whether all lu finished | |
702 | * initialization | |
703 | * @rgn_size: device reported HPB region size | |
704 | * @srgn_size: device reported HPB sub-region size | |
705 | * @slave_conf_cnt: counter to check all lu finished initialization | |
706 | * @hpb_disabled: flag to check if HPB is disabled | |
41d8a933 DP |
707 | * @max_hpb_single_cmd: device reported bMAX_DATA_SIZE_FOR_SINGLE_CMD value |
708 | * @is_legacy: flag to check HPB 1.0 | |
119ee38c | 709 | * @control_mode: either host or device |
f02bc975 DP |
710 | */ |
711 | struct ufshpb_dev_info { | |
712 | int num_lu; | |
713 | int rgn_size; | |
714 | int srgn_size; | |
715 | atomic_t slave_conf_cnt; | |
716 | bool hpb_disabled; | |
41d8a933 DP |
717 | u8 max_hpb_single_cmd; |
718 | bool is_legacy; | |
119ee38c | 719 | u8 control_mode; |
f02bc975 DP |
720 | }; |
721 | #endif | |
722 | ||
1d8613a2 CG |
723 | struct ufs_hba_monitor { |
724 | unsigned long chunk_size; | |
725 | ||
726 | unsigned long nr_sec_rw[2]; | |
727 | ktime_t total_busy[2]; | |
728 | ||
729 | unsigned long nr_req[2]; | |
730 | /* latencies*/ | |
731 | ktime_t lat_sum[2]; | |
732 | ktime_t lat_max[2]; | |
733 | ktime_t lat_min[2]; | |
734 | ||
735 | u32 nr_queued[2]; | |
736 | ktime_t busy_start_ts[2]; | |
737 | ||
738 | ktime_t enabled_ts; | |
739 | bool enabled; | |
740 | }; | |
741 | ||
c263b4ef AD |
742 | /** |
743 | * struct ufshcd_res_info_t - MCQ related resource regions | |
744 | * | |
745 | * @name: resource name | |
746 | * @resource: pointer to resource region | |
747 | * @base: register base address | |
748 | */ | |
749 | struct ufshcd_res_info { | |
750 | const char *name; | |
751 | struct resource *resource; | |
752 | void __iomem *base; | |
753 | }; | |
754 | ||
755 | enum ufshcd_res { | |
756 | RES_UFS, | |
757 | RES_MCQ, | |
758 | RES_MCQ_SQD, | |
759 | RES_MCQ_SQIS, | |
760 | RES_MCQ_CQD, | |
761 | RES_MCQ_CQIS, | |
762 | RES_MCQ_VS, | |
763 | RES_MAX, | |
764 | }; | |
765 | ||
2468da61 AD |
766 | /** |
767 | * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers | |
768 | * | |
769 | * @offset: Doorbell Address Offset | |
770 | * @stride: Steps proportional to queue [0...31] | |
771 | * @base: base address | |
772 | */ | |
773 | struct ufshcd_mcq_opr_info_t { | |
774 | unsigned long offset; | |
775 | unsigned long stride; | |
776 | void __iomem *base; | |
777 | }; | |
778 | ||
779 | enum ufshcd_mcq_opr { | |
780 | OPR_SQD, | |
781 | OPR_SQIS, | |
782 | OPR_CQD, | |
783 | OPR_CQIS, | |
784 | OPR_MAX, | |
785 | }; | |
786 | ||
e0eca63e VH |
787 | /** |
788 | * struct ufs_hba - per adapter private structure | |
789 | * @mmio_base: UFSHCI base register address | |
790 | * @ucdl_base_addr: UFS Command Descriptor base address | |
791 | * @utrdl_base_addr: UTP Transfer Request Descriptor base address | |
792 | * @utmrdl_base_addr: UTP Task Management Descriptor base address | |
793 | * @ucdl_dma_addr: UFS Command Descriptor DMA address | |
794 | * @utrdl_dma_addr: UTRDL DMA address | |
795 | * @utmrdl_dma_addr: UTMRDL DMA address | |
796 | * @host: Scsi_Host instance of the driver | |
797 | * @dev: device handle | |
e2106584 | 798 | * @ufs_device_wlun: WLUN that controls the entire UFS device. |
cff91daf BVA |
799 | * @hwmon_device: device instance registered with the hwmon core. |
800 | * @curr_dev_pwr_mode: active UFS device power mode. | |
801 | * @uic_link_state: active state of the link to the UFS device. | |
802 | * @rpm_lvl: desired UFS power management level during runtime PM. | |
803 | * @spm_lvl: desired UFS power management level during system PM. | |
804 | * @pm_op_in_progress: whether or not a PM operation is in progress. | |
805 | * @ahit: value of Auto-Hibernate Idle Timer register. | |
e0eca63e VH |
806 | * @lrb: local reference block |
807 | * @outstanding_tasks: Bits representing outstanding task requests | |
169f5eb2 | 808 | * @outstanding_lock: Protects @outstanding_reqs. |
e0eca63e VH |
809 | * @outstanding_reqs: Bits representing outstanding transfer requests |
810 | * @capabilities: UFS Controller Capabilities | |
6e1d850a | 811 | * @mcq_capabilities: UFS Multi Circular Queue capabilities |
e0eca63e VH |
812 | * @nutrs: Transfer Request Queue depth supported by controller |
813 | * @nutmrs: Task Management Queue depth supported by controller | |
945c3cca | 814 | * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. |
e0eca63e | 815 | * @ufs_version: UFS Version to which controller complies |
5c0c28a8 | 816 | * @vops: pointer to variant specific operations |
cff91daf | 817 | * @vps: pointer to variant specific parameters |
5c0c28a8 | 818 | * @priv: pointer to variant specific private data |
ada1e653 | 819 | * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) |
e0eca63e | 820 | * @irq: Irq number of the controller |
cff91daf BVA |
821 | * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. |
822 | * @dev_ref_clk_freq: reference clock frequency | |
823 | * @quirks: bitmask with information about deviations from the UFSHCI standard. | |
824 | * @dev_quirks: bitmask with information about deviations from the UFS standard. | |
69a6c269 BVA |
825 | * @tmf_tag_set: TMF tag set. |
826 | * @tmf_queue: Used to allocate TMF tags. | |
cff91daf BVA |
827 | * @tmf_rqs: array with pointers to TMF requests while these are in progress. |
828 | * @active_uic_cmd: handle of active UIC command | |
829 | * @uic_cmd_mutex: mutex for UIC command | |
830 | * @uic_async_done: completion used during UIC processing | |
9c202090 | 831 | * @ufshcd_state: UFSHCD state |
3441da7d | 832 | * @eh_flags: Error handling flags |
2fbd009b | 833 | * @intr_mask: Interrupt Mask Bits |
66ec6d59 | 834 | * @ee_ctrl_mask: Exception event control mask |
cff91daf BVA |
835 | * @ee_drv_mask: Exception event mask for driver |
836 | * @ee_usr_mask: Exception event mask for user (set via debugfs) | |
837 | * @ee_ctrl_mutex: Used to serialize exception event information. | |
1d337ec2 | 838 | * @is_powered: flag to check if HBA is powered |
9cd20d3f CG |
839 | * @shutting_down: flag to check if shutdown has been invoked |
840 | * @host_sem: semaphore used to serialize concurrent contexts | |
88b09900 AH |
841 | * @eh_wq: Workqueue that eh_work works on |
842 | * @eh_work: Worker to handle UFS errors that require s/w attention | |
66ec6d59 | 843 | * @eeh_work: Worker to handle exception events |
e0eca63e | 844 | * @errors: HBA errors |
e8e7f271 SRT |
845 | * @uic_error: UFS interconnect layer error status |
846 | * @saved_err: sticky error mask | |
847 | * @saved_uic_err: sticky UIC error mask | |
cff91daf | 848 | * @ufs_stats: various error counters |
4db7a236 | 849 | * @force_reset: flag to force eh_work perform a full reset |
2355b66e | 850 | * @force_pmc: flag to force a power mode change |
2df74b69 | 851 | * @silence_err_logs: flag to silence error logs |
5a0b0cb9 | 852 | * @dev_cmd: ufs device management command information |
cad2e03d | 853 | * @last_dme_cmd_tstamp: time stamp of the last completed DME command |
cff91daf BVA |
854 | * @nop_out_timeout: NOP OUT timeout value |
855 | * @dev_info: information about the UFS device | |
66ec6d59 | 856 | * @auto_bkops_enabled: to track whether bkops is enabled in device |
aa497613 | 857 | * @vreg_info: UFS device voltage regulator information |
c6e79dac | 858 | * @clk_list_head: UFS host controller clocks list node head |
cff91daf BVA |
859 | * @req_abort_count: number of times ufshcd_abort() has been called |
860 | * @lanes_per_direction: number of lanes per data direction between the UFS | |
861 | * controller and the UFS device. | |
7eb584db DR |
862 | * @pwr_info: holds current power mode |
863 | * @max_pwr_info: keeps the device max valid pwm | |
cff91daf BVA |
864 | * @clk_gating: information related to clock gating |
865 | * @caps: bitmask with information about UFS controller capabilities | |
866 | * @devfreq: frequency scaling information owned by the devfreq core | |
867 | * @clk_scaling: frequency scaling information owned by the UFS driver | |
1a547cbc BVA |
868 | * @system_suspending: system suspend has been started and system resume has |
869 | * not yet finished. | |
870 | * @is_sys_suspended: UFS device has been suspended because of system suspend | |
afdfff59 YG |
871 | * @urgent_bkops_lvl: keeps track of urgent bkops level for device |
872 | * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for | |
873 | * device is known or not. | |
cff91daf BVA |
874 | * @clk_scaling_lock: used to serialize device commands and clock scaling |
875 | * @desc_size: descriptor sizes reported by device | |
38135535 | 876 | * @scsi_block_reqs_cnt: reference counting for scsi block requests |
cff91daf BVA |
877 | * @bsg_dev: struct device associated with the BSG queue |
878 | * @bsg_queue: BSG queue associated with the UFS controller | |
879 | * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power | |
880 | * management) after the UFS device has finished a WriteBooster buffer | |
881 | * flush or auto BKOP. | |
882 | * @ufshpb_dev: information related to HPB (Host Performance Booster). | |
883 | * @monitor: statistics about UFS commands | |
70297a8a ST |
884 | * @crypto_capabilities: Content of crypto capabilities register (0x100) |
885 | * @crypto_cap_array: Array of crypto capabilities | |
886 | * @crypto_cfg_register: Start of the crypto cfg array | |
cb77cb5a | 887 | * @crypto_profile: the crypto profile of this hba (if applicable) |
cff91daf BVA |
888 | * @debugfs_root: UFS controller debugfs root directory |
889 | * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay | |
890 | * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore | |
891 | * ee_ctrl_mask | |
892 | * @luns_avail: number of regular and well known LUNs supported by the UFS | |
893 | * device | |
57b1c0ef AD |
894 | * @nr_hw_queues: number of hardware queues configured |
895 | * @nr_queues: number of Queues of different queue types | |
cff91daf BVA |
896 | * @complete_put: whether or not to call ufshcd_rpm_put() from inside |
897 | * ufshcd_resume_complete() | |
6e1d850a | 898 | * @ext_iid_sup: is EXT_IID is supported by UFSHC |
305a357d | 899 | * @mcq_sup: is mcq supported by UFSHC |
2468da61 | 900 | * @mcq_enabled: is mcq ready to accept requests |
c263b4ef AD |
901 | * @res: array of resource info of MCQ registers |
902 | * @mcq_base: Multi circular queue registers base address | |
4682abfa AD |
903 | * @uhq: array of supported hardware queues |
904 | * @dev_cmd_queue: Queue for issuing device management commands | |
e0eca63e VH |
905 | */ |
906 | struct ufs_hba { | |
907 | void __iomem *mmio_base; | |
908 | ||
909 | /* Virtual memory reference */ | |
910 | struct utp_transfer_cmd_desc *ucdl_base_addr; | |
911 | struct utp_transfer_req_desc *utrdl_base_addr; | |
912 | struct utp_task_req_desc *utmrdl_base_addr; | |
913 | ||
914 | /* DMA memory reference */ | |
915 | dma_addr_t ucdl_dma_addr; | |
916 | dma_addr_t utrdl_dma_addr; | |
917 | dma_addr_t utmrdl_dma_addr; | |
918 | ||
919 | struct Scsi_Host *host; | |
920 | struct device *dev; | |
e2106584 | 921 | struct scsi_device *ufs_device_wlun; |
e0eca63e | 922 | |
e88e2d32 AA |
923 | #ifdef CONFIG_SCSI_UFS_HWMON |
924 | struct device *hwmon_device; | |
925 | #endif | |
926 | ||
57d104c1 SJ |
927 | enum ufs_dev_pwr_mode curr_dev_pwr_mode; |
928 | enum uic_link_state uic_link_state; | |
929 | /* Desired UFS power management level during runtime PM */ | |
930 | enum ufs_pm_level rpm_lvl; | |
931 | /* Desired UFS power management level during system PM */ | |
932 | enum ufs_pm_level spm_lvl; | |
933 | int pm_op_in_progress; | |
934 | ||
ad448378 AH |
935 | /* Auto-Hibernate Idle Timer register value */ |
936 | u32 ahit; | |
937 | ||
e0eca63e VH |
938 | struct ufshcd_lrb *lrb; |
939 | ||
940 | unsigned long outstanding_tasks; | |
169f5eb2 | 941 | spinlock_t outstanding_lock; |
e0eca63e VH |
942 | unsigned long outstanding_reqs; |
943 | ||
944 | u32 capabilities; | |
945 | int nutrs; | |
6e1d850a | 946 | u32 mcq_capabilities; |
e0eca63e | 947 | int nutmrs; |
945c3cca | 948 | u32 reserved_slot; |
e0eca63e | 949 | u32 ufs_version; |
176eb927 | 950 | const struct ufs_hba_variant_ops *vops; |
90b8491c | 951 | struct ufs_hba_variant_params *vps; |
5c0c28a8 | 952 | void *priv; |
ada1e653 EB |
953 | #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE |
954 | size_t sg_entry_size; | |
955 | #endif | |
e0eca63e | 956 | unsigned int irq; |
57d104c1 | 957 | bool is_irq_enabled; |
9e1e8a75 | 958 | enum ufs_ref_clk_freq dev_ref_clk_freq; |
e0eca63e | 959 | |
cad2e03d | 960 | unsigned int quirks; /* Deviations from standard UFSHCI spec. */ |
6ccf44fe | 961 | |
c58ab7aa YG |
962 | /* Device deviations from standard UFS device spec. */ |
963 | unsigned int dev_quirks; | |
964 | ||
69a6c269 BVA |
965 | struct blk_mq_tag_set tmf_tag_set; |
966 | struct request_queue *tmf_queue; | |
f5ef336f | 967 | struct request **tmf_rqs; |
e0eca63e | 968 | |
57d104c1 SJ |
969 | struct uic_command *active_uic_cmd; |
970 | struct mutex uic_cmd_mutex; | |
971 | struct completion *uic_async_done; | |
53b3d9c3 | 972 | |
9c202090 | 973 | enum ufshcd_state ufshcd_state; |
3441da7d | 974 | u32 eh_flags; |
2fbd009b | 975 | u32 intr_mask; |
cff91daf BVA |
976 | u16 ee_ctrl_mask; |
977 | u16 ee_drv_mask; | |
978 | u16 ee_usr_mask; | |
cd469475 | 979 | struct mutex ee_ctrl_mutex; |
1d337ec2 | 980 | bool is_powered; |
9cd20d3f CG |
981 | bool shutting_down; |
982 | struct semaphore host_sem; | |
e0eca63e VH |
983 | |
984 | /* Work Queues */ | |
88b09900 AH |
985 | struct workqueue_struct *eh_wq; |
986 | struct work_struct eh_work; | |
66ec6d59 | 987 | struct work_struct eeh_work; |
e0eca63e VH |
988 | |
989 | /* HBA Errors */ | |
990 | u32 errors; | |
e8e7f271 SRT |
991 | u32 uic_error; |
992 | u32 saved_err; | |
993 | u32 saved_uic_err; | |
ff8e20c6 | 994 | struct ufs_stats ufs_stats; |
4db7a236 | 995 | bool force_reset; |
2355b66e | 996 | bool force_pmc; |
2df74b69 | 997 | bool silence_err_logs; |
5a0b0cb9 SRT |
998 | |
999 | /* Device management request data */ | |
1000 | struct ufs_dev_cmd dev_cmd; | |
cad2e03d | 1001 | ktime_t last_dme_cmd_tstamp; |
1cbc9ad3 | 1002 | int nop_out_timeout; |
66ec6d59 | 1003 | |
57d104c1 SJ |
1004 | /* Keeps information of the UFS device connected to this host */ |
1005 | struct ufs_dev_info dev_info; | |
66ec6d59 | 1006 | bool auto_bkops_enabled; |
aa497613 | 1007 | struct ufs_vreg_info vreg_info; |
c6e79dac | 1008 | struct list_head clk_list_head; |
57d104c1 | 1009 | |
7fabb77b GB |
1010 | /* Number of requests aborts */ |
1011 | int req_abort_count; | |
1012 | ||
54b879b7 YG |
1013 | /* Number of lanes available (1 or 2) for Rx/Tx */ |
1014 | u32 lanes_per_direction; | |
7eb584db DR |
1015 | struct ufs_pa_layer_attr pwr_info; |
1016 | struct ufs_pwr_mode_info max_pwr_info; | |
1ab27c9c ST |
1017 | |
1018 | struct ufs_clk_gating clk_gating; | |
1019 | /* Control to enable/disable host capabilities */ | |
1020 | u32 caps; | |
856b3483 ST |
1021 | |
1022 | struct devfreq *devfreq; | |
1023 | struct ufs_clk_scaling clk_scaling; | |
1a547cbc | 1024 | bool system_suspending; |
e785060e | 1025 | bool is_sys_suspended; |
afdfff59 YG |
1026 | |
1027 | enum bkops_status urgent_bkops_lvl; | |
1028 | bool is_urgent_bkops_lvl_checked; | |
a3cd5ec5 | 1029 | |
1030 | struct rw_semaphore clk_scaling_lock; | |
38135535 | 1031 | atomic_t scsi_block_reqs_cnt; |
df032bf2 AA |
1032 | |
1033 | struct device bsg_dev; | |
1034 | struct request_queue *bsg_queue; | |
51dd905b | 1035 | struct delayed_work rpm_dev_flush_recheck_work; |
70297a8a | 1036 | |
f02bc975 DP |
1037 | #ifdef CONFIG_SCSI_UFS_HPB |
1038 | struct ufshpb_dev_info ufshpb_dev; | |
1039 | #endif | |
1040 | ||
1d8613a2 CG |
1041 | struct ufs_hba_monitor monitor; |
1042 | ||
70297a8a ST |
1043 | #ifdef CONFIG_SCSI_UFS_CRYPTO |
1044 | union ufs_crypto_capabilities crypto_capabilities; | |
1045 | union ufs_crypto_cap_entry *crypto_cap_array; | |
1046 | u32 crypto_cfg_register; | |
cb77cb5a | 1047 | struct blk_crypto_profile crypto_profile; |
70297a8a | 1048 | #endif |
b6cacaf2 AH |
1049 | #ifdef CONFIG_DEBUG_FS |
1050 | struct dentry *debugfs_root; | |
7deedfda AH |
1051 | struct delayed_work debugfs_ee_work; |
1052 | u32 debugfs_ee_rate_limit_ms; | |
b6cacaf2 | 1053 | #endif |
b294ff3e | 1054 | u32 luns_avail; |
57b1c0ef AD |
1055 | unsigned int nr_hw_queues; |
1056 | unsigned int nr_queues[HCTX_MAX_TYPES]; | |
b294ff3e | 1057 | bool complete_put; |
6e1d850a | 1058 | bool ext_iid_sup; |
0cab4023 | 1059 | bool scsi_host_added; |
305a357d | 1060 | bool mcq_sup; |
2468da61 | 1061 | bool mcq_enabled; |
c263b4ef AD |
1062 | struct ufshcd_res_info res[RES_MAX]; |
1063 | void __iomem *mcq_base; | |
4682abfa AD |
1064 | struct ufs_hw_queue *uhq; |
1065 | struct ufs_hw_queue *dev_cmd_queue; | |
2468da61 | 1066 | struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX]; |
4682abfa AD |
1067 | }; |
1068 | ||
1069 | /** | |
1070 | * struct ufs_hw_queue - per hardware queue structure | |
2468da61 AD |
1071 | * @mcq_sq_head: base address of submission queue head pointer |
1072 | * @mcq_sq_tail: base address of submission queue tail pointer | |
1073 | * @mcq_cq_head: base address of completion queue head pointer | |
1074 | * @mcq_cq_tail: base address of completion queue tail pointer | |
4682abfa AD |
1075 | * @sqe_base_addr: submission queue entry base address |
1076 | * @sqe_dma_addr: submission queue dma address | |
1077 | * @cqe_base_addr: completion queue base address | |
1078 | * @cqe_dma_addr: completion queue dma address | |
1079 | * @max_entries: max number of slots in this hardware queue | |
2468da61 | 1080 | * @id: hardware queue ID |
4682abfa AD |
1081 | */ |
1082 | struct ufs_hw_queue { | |
2468da61 AD |
1083 | void __iomem *mcq_sq_head; |
1084 | void __iomem *mcq_sq_tail; | |
1085 | void __iomem *mcq_cq_head; | |
1086 | void __iomem *mcq_cq_tail; | |
1087 | ||
4682abfa AD |
1088 | void *sqe_base_addr; |
1089 | dma_addr_t sqe_dma_addr; | |
1090 | struct cq_entry *cqe_base_addr; | |
1091 | dma_addr_t cqe_dma_addr; | |
1092 | u32 max_entries; | |
2468da61 | 1093 | u32 id; |
e0eca63e VH |
1094 | }; |
1095 | ||
2468da61 AD |
1096 | static inline bool is_mcq_enabled(struct ufs_hba *hba) |
1097 | { | |
1098 | return hba->mcq_enabled; | |
1099 | } | |
1100 | ||
ada1e653 EB |
1101 | #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE |
1102 | static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) | |
1103 | { | |
1104 | return hba->sg_entry_size; | |
1105 | } | |
1106 | ||
1107 | static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) | |
1108 | { | |
1109 | WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); | |
1110 | hba->sg_entry_size = sg_entry_size; | |
1111 | } | |
1112 | #else | |
1113 | static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) | |
1114 | { | |
1115 | return sizeof(struct ufshcd_sg_entry); | |
1116 | } | |
1117 | ||
1118 | #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ | |
1119 | ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) | |
1120 | #endif | |
1121 | ||
1122 | static inline size_t sizeof_utp_transfer_cmd_desc(const struct ufs_hba *hba) | |
1123 | { | |
1124 | return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); | |
1125 | } | |
1126 | ||
1ab27c9c ST |
1127 | /* Returns true if clocks can be gated. Otherwise false */ |
1128 | static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) | |
1129 | { | |
1130 | return hba->caps & UFSHCD_CAP_CLK_GATING; | |
1131 | } | |
1132 | static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) | |
1133 | { | |
1134 | return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; | |
1135 | } | |
fcb0c4b0 | 1136 | static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) |
856b3483 ST |
1137 | { |
1138 | return hba->caps & UFSHCD_CAP_CLK_SCALING; | |
1139 | } | |
374a246e SJ |
1140 | static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) |
1141 | { | |
1142 | return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; | |
1143 | } | |
49615ba1 SC |
1144 | static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) |
1145 | { | |
1146 | return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; | |
1147 | } | |
374a246e | 1148 | |
b852190e YG |
1149 | static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) |
1150 | { | |
1c0810e7 KP |
1151 | return (hba->caps & UFSHCD_CAP_INTR_AGGR) && |
1152 | !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); | |
b852190e YG |
1153 | } |
1154 | ||
dd7143e2 CG |
1155 | static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) |
1156 | { | |
1157 | return !!(ufshcd_is_link_hibern8(hba) && | |
1158 | (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); | |
1159 | } | |
1160 | ||
ee5f1042 SC |
1161 | static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) |
1162 | { | |
8da76f71 AH |
1163 | return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && |
1164 | !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); | |
ee5f1042 SC |
1165 | } |
1166 | ||
5a244e0e SC |
1167 | static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) |
1168 | { | |
51d1628f | 1169 | return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); |
5a244e0e SC |
1170 | } |
1171 | ||
3d17b9b5 AD |
1172 | static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) |
1173 | { | |
1174 | return hba->caps & UFSHCD_CAP_WB_EN; | |
1175 | } | |
1176 | ||
87bd0501 PW |
1177 | static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) |
1178 | { | |
1179 | return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; | |
1180 | } | |
1181 | ||
2468da61 AD |
1182 | #define ufsmcq_writel(hba, val, reg) \ |
1183 | writel((val), (hba)->mcq_base + (reg)) | |
1184 | #define ufsmcq_readl(hba, reg) \ | |
1185 | readl((hba)->mcq_base + (reg)) | |
1186 | ||
1187 | #define ufsmcq_writelx(hba, val, reg) \ | |
1188 | writel_relaxed((val), (hba)->mcq_base + (reg)) | |
1189 | #define ufsmcq_readlx(hba, reg) \ | |
1190 | readl_relaxed((hba)->mcq_base + (reg)) | |
1191 | ||
b873a275 SJ |
1192 | #define ufshcd_writel(hba, val, reg) \ |
1193 | writel((val), (hba)->mmio_base + (reg)) | |
1194 | #define ufshcd_readl(hba, reg) \ | |
1195 | readl((hba)->mmio_base + (reg)) | |
1196 | ||
e785060e | 1197 | /** |
cff91daf BVA |
1198 | * ufshcd_rmwl - perform read/modify/write for a controller register |
1199 | * @hba: per adapter instance | |
1200 | * @mask: mask to apply on read value | |
1201 | * @val: actual value to write | |
1202 | * @reg: register address | |
e785060e DR |
1203 | */ |
1204 | static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) | |
1205 | { | |
1206 | u32 tmp; | |
1207 | ||
1208 | tmp = ufshcd_readl(hba, reg); | |
1209 | tmp &= ~mask; | |
1210 | tmp |= (val & mask); | |
1211 | ufshcd_writel(hba, tmp, reg); | |
1212 | } | |
1213 | ||
5c0c28a8 | 1214 | int ufshcd_alloc_host(struct device *, struct ufs_hba **); |
47555a5c | 1215 | void ufshcd_dealloc_host(struct ufs_hba *); |
9d19bf7a | 1216 | int ufshcd_hba_enable(struct ufs_hba *hba); |
ecd7beb3 | 1217 | int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); |
087c5efa | 1218 | int ufshcd_link_recovery(struct ufs_hba *hba); |
9d19bf7a | 1219 | int ufshcd_make_hba_operational(struct ufs_hba *hba); |
e0eca63e | 1220 | void ufshcd_remove(struct ufs_hba *); |
525943a5 | 1221 | int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); |
9d19bf7a | 1222 | int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); |
5c955c10 | 1223 | void ufshcd_delay_us(unsigned long us, unsigned long tolerance); |
9e1e8a75 | 1224 | void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); |
e965e5e0 | 1225 | void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); |
3a95f5b3 | 1226 | void ufshcd_hba_stop(struct ufs_hba *hba); |
267a59f6 | 1227 | void ufshcd_schedule_eh_work(struct ufs_hba *hba); |
e0eca63e | 1228 | |
1ce5898a YG |
1229 | /** |
1230 | * ufshcd_set_variant - set variant specific data to the hba | |
cff91daf BVA |
1231 | * @hba: per adapter instance |
1232 | * @variant: pointer to variant specific data | |
1ce5898a YG |
1233 | */ |
1234 | static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) | |
1235 | { | |
1236 | BUG_ON(!hba); | |
1237 | hba->priv = variant; | |
1238 | } | |
1239 | ||
1240 | /** | |
1241 | * ufshcd_get_variant - get variant specific data from the hba | |
cff91daf | 1242 | * @hba: per adapter instance |
1ce5898a YG |
1243 | */ |
1244 | static inline void *ufshcd_get_variant(struct ufs_hba *hba) | |
1245 | { | |
1246 | BUG_ON(!hba); | |
1247 | return hba->priv; | |
1248 | } | |
e88e2d32 | 1249 | |
9bb25e5d | 1250 | #ifdef CONFIG_PM |
f1ecbe1e BVA |
1251 | extern int ufshcd_runtime_suspend(struct device *dev); |
1252 | extern int ufshcd_runtime_resume(struct device *dev); | |
9bb25e5d BVA |
1253 | #endif |
1254 | #ifdef CONFIG_PM_SLEEP | |
f1ecbe1e BVA |
1255 | extern int ufshcd_system_suspend(struct device *dev); |
1256 | extern int ufshcd_system_resume(struct device *dev); | |
9bb25e5d | 1257 | #endif |
57d104c1 | 1258 | extern int ufshcd_shutdown(struct ufs_hba *hba); |
fc85a74e SC |
1259 | extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, |
1260 | int agreed_gear, | |
1261 | int adapt_val); | |
12b4fdb4 SJ |
1262 | extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, |
1263 | u8 attr_set, u32 mib_val, u8 peer); | |
1264 | extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, | |
1265 | u32 *mib_val, u8 peer); | |
0d846e70 AA |
1266 | extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, |
1267 | struct ufs_pa_layer_attr *desired_pwr_mode); | |
fc53683b | 1268 | extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); |
12b4fdb4 SJ |
1269 | |
1270 | /* UIC command interfaces for DME primitives */ | |
1271 | #define DME_LOCAL 0 | |
1272 | #define DME_PEER 1 | |
1273 | #define ATTR_SET_NOR 0 /* NORMAL */ | |
1274 | #define ATTR_SET_ST 1 /* STATIC */ | |
1275 | ||
1276 | static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, | |
1277 | u32 mib_val) | |
1278 | { | |
1279 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, | |
1280 | mib_val, DME_LOCAL); | |
1281 | } | |
1282 | ||
1283 | static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, | |
1284 | u32 mib_val) | |
1285 | { | |
1286 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, | |
1287 | mib_val, DME_LOCAL); | |
1288 | } | |
1289 | ||
1290 | static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, | |
1291 | u32 mib_val) | |
1292 | { | |
1293 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, | |
1294 | mib_val, DME_PEER); | |
1295 | } | |
1296 | ||
1297 | static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, | |
1298 | u32 mib_val) | |
1299 | { | |
1300 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, | |
1301 | mib_val, DME_PEER); | |
1302 | } | |
1303 | ||
1304 | static inline int ufshcd_dme_get(struct ufs_hba *hba, | |
1305 | u32 attr_sel, u32 *mib_val) | |
1306 | { | |
1307 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); | |
1308 | } | |
1309 | ||
1310 | static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, | |
1311 | u32 attr_sel, u32 *mib_val) | |
1312 | { | |
1313 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); | |
1314 | } | |
1315 | ||
f37aabcf YG |
1316 | static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) |
1317 | { | |
1318 | return (pwr_info->pwr_rx == FAST_MODE || | |
1319 | pwr_info->pwr_rx == FASTAUTO_MODE) && | |
1320 | (pwr_info->pwr_tx == FAST_MODE || | |
1321 | pwr_info->pwr_tx == FASTAUTO_MODE); | |
1322 | } | |
1323 | ||
984eaac1 SC |
1324 | static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) |
1325 | { | |
1326 | return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); | |
1327 | } | |
1328 | ||
71d848b8 | 1329 | void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); |
ba7af5ec | 1330 | void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); |
aead21f3 BVA |
1331 | void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, |
1332 | const struct ufs_dev_quirk *fixups); | |
4b828fe1 TW |
1333 | #define SD_ASCII_STD true |
1334 | #define SD_RAW false | |
1335 | int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, | |
1336 | u8 **buf, bool ascii); | |
2238d31c | 1337 | |
1ab27c9c ST |
1338 | int ufshcd_hold(struct ufs_hba *hba, bool async); |
1339 | void ufshcd_release(struct ufs_hba *hba); | |
a4b0e8a4 | 1340 | |
ad8a647e BVA |
1341 | void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); |
1342 | ||
37113106 | 1343 | u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); |
0263bcd0 | 1344 | |
1d6f9dec SC |
1345 | int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); |
1346 | ||
e77044c5 AA |
1347 | int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); |
1348 | ||
5e0a86ee AA |
1349 | int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, |
1350 | struct utp_upiu_req *req_upiu, | |
1351 | struct utp_upiu_req *rsp_upiu, | |
1352 | int msgcode, | |
1353 | u8 *desc_buff, int *buff_len, | |
1354 | enum query_opcode desc_op); | |
6ff265fc BH |
1355 | int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, |
1356 | struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, | |
1357 | struct ufs_ehs *ehs_rsp, int sg_cnt, | |
1358 | struct scatterlist *sg_list, enum dma_data_direction dir); | |
3b5f3c0d | 1359 | int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); |
6c4148ce | 1360 | int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); |
b294ff3e | 1361 | int ufshcd_suspend_prepare(struct device *dev); |
ddba1cf7 | 1362 | int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); |
b294ff3e | 1363 | void ufshcd_resume_complete(struct device *dev); |
8e834ca5 | 1364 | |
0263bcd0 | 1365 | /* Wrapper functions for safely calling variant operations */ |
0263bcd0 YG |
1366 | static inline int ufshcd_vops_init(struct ufs_hba *hba) |
1367 | { | |
1368 | if (hba->vops && hba->vops->init) | |
1369 | return hba->vops->init(hba); | |
1370 | ||
1371 | return 0; | |
1372 | } | |
1373 | ||
92bcebe4 SC |
1374 | static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) |
1375 | { | |
1376 | if (hba->vops && hba->vops->phy_initialization) | |
1377 | return hba->vops->phy_initialization(hba); | |
1378 | ||
1379 | return 0; | |
1380 | } | |
1381 | ||
35d11ec2 | 1382 | extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; |
cbb6813e | 1383 | |
ba80917d TW |
1384 | int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, |
1385 | const char *prefix); | |
1386 | ||
7deedfda AH |
1387 | int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); |
1388 | int ufshcd_write_ee_control(struct ufs_hba *hba); | |
35d11ec2 KK |
1389 | int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, |
1390 | const u16 *other_mask, u16 set, u16 clr); | |
cd469475 | 1391 | |
e0eca63e | 1392 | #endif /* End of Header */ |