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e2be04c7 | 1 | /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ |
674e95ca DH |
2 | /* |
3 | * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, | |
4 | * Creative Labs, Inc. | |
5 | * Definitions for EMU10K1 (SB Live!) chips | |
6 | * | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | #ifndef _UAPI__SOUND_EMU10K1_H | |
24 | #define _UAPI__SOUND_EMU10K1_H | |
25 | ||
26 | #include <linux/types.h> | |
b9956409 | 27 | #include <sound/asound.h> |
674e95ca DH |
28 | |
29 | /* | |
30 | * ---- FX8010 ---- | |
31 | */ | |
32 | ||
33 | #define EMU10K1_CARD_CREATIVE 0x00000000 | |
34 | #define EMU10K1_CARD_EMUAPS 0x00000001 | |
35 | ||
36 | #define EMU10K1_FX8010_PCM_COUNT 8 | |
37 | ||
a82d24f8 MR |
38 | /* |
39 | * Following definition is copied from linux/types.h to support compiling | |
40 | * this header file in userspace since they are not generally available for | |
41 | * uapi headers. | |
42 | */ | |
43 | #define __EMU10K1_DECLARE_BITMAP(name,bits) \ | |
44 | unsigned long name[(bits) / (sizeof(unsigned long) * 8)] | |
45 | ||
674e95ca DH |
46 | /* instruction set */ |
47 | #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */ | |
48 | #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */ | |
49 | #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */ | |
50 | #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */ | |
51 | #define iMACINT0 0x04 /* R = A + X * Y ; saturation */ | |
52 | #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */ | |
53 | #define iACC3 0x06 /* R = A + X + Y ; saturation */ | |
54 | #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */ | |
55 | #define iANDXOR 0x08 /* R = (A & X) ^ Y */ | |
56 | #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */ | |
57 | #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */ | |
58 | #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */ | |
59 | #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */ | |
60 | #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */ | |
61 | #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */ | |
62 | #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */ | |
63 | ||
64 | /* GPRs */ | |
65 | #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */ | |
66 | #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */ | |
67 | #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */ | |
68 | #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */ | |
69 | /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */ | |
70 | ||
71 | #define C_00000000 0x40 | |
72 | #define C_00000001 0x41 | |
73 | #define C_00000002 0x42 | |
74 | #define C_00000003 0x43 | |
75 | #define C_00000004 0x44 | |
76 | #define C_00000008 0x45 | |
77 | #define C_00000010 0x46 | |
78 | #define C_00000020 0x47 | |
79 | #define C_00000100 0x48 | |
80 | #define C_00010000 0x49 | |
81 | #define C_00080000 0x4a | |
82 | #define C_10000000 0x4b | |
83 | #define C_20000000 0x4c | |
84 | #define C_40000000 0x4d | |
85 | #define C_80000000 0x4e | |
86 | #define C_7fffffff 0x4f | |
87 | #define C_ffffffff 0x50 | |
88 | #define C_fffffffe 0x51 | |
89 | #define C_c0000000 0x52 | |
90 | #define C_4f1bbcdc 0x53 | |
91 | #define C_5a7ef9db 0x54 | |
92 | #define C_00100000 0x55 /* ?? */ | |
93 | #define GPR_ACCU 0x56 /* ACCUM, accumulator */ | |
94 | #define GPR_COND 0x57 /* CCR, condition register */ | |
95 | #define GPR_NOISE0 0x58 /* noise source */ | |
96 | #define GPR_NOISE1 0x59 /* noise source */ | |
97 | #define GPR_IRQ 0x5a /* IRQ register */ | |
98 | #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */ | |
99 | #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */ | |
100 | #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ | |
101 | #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ | |
102 | #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ | |
103 | #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ | |
104 | ||
105 | #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ | |
106 | #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ | |
107 | #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ | |
108 | #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ | |
109 | #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ | |
110 | #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ | |
111 | ||
112 | #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */ | |
113 | #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */ | |
114 | #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */ | |
115 | #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */ | |
116 | #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */ | |
117 | #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */ | |
118 | #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */ | |
119 | #define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */ | |
120 | #define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */ | |
121 | #define A_GPR(x) (A_FXGPREGBASE + (x)) | |
122 | ||
123 | /* cc_reg constants */ | |
124 | #define CC_REG_NORMALIZED C_00000001 | |
125 | #define CC_REG_BORROW C_00000002 | |
126 | #define CC_REG_MINUS C_00000004 | |
127 | #define CC_REG_ZERO C_00000008 | |
128 | #define CC_REG_SATURATE C_00000010 | |
129 | #define CC_REG_NONZERO C_00000100 | |
130 | ||
131 | /* FX buses */ | |
132 | #define FXBUS_PCM_LEFT 0x00 | |
133 | #define FXBUS_PCM_RIGHT 0x01 | |
134 | #define FXBUS_PCM_LEFT_REAR 0x02 | |
135 | #define FXBUS_PCM_RIGHT_REAR 0x03 | |
136 | #define FXBUS_MIDI_LEFT 0x04 | |
137 | #define FXBUS_MIDI_RIGHT 0x05 | |
138 | #define FXBUS_PCM_CENTER 0x06 | |
139 | #define FXBUS_PCM_LFE 0x07 | |
140 | #define FXBUS_PCM_LEFT_FRONT 0x08 | |
141 | #define FXBUS_PCM_RIGHT_FRONT 0x09 | |
142 | #define FXBUS_MIDI_REVERB 0x0c | |
143 | #define FXBUS_MIDI_CHORUS 0x0d | |
144 | #define FXBUS_PCM_LEFT_SIDE 0x0e | |
145 | #define FXBUS_PCM_RIGHT_SIDE 0x0f | |
146 | #define FXBUS_PT_LEFT 0x14 | |
147 | #define FXBUS_PT_RIGHT 0x15 | |
148 | ||
149 | /* Inputs */ | |
150 | #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ | |
151 | #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ | |
152 | #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */ | |
153 | #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */ | |
154 | #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */ | |
155 | #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */ | |
156 | #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */ | |
157 | #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */ | |
158 | #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */ | |
159 | #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */ | |
160 | #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */ | |
161 | #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */ | |
162 | #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */ | |
163 | #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */ | |
164 | ||
165 | /* Outputs */ | |
166 | #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */ | |
167 | #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */ | |
168 | #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */ | |
169 | #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */ | |
170 | #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */ | |
171 | #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */ | |
172 | #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */ | |
173 | #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */ | |
174 | #define EXTOUT_REAR_L 0x08 /* Rear channel - left */ | |
175 | #define EXTOUT_REAR_R 0x09 /* Rear channel - right */ | |
176 | #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */ | |
177 | #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */ | |
178 | #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */ | |
179 | #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */ | |
180 | #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */ | |
181 | #define EXTOUT_ACENTER 0x11 /* Analog Center */ | |
182 | #define EXTOUT_ALFE 0x12 /* Analog LFE */ | |
183 | ||
184 | /* Audigy Inputs */ | |
185 | #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ | |
186 | #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ | |
187 | #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */ | |
188 | #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */ | |
189 | #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */ | |
190 | #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */ | |
191 | #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */ | |
192 | #define A_EXTIN_LINE2_R 0x09 /* right */ | |
193 | #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */ | |
194 | #define A_EXTIN_ADC_R 0x0b /* right */ | |
195 | #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */ | |
196 | #define A_EXTIN_AUX2_R 0x0d /* - right */ | |
197 | ||
198 | /* Audigiy Outputs */ | |
199 | #define A_EXTOUT_FRONT_L 0x00 /* digital front left */ | |
200 | #define A_EXTOUT_FRONT_R 0x01 /* right */ | |
201 | #define A_EXTOUT_CENTER 0x02 /* digital front center */ | |
202 | #define A_EXTOUT_LFE 0x03 /* digital front lfe */ | |
203 | #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */ | |
204 | #define A_EXTOUT_HEADPHONE_R 0x05 /* right */ | |
205 | #define A_EXTOUT_REAR_L 0x06 /* digital rear left */ | |
206 | #define A_EXTOUT_REAR_R 0x07 /* right */ | |
207 | #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */ | |
208 | #define A_EXTOUT_AFRONT_R 0x09 /* right */ | |
209 | #define A_EXTOUT_ACENTER 0x0a /* analog center */ | |
210 | #define A_EXTOUT_ALFE 0x0b /* analog LFE */ | |
211 | #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */ | |
212 | #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */ | |
213 | #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */ | |
214 | #define A_EXTOUT_AREAR_R 0x0f /* right */ | |
215 | #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */ | |
216 | #define A_EXTOUT_AC97_R 0x11 /* right */ | |
217 | #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */ | |
218 | #define A_EXTOUT_ADC_CAP_R 0x17 /* right */ | |
219 | #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */ | |
220 | ||
221 | /* Audigy constants */ | |
222 | #define A_C_00000000 0xc0 | |
223 | #define A_C_00000001 0xc1 | |
224 | #define A_C_00000002 0xc2 | |
225 | #define A_C_00000003 0xc3 | |
226 | #define A_C_00000004 0xc4 | |
227 | #define A_C_00000008 0xc5 | |
228 | #define A_C_00000010 0xc6 | |
229 | #define A_C_00000020 0xc7 | |
230 | #define A_C_00000100 0xc8 | |
231 | #define A_C_00010000 0xc9 | |
232 | #define A_C_00000800 0xca | |
233 | #define A_C_10000000 0xcb | |
234 | #define A_C_20000000 0xcc | |
235 | #define A_C_40000000 0xcd | |
236 | #define A_C_80000000 0xce | |
237 | #define A_C_7fffffff 0xcf | |
238 | #define A_C_ffffffff 0xd0 | |
239 | #define A_C_fffffffe 0xd1 | |
240 | #define A_C_c0000000 0xd2 | |
241 | #define A_C_4f1bbcdc 0xd3 | |
242 | #define A_C_5a7ef9db 0xd4 | |
243 | #define A_C_00100000 0xd5 | |
244 | #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */ | |
245 | #define A_GPR_COND 0xd7 /* CCR, condition register */ | |
246 | #define A_GPR_NOISE0 0xd8 /* noise source */ | |
247 | #define A_GPR_NOISE1 0xd9 /* noise source */ | |
248 | #define A_GPR_IRQ 0xda /* IRQ register */ | |
249 | #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */ | |
250 | #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */ | |
251 | ||
252 | /* definitions for debug register */ | |
253 | #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */ | |
254 | #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */ | |
255 | #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */ | |
256 | #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */ | |
257 | #define EMU10K1_DBG_STEP 0x00004000 /* start single step */ | |
258 | #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */ | |
259 | #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */ | |
260 | ||
261 | /* tank memory address line */ | |
262 | #ifndef __KERNEL__ | |
263 | #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ | |
264 | #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ | |
265 | #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ | |
266 | #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ | |
267 | #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ | |
268 | #endif | |
269 | ||
270 | struct snd_emu10k1_fx8010_info { | |
271 | unsigned int internal_tram_size; /* in samples */ | |
272 | unsigned int external_tram_size; /* in samples */ | |
273 | char fxbus_names[16][32]; /* names of FXBUSes */ | |
274 | char extin_names[16][32]; /* names of external inputs */ | |
275 | char extout_names[32][32]; /* names of external outputs */ | |
276 | unsigned int gpr_controls; /* count of GPR controls */ | |
277 | }; | |
278 | ||
279 | #define EMU10K1_GPR_TRANSLATION_NONE 0 | |
280 | #define EMU10K1_GPR_TRANSLATION_TABLE100 1 | |
281 | #define EMU10K1_GPR_TRANSLATION_BASS 2 | |
282 | #define EMU10K1_GPR_TRANSLATION_TREBLE 3 | |
283 | #define EMU10K1_GPR_TRANSLATION_ONOFF 4 | |
284 | ||
285 | struct snd_emu10k1_fx8010_control_gpr { | |
286 | struct snd_ctl_elem_id id; /* full control ID definition */ | |
287 | unsigned int vcount; /* visible count */ | |
288 | unsigned int count; /* count of GPR (1..16) */ | |
289 | unsigned short gpr[32]; /* GPR number(s) */ | |
290 | unsigned int value[32]; /* initial values */ | |
291 | unsigned int min; /* minimum range */ | |
292 | unsigned int max; /* maximum range */ | |
293 | unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ | |
294 | const unsigned int *tlv; | |
295 | }; | |
296 | ||
297 | /* old ABI without TLV support */ | |
298 | struct snd_emu10k1_fx8010_control_old_gpr { | |
299 | struct snd_ctl_elem_id id; | |
300 | unsigned int vcount; | |
301 | unsigned int count; | |
302 | unsigned short gpr[32]; | |
303 | unsigned int value[32]; | |
304 | unsigned int min; | |
305 | unsigned int max; | |
306 | unsigned int translation; | |
307 | }; | |
308 | ||
309 | struct snd_emu10k1_fx8010_code { | |
310 | char name[128]; | |
311 | ||
a82d24f8 | 312 | __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */ |
674e95ca DH |
313 | __u32 __user *gpr_map; /* initializers */ |
314 | ||
315 | unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */ | |
316 | struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls; /* GPR controls to add/replace */ | |
317 | ||
318 | unsigned int gpr_del_control_count; /* count of GPR controls to remove */ | |
319 | struct snd_ctl_elem_id __user *gpr_del_controls; /* IDs of GPR controls to remove */ | |
320 | ||
321 | unsigned int gpr_list_control_count; /* count of GPR controls to list */ | |
322 | unsigned int gpr_list_control_total; /* total count of GPR controls */ | |
323 | struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls; /* listed GPR controls */ | |
324 | ||
a82d24f8 | 325 | __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */ |
674e95ca DH |
326 | __u32 __user *tram_data_map; /* data initializers */ |
327 | __u32 __user *tram_addr_map; /* map initializers */ | |
328 | ||
a82d24f8 | 329 | __EMU10K1_DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */ |
674e95ca DH |
330 | __u32 __user *code; /* one instruction - 64 bits */ |
331 | }; | |
332 | ||
333 | struct snd_emu10k1_fx8010_tram { | |
334 | unsigned int address; /* 31.bit == 1 -> external TRAM */ | |
335 | unsigned int size; /* size in samples (4 bytes) */ | |
336 | unsigned int *samples; /* pointer to samples (20-bit) */ | |
337 | /* NULL->clear memory */ | |
338 | }; | |
339 | ||
340 | struct snd_emu10k1_fx8010_pcm_rec { | |
341 | unsigned int substream; /* substream number */ | |
342 | unsigned int res1; /* reserved */ | |
343 | unsigned int channels; /* 16-bit channels count, zero = remove this substream */ | |
344 | unsigned int tram_start; /* ring buffer position in TRAM (in samples) */ | |
345 | unsigned int buffer_size; /* count of buffered samples */ | |
346 | unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */ | |
347 | unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ | |
348 | unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ | |
349 | unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ | |
350 | unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ | |
351 | unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ | |
352 | unsigned char pad; /* reserved */ | |
353 | unsigned char etram[32]; /* external TRAM address & data (one per channel) */ | |
354 | unsigned int res2; /* reserved */ | |
355 | }; | |
356 | ||
357 | #define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) | |
358 | ||
359 | #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info) | |
360 | #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code) | |
361 | #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code) | |
362 | #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int) | |
363 | #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram) | |
364 | #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram) | |
365 | #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec) | |
366 | #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec) | |
367 | #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int) | |
368 | #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80) | |
369 | #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81) | |
370 | #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82) | |
371 | #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int) | |
372 | #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int) | |
373 | ||
374 | /* typedefs for compatibility to user-space */ | |
375 | typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t; | |
376 | typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t; | |
377 | typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t; | |
378 | typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t; | |
379 | typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t; | |
380 | ||
381 | #endif /* _UAPI__SOUND_EMU10K1_H */ |