[linux-2.6-block.git] / include / uapi / rdma / mlx5-abi.h

/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX5_ABI_USER_H
#define MLX5_ABI_USER_H

#include <linux/types.h>
#include <linux/if_ether.h>	/* For ETH_ALEN. */

enum {
	MLX5_QP_FLAG_SIGNATURE		= 1 << 0,
	MLX5_QP_FLAG_SCATTER_CQE	= 1 << 1,
	MLX5_QP_FLAG_TUNNEL_OFFLOADS	= 1 << 2,
	MLX5_QP_FLAG_BFREG_INDEX	= 1 << 3,
	MLX5_QP_FLAG_TYPE_DCT		= 1 << 4,
	MLX5_QP_FLAG_TYPE_DCI		= 1 << 5,
};

enum {
	MLX5_SRQ_FLAG_SIGNATURE		= 1 << 0,
};

enum {
	MLX5_WQ_FLAG_SIGNATURE		= 1 << 0,
};

/* Increment this value if any changes that break userspace ABI
 * compatibility are made.
 */
#define MLX5_IB_UVERBS_ABI_VERSION	1

/* Make sure that all structs defined in this file remain laid out so
 * that they pack the same way on 32-bit and 64-bit architectures (to
 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
 * In particular do not use pointer types -- pass pointers in __u64
 * instead.
 */

struct mlx5_ib_alloc_ucontext_req {
	__u32	total_num_bfregs;
	__u32	num_low_latency_bfregs;
};

enum mlx5_lib_caps {
	MLX5_LIB_CAP_4K_UAR	= (__u64)1 << 0,
};

struct mlx5_ib_alloc_ucontext_req_v2 {
	__u32	total_num_bfregs;
	__u32	num_low_latency_bfregs;
	__u32	flags;
	__u32	comp_mask;
	__u8	max_cqe_version;
	__u8	reserved0;
	__u16	reserved1;
	__u32	reserved2;
	__aligned_u64 lib_caps;
};

enum mlx5_ib_alloc_ucontext_resp_mask {
	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
};

enum mlx5_user_cmds_supp_uhw {
	MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
	MLX5_USER_CMDS_SUPP_UHW_CREATE_AH    = 1 << 1,
};

/* The eth_min_inline response value is set to off-by-one vs the FW
 * returned value to allow user-space to deal with older kernels.
 */
enum mlx5_user_inline_mode {
	MLX5_USER_INLINE_MODE_NA,
	MLX5_USER_INLINE_MODE_NONE,
	MLX5_USER_INLINE_MODE_L2,
	MLX5_USER_INLINE_MODE_IP,
	MLX5_USER_INLINE_MODE_TCP_UDP,
};

enum {
	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
};

struct mlx5_ib_alloc_ucontext_resp {
	__u32	qp_tab_size;
	__u32	bf_reg_size;
	__u32	tot_bfregs;
	__u32	cache_line_size;
	__u16	max_sq_desc_sz;
	__u16	max_rq_desc_sz;
	__u32	max_send_wqebb;
	__u32	max_recv_wr;
	__u32	max_srq_recv_wr;
	__u16	num_ports;
	__u16	flow_action_flags;
	__u32	comp_mask;
	__u32	response_length;
	__u8	cqe_version;
	__u8	cmds_supp_uhw;
	__u8	eth_min_inline;
	__u8	clock_info_versions;
	__aligned_u64 hca_core_clock_offset;
	__u32	log_uar_size;
	__u32	num_uars_per_page;
	__u32	num_dyn_bfregs;
	__u32	reserved3;
};

struct mlx5_ib_alloc_pd_resp {
	__u32	pdn;
};

struct mlx5_ib_tso_caps {
	__u32 max_tso; /* Maximum tso payload size in bytes */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_UD
	 */
	__u32 supported_qpts;
};

struct mlx5_ib_rss_caps {
	__aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	__u8 reserved[7];
};

enum mlx5_ib_cqe_comp_res_format {
	MLX5_IB_CQE_RES_FORMAT_HASH	= 1 << 0,
	MLX5_IB_CQE_RES_FORMAT_CSUM	= 1 << 1,
	MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
};

struct mlx5_ib_cqe_comp_caps {
	__u32 max_num;
	__u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
};

enum mlx5_ib_packet_pacing_cap_flags {
	MLX5_IB_PP_SUPPORT_BURST	= 1 << 0,
};

struct mlx5_packet_pacing_caps {
	__u32 qp_rate_limit_min;
	__u32 qp_rate_limit_max; /* In kpbs */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
	 */
	__u32 supported_qpts;
	__u8  cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
	__u8  reserved[3];
};

enum mlx5_ib_mpw_caps {
	MPW_RESERVED		= 1 << 0,
	MLX5_IB_ALLOW_MPW	= 1 << 1,
	MLX5_IB_SUPPORT_EMPW	= 1 << 2,
};

enum mlx5_ib_sw_parsing_offloads {
	MLX5_IB_SW_PARSING = 1 << 0,
	MLX5_IB_SW_PARSING_CSUM = 1 << 1,
	MLX5_IB_SW_PARSING_LSO = 1 << 2,
};

struct mlx5_ib_sw_parsing_caps {
	__u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
	 */
	__u32 supported_qpts;
};

struct mlx5_ib_striding_rq_caps {
	__u32 min_single_stride_log_num_of_bytes;
	__u32 max_single_stride_log_num_of_bytes;
	__u32 min_single_wqe_log_num_of_strides;
	__u32 max_single_wqe_log_num_of_strides;

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
	 */
	__u32 supported_qpts;
	__u32 reserved;
};

enum mlx5_ib_query_dev_resp_flags {
	/* Support 128B CQE compression */
	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD  = 1 << 1,
};

enum mlx5_ib_tunnel_offloads {
	MLX5_IB_TUNNELED_OFFLOADS_VXLAN  = 1 << 0,
	MLX5_IB_TUNNELED_OFFLOADS_GRE    = 1 << 1,
	MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2
};

struct mlx5_ib_query_device_resp {
	__u32	comp_mask;
	__u32	response_length;
	struct	mlx5_ib_tso_caps tso_caps;
	struct	mlx5_ib_rss_caps rss_caps;
	struct	mlx5_ib_cqe_comp_caps cqe_comp_caps;
	struct	mlx5_packet_pacing_caps packet_pacing_caps;
	__u32	mlx5_ib_support_multi_pkt_send_wqes;
	__u32	flags; /* Use enum mlx5_ib_query_dev_resp_flags */
	struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
	struct mlx5_ib_striding_rq_caps striding_rq_caps;
	__u32	tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
	__u32	reserved;
};

enum mlx5_ib_create_cq_flags {
	MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD	= 1 << 0,
};

struct mlx5_ib_create_cq {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
	__u32	cqe_size;
	__u8    cqe_comp_en;
	__u8    cqe_comp_res_format;
	__u16	flags;
};

struct mlx5_ib_create_cq_resp {
	__u32	cqn;
	__u32	reserved;
};

struct mlx5_ib_resize_cq {
	__aligned_u64 buf_addr;
	__u16	cqe_size;
	__u16	reserved0;
	__u32	reserved1;
};

struct mlx5_ib_create_srq {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
	__u32	flags;
	__u32	reserved0; /* explicit padding (optional on i386) */
	__u32	uidx;
	__u32	reserved1;
};

struct mlx5_ib_create_srq_resp {
	__u32	srqn;
	__u32	reserved;
};

struct mlx5_ib_create_qp {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
	__u32	sq_wqe_count;
	__u32	rq_wqe_count;
	__u32	rq_wqe_shift;
	__u32	flags;
	__u32	uidx;
	__u32	bfreg_index;
	union {
		__aligned_u64 sq_buf_addr;
		__aligned_u64 access_key;
	};
};

/* RX Hash function flags */
enum mlx5_rx_hash_function_flags {
	MLX5_RX_HASH_FUNC_TOEPLITZ	= 1 << 0,
};

/*
 * RX Hash flags, these flags allows to set which incoming packet's field should
 * participates in RX Hash. Each flag represent certain packet's field,
 * when the flag is set the field that is represented by the flag will
 * participate in RX Hash calculation.
 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
 * and *TCP and *UDP flags can't be enabled together on the same QP.
*/
enum mlx5_rx_hash_fields {
	MLX5_RX_HASH_SRC_IPV4	= 1 << 0,
	MLX5_RX_HASH_DST_IPV4	= 1 << 1,
	MLX5_RX_HASH_SRC_IPV6	= 1 << 2,
	MLX5_RX_HASH_DST_IPV6	= 1 << 3,
	MLX5_RX_HASH_SRC_PORT_TCP	= 1 << 4,
	MLX5_RX_HASH_DST_PORT_TCP	= 1 << 5,
	MLX5_RX_HASH_SRC_PORT_UDP	= 1 << 6,
	MLX5_RX_HASH_DST_PORT_UDP	= 1 << 7,
	MLX5_RX_HASH_IPSEC_SPI		= 1 << 8,
	/* Save bits for future fields */
	MLX5_RX_HASH_INNER		= (1UL << 31),
};

struct mlx5_ib_create_qp_rss {
	__aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	__u8 rx_key_len; /* valid only for Toeplitz */
	__u8 reserved[6];
	__u8 rx_hash_key[128]; /* valid only for Toeplitz */
	__u32   comp_mask;
	__u32	flags;
};

struct mlx5_ib_create_qp_resp {
	__u32	bfreg_index;
	__u32   reserved;
};

struct mlx5_ib_alloc_mw {
	__u32	comp_mask;
	__u8	num_klms;
	__u8	reserved1;
	__u16	reserved2;
};

enum mlx5_ib_create_wq_mask {
	MLX5_IB_CREATE_WQ_STRIDING_RQ	= (1 << 0),
};

struct mlx5_ib_create_wq {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
	__u32   rq_wqe_count;
	__u32   rq_wqe_shift;
	__u32   user_index;
	__u32   flags;
	__u32   comp_mask;
	__u32	single_stride_log_num_of_bytes;
	__u32	single_wqe_log_num_of_strides;
	__u32	two_byte_shift_en;
};

struct mlx5_ib_create_ah_resp {
	__u32	response_length;
	__u8	dmac[ETH_ALEN];
	__u8	reserved[6];
};

struct mlx5_ib_burst_info {
	__u32       max_burst_sz;
	__u16       typical_pkt_sz;
	__u16       reserved;
};

struct mlx5_ib_modify_qp {
	__u32			   comp_mask;
	struct mlx5_ib_burst_info  burst_info;
	__u32			   reserved;
};

struct mlx5_ib_modify_qp_resp {
	__u32	response_length;
	__u32	dctn;
};

struct mlx5_ib_create_wq_resp {
	__u32	response_length;
	__u32	reserved;
};

struct mlx5_ib_create_rwq_ind_tbl_resp {
	__u32	response_length;
	__u32	reserved;
};

struct mlx5_ib_modify_wq {
	__u32	comp_mask;
	__u32	reserved;
};

struct mlx5_ib_clock_info {
	__u32 sign;
	__u32 resv;
	__aligned_u64 nsec;
	__aligned_u64 cycles;
	__aligned_u64 frac;
	__u32 mult;
	__u32 shift;
	__aligned_u64 mask;
	__aligned_u64 overflow_period;
};

enum mlx5_ib_mmap_cmd {
	MLX5_IB_MMAP_REGULAR_PAGE               = 0,
	MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES       = 1,
	MLX5_IB_MMAP_WC_PAGE                    = 2,
	MLX5_IB_MMAP_NC_PAGE                    = 3,
	/* 5 is chosen in order to be compatible with old versions of libmlx5 */
	MLX5_IB_MMAP_CORE_CLOCK                 = 5,
	MLX5_IB_MMAP_ALLOC_WC                   = 6,
	MLX5_IB_MMAP_CLOCK_INFO                 = 7,
	MLX5_IB_MMAP_DEVICE_MEM                 = 8,
};

enum {
	MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
};

/* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
enum {
	MLX5_IB_CLOCK_INFO_V1              = 0,
};
#endif /* MLX5_ABI_USER_H */
Commit	Line	Data
e2be04c7	1	/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
e126ba97	2	/*
6cf0a15f	3	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenIB.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*/
	33
3085e29e LR	34	#ifndef MLX5_ABI_USER_H
3085e29e LR	35	#define MLX5_ABI_USER_H
e126ba97 EC	36
e126ba97 EC	37	#include <linux/types.h>
812755d6	38	#include <linux/if_ether.h> /* For ETH_ALEN. */
e126ba97 EC	39
	40	enum {
	41	MLX5_QP_FLAG_SIGNATURE = 1 << 0,
	42	MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
f95ef6cb	43	MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
1ee47ab3	44	MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
b4aaa1f0 MS	45	MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
b4aaa1f0 MS	46	MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
e126ba97 EC	47	};
	48
	49	enum {
	50	MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
	51	};
	52
79b20a6c YH	53	enum {
	54	MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
	55	};
	56
e126ba97 EC	57	/* Increment this value if any changes that break userspace ABI
	58	* compatibility are made.
	59	*/
	60	#define MLX5_IB_UVERBS_ABI_VERSION 1
	61
	62	/* Make sure that all structs defined in this file remain laid out so
	63	* that they pack the same way on 32-bit and 64-bit architectures (to
	64	* avoid incompatibility between 32-bit userspace and 64-bit kernels).
	65	* In particular do not use pointer types -- pass pointers in __u64
	66	* instead.
	67	*/
	68
	69	struct mlx5_ib_alloc_ucontext_req {
2f5ff264 EC	70	__u32 total_num_bfregs;
2f5ff264 EC	71	__u32 num_low_latency_bfregs;
e126ba97 EC	72	};
e126ba97 EC	73
30aa60b3	74	enum mlx5_lib_caps {
812755d6	75	MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
30aa60b3 EC	76	};
30aa60b3 EC	77
78c0f98c	78	struct mlx5_ib_alloc_ucontext_req_v2 {
2f5ff264 EC	79	__u32 total_num_bfregs;
2f5ff264 EC	80	__u32 num_low_latency_bfregs;
78c0f98c	81	__u32 flags;
b368d7cb	82	__u32 comp_mask;
f72300c5 HA	83	__u8 max_cqe_version;
	84	__u8 reserved0;
	85	__u16 reserved1;
	86	__u32 reserved2;
26b99066	87	__aligned_u64 lib_caps;
b368d7cb MB	88	};
	89
	90	enum mlx5_ib_alloc_ucontext_resp_mask {
	91	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
78c0f98c EC	92	};
78c0f98c EC	93
402ca536 BW	94	enum mlx5_user_cmds_supp_uhw {
402ca536 BW	95	MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
6ad279c5	96	MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
402ca536 BW	97	};
402ca536 BW	98
78984898 OG	99	/* The eth_min_inline response value is set to off-by-one vs the FW
	100	* returned value to allow user-space to deal with older kernels.
	101	*/
	102	enum mlx5_user_inline_mode {
	103	MLX5_USER_INLINE_MODE_NA,
	104	MLX5_USER_INLINE_MODE_NONE,
	105	MLX5_USER_INLINE_MODE_L2,
	106	MLX5_USER_INLINE_MODE_IP,
	107	MLX5_USER_INLINE_MODE_TCP_UDP,
	108	};
	109
c03faa56 MB	110	enum {
	111	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
	112	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
	113	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
	114	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
	115	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
	116	};
	117
e126ba97 EC	118	struct mlx5_ib_alloc_ucontext_resp {
	119	__u32 qp_tab_size;
	120	__u32 bf_reg_size;
2f5ff264	121	__u32 tot_bfregs;
e126ba97 EC	122	__u32 cache_line_size;
	123	__u16 max_sq_desc_sz;
	124	__u16 max_rq_desc_sz;
	125	__u32 max_send_wqebb;
	126	__u32 max_recv_wr;
	127	__u32 max_srq_recv_wr;
	128	__u16 num_ports;
c03faa56	129	__u16 flow_action_flags;
b368d7cb MB	130	__u32 comp_mask;
b368d7cb MB	131	__u32 response_length;
f72300c5	132	__u8 cqe_version;
402ca536	133	__u8 cmds_supp_uhw;
78984898	134	__u8 eth_min_inline;
5c99eaec	135	__u8 clock_info_versions;
26b99066	136	__aligned_u64 hca_core_clock_offset;
30aa60b3 EC	137	__u32 log_uar_size;
30aa60b3 EC	138	__u32 num_uars_per_page;
31a78a5a YH	139	__u32 num_dyn_bfregs;
31a78a5a YH	140	__u32 reserved3;
e126ba97 EC	141	};
	142
	143	struct mlx5_ib_alloc_pd_resp {
	144	__u32 pdn;
	145	};
	146
402ca536 BW	147	struct mlx5_ib_tso_caps {
	148	__u32 max_tso; /* Maximum tso payload size in bytes */
	149
	150	/* Corresponding bit will be set if qp type from
	151	* 'enum ib_qp_type' is supported, e.g.
	152	* supported_qpts \|= 1 << IB_QPT_UD
	153	*/
	154	__u32 supported_qpts;
	155	};
	156
31f69a82	157	struct mlx5_ib_rss_caps {
26b99066	158	__aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
31f69a82 YH	159	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	160	__u8 reserved[7];
	161	};
	162
7e43a2a5 BW	163	enum mlx5_ib_cqe_comp_res_format {
	164	MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
	165	MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
6f1006a4	166	MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
7e43a2a5 BW	167	};
	168
	169	struct mlx5_ib_cqe_comp_caps {
	170	__u32 max_num;
	171	__u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
	172	};
	173
61147f39 BW	174	enum mlx5_ib_packet_pacing_cap_flags {
	175	MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
	176	};
	177
d949167d BW	178	struct mlx5_packet_pacing_caps {
	179	__u32 qp_rate_limit_min;
	180	__u32 qp_rate_limit_max; /* In kpbs */
	181
	182	/* Corresponding bit will be set if qp type from
	183	* 'enum ib_qp_type' is supported, e.g.
	184	* supported_qpts \|= 1 << IB_QPT_RAW_PACKET
	185	*/
	186	__u32 supported_qpts;
61147f39 BW	187	__u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
61147f39 BW	188	__u8 reserved[3];
d949167d BW	189	};
d949167d BW	190
795b609c BW	191	enum mlx5_ib_mpw_caps {
	192	MPW_RESERVED = 1 << 0,
	193	MLX5_IB_ALLOW_MPW = 1 << 1,
050da902	194	MLX5_IB_SUPPORT_EMPW = 1 << 2,
795b609c BW	195	};
795b609c BW	196
96dc3fc5 NO	197	enum mlx5_ib_sw_parsing_offloads {
	198	MLX5_IB_SW_PARSING = 1 << 0,
	199	MLX5_IB_SW_PARSING_CSUM = 1 << 1,
	200	MLX5_IB_SW_PARSING_LSO = 1 << 2,
	201	};
	202
	203	struct mlx5_ib_sw_parsing_caps {
	204	__u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
	205
	206	/* Corresponding bit will be set if qp type from
	207	* 'enum ib_qp_type' is supported, e.g.
	208	* supported_qpts \|= 1 << IB_QPT_RAW_PACKET
	209	*/
	210	__u32 supported_qpts;
	211	};
	212
b4f34597 NO	213	struct mlx5_ib_striding_rq_caps {
	214	__u32 min_single_stride_log_num_of_bytes;
	215	__u32 max_single_stride_log_num_of_bytes;
	216	__u32 min_single_wqe_log_num_of_strides;
	217	__u32 max_single_wqe_log_num_of_strides;
	218
	219	/* Corresponding bit will be set if qp type from
	220	* 'enum ib_qp_type' is supported, e.g.
	221	* supported_qpts \|= 1 << IB_QPT_RAW_PACKET
	222	*/
	223	__u32 supported_qpts;
f17966f1	224	__u32 reserved;
b4f34597 NO	225	};
b4f34597 NO	226
de57f2ad GL	227	enum mlx5_ib_query_dev_resp_flags {
	228	/* Support 128B CQE compression */
	229	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
7a0c8f42	230	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
de57f2ad GL	231	};
de57f2ad GL	232
f95ef6cb MG	233	enum mlx5_ib_tunnel_offloads {
	234	MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
	235	MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
	236	MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2
	237	};
	238
402ca536 BW	239	struct mlx5_ib_query_device_resp {
	240	__u32 comp_mask;
	241	__u32 response_length;
	242	struct mlx5_ib_tso_caps tso_caps;
31f69a82	243	struct mlx5_ib_rss_caps rss_caps;
7e43a2a5	244	struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
d949167d	245	struct mlx5_packet_pacing_caps packet_pacing_caps;
191ded4a	246	__u32 mlx5_ib_support_multi_pkt_send_wqes;
de57f2ad	247	__u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
96dc3fc5	248	struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
b4f34597	249	struct mlx5_ib_striding_rq_caps striding_rq_caps;
f95ef6cb MG	250	__u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
f95ef6cb MG	251	__u32 reserved;
402ca536 BW	252	};
402ca536 BW	253
7a0c8f42 GL	254	enum mlx5_ib_create_cq_flags {
7a0c8f42 GL	255	MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
402ca536 BW	256	};
402ca536 BW	257
e126ba97	258	struct mlx5_ib_create_cq {
26b99066 JG	259	__aligned_u64 buf_addr;
26b99066 JG	260	__aligned_u64 db_addr;
e126ba97	261	__u32 cqe_size;
1cbe6fc8 BW	262	__u8 cqe_comp_en;
1cbe6fc8 BW	263	__u8 cqe_comp_res_format;
7a0c8f42	264	__u16 flags;
e126ba97 EC	265	};
	266
	267	struct mlx5_ib_create_cq_resp {
	268	__u32 cqn;
	269	__u32 reserved;
	270	};
	271
	272	struct mlx5_ib_resize_cq {
26b99066	273	__aligned_u64 buf_addr;
bde51583 EC	274	__u16 cqe_size;
	275	__u16 reserved0;
	276	__u32 reserved1;
e126ba97 EC	277	};
	278
	279	struct mlx5_ib_create_srq {
26b99066 JG	280	__aligned_u64 buf_addr;
26b99066 JG	281	__aligned_u64 db_addr;
e126ba97	282	__u32 flags;
cfb5e088 HA	283	__u32 reserved0; /* explicit padding (optional on i386) */
	284	__u32 uidx;
	285	__u32 reserved1;
e126ba97 EC	286	};
	287
	288	struct mlx5_ib_create_srq_resp {
	289	__u32 srqn;
	290	__u32 reserved;
	291	};
	292
	293	struct mlx5_ib_create_qp {
26b99066 JG	294	__aligned_u64 buf_addr;
26b99066 JG	295	__aligned_u64 db_addr;
e126ba97 EC	296	__u32 sq_wqe_count;
	297	__u32 rq_wqe_count;
	298	__u32 rq_wqe_shift;
	299	__u32 flags;
cfb5e088	300	__u32 uidx;
1ee47ab3	301	__u32 bfreg_index;
b4aaa1f0	302	union {
26b99066 JG	303	__aligned_u64 sq_buf_addr;
26b99066 JG	304	__aligned_u64 access_key;
b4aaa1f0	305	};
e126ba97 EC	306	};
e126ba97 EC	307
28d61370 YH	308	/* RX Hash function flags */
	309	enum mlx5_rx_hash_function_flags {
	310	MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
	311	};
	312
	313	/*
	314	* RX Hash flags, these flags allows to set which incoming packet's field should
	315	* participates in RX Hash. Each flag represent certain packet's field,
	316	* when the flag is set the field that is represented by the flag will
	317	* participate in RX Hash calculation.
	318	* Note: IPV4 and IPV6 flags can't be enabled together on the same QP
	319	* and TCP and UDP flags can't be enabled together on the same QP.
	320	*/
	321	enum mlx5_rx_hash_fields {
	322	MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
	323	MLX5_RX_HASH_DST_IPV4 = 1 << 1,
	324	MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
	325	MLX5_RX_HASH_DST_IPV6 = 1 << 3,
	326	MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
	327	MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
	328	MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
309fa347	329	MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
2d93fc85	330	MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
309fa347	331	/* Save bits for future fields */
4e2b53a5	332	MLX5_RX_HASH_INNER = (1UL << 31),
28d61370 YH	333	};
	334
	335	struct mlx5_ib_create_qp_rss {
26b99066	336	__aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
28d61370 YH	337	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	338	__u8 rx_key_len; /* valid only for Toeplitz */
	339	__u8 reserved[6];
	340	__u8 rx_hash_key[128]; /* valid only for Toeplitz */
	341	__u32 comp_mask;
f95ef6cb	342	__u32 flags;
28d61370 YH	343	};
28d61370 YH	344
e126ba97	345	struct mlx5_ib_create_qp_resp {
2f5ff264	346	__u32 bfreg_index;
41d902cb	347	__u32 reserved;
e126ba97	348	};
cfb5e088	349
d2370e0a MB	350	struct mlx5_ib_alloc_mw {
	351	__u32 comp_mask;
	352	__u8 num_klms;
	353	__u8 reserved1;
	354	__u16 reserved2;
	355	};
	356
ccc87087 NO	357	enum mlx5_ib_create_wq_mask {
	358	MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
	359	};
	360
79b20a6c	361	struct mlx5_ib_create_wq {
26b99066 JG	362	__aligned_u64 buf_addr;
26b99066 JG	363	__aligned_u64 db_addr;
79b20a6c YH	364	__u32 rq_wqe_count;
	365	__u32 rq_wqe_shift;
	366	__u32 user_index;
	367	__u32 flags;
	368	__u32 comp_mask;
ccc87087 NO	369	__u32 single_stride_log_num_of_bytes;
	370	__u32 single_wqe_log_num_of_strides;
	371	__u32 two_byte_shift_en;
79b20a6c YH	372	};
79b20a6c YH	373
5097e71f MS	374	struct mlx5_ib_create_ah_resp {
	375	__u32 response_length;
	376	__u8 dmac[ETH_ALEN];
	377	__u8 reserved[6];
	378	};
	379
61147f39 BW	380	struct mlx5_ib_burst_info {
	381	__u32 max_burst_sz;
	382	__u16 typical_pkt_sz;
	383	__u16 reserved;
	384	};
	385
	386	struct mlx5_ib_modify_qp {
	387	__u32 comp_mask;
	388	struct mlx5_ib_burst_info burst_info;
	389	__u32 reserved;
	390	};
	391
776a3906 MS	392	struct mlx5_ib_modify_qp_resp {
	393	__u32 response_length;
	394	__u32 dctn;
	395	};
	396
79b20a6c YH	397	struct mlx5_ib_create_wq_resp {
	398	__u32 response_length;
	399	__u32 reserved;
	400	};
	401
c5f90929 YH	402	struct mlx5_ib_create_rwq_ind_tbl_resp {
	403	__u32 response_length;
	404	__u32 reserved;
	405	};
	406
79b20a6c YH	407	struct mlx5_ib_modify_wq {
	408	__u32 comp_mask;
	409	__u32 reserved;
	410	};
24d33d2c FD	411
	412	struct mlx5_ib_clock_info {
	413	__u32 sign;
	414	__u32 resv;
26b99066 JG	415	__aligned_u64 nsec;
	416	__aligned_u64 cycles;
	417	__aligned_u64 frac;
24d33d2c FD	418	__u32 mult;
24d33d2c FD	419	__u32 shift;
26b99066 JG	420	__aligned_u64 mask;
26b99066 JG	421	__aligned_u64 overflow_period;
24d33d2c FD	422	};
24d33d2c FD	423
5c99eaec FD	424	enum mlx5_ib_mmap_cmd {
	425	MLX5_IB_MMAP_REGULAR_PAGE = 0,
	426	MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
	427	MLX5_IB_MMAP_WC_PAGE = 2,
	428	MLX5_IB_MMAP_NC_PAGE = 3,
	429	/* 5 is chosen in order to be compatible with old versions of libmlx5 */
	430	MLX5_IB_MMAP_CORE_CLOCK = 5,
	431	MLX5_IB_MMAP_ALLOC_WC = 6,
	432	MLX5_IB_MMAP_CLOCK_INFO = 7,
24da0016	433	MLX5_IB_MMAP_DEVICE_MEM = 8,
5c99eaec FD	434	};
5c99eaec FD	435
24d33d2c FD	436	enum {
	437	MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
	438	};
5c99eaec FD	439
	440	/* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
	441	enum {
	442	MLX5_IB_CLOCK_INFO_V1 = 0,
	443	};
3085e29e	444	#endif /* MLX5_ABI_USER_H */