[linux-2.6-block.git] / include / uapi / rdma / mlx5-abi.h

/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX5_ABI_USER_H
#define MLX5_ABI_USER_H

#include <linux/types.h>
#include <linux/if_ether.h>	/* For ETH_ALEN. */

enum {
	MLX5_QP_FLAG_SIGNATURE		= 1 << 0,
	MLX5_QP_FLAG_SCATTER_CQE	= 1 << 1,
	MLX5_QP_FLAG_TUNNEL_OFFLOADS	= 1 << 2,
};

enum {
	MLX5_SRQ_FLAG_SIGNATURE		= 1 << 0,
};

enum {
	MLX5_WQ_FLAG_SIGNATURE		= 1 << 0,
};

/* Increment this value if any changes that break userspace ABI
 * compatibility are made.
 */
#define MLX5_IB_UVERBS_ABI_VERSION	1

/* Make sure that all structs defined in this file remain laid out so
 * that they pack the same way on 32-bit and 64-bit architectures (to
 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
 * In particular do not use pointer types -- pass pointers in __u64
 * instead.
 */

struct mlx5_ib_alloc_ucontext_req {
	__u32	total_num_bfregs;
	__u32	num_low_latency_bfregs;
};

enum mlx5_lib_caps {
	MLX5_LIB_CAP_4K_UAR	= (__u64)1 << 0,
};

struct mlx5_ib_alloc_ucontext_req_v2 {
	__u32	total_num_bfregs;
	__u32	num_low_latency_bfregs;
	__u32	flags;
	__u32	comp_mask;
	__u8	max_cqe_version;
	__u8	reserved0;
	__u16	reserved1;
	__u32	reserved2;
	__u64	lib_caps;
};

enum mlx5_ib_alloc_ucontext_resp_mask {
	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
};

enum mlx5_user_cmds_supp_uhw {
	MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
	MLX5_USER_CMDS_SUPP_UHW_CREATE_AH    = 1 << 1,
};

/* The eth_min_inline response value is set to off-by-one vs the FW
 * returned value to allow user-space to deal with older kernels.
 */
enum mlx5_user_inline_mode {
	MLX5_USER_INLINE_MODE_NA,
	MLX5_USER_INLINE_MODE_NONE,
	MLX5_USER_INLINE_MODE_L2,
	MLX5_USER_INLINE_MODE_IP,
	MLX5_USER_INLINE_MODE_TCP_UDP,
};

struct mlx5_ib_alloc_ucontext_resp {
	__u32	qp_tab_size;
	__u32	bf_reg_size;
	__u32	tot_bfregs;
	__u32	cache_line_size;
	__u16	max_sq_desc_sz;
	__u16	max_rq_desc_sz;
	__u32	max_send_wqebb;
	__u32	max_recv_wr;
	__u32	max_srq_recv_wr;
	__u16	num_ports;
	__u16	reserved1;
	__u32	comp_mask;
	__u32	response_length;
	__u8	cqe_version;
	__u8	cmds_supp_uhw;
	__u8	eth_min_inline;
	__u8	reserved2;
	__u64	hca_core_clock_offset;
	__u32	log_uar_size;
	__u32	num_uars_per_page;
	__u32	num_dyn_bfregs;
	__u32	reserved3;
};

struct mlx5_ib_alloc_pd_resp {
	__u32	pdn;
};

struct mlx5_ib_tso_caps {
	__u32 max_tso; /* Maximum tso payload size in bytes */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_UD
	 */
	__u32 supported_qpts;
};

struct mlx5_ib_rss_caps {
	__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	__u8 reserved[7];
};

enum mlx5_ib_cqe_comp_res_format {
	MLX5_IB_CQE_RES_FORMAT_HASH	= 1 << 0,
	MLX5_IB_CQE_RES_FORMAT_CSUM	= 1 << 1,
	MLX5_IB_CQE_RES_RESERVED	= 1 << 2,
};

struct mlx5_ib_cqe_comp_caps {
	__u32 max_num;
	__u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
};

struct mlx5_packet_pacing_caps {
	__u32 qp_rate_limit_min;
	__u32 qp_rate_limit_max; /* In kpbs */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
	 */
	__u32 supported_qpts;
	__u32 reserved;
};

enum mlx5_ib_mpw_caps {
	MPW_RESERVED		= 1 << 0,
	MLX5_IB_ALLOW_MPW	= 1 << 1,
	MLX5_IB_SUPPORT_EMPW	= 1 << 2,
};

enum mlx5_ib_sw_parsing_offloads {
	MLX5_IB_SW_PARSING = 1 << 0,
	MLX5_IB_SW_PARSING_CSUM = 1 << 1,
	MLX5_IB_SW_PARSING_LSO = 1 << 2,
};

struct mlx5_ib_sw_parsing_caps {
	__u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
	 */
	__u32 supported_qpts;
};

struct mlx5_ib_striding_rq_caps {
	__u32 min_single_stride_log_num_of_bytes;
	__u32 max_single_stride_log_num_of_bytes;
	__u32 min_single_wqe_log_num_of_strides;
	__u32 max_single_wqe_log_num_of_strides;

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
	 */
	__u32 supported_qpts;
	__u32 reserved;
};

enum mlx5_ib_query_dev_resp_flags {
	/* Support 128B CQE compression */
	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD  = 1 << 1,
};

enum mlx5_ib_tunnel_offloads {
	MLX5_IB_TUNNELED_OFFLOADS_VXLAN  = 1 << 0,
	MLX5_IB_TUNNELED_OFFLOADS_GRE    = 1 << 1,
	MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2
};

struct mlx5_ib_query_device_resp {
	__u32	comp_mask;
	__u32	response_length;
	struct	mlx5_ib_tso_caps tso_caps;
	struct	mlx5_ib_rss_caps rss_caps;
	struct	mlx5_ib_cqe_comp_caps cqe_comp_caps;
	struct	mlx5_packet_pacing_caps packet_pacing_caps;
	__u32	mlx5_ib_support_multi_pkt_send_wqes;
	__u32	flags; /* Use enum mlx5_ib_query_dev_resp_flags */
	struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
	struct mlx5_ib_striding_rq_caps striding_rq_caps;
	__u32	tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
	__u32	reserved;
};

enum mlx5_ib_create_cq_flags {
	MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD	= 1 << 0,
};

struct mlx5_ib_create_cq {
	__u64	buf_addr;
	__u64	db_addr;
	__u32	cqe_size;
	__u8    cqe_comp_en;
	__u8    cqe_comp_res_format;
	__u16	flags;
};

struct mlx5_ib_create_cq_resp {
	__u32	cqn;
	__u32	reserved;
};

struct mlx5_ib_resize_cq {
	__u64	buf_addr;
	__u16	cqe_size;
	__u16	reserved0;
	__u32	reserved1;
};

struct mlx5_ib_create_srq {
	__u64	buf_addr;
	__u64	db_addr;
	__u32	flags;
	__u32	reserved0; /* explicit padding (optional on i386) */
	__u32	uidx;
	__u32	reserved1;
};

struct mlx5_ib_create_srq_resp {
	__u32	srqn;
	__u32	reserved;
};

struct mlx5_ib_create_qp {
	__u64	buf_addr;
	__u64	db_addr;
	__u32	sq_wqe_count;
	__u32	rq_wqe_count;
	__u32	rq_wqe_shift;
	__u32	flags;
	__u32	uidx;
	__u32	reserved0;
	__u64	sq_buf_addr;
};

/* RX Hash function flags */
enum mlx5_rx_hash_function_flags {
	MLX5_RX_HASH_FUNC_TOEPLITZ	= 1 << 0,
};

/*
 * RX Hash flags, these flags allows to set which incoming packet's field should
 * participates in RX Hash. Each flag represent certain packet's field,
 * when the flag is set the field that is represented by the flag will
 * participate in RX Hash calculation.
 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
 * and *TCP and *UDP flags can't be enabled together on the same QP.
*/
enum mlx5_rx_hash_fields {
	MLX5_RX_HASH_SRC_IPV4	= 1 << 0,
	MLX5_RX_HASH_DST_IPV4	= 1 << 1,
	MLX5_RX_HASH_SRC_IPV6	= 1 << 2,
	MLX5_RX_HASH_DST_IPV6	= 1 << 3,
	MLX5_RX_HASH_SRC_PORT_TCP	= 1 << 4,
	MLX5_RX_HASH_DST_PORT_TCP	= 1 << 5,
	MLX5_RX_HASH_SRC_PORT_UDP	= 1 << 6,
	MLX5_RX_HASH_DST_PORT_UDP	= 1 << 7,
	/* Save bits for future fields */
	MLX5_RX_HASH_INNER		= (1UL << 31),
};

struct mlx5_ib_create_qp_rss {
	__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	__u8 rx_key_len; /* valid only for Toeplitz */
	__u8 reserved[6];
	__u8 rx_hash_key[128]; /* valid only for Toeplitz */
	__u32   comp_mask;
	__u32	flags;
};

struct mlx5_ib_create_qp_resp {
	__u32	bfreg_index;
};

struct mlx5_ib_alloc_mw {
	__u32	comp_mask;
	__u8	num_klms;
	__u8	reserved1;
	__u16	reserved2;
};

enum mlx5_ib_create_wq_mask {
	MLX5_IB_CREATE_WQ_STRIDING_RQ	= (1 << 0),
};

struct mlx5_ib_create_wq {
	__u64   buf_addr;
	__u64   db_addr;
	__u32   rq_wqe_count;
	__u32   rq_wqe_shift;
	__u32   user_index;
	__u32   flags;
	__u32   comp_mask;
	__u32	single_stride_log_num_of_bytes;
	__u32	single_wqe_log_num_of_strides;
	__u32	two_byte_shift_en;
};

struct mlx5_ib_create_ah_resp {
	__u32	response_length;
	__u8	dmac[ETH_ALEN];
	__u8	reserved[6];
};

struct mlx5_ib_create_wq_resp {
	__u32	response_length;
	__u32	reserved;
};

struct mlx5_ib_create_rwq_ind_tbl_resp {
	__u32	response_length;
	__u32	reserved;
};

struct mlx5_ib_modify_wq {
	__u32	comp_mask;
	__u32	reserved;
};
#endif /* MLX5_ABI_USER_H */
Commit	Line	Data
e2be04c7	1	/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
e126ba97	2	/*
6cf0a15f	3	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenIB.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*/
	33
3085e29e LR	34	#ifndef MLX5_ABI_USER_H
3085e29e LR	35	#define MLX5_ABI_USER_H
e126ba97 EC	36
e126ba97 EC	37	#include <linux/types.h>
812755d6	38	#include <linux/if_ether.h> /* For ETH_ALEN. */
e126ba97 EC	39
	40	enum {
	41	MLX5_QP_FLAG_SIGNATURE = 1 << 0,
	42	MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
f95ef6cb	43	MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
e126ba97 EC	44	};
	45
	46	enum {
	47	MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
	48	};
	49
79b20a6c YH	50	enum {
	51	MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
	52	};
	53
e126ba97 EC	54	/* Increment this value if any changes that break userspace ABI
	55	* compatibility are made.
	56	*/
	57	#define MLX5_IB_UVERBS_ABI_VERSION 1
	58
	59	/* Make sure that all structs defined in this file remain laid out so
	60	* that they pack the same way on 32-bit and 64-bit architectures (to
	61	* avoid incompatibility between 32-bit userspace and 64-bit kernels).
	62	* In particular do not use pointer types -- pass pointers in __u64
	63	* instead.
	64	*/
	65
	66	struct mlx5_ib_alloc_ucontext_req {
2f5ff264 EC	67	__u32 total_num_bfregs;
2f5ff264 EC	68	__u32 num_low_latency_bfregs;
e126ba97 EC	69	};
e126ba97 EC	70
30aa60b3	71	enum mlx5_lib_caps {
812755d6	72	MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
30aa60b3 EC	73	};
30aa60b3 EC	74
78c0f98c	75	struct mlx5_ib_alloc_ucontext_req_v2 {
2f5ff264 EC	76	__u32 total_num_bfregs;
2f5ff264 EC	77	__u32 num_low_latency_bfregs;
78c0f98c	78	__u32 flags;
b368d7cb	79	__u32 comp_mask;
f72300c5 HA	80	__u8 max_cqe_version;
	81	__u8 reserved0;
	82	__u16 reserved1;
	83	__u32 reserved2;
30aa60b3	84	__u64 lib_caps;
b368d7cb MB	85	};
	86
	87	enum mlx5_ib_alloc_ucontext_resp_mask {
	88	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
78c0f98c EC	89	};
78c0f98c EC	90
402ca536 BW	91	enum mlx5_user_cmds_supp_uhw {
402ca536 BW	92	MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
6ad279c5	93	MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
402ca536 BW	94	};
402ca536 BW	95
78984898 OG	96	/* The eth_min_inline response value is set to off-by-one vs the FW
	97	* returned value to allow user-space to deal with older kernels.
	98	*/
	99	enum mlx5_user_inline_mode {
	100	MLX5_USER_INLINE_MODE_NA,
	101	MLX5_USER_INLINE_MODE_NONE,
	102	MLX5_USER_INLINE_MODE_L2,
	103	MLX5_USER_INLINE_MODE_IP,
	104	MLX5_USER_INLINE_MODE_TCP_UDP,
	105	};
	106
e126ba97 EC	107	struct mlx5_ib_alloc_ucontext_resp {
	108	__u32 qp_tab_size;
	109	__u32 bf_reg_size;
2f5ff264	110	__u32 tot_bfregs;
e126ba97 EC	111	__u32 cache_line_size;
	112	__u16 max_sq_desc_sz;
	113	__u16 max_rq_desc_sz;
	114	__u32 max_send_wqebb;
	115	__u32 max_recv_wr;
	116	__u32 max_srq_recv_wr;
	117	__u16 num_ports;
b368d7cb MB	118	__u16 reserved1;
	119	__u32 comp_mask;
	120	__u32 response_length;
f72300c5	121	__u8 cqe_version;
402ca536	122	__u8 cmds_supp_uhw;
78984898 OG	123	__u8 eth_min_inline;
78984898 OG	124	__u8 reserved2;
b368d7cb	125	__u64 hca_core_clock_offset;
30aa60b3 EC	126	__u32 log_uar_size;
30aa60b3 EC	127	__u32 num_uars_per_page;
31a78a5a YH	128	__u32 num_dyn_bfregs;
31a78a5a YH	129	__u32 reserved3;
e126ba97 EC	130	};
	131
	132	struct mlx5_ib_alloc_pd_resp {
	133	__u32 pdn;
	134	};
	135
402ca536 BW	136	struct mlx5_ib_tso_caps {
	137	__u32 max_tso; /* Maximum tso payload size in bytes */
	138
	139	/* Corresponding bit will be set if qp type from
	140	* 'enum ib_qp_type' is supported, e.g.
	141	* supported_qpts \|= 1 << IB_QPT_UD
	142	*/
	143	__u32 supported_qpts;
	144	};
	145
31f69a82 YH	146	struct mlx5_ib_rss_caps {
	147	__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	148	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	149	__u8 reserved[7];
	150	};
	151
7e43a2a5 BW	152	enum mlx5_ib_cqe_comp_res_format {
	153	MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
	154	MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
	155	MLX5_IB_CQE_RES_RESERVED = 1 << 2,
	156	};
	157
	158	struct mlx5_ib_cqe_comp_caps {
	159	__u32 max_num;
	160	__u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
	161	};
	162
d949167d BW	163	struct mlx5_packet_pacing_caps {
	164	__u32 qp_rate_limit_min;
	165	__u32 qp_rate_limit_max; /* In kpbs */
	166
	167	/* Corresponding bit will be set if qp type from
	168	* 'enum ib_qp_type' is supported, e.g.
	169	* supported_qpts \|= 1 << IB_QPT_RAW_PACKET
	170	*/
	171	__u32 supported_qpts;
	172	__u32 reserved;
	173	};
	174
795b609c BW	175	enum mlx5_ib_mpw_caps {
	176	MPW_RESERVED = 1 << 0,
	177	MLX5_IB_ALLOW_MPW = 1 << 1,
050da902	178	MLX5_IB_SUPPORT_EMPW = 1 << 2,
795b609c BW	179	};
795b609c BW	180
96dc3fc5 NO	181	enum mlx5_ib_sw_parsing_offloads {
	182	MLX5_IB_SW_PARSING = 1 << 0,
	183	MLX5_IB_SW_PARSING_CSUM = 1 << 1,
	184	MLX5_IB_SW_PARSING_LSO = 1 << 2,
	185	};
	186
	187	struct mlx5_ib_sw_parsing_caps {
	188	__u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
	189
	190	/* Corresponding bit will be set if qp type from
	191	* 'enum ib_qp_type' is supported, e.g.
	192	* supported_qpts \|= 1 << IB_QPT_RAW_PACKET
	193	*/
	194	__u32 supported_qpts;
	195	};
	196
b4f34597 NO	197	struct mlx5_ib_striding_rq_caps {
	198	__u32 min_single_stride_log_num_of_bytes;
	199	__u32 max_single_stride_log_num_of_bytes;
	200	__u32 min_single_wqe_log_num_of_strides;
	201	__u32 max_single_wqe_log_num_of_strides;
	202
	203	/* Corresponding bit will be set if qp type from
	204	* 'enum ib_qp_type' is supported, e.g.
	205	* supported_qpts \|= 1 << IB_QPT_RAW_PACKET
	206	*/
	207	__u32 supported_qpts;
f17966f1	208	__u32 reserved;
b4f34597 NO	209	};
b4f34597 NO	210
de57f2ad GL	211	enum mlx5_ib_query_dev_resp_flags {
	212	/* Support 128B CQE compression */
	213	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
7a0c8f42	214	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
de57f2ad GL	215	};
de57f2ad GL	216
f95ef6cb MG	217	enum mlx5_ib_tunnel_offloads {
	218	MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
	219	MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
	220	MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2
	221	};
	222
402ca536 BW	223	struct mlx5_ib_query_device_resp {
	224	__u32 comp_mask;
	225	__u32 response_length;
	226	struct mlx5_ib_tso_caps tso_caps;
31f69a82	227	struct mlx5_ib_rss_caps rss_caps;
7e43a2a5	228	struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
d949167d	229	struct mlx5_packet_pacing_caps packet_pacing_caps;
191ded4a	230	__u32 mlx5_ib_support_multi_pkt_send_wqes;
de57f2ad	231	__u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
96dc3fc5	232	struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
b4f34597	233	struct mlx5_ib_striding_rq_caps striding_rq_caps;
f95ef6cb MG	234	__u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
f95ef6cb MG	235	__u32 reserved;
402ca536 BW	236	};
402ca536 BW	237
7a0c8f42 GL	238	enum mlx5_ib_create_cq_flags {
7a0c8f42 GL	239	MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
402ca536 BW	240	};
402ca536 BW	241
e126ba97 EC	242	struct mlx5_ib_create_cq {
	243	__u64 buf_addr;
	244	__u64 db_addr;
	245	__u32 cqe_size;
1cbe6fc8 BW	246	__u8 cqe_comp_en;
1cbe6fc8 BW	247	__u8 cqe_comp_res_format;
7a0c8f42	248	__u16 flags;
e126ba97 EC	249	};
	250
	251	struct mlx5_ib_create_cq_resp {
	252	__u32 cqn;
	253	__u32 reserved;
	254	};
	255
	256	struct mlx5_ib_resize_cq {
	257	__u64 buf_addr;
bde51583 EC	258	__u16 cqe_size;
	259	__u16 reserved0;
	260	__u32 reserved1;
e126ba97 EC	261	};
	262
	263	struct mlx5_ib_create_srq {
	264	__u64 buf_addr;
	265	__u64 db_addr;
	266	__u32 flags;
cfb5e088 HA	267	__u32 reserved0; /* explicit padding (optional on i386) */
	268	__u32 uidx;
	269	__u32 reserved1;
e126ba97 EC	270	};
	271
	272	struct mlx5_ib_create_srq_resp {
	273	__u32 srqn;
	274	__u32 reserved;
	275	};
	276
	277	struct mlx5_ib_create_qp {
	278	__u64 buf_addr;
	279	__u64 db_addr;
	280	__u32 sq_wqe_count;
	281	__u32 rq_wqe_count;
	282	__u32 rq_wqe_shift;
	283	__u32 flags;
cfb5e088 HA	284	__u32 uidx;
cfb5e088 HA	285	__u32 reserved0;
0fb2ed66	286	__u64 sq_buf_addr;
e126ba97 EC	287	};
e126ba97 EC	288
28d61370 YH	289	/* RX Hash function flags */
	290	enum mlx5_rx_hash_function_flags {
	291	MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
	292	};
	293
	294	/*
	295	* RX Hash flags, these flags allows to set which incoming packet's field should
	296	* participates in RX Hash. Each flag represent certain packet's field,
	297	* when the flag is set the field that is represented by the flag will
	298	* participate in RX Hash calculation.
	299	* Note: IPV4 and IPV6 flags can't be enabled together on the same QP
	300	* and TCP and UDP flags can't be enabled together on the same QP.
	301	*/
	302	enum mlx5_rx_hash_fields {
	303	MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
	304	MLX5_RX_HASH_DST_IPV4 = 1 << 1,
	305	MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
	306	MLX5_RX_HASH_DST_IPV6 = 1 << 3,
	307	MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
	308	MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
	309	MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
309fa347 MG	310	MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
309fa347 MG	311	/* Save bits for future fields */
4e2b53a5	312	MLX5_RX_HASH_INNER = (1UL << 31),
28d61370 YH	313	};
	314
	315	struct mlx5_ib_create_qp_rss {
	316	__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	317	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	318	__u8 rx_key_len; /* valid only for Toeplitz */
	319	__u8 reserved[6];
	320	__u8 rx_hash_key[128]; /* valid only for Toeplitz */
	321	__u32 comp_mask;
f95ef6cb	322	__u32 flags;
28d61370 YH	323	};
28d61370 YH	324
e126ba97	325	struct mlx5_ib_create_qp_resp {
2f5ff264	326	__u32 bfreg_index;
e126ba97	327	};
cfb5e088	328
d2370e0a MB	329	struct mlx5_ib_alloc_mw {
	330	__u32 comp_mask;
	331	__u8 num_klms;
	332	__u8 reserved1;
	333	__u16 reserved2;
	334	};
	335
ccc87087 NO	336	enum mlx5_ib_create_wq_mask {
	337	MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
	338	};
	339
79b20a6c YH	340	struct mlx5_ib_create_wq {
	341	__u64 buf_addr;
	342	__u64 db_addr;
	343	__u32 rq_wqe_count;
	344	__u32 rq_wqe_shift;
	345	__u32 user_index;
	346	__u32 flags;
	347	__u32 comp_mask;
ccc87087 NO	348	__u32 single_stride_log_num_of_bytes;
	349	__u32 single_wqe_log_num_of_strides;
	350	__u32 two_byte_shift_en;
79b20a6c YH	351	};
79b20a6c YH	352
5097e71f MS	353	struct mlx5_ib_create_ah_resp {
	354	__u32 response_length;
	355	__u8 dmac[ETH_ALEN];
	356	__u8 reserved[6];
	357	};
	358
79b20a6c YH	359	struct mlx5_ib_create_wq_resp {
	360	__u32 response_length;
	361	__u32 reserved;
	362	};
	363
c5f90929 YH	364	struct mlx5_ib_create_rwq_ind_tbl_resp {
	365	__u32 response_length;
	366	__u32 reserved;
	367	};
	368
79b20a6c YH	369	struct mlx5_ib_modify_wq {
	370	__u32 comp_mask;
	371	__u32 reserved;
	372	};
3085e29e	373	#endif /* MLX5_ABI_USER_H */