[linux-2.6-block.git] / include / uapi / rdma / mlx4-abi.h

/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
/*
 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_ABI_USER_H
#define MLX4_ABI_USER_H

#include <linux/types.h>

/*
 * Increment this value if any changes that break userspace ABI
 * compatibility are made.
 */

#define MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION	3
#define MLX4_IB_UVERBS_ABI_VERSION		4

/*
 * Make sure that all structs defined in this file remain laid out so
 * that they pack the same way on 32-bit and 64-bit architectures (to
 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
 * In particular do not use pointer types -- pass pointers in __u64
 * instead.
 */

struct mlx4_ib_alloc_ucontext_resp_v3 {
	__u32	qp_tab_size;
	__u16	bf_reg_size;
	__u16	bf_regs_per_page;
};

enum {
	MLX4_USER_DEV_CAP_LARGE_CQE	= 1L << 0,
};

struct mlx4_ib_alloc_ucontext_resp {
	__u32	dev_caps;
	__u32	qp_tab_size;
	__u16	bf_reg_size;
	__u16	bf_regs_per_page;
	__u32	cqe_size;
};

struct mlx4_ib_alloc_pd_resp {
	__u32	pdn;
	__u32	reserved;
};

struct mlx4_ib_create_cq {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
};

struct mlx4_ib_create_cq_resp {
	__u32	cqn;
	__u32	reserved;
};

struct mlx4_ib_resize_cq {
	__aligned_u64 buf_addr;
};

struct mlx4_ib_create_srq {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
};

struct mlx4_ib_create_srq_resp {
	__u32	srqn;
	__u32	reserved;
};

struct mlx4_ib_create_qp_rss {
	__aligned_u64 rx_hash_fields_mask; /* Use  enum mlx4_ib_rx_hash_fields */
	__u8    rx_hash_function; /* Use enum mlx4_ib_rx_hash_function_flags */
	__u8    reserved[7];
	__u8    rx_hash_key[40];
	__u32   comp_mask;
	__u32   reserved1;
};

struct mlx4_ib_create_qp {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
	__u8	log_sq_bb_count;
	__u8	log_sq_stride;
	__u8	sq_no_prefetch;
	__u8	reserved;
	__u32	inl_recv_sz;
};

struct mlx4_ib_create_wq {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
	__u8	log_range_size;
	__u8	reserved[3];
	__u32   comp_mask;
};

struct mlx4_ib_modify_wq {
	__u32	comp_mask;
	__u32	reserved;
};

struct mlx4_ib_create_rwq_ind_tbl_resp {
	__u32	response_length;
	__u32	reserved;
};

/* RX Hash function flags */
enum mlx4_ib_rx_hash_function_flags {
	MLX4_IB_RX_HASH_FUNC_TOEPLITZ	= 1 << 0,
};

/*
 * RX Hash flags, these flags allows to set which incoming packet's field should
 * participates in RX Hash. Each flag represent certain packet's field,
 * when the flag is set the field that is represented by the flag will
 * participate in RX Hash calculation.
 */
enum mlx4_ib_rx_hash_fields {
	MLX4_IB_RX_HASH_SRC_IPV4	= 1 << 0,
	MLX4_IB_RX_HASH_DST_IPV4	= 1 << 1,
	MLX4_IB_RX_HASH_SRC_IPV6	= 1 << 2,
	MLX4_IB_RX_HASH_DST_IPV6	= 1 << 3,
	MLX4_IB_RX_HASH_SRC_PORT_TCP	= 1 << 4,
	MLX4_IB_RX_HASH_DST_PORT_TCP	= 1 << 5,
	MLX4_IB_RX_HASH_SRC_PORT_UDP	= 1 << 6,
	MLX4_IB_RX_HASH_DST_PORT_UDP	= 1 << 7,
	MLX4_IB_RX_HASH_INNER		= 1ULL << 31,
};

struct mlx4_ib_rss_caps {
	__aligned_u64 rx_hash_fields_mask; /* enum mlx4_ib_rx_hash_fields */
	__u8 rx_hash_function; /* enum mlx4_ib_rx_hash_function_flags */
	__u8 reserved[7];
};

enum query_device_resp_mask {
	MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
};

struct mlx4_ib_tso_caps {
	__u32 max_tso; /* Maximum tso payload size in bytes */
	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported.
	 */
	__u32 supported_qpts;
};

struct mlx4_uverbs_ex_query_device_resp {
	__u32			comp_mask;
	__u32			response_length;
	__aligned_u64		hca_core_clock_offset;
	__u32			max_inl_recv_sz;
	__u32			reserved;
	struct mlx4_ib_rss_caps	rss_caps;
	struct mlx4_ib_tso_caps tso_caps;
};

#endif /* MLX4_ABI_USER_H */
Commit	Line	Data
d50e14ab	1	/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
225c7b1f RD	2	/*
225c7b1f RD	3	* Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0	4	* Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f RD	5	*
	6	* This software is available to you under a choice of one of two
	7	* licenses. You may choose to be licensed under the terms of the GNU
	8	* General Public License (GPL) Version 2, available from the file
	9	* COPYING in the main directory of this source tree, or the
	10	* OpenIB.org BSD license below:
	11	*
	12	* Redistribution and use in source and binary forms, with or
	13	* without modification, are permitted provided that the following
	14	* conditions are met:
	15	*
	16	* - Redistributions of source code must retain the above
	17	* copyright notice, this list of conditions and the following
	18	* disclaimer.
	19	*
	20	* - Redistributions in binary form must reproduce the above
	21	* copyright notice, this list of conditions and the following
	22	* disclaimer in the documentation and/or other materials
	23	* provided with the distribution.
	24	*
	25	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	26	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	27	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	28	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	29	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	30	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	31	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	32	* SOFTWARE.
	33	*/
	34
9ce28a20 LR	35	#ifndef MLX4_ABI_USER_H
9ce28a20 LR	36	#define MLX4_ABI_USER_H
225c7b1f RD	37
	38	#include <linux/types.h>
	39
	40	/*
	41	* Increment this value if any changes that break userspace ABI
	42	* compatibility are made.
	43	*/
08ff3235 OG	44
	45	#define MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION 3
	46	#define MLX4_IB_UVERBS_ABI_VERSION 4
225c7b1f RD	47
	48	/*
	49	* Make sure that all structs defined in this file remain laid out so
	50	* that they pack the same way on 32-bit and 64-bit architectures (to
	51	* avoid incompatibility between 32-bit userspace and 64-bit kernels).
	52	* In particular do not use pointer types -- pass pointers in __u64
	53	* instead.
	54	*/
	55
08ff3235 OG	56	struct mlx4_ib_alloc_ucontext_resp_v3 {
	57	__u32 qp_tab_size;
	58	__u16 bf_reg_size;
	59	__u16 bf_regs_per_page;
	60	};
	61
48962f5c JG	62	enum {
	63	MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0,
	64	};
	65
225c7b1f	66	struct mlx4_ib_alloc_ucontext_resp {
08ff3235	67	__u32 dev_caps;
225c7b1f RD	68	__u32 qp_tab_size;
	69	__u16 bf_reg_size;
	70	__u16 bf_regs_per_page;
08ff3235	71	__u32 cqe_size;
225c7b1f RD	72	};
	73
	74	struct mlx4_ib_alloc_pd_resp {
	75	__u32 pdn;
	76	__u32 reserved;
	77	};
	78
	79	struct mlx4_ib_create_cq {
26b99066 JG	80	__aligned_u64 buf_addr;
26b99066 JG	81	__aligned_u64 db_addr;
225c7b1f RD	82	};
	83
	84	struct mlx4_ib_create_cq_resp {
	85	__u32 cqn;
	86	__u32 reserved;
	87	};
	88
	89	struct mlx4_ib_resize_cq {
26b99066	90	__aligned_u64 buf_addr;
225c7b1f RD	91	};
	92
	93	struct mlx4_ib_create_srq {
26b99066 JG	94	__aligned_u64 buf_addr;
26b99066 JG	95	__aligned_u64 db_addr;
225c7b1f RD	96	};
	97
	98	struct mlx4_ib_create_srq_resp {
	99	__u32 srqn;
	100	__u32 reserved;
	101	};
	102
3078f5f1	103	struct mlx4_ib_create_qp_rss {
26b99066	104	__aligned_u64 rx_hash_fields_mask; /* Use enum mlx4_ib_rx_hash_fields */
07d84f7b	105	__u8 rx_hash_function; /* Use enum mlx4_ib_rx_hash_function_flags */
b23673f8	106	__u8 reserved[7];
3078f5f1 GL	107	__u8 rx_hash_key[40];
	108	__u32 comp_mask;
	109	__u32 reserved1;
	110	};
	111
225c7b1f	112	struct mlx4_ib_create_qp {
26b99066 JG	113	__aligned_u64 buf_addr;
26b99066 JG	114	__aligned_u64 db_addr;
0e6e7416 RD	115	__u8 log_sq_bb_count;
	116	__u8 log_sq_stride;
	117	__u8 sq_no_prefetch;
ea30b966	118	__u8 reserved;
55f2467c	119	__u32 inl_recv_sz;
225c7b1f RD	120	};
225c7b1f RD	121
400b1ebc	122	struct mlx4_ib_create_wq {
26b99066 JG	123	__aligned_u64 buf_addr;
26b99066 JG	124	__aligned_u64 db_addr;
400b1ebc GL	125	__u8 log_range_size;
	126	__u8 reserved[3];
	127	__u32 comp_mask;
400b1ebc GL	128	};
	129
	130	struct mlx4_ib_modify_wq {
	131	__u32 comp_mask;
	132	__u32 reserved;
	133	};
	134
b8d46ca0 GL	135	struct mlx4_ib_create_rwq_ind_tbl_resp {
	136	__u32 response_length;
	137	__u32 reserved;
	138	};
3078f5f1 GL	139
	140	/* RX Hash function flags */
	141	enum mlx4_ib_rx_hash_function_flags {
	142	MLX4_IB_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
	143	};
	144
	145	/*
	146	* RX Hash flags, these flags allows to set which incoming packet's field should
	147	* participates in RX Hash. Each flag represent certain packet's field,
	148	* when the flag is set the field that is represented by the flag will
	149	* participate in RX Hash calculation.
	150	*/
	151	enum mlx4_ib_rx_hash_fields {
	152	MLX4_IB_RX_HASH_SRC_IPV4 = 1 << 0,
	153	MLX4_IB_RX_HASH_DST_IPV4 = 1 << 1,
	154	MLX4_IB_RX_HASH_SRC_IPV6 = 1 << 2,
	155	MLX4_IB_RX_HASH_DST_IPV6 = 1 << 3,
	156	MLX4_IB_RX_HASH_SRC_PORT_TCP = 1 << 4,
	157	MLX4_IB_RX_HASH_DST_PORT_TCP = 1 << 5,
	158	MLX4_IB_RX_HASH_SRC_PORT_UDP = 1 << 6,
07d84f7b GL	159	MLX4_IB_RX_HASH_DST_PORT_UDP = 1 << 7,
07d84f7b GL	160	MLX4_IB_RX_HASH_INNER = 1ULL << 31,
3078f5f1 GL	161	};
3078f5f1 GL	162
d50a8a96	163	struct mlx4_ib_rss_caps {
26b99066	164	__aligned_u64 rx_hash_fields_mask; /* enum mlx4_ib_rx_hash_fields */
d50a8a96 YH	165	__u8 rx_hash_function; /* enum mlx4_ib_rx_hash_function_flags */
	166	__u8 reserved[7];
	167	};
	168
48962f5c JG	169	enum query_device_resp_mask {
	170	MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
	171	};
	172
9c71172c YH	173	struct mlx4_ib_tso_caps {
	174	__u32 max_tso; /* Maximum tso payload size in bytes */
	175	/* Corresponding bit will be set if qp type from
	176	* 'enum ib_qp_type' is supported.
	177	*/
	178	__u32 supported_qpts;
	179	};
	180
d50a8a96 YH	181	struct mlx4_uverbs_ex_query_device_resp {
	182	__u32 comp_mask;
	183	__u32 response_length;
26b99066	184	__aligned_u64 hca_core_clock_offset;
d50a8a96	185	__u32 max_inl_recv_sz;
366380a0	186	__u32 reserved;
d50a8a96	187	struct mlx4_ib_rss_caps rss_caps;
9c71172c	188	struct mlx4_ib_tso_caps tso_caps;
d50a8a96 YH	189	};
d50a8a96 YH	190
9ce28a20	191	#endif /* MLX4_ABI_USER_H */