[linux-2.6-block.git] / include / uapi / linux / virtio_gpu.h

/*
 * Virtio GPU Device
 *
 * Copyright Red Hat, Inc. 2013-2014
 *
 * Authors:
 *     Dave Airlie <airlied@redhat.com>
 *     Gerd Hoffmann <kraxel@redhat.com>
 *
 * This header is BSD licensed so anyone can use the definitions
 * to implement compatible drivers/servers:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of IBM nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef VIRTIO_GPU_HW_H
#define VIRTIO_GPU_HW_H

#include <linux/types.h>

#define VIRTIO_GPU_F_VIRGL 0
#define VIRTIO_GPU_F_EDID  1

enum virtio_gpu_ctrl_type {
	VIRTIO_GPU_UNDEFINED = 0,

	/* 2d commands */
	VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
	VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
	VIRTIO_GPU_CMD_RESOURCE_UNREF,
	VIRTIO_GPU_CMD_SET_SCANOUT,
	VIRTIO_GPU_CMD_RESOURCE_FLUSH,
	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
	VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
	VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
	VIRTIO_GPU_CMD_GET_CAPSET_INFO,
	VIRTIO_GPU_CMD_GET_CAPSET,
	VIRTIO_GPU_CMD_GET_EDID,

	/* 3d commands */
	VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
	VIRTIO_GPU_CMD_CTX_DESTROY,
	VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
	VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
	VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
	VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
	VIRTIO_GPU_CMD_SUBMIT_3D,

	/* cursor commands */
	VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
	VIRTIO_GPU_CMD_MOVE_CURSOR,

	/* success responses */
	VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
	VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
	VIRTIO_GPU_RESP_OK_CAPSET_INFO,
	VIRTIO_GPU_RESP_OK_CAPSET,
	VIRTIO_GPU_RESP_OK_EDID,

	/* error responses */
	VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
	VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
	VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
	VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
	VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
	VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
};

#define VIRTIO_GPU_FLAG_FENCE (1 << 0)

struct virtio_gpu_ctrl_hdr {
	__le32 type;
	__le32 flags;
	__le64 fence_id;
	__le32 ctx_id;
	__le32 padding;
};

/* data passed in the cursor vq */

struct virtio_gpu_cursor_pos {
	__le32 scanout_id;
	__le32 x;
	__le32 y;
	__le32 padding;
};

/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
struct virtio_gpu_update_cursor {
	struct virtio_gpu_ctrl_hdr hdr;
	struct virtio_gpu_cursor_pos pos;  /* update & move */
	__le32 resource_id;           /* update only */
	__le32 hot_x;                 /* update only */
	__le32 hot_y;                 /* update only */
	__le32 padding;
};

/* data passed in the control vq, 2d related */

struct virtio_gpu_rect {
	__le32 x;
	__le32 y;
	__le32 width;
	__le32 height;
};

/* VIRTIO_GPU_CMD_RESOURCE_UNREF */
struct virtio_gpu_resource_unref {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 resource_id;
	__le32 padding;
};

/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
struct virtio_gpu_resource_create_2d {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 resource_id;
	__le32 format;
	__le32 width;
	__le32 height;
};

/* VIRTIO_GPU_CMD_SET_SCANOUT */
struct virtio_gpu_set_scanout {
	struct virtio_gpu_ctrl_hdr hdr;
	struct virtio_gpu_rect r;
	__le32 scanout_id;
	__le32 resource_id;
};

/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
struct virtio_gpu_resource_flush {
	struct virtio_gpu_ctrl_hdr hdr;
	struct virtio_gpu_rect r;
	__le32 resource_id;
	__le32 padding;
};

/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
struct virtio_gpu_transfer_to_host_2d {
	struct virtio_gpu_ctrl_hdr hdr;
	struct virtio_gpu_rect r;
	__le64 offset;
	__le32 resource_id;
	__le32 padding;
};

struct virtio_gpu_mem_entry {
	__le64 addr;
	__le32 length;
	__le32 padding;
};

/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
struct virtio_gpu_resource_attach_backing {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 resource_id;
	__le32 nr_entries;
};

/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
struct virtio_gpu_resource_detach_backing {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 resource_id;
	__le32 padding;
};

/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
#define VIRTIO_GPU_MAX_SCANOUTS 16
struct virtio_gpu_resp_display_info {
	struct virtio_gpu_ctrl_hdr hdr;
	struct virtio_gpu_display_one {
		struct virtio_gpu_rect r;
		__le32 enabled;
		__le32 flags;
	} pmodes[VIRTIO_GPU_MAX_SCANOUTS];
};

/* data passed in the control vq, 3d related */

struct virtio_gpu_box {
	__le32 x, y, z;
	__le32 w, h, d;
};

/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
struct virtio_gpu_transfer_host_3d {
	struct virtio_gpu_ctrl_hdr hdr;
	struct virtio_gpu_box box;
	__le64 offset;
	__le32 resource_id;
	__le32 level;
	__le32 stride;
	__le32 layer_stride;
};

/* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
struct virtio_gpu_resource_create_3d {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 resource_id;
	__le32 target;
	__le32 format;
	__le32 bind;
	__le32 width;
	__le32 height;
	__le32 depth;
	__le32 array_size;
	__le32 last_level;
	__le32 nr_samples;
	__le32 flags;
	__le32 padding;
};

/* VIRTIO_GPU_CMD_CTX_CREATE */
struct virtio_gpu_ctx_create {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 nlen;
	__le32 padding;
	char debug_name[64];
};

/* VIRTIO_GPU_CMD_CTX_DESTROY */
struct virtio_gpu_ctx_destroy {
	struct virtio_gpu_ctrl_hdr hdr;
};

/* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
struct virtio_gpu_ctx_resource {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 resource_id;
	__le32 padding;
};

/* VIRTIO_GPU_CMD_SUBMIT_3D */
struct virtio_gpu_cmd_submit {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 size;
	__le32 padding;
};

#define VIRTIO_GPU_CAPSET_VIRGL 1
#define VIRTIO_GPU_CAPSET_VIRGL2 2

/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
struct virtio_gpu_get_capset_info {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 capset_index;
	__le32 padding;
};

/* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
struct virtio_gpu_resp_capset_info {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 capset_id;
	__le32 capset_max_version;
	__le32 capset_max_size;
	__le32 padding;
};

/* VIRTIO_GPU_CMD_GET_CAPSET */
struct virtio_gpu_get_capset {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 capset_id;
	__le32 capset_version;
};

/* VIRTIO_GPU_RESP_OK_CAPSET */
struct virtio_gpu_resp_capset {
	struct virtio_gpu_ctrl_hdr hdr;
	__u8 capset_data[];
};

/* VIRTIO_GPU_CMD_GET_EDID */
struct virtio_gpu_cmd_get_edid {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 scanout;
	__le32 padding;
};

/* VIRTIO_GPU_RESP_OK_EDID */
struct virtio_gpu_resp_edid {
	struct virtio_gpu_ctrl_hdr hdr;
	__le32 size;
	__le32 padding;
	__u8 edid[1024];
};

#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)

struct virtio_gpu_config {
	__u32 events_read;
	__u32 events_clear;
	__u32 num_scanouts;
	__u32 num_capsets;
};

/* simple formats for fbcon/X use */
enum virtio_gpu_formats {
	VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM  = 1,
	VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM  = 2,
	VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM  = 3,
	VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM  = 4,

	VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM  = 67,
	VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM  = 68,

	VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM  = 121,
	VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM  = 134,
};

#endif
Commit	Line	Data
dc5698e8 DA	1	/*
	2	* Virtio GPU Device
	3	*
	4	* Copyright Red Hat, Inc. 2013-2014
	5	*
	6	* Authors:
	7	* Dave Airlie <airlied@redhat.com>
	8	* Gerd Hoffmann <kraxel@redhat.com>
	9	*
	10	* This header is BSD licensed so anyone can use the definitions
	11	* to implement compatible drivers/servers:
	12	*
	13	* Redistribution and use in source and binary forms, with or without
	14	* modification, are permitted provided that the following conditions
	15	* are met:
	16	* 1. Redistributions of source code must retain the above copyright
	17	* notice, this list of conditions and the following disclaimer.
	18	* 2. Redistributions in binary form must reproduce the above copyright
	19	* notice, this list of conditions and the following disclaimer in the
	20	* documentation and/or other materials provided with the distribution.
	21	* 3. Neither the name of IBM nor the names of its contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	25	* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	26	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
	27	* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR
	28	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	29	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	30	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	31	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	32	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
	34	* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	35	* SUCH DAMAGE.
	36	*/
	37
	38	#ifndef VIRTIO_GPU_HW_H
	39	#define VIRTIO_GPU_HW_H
	40
ae455773 DA	41	#include <linux/types.h>
ae455773 DA	42
62fb7a5e	43	#define VIRTIO_GPU_F_VIRGL 0
610c0c2b	44	#define VIRTIO_GPU_F_EDID 1
62fb7a5e	45
dc5698e8 DA	46	enum virtio_gpu_ctrl_type {
	47	VIRTIO_GPU_UNDEFINED = 0,
	48
	49	/* 2d commands */
	50	VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
	51	VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
	52	VIRTIO_GPU_CMD_RESOURCE_UNREF,
	53	VIRTIO_GPU_CMD_SET_SCANOUT,
	54	VIRTIO_GPU_CMD_RESOURCE_FLUSH,
	55	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
	56	VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
	57	VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
62fb7a5e GH	58	VIRTIO_GPU_CMD_GET_CAPSET_INFO,
62fb7a5e GH	59	VIRTIO_GPU_CMD_GET_CAPSET,
610c0c2b	60	VIRTIO_GPU_CMD_GET_EDID,
62fb7a5e GH	61
	62	/* 3d commands */
	63	VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
	64	VIRTIO_GPU_CMD_CTX_DESTROY,
	65	VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
	66	VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
	67	VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
	68	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
	69	VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
	70	VIRTIO_GPU_CMD_SUBMIT_3D,
dc5698e8 DA	71
	72	/* cursor commands */
	73	VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
	74	VIRTIO_GPU_CMD_MOVE_CURSOR,
	75
	76	/* success responses */
	77	VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
	78	VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
62fb7a5e GH	79	VIRTIO_GPU_RESP_OK_CAPSET_INFO,
62fb7a5e GH	80	VIRTIO_GPU_RESP_OK_CAPSET,
610c0c2b	81	VIRTIO_GPU_RESP_OK_EDID,
dc5698e8 DA	82
	83	/* error responses */
	84	VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
	85	VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
	86	VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
	87	VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
	88	VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
	89	VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
	90	};
	91
	92	#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
	93
	94	struct virtio_gpu_ctrl_hdr {
	95	__le32 type;
	96	__le32 flags;
	97	__le64 fence_id;
	98	__le32 ctx_id;
	99	__le32 padding;
	100	};
	101
	102	/* data passed in the cursor vq */
	103
	104	struct virtio_gpu_cursor_pos {
	105	__le32 scanout_id;
	106	__le32 x;
	107	__le32 y;
	108	__le32 padding;
	109	};
	110
	111	/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
	112	struct virtio_gpu_update_cursor {
	113	struct virtio_gpu_ctrl_hdr hdr;
	114	struct virtio_gpu_cursor_pos pos; /* update & move */
	115	__le32 resource_id; /* update only */
	116	__le32 hot_x; /* update only */
	117	__le32 hot_y; /* update only */
	118	__le32 padding;
	119	};
	120
	121	/* data passed in the control vq, 2d related */
	122
	123	struct virtio_gpu_rect {
	124	__le32 x;
	125	__le32 y;
	126	__le32 width;
	127	__le32 height;
	128	};
	129
	130	/* VIRTIO_GPU_CMD_RESOURCE_UNREF */
	131	struct virtio_gpu_resource_unref {
	132	struct virtio_gpu_ctrl_hdr hdr;
	133	__le32 resource_id;
	134	__le32 padding;
	135	};
	136
	137	/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
	138	struct virtio_gpu_resource_create_2d {
	139	struct virtio_gpu_ctrl_hdr hdr;
	140	__le32 resource_id;
	141	__le32 format;
	142	__le32 width;
	143	__le32 height;
	144	};
	145
146	/* VIRTIO_GPU_CMD_SET_SCANOUT */
147	struct virtio_gpu_set_scanout {
148	struct virtio_gpu_ctrl_hdr hdr;
149	struct virtio_gpu_rect r;
150	__le32 scanout_id;
151	__le32 resource_id;
152	};
153
154	/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
155	struct virtio_gpu_resource_flush {
156	struct virtio_gpu_ctrl_hdr hdr;
157	struct virtio_gpu_rect r;
158	__le32 resource_id;
159	__le32 padding;
160	};
161
162	/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
163	struct virtio_gpu_transfer_to_host_2d {
164	struct virtio_gpu_ctrl_hdr hdr;
165	struct virtio_gpu_rect r;
166	__le64 offset;
167	__le32 resource_id;
168	__le32 padding;
169	};
170
171	struct virtio_gpu_mem_entry {
172	__le64 addr;
173	__le32 length;
174	__le32 padding;
175	};
176
177	/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
178	struct virtio_gpu_resource_attach_backing {
179	struct virtio_gpu_ctrl_hdr hdr;
180	__le32 resource_id;
181	__le32 nr_entries;
182	};
183
184	/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
185	struct virtio_gpu_resource_detach_backing {
186	struct virtio_gpu_ctrl_hdr hdr;
187	__le32 resource_id;
188	__le32 padding;
189	};
190
191	/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
192	#define VIRTIO_GPU_MAX_SCANOUTS 16
193	struct virtio_gpu_resp_display_info {
194	struct virtio_gpu_ctrl_hdr hdr;
195	struct virtio_gpu_display_one {
196	struct virtio_gpu_rect r;
197	__le32 enabled;
198	__le32 flags;
199	} pmodes[VIRTIO_GPU_MAX_SCANOUTS];
200	};
201
62fb7a5e GH	202	/* data passed in the control vq, 3d related */
	203
	204	struct virtio_gpu_box {
	205	__le32 x, y, z;
	206	__le32 w, h, d;
	207	};
	208
	209	/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
	210	struct virtio_gpu_transfer_host_3d {
	211	struct virtio_gpu_ctrl_hdr hdr;
	212	struct virtio_gpu_box box;
	213	__le64 offset;
	214	__le32 resource_id;
	215	__le32 level;
	216	__le32 stride;
	217	__le32 layer_stride;
	218	};
	219
	220	/* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
	221	#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
	222	struct virtio_gpu_resource_create_3d {
	223	struct virtio_gpu_ctrl_hdr hdr;
	224	__le32 resource_id;
	225	__le32 target;
	226	__le32 format;
	227	__le32 bind;
	228	__le32 width;
	229	__le32 height;
	230	__le32 depth;
	231	__le32 array_size;
	232	__le32 last_level;
	233	__le32 nr_samples;
	234	__le32 flags;
	235	__le32 padding;
	236	};
	237
	238	/* VIRTIO_GPU_CMD_CTX_CREATE */
	239	struct virtio_gpu_ctx_create {
	240	struct virtio_gpu_ctrl_hdr hdr;
	241	__le32 nlen;
	242	__le32 padding;
	243	char debug_name[64];
	244	};
	245
	246	/* VIRTIO_GPU_CMD_CTX_DESTROY */
	247	struct virtio_gpu_ctx_destroy {
	248	struct virtio_gpu_ctrl_hdr hdr;
	249	};
	250
	251	/* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
	252	struct virtio_gpu_ctx_resource {
	253	struct virtio_gpu_ctrl_hdr hdr;
	254	__le32 resource_id;
	255	__le32 padding;
	256	};
	257
	258	/* VIRTIO_GPU_CMD_SUBMIT_3D */
	259	struct virtio_gpu_cmd_submit {
	260	struct virtio_gpu_ctrl_hdr hdr;
	261	__le32 size;
	262	__le32 padding;
	263	};
	264
	265	#define VIRTIO_GPU_CAPSET_VIRGL 1
110ab11d	266	#define VIRTIO_GPU_CAPSET_VIRGL2 2
62fb7a5e GH	267
	268	/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
	269	struct virtio_gpu_get_capset_info {
	270	struct virtio_gpu_ctrl_hdr hdr;
	271	__le32 capset_index;
	272	__le32 padding;
	273	};
	274
	275	/* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
	276	struct virtio_gpu_resp_capset_info {
	277	struct virtio_gpu_ctrl_hdr hdr;
	278	__le32 capset_id;
	279	__le32 capset_max_version;
	280	__le32 capset_max_size;
	281	__le32 padding;
	282	};
	283
	284	/* VIRTIO_GPU_CMD_GET_CAPSET */
	285	struct virtio_gpu_get_capset {
	286	struct virtio_gpu_ctrl_hdr hdr;
	287	__le32 capset_id;
	288	__le32 capset_version;
	289	};
	290
	291	/* VIRTIO_GPU_RESP_OK_CAPSET */
	292	struct virtio_gpu_resp_capset {
	293	struct virtio_gpu_ctrl_hdr hdr;
89545d6d	294	__u8 capset_data[];
62fb7a5e GH	295	};
62fb7a5e GH	296
610c0c2b GH	297	/* VIRTIO_GPU_CMD_GET_EDID */
	298	struct virtio_gpu_cmd_get_edid {
	299	struct virtio_gpu_ctrl_hdr hdr;
	300	__le32 scanout;
	301	__le32 padding;
	302	};
	303
	304	/* VIRTIO_GPU_RESP_OK_EDID */
	305	struct virtio_gpu_resp_edid {
	306	struct virtio_gpu_ctrl_hdr hdr;
	307	__le32 size;
	308	__le32 padding;
	309	__u8 edid[1024];
	310	};
	311
dc5698e8 DA	312	#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
	313
	314	struct virtio_gpu_config {
	315	__u32 events_read;
	316	__u32 events_clear;
	317	__u32 num_scanouts;
62fb7a5e	318	__u32 num_capsets;
dc5698e8 DA	319	};
	320
	321	/* simple formats for fbcon/X use */
	322	enum virtio_gpu_formats {
	323	VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
	324	VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
	325	VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
	326	VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
	327
	328	VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
	329	VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
	330
	331	VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
	332	VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
	333	};
	334
	335	#endif