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e2be04c7 | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
607ca46e DH |
2 | /* |
3 | * Performance events: | |
4 | * | |
5 | * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> | |
6 | * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar | |
7 | * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra | |
8 | * | |
9 | * Data type definitions, declarations, prototypes. | |
10 | * | |
11 | * Started by: Thomas Gleixner and Ingo Molnar | |
12 | * | |
13 | * For licencing details see kernel-base/COPYING | |
14 | */ | |
15 | #ifndef _UAPI_LINUX_PERF_EVENT_H | |
16 | #define _UAPI_LINUX_PERF_EVENT_H | |
17 | ||
18 | #include <linux/types.h> | |
19 | #include <linux/ioctl.h> | |
20 | #include <asm/byteorder.h> | |
21 | ||
22 | /* | |
23 | * User-space ABI bits: | |
24 | */ | |
25 | ||
26 | /* | |
27 | * attr.type | |
28 | */ | |
29 | enum perf_type_id { | |
30 | PERF_TYPE_HARDWARE = 0, | |
31 | PERF_TYPE_SOFTWARE = 1, | |
32 | PERF_TYPE_TRACEPOINT = 2, | |
33 | PERF_TYPE_HW_CACHE = 3, | |
34 | PERF_TYPE_RAW = 4, | |
35 | PERF_TYPE_BREAKPOINT = 5, | |
36 | ||
37 | PERF_TYPE_MAX, /* non-ABI */ | |
38 | }; | |
39 | ||
40 | /* | |
41 | * Generalized performance event event_id types, used by the | |
42 | * attr.event_id parameter of the sys_perf_event_open() | |
43 | * syscall: | |
44 | */ | |
45 | enum perf_hw_id { | |
46 | /* | |
47 | * Common hardware events, generalized by the kernel: | |
48 | */ | |
49 | PERF_COUNT_HW_CPU_CYCLES = 0, | |
50 | PERF_COUNT_HW_INSTRUCTIONS = 1, | |
51 | PERF_COUNT_HW_CACHE_REFERENCES = 2, | |
52 | PERF_COUNT_HW_CACHE_MISSES = 3, | |
53 | PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, | |
54 | PERF_COUNT_HW_BRANCH_MISSES = 5, | |
55 | PERF_COUNT_HW_BUS_CYCLES = 6, | |
56 | PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, | |
57 | PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, | |
58 | PERF_COUNT_HW_REF_CPU_CYCLES = 9, | |
59 | ||
60 | PERF_COUNT_HW_MAX, /* non-ABI */ | |
61 | }; | |
62 | ||
63 | /* | |
64 | * Generalized hardware cache events: | |
65 | * | |
66 | * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x | |
67 | * { read, write, prefetch } x | |
68 | * { accesses, misses } | |
69 | */ | |
70 | enum perf_hw_cache_id { | |
71 | PERF_COUNT_HW_CACHE_L1D = 0, | |
72 | PERF_COUNT_HW_CACHE_L1I = 1, | |
73 | PERF_COUNT_HW_CACHE_LL = 2, | |
74 | PERF_COUNT_HW_CACHE_DTLB = 3, | |
75 | PERF_COUNT_HW_CACHE_ITLB = 4, | |
76 | PERF_COUNT_HW_CACHE_BPU = 5, | |
77 | PERF_COUNT_HW_CACHE_NODE = 6, | |
78 | ||
79 | PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ | |
80 | }; | |
81 | ||
82 | enum perf_hw_cache_op_id { | |
83 | PERF_COUNT_HW_CACHE_OP_READ = 0, | |
84 | PERF_COUNT_HW_CACHE_OP_WRITE = 1, | |
85 | PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, | |
86 | ||
87 | PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ | |
88 | }; | |
89 | ||
90 | enum perf_hw_cache_op_result_id { | |
91 | PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, | |
92 | PERF_COUNT_HW_CACHE_RESULT_MISS = 1, | |
93 | ||
94 | PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ | |
95 | }; | |
96 | ||
97 | /* | |
98 | * Special "software" events provided by the kernel, even if the hardware | |
99 | * does not support performance events. These events measure various | |
100 | * physical and sw events of the kernel (and allow the profiling of them as | |
101 | * well): | |
102 | */ | |
103 | enum perf_sw_ids { | |
104 | PERF_COUNT_SW_CPU_CLOCK = 0, | |
105 | PERF_COUNT_SW_TASK_CLOCK = 1, | |
106 | PERF_COUNT_SW_PAGE_FAULTS = 2, | |
107 | PERF_COUNT_SW_CONTEXT_SWITCHES = 3, | |
108 | PERF_COUNT_SW_CPU_MIGRATIONS = 4, | |
109 | PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, | |
110 | PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, | |
111 | PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, | |
112 | PERF_COUNT_SW_EMULATION_FAULTS = 8, | |
fa0097ee | 113 | PERF_COUNT_SW_DUMMY = 9, |
a43eec30 | 114 | PERF_COUNT_SW_BPF_OUTPUT = 10, |
607ca46e DH |
115 | |
116 | PERF_COUNT_SW_MAX, /* non-ABI */ | |
117 | }; | |
118 | ||
119 | /* | |
120 | * Bits that can be set in attr.sample_type to request information | |
121 | * in the overflow packets. | |
122 | */ | |
123 | enum perf_event_sample_format { | |
124 | PERF_SAMPLE_IP = 1U << 0, | |
125 | PERF_SAMPLE_TID = 1U << 1, | |
126 | PERF_SAMPLE_TIME = 1U << 2, | |
127 | PERF_SAMPLE_ADDR = 1U << 3, | |
128 | PERF_SAMPLE_READ = 1U << 4, | |
129 | PERF_SAMPLE_CALLCHAIN = 1U << 5, | |
130 | PERF_SAMPLE_ID = 1U << 6, | |
131 | PERF_SAMPLE_CPU = 1U << 7, | |
132 | PERF_SAMPLE_PERIOD = 1U << 8, | |
133 | PERF_SAMPLE_STREAM_ID = 1U << 9, | |
134 | PERF_SAMPLE_RAW = 1U << 10, | |
135 | PERF_SAMPLE_BRANCH_STACK = 1U << 11, | |
136 | PERF_SAMPLE_REGS_USER = 1U << 12, | |
137 | PERF_SAMPLE_STACK_USER = 1U << 13, | |
c3feedf2 | 138 | PERF_SAMPLE_WEIGHT = 1U << 14, |
d6be9ad6 | 139 | PERF_SAMPLE_DATA_SRC = 1U << 15, |
ff3d527c | 140 | PERF_SAMPLE_IDENTIFIER = 1U << 16, |
fdfbbd07 | 141 | PERF_SAMPLE_TRANSACTION = 1U << 17, |
60e2364e | 142 | PERF_SAMPLE_REGS_INTR = 1U << 18, |
fc7ce9c7 | 143 | PERF_SAMPLE_PHYS_ADDR = 1U << 19, |
c3feedf2 | 144 | |
fc7ce9c7 | 145 | PERF_SAMPLE_MAX = 1U << 20, /* non-ABI */ |
6cbc304f | 146 | |
09121255 | 147 | __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ |
607ca46e DH |
148 | }; |
149 | ||
150 | /* | |
151 | * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set | |
152 | * | |
153 | * If the user does not pass priv level information via branch_sample_type, | |
154 | * the kernel uses the event's priv level. Branch and event priv levels do | |
155 | * not have to match. Branch priv level is checked for permissions. | |
156 | * | |
157 | * The branch types can be combined, however BRANCH_ANY covers all types | |
158 | * of branches and therefore it supersedes all the other types. | |
159 | */ | |
27ac905b YZ |
160 | enum perf_branch_sample_type_shift { |
161 | PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ | |
162 | PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ | |
163 | PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ | |
164 | ||
165 | PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ | |
166 | PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ | |
167 | PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ | |
168 | PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ | |
169 | PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ | |
170 | PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ | |
171 | PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ | |
172 | PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ | |
173 | ||
2c44b193 | 174 | PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ |
c9fdfa14 | 175 | PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ |
c229bf9d | 176 | PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ |
2c44b193 | 177 | |
b16a5b52 AK |
178 | PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ |
179 | PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ | |
180 | ||
eb0baf8a JY |
181 | PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ |
182 | ||
27ac905b YZ |
183 | PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ |
184 | }; | |
185 | ||
607ca46e | 186 | enum perf_branch_sample_type { |
27ac905b YZ |
187 | PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, |
188 | PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, | |
189 | PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, | |
190 | ||
191 | PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, | |
2c44b193 PZ |
192 | PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, |
193 | PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, | |
194 | PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, | |
195 | PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, | |
27ac905b YZ |
196 | PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, |
197 | PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, | |
198 | PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, | |
199 | ||
2c44b193 | 200 | PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, |
c9fdfa14 | 201 | PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, |
c229bf9d | 202 | PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, |
2c44b193 | 203 | |
b16a5b52 AK |
204 | PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, |
205 | PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, | |
206 | ||
eb0baf8a JY |
207 | PERF_SAMPLE_BRANCH_TYPE_SAVE = |
208 | 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, | |
209 | ||
27ac905b | 210 | PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, |
607ca46e DH |
211 | }; |
212 | ||
eb0baf8a JY |
213 | /* |
214 | * Common flow change classification | |
215 | */ | |
216 | enum { | |
217 | PERF_BR_UNKNOWN = 0, /* unknown */ | |
218 | PERF_BR_COND = 1, /* conditional */ | |
219 | PERF_BR_UNCOND = 2, /* unconditional */ | |
220 | PERF_BR_IND = 3, /* indirect */ | |
221 | PERF_BR_CALL = 4, /* function call */ | |
222 | PERF_BR_IND_CALL = 5, /* indirect function call */ | |
223 | PERF_BR_RET = 6, /* function return */ | |
224 | PERF_BR_SYSCALL = 7, /* syscall */ | |
225 | PERF_BR_SYSRET = 8, /* syscall return */ | |
226 | PERF_BR_COND_CALL = 9, /* conditional function call */ | |
227 | PERF_BR_COND_RET = 10, /* conditional function return */ | |
228 | PERF_BR_MAX, | |
229 | }; | |
230 | ||
607ca46e DH |
231 | #define PERF_SAMPLE_BRANCH_PLM_ALL \ |
232 | (PERF_SAMPLE_BRANCH_USER|\ | |
233 | PERF_SAMPLE_BRANCH_KERNEL|\ | |
234 | PERF_SAMPLE_BRANCH_HV) | |
235 | ||
236 | /* | |
237 | * Values to determine ABI of the registers dump. | |
238 | */ | |
239 | enum perf_sample_regs_abi { | |
240 | PERF_SAMPLE_REGS_ABI_NONE = 0, | |
241 | PERF_SAMPLE_REGS_ABI_32 = 1, | |
242 | PERF_SAMPLE_REGS_ABI_64 = 2, | |
243 | }; | |
244 | ||
fdfbbd07 AK |
245 | /* |
246 | * Values for the memory transaction event qualifier, mostly for | |
247 | * abort events. Multiple bits can be set. | |
248 | */ | |
249 | enum { | |
250 | PERF_TXN_ELISION = (1 << 0), /* From elision */ | |
251 | PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ | |
252 | PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ | |
253 | PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ | |
254 | PERF_TXN_RETRY = (1 << 4), /* Retry possible */ | |
255 | PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ | |
256 | PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ | |
257 | PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ | |
258 | ||
259 | PERF_TXN_MAX = (1 << 8), /* non-ABI */ | |
260 | ||
261 | /* bits 32..63 are reserved for the abort code */ | |
262 | ||
263 | PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), | |
264 | PERF_TXN_ABORT_SHIFT = 32, | |
265 | }; | |
266 | ||
607ca46e DH |
267 | /* |
268 | * The format of the data returned by read() on a perf event fd, | |
269 | * as specified by attr.read_format: | |
270 | * | |
271 | * struct read_format { | |
272 | * { u64 value; | |
273 | * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED | |
274 | * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING | |
275 | * { u64 id; } && PERF_FORMAT_ID | |
276 | * } && !PERF_FORMAT_GROUP | |
277 | * | |
278 | * { u64 nr; | |
279 | * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED | |
280 | * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING | |
281 | * { u64 value; | |
282 | * { u64 id; } && PERF_FORMAT_ID | |
283 | * } cntr[nr]; | |
284 | * } && PERF_FORMAT_GROUP | |
285 | * }; | |
286 | */ | |
287 | enum perf_event_read_format { | |
288 | PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, | |
289 | PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, | |
290 | PERF_FORMAT_ID = 1U << 2, | |
291 | PERF_FORMAT_GROUP = 1U << 3, | |
292 | ||
293 | PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ | |
294 | }; | |
295 | ||
296 | #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ | |
297 | #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ | |
298 | #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ | |
299 | #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ | |
300 | /* add: sample_stack_user */ | |
60e2364e | 301 | #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ |
1a594131 | 302 | #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ |
607ca46e DH |
303 | |
304 | /* | |
305 | * Hardware event_id to monitor via a performance monitoring event: | |
97c79a38 ACM |
306 | * |
307 | * @sample_max_stack: Max number of frame pointers in a callchain, | |
308 | * should be < /proc/sys/kernel/perf_event_max_stack | |
607ca46e DH |
309 | */ |
310 | struct perf_event_attr { | |
311 | ||
312 | /* | |
313 | * Major type: hardware/software/tracepoint/etc. | |
314 | */ | |
315 | __u32 type; | |
316 | ||
317 | /* | |
318 | * Size of the attr structure, for fwd/bwd compat. | |
319 | */ | |
320 | __u32 size; | |
321 | ||
322 | /* | |
323 | * Type specific configuration information. | |
324 | */ | |
325 | __u64 config; | |
326 | ||
327 | union { | |
328 | __u64 sample_period; | |
329 | __u64 sample_freq; | |
330 | }; | |
331 | ||
332 | __u64 sample_type; | |
333 | __u64 read_format; | |
334 | ||
335 | __u64 disabled : 1, /* off by default */ | |
336 | inherit : 1, /* children inherit it */ | |
337 | pinned : 1, /* must always be on PMU */ | |
338 | exclusive : 1, /* only group on PMU */ | |
339 | exclude_user : 1, /* don't count user */ | |
340 | exclude_kernel : 1, /* ditto kernel */ | |
341 | exclude_hv : 1, /* ditto hypervisor */ | |
342 | exclude_idle : 1, /* don't count when idle */ | |
343 | mmap : 1, /* include mmap data */ | |
344 | comm : 1, /* include comm data */ | |
345 | freq : 1, /* use freq, not period */ | |
346 | inherit_stat : 1, /* per task counts */ | |
347 | enable_on_exec : 1, /* next exec enables */ | |
348 | task : 1, /* trace fork/exit */ | |
349 | watermark : 1, /* wakeup_watermark */ | |
350 | /* | |
351 | * precise_ip: | |
352 | * | |
353 | * 0 - SAMPLE_IP can have arbitrary skid | |
354 | * 1 - SAMPLE_IP must have constant skid | |
355 | * 2 - SAMPLE_IP requested to have 0 skid | |
356 | * 3 - SAMPLE_IP must have 0 skid | |
357 | * | |
358 | * See also PERF_RECORD_MISC_EXACT_IP | |
359 | */ | |
360 | precise_ip : 2, /* skid constraint */ | |
361 | mmap_data : 1, /* non-exec mmap data */ | |
362 | sample_id_all : 1, /* sample_type all events */ | |
363 | ||
364 | exclude_host : 1, /* don't count in host */ | |
365 | exclude_guest : 1, /* don't count in guest */ | |
366 | ||
367 | exclude_callchain_kernel : 1, /* exclude kernel callchains */ | |
368 | exclude_callchain_user : 1, /* exclude user callchains */ | |
13d7a241 | 369 | mmap2 : 1, /* include mmap with inode data */ |
82b89778 | 370 | comm_exec : 1, /* flag comm events that are due to an exec */ |
34f43927 | 371 | use_clockid : 1, /* use @clockid for time fields */ |
45ac1403 | 372 | context_switch : 1, /* context switch data */ |
9ecda41a | 373 | write_backward : 1, /* Write ring buffer from end to beginning */ |
e4222673 HB |
374 | namespaces : 1, /* include namespaces data */ |
375 | __reserved_1 : 35; | |
607ca46e DH |
376 | |
377 | union { | |
378 | __u32 wakeup_events; /* wakeup every n events */ | |
379 | __u32 wakeup_watermark; /* bytes before wakeup */ | |
380 | }; | |
381 | ||
382 | __u32 bp_type; | |
383 | union { | |
384 | __u64 bp_addr; | |
65074d43 SL |
385 | __u64 kprobe_func; /* for perf_kprobe */ |
386 | __u64 uprobe_path; /* for perf_uprobe */ | |
607ca46e DH |
387 | __u64 config1; /* extension of config */ |
388 | }; | |
389 | union { | |
390 | __u64 bp_len; | |
65074d43 SL |
391 | __u64 kprobe_addr; /* when kprobe_func == NULL */ |
392 | __u64 probe_offset; /* for perf_[k,u]probe */ | |
607ca46e DH |
393 | __u64 config2; /* extension of config1 */ |
394 | }; | |
395 | __u64 branch_sample_type; /* enum perf_branch_sample_type */ | |
396 | ||
397 | /* | |
398 | * Defines set of user regs to dump on samples. | |
399 | * See asm/perf_regs.h for details. | |
400 | */ | |
401 | __u64 sample_regs_user; | |
402 | ||
403 | /* | |
404 | * Defines size of the user stack to dump on samples. | |
405 | */ | |
406 | __u32 sample_stack_user; | |
407 | ||
34f43927 | 408 | __s32 clockid; |
60e2364e SE |
409 | /* |
410 | * Defines set of regs to dump for each sample | |
411 | * state captured on: | |
412 | * - precise = 0: PMU interrupt | |
413 | * - precise > 0: sampled instruction | |
414 | * | |
415 | * See asm/perf_regs.h for details. | |
416 | */ | |
417 | __u64 sample_regs_intr; | |
1a594131 AS |
418 | |
419 | /* | |
420 | * Wakeup watermark for AUX area | |
421 | */ | |
422 | __u32 aux_watermark; | |
97c79a38 ACM |
423 | __u16 sample_max_stack; |
424 | __u16 __reserved_2; /* align to __u64 */ | |
607ca46e DH |
425 | }; |
426 | ||
f371b304 YS |
427 | /* |
428 | * Structure used by below PERF_EVENT_IOC_QUERY_BPF command | |
429 | * to query bpf programs attached to the same perf tracepoint | |
430 | * as the given perf event. | |
431 | */ | |
432 | struct perf_event_query_bpf { | |
433 | /* | |
434 | * The below ids array length | |
435 | */ | |
436 | __u32 ids_len; | |
437 | /* | |
438 | * Set by the kernel to indicate the number of | |
439 | * available programs | |
440 | */ | |
441 | __u32 prog_cnt; | |
442 | /* | |
443 | * User provided buffer to store program ids | |
444 | */ | |
445 | __u32 ids[0]; | |
446 | }; | |
447 | ||
607ca46e DH |
448 | #define perf_flags(attr) (*(&(attr)->read_format + 1)) |
449 | ||
450 | /* | |
451 | * Ioctls that can be done on a perf event fd: | |
452 | */ | |
32ff77e8 MC |
453 | #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) |
454 | #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) | |
455 | #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) | |
456 | #define PERF_EVENT_IOC_RESET _IO ('$', 3) | |
457 | #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) | |
458 | #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) | |
459 | #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) | |
460 | #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) | |
461 | #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) | |
462 | #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) | |
463 | #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) | |
464 | #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) | |
607ca46e DH |
465 | |
466 | enum perf_event_ioc_flags { | |
467 | PERF_IOC_FLAG_GROUP = 1U << 0, | |
468 | }; | |
469 | ||
470 | /* | |
471 | * Structure of the page that can be mapped via mmap | |
472 | */ | |
473 | struct perf_event_mmap_page { | |
474 | __u32 version; /* version number of this structure */ | |
475 | __u32 compat_version; /* lowest version this is compat with */ | |
476 | ||
477 | /* | |
478 | * Bits needed to read the hw events in user-space. | |
479 | * | |
b438b1ab | 480 | * u32 seq, time_mult, time_shift, index, width; |
607ca46e DH |
481 | * u64 count, enabled, running; |
482 | * u64 cyc, time_offset; | |
483 | * s64 pmc = 0; | |
484 | * | |
485 | * do { | |
486 | * seq = pc->lock; | |
487 | * barrier() | |
488 | * | |
489 | * enabled = pc->time_enabled; | |
490 | * running = pc->time_running; | |
491 | * | |
492 | * if (pc->cap_usr_time && enabled != running) { | |
493 | * cyc = rdtsc(); | |
494 | * time_offset = pc->time_offset; | |
495 | * time_mult = pc->time_mult; | |
496 | * time_shift = pc->time_shift; | |
497 | * } | |
498 | * | |
b438b1ab | 499 | * index = pc->index; |
607ca46e | 500 | * count = pc->offset; |
b438b1ab | 501 | * if (pc->cap_user_rdpmc && index) { |
607ca46e | 502 | * width = pc->pmc_width; |
b438b1ab | 503 | * pmc = rdpmc(index - 1); |
607ca46e DH |
504 | * } |
505 | * | |
506 | * barrier(); | |
507 | * } while (pc->lock != seq); | |
508 | * | |
509 | * NOTE: for obvious reason this only works on self-monitoring | |
510 | * processes. | |
511 | */ | |
512 | __u32 lock; /* seqlock for synchronization */ | |
513 | __u32 index; /* hardware event identifier */ | |
514 | __s64 offset; /* add to hardware event value */ | |
515 | __u64 time_enabled; /* time event active */ | |
516 | __u64 time_running; /* time event on cpu */ | |
517 | union { | |
518 | __u64 capabilities; | |
860f085b | 519 | struct { |
fa731587 PZ |
520 | __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ |
521 | cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ | |
522 | ||
523 | cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ | |
524 | cap_user_time : 1, /* The time_* fields are used */ | |
525 | cap_user_time_zero : 1, /* The time_zero field is used */ | |
526 | cap_____res : 59; | |
860f085b | 527 | }; |
607ca46e DH |
528 | }; |
529 | ||
530 | /* | |
b438b1ab | 531 | * If cap_user_rdpmc this field provides the bit-width of the value |
607ca46e DH |
532 | * read using the rdpmc() or equivalent instruction. This can be used |
533 | * to sign extend the result like: | |
534 | * | |
535 | * pmc <<= 64 - width; | |
536 | * pmc >>= 64 - width; // signed shift right | |
537 | * count += pmc; | |
538 | */ | |
539 | __u16 pmc_width; | |
540 | ||
541 | /* | |
542 | * If cap_usr_time the below fields can be used to compute the time | |
543 | * delta since time_enabled (in ns) using rdtsc or similar. | |
544 | * | |
545 | * u64 quot, rem; | |
546 | * u64 delta; | |
547 | * | |
548 | * quot = (cyc >> time_shift); | |
b9511cd7 | 549 | * rem = cyc & (((u64)1 << time_shift) - 1); |
607ca46e DH |
550 | * delta = time_offset + quot * time_mult + |
551 | * ((rem * time_mult) >> time_shift); | |
552 | * | |
553 | * Where time_offset,time_mult,time_shift and cyc are read in the | |
554 | * seqcount loop described above. This delta can then be added to | |
b438b1ab | 555 | * enabled and possible running (if index), improving the scaling: |
607ca46e DH |
556 | * |
557 | * enabled += delta; | |
b438b1ab | 558 | * if (index) |
607ca46e DH |
559 | * running += delta; |
560 | * | |
561 | * quot = count / running; | |
562 | * rem = count % running; | |
563 | * count = quot * enabled + (rem * enabled) / running; | |
564 | */ | |
565 | __u16 time_shift; | |
566 | __u32 time_mult; | |
567 | __u64 time_offset; | |
c73deb6a AH |
568 | /* |
569 | * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated | |
570 | * from sample timestamps. | |
571 | * | |
572 | * time = timestamp - time_zero; | |
573 | * quot = time / time_mult; | |
574 | * rem = time % time_mult; | |
575 | * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; | |
576 | * | |
577 | * And vice versa: | |
578 | * | |
579 | * quot = cyc >> time_shift; | |
b9511cd7 | 580 | * rem = cyc & (((u64)1 << time_shift) - 1); |
c73deb6a AH |
581 | * timestamp = time_zero + quot * time_mult + |
582 | * ((rem * time_mult) >> time_shift); | |
583 | */ | |
584 | __u64 time_zero; | |
fa731587 | 585 | __u32 size; /* Header size up to __reserved[] fields. */ |
607ca46e DH |
586 | |
587 | /* | |
588 | * Hole for extension of the self monitor capabilities | |
589 | */ | |
590 | ||
fa731587 | 591 | __u8 __reserved[118*8+4]; /* align to 1k. */ |
607ca46e DH |
592 | |
593 | /* | |
594 | * Control data for the mmap() data buffer. | |
595 | * | |
bf378d34 PZ |
596 | * User-space reading the @data_head value should issue an smp_rmb(), |
597 | * after reading this value. | |
607ca46e DH |
598 | * |
599 | * When the mapping is PROT_WRITE the @data_tail value should be | |
bf378d34 PZ |
600 | * written by userspace to reflect the last read data, after issueing |
601 | * an smp_mb() to separate the data read from the ->data_tail store. | |
602 | * In this case the kernel will not over-write unread data. | |
603 | * | |
604 | * See perf_output_put_handle() for the data ordering. | |
e8c6deac AS |
605 | * |
606 | * data_{offset,size} indicate the location and size of the perf record | |
607 | * buffer within the mmapped area. | |
607ca46e DH |
608 | */ |
609 | __u64 data_head; /* head in the data section */ | |
610 | __u64 data_tail; /* user-space written tail */ | |
e8c6deac AS |
611 | __u64 data_offset; /* where the buffer starts */ |
612 | __u64 data_size; /* data buffer size */ | |
45bfb2e5 PZ |
613 | |
614 | /* | |
615 | * AUX area is defined by aux_{offset,size} fields that should be set | |
616 | * by the userspace, so that | |
617 | * | |
618 | * aux_offset >= data_offset + data_size | |
619 | * | |
620 | * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. | |
621 | * | |
622 | * Ring buffer pointers aux_{head,tail} have the same semantics as | |
623 | * data_{head,tail} and same ordering rules apply. | |
624 | */ | |
625 | __u64 aux_head; | |
626 | __u64 aux_tail; | |
627 | __u64 aux_offset; | |
628 | __u64 aux_size; | |
607ca46e DH |
629 | }; |
630 | ||
631 | #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) | |
632 | #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) | |
633 | #define PERF_RECORD_MISC_KERNEL (1 << 0) | |
634 | #define PERF_RECORD_MISC_USER (2 << 0) | |
635 | #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) | |
636 | #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) | |
637 | #define PERF_RECORD_MISC_GUEST_USER (5 << 0) | |
638 | ||
930e6fcd KL |
639 | /* |
640 | * Indicates that /proc/PID/maps parsing are truncated by time out. | |
641 | */ | |
642 | #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) | |
82b89778 | 643 | /* |
972c1488 JO |
644 | * Following PERF_RECORD_MISC_* are used on different |
645 | * events, so can reuse the same bit position: | |
646 | * | |
647 | * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events | |
648 | * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event | |
649 | * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events | |
82b89778 | 650 | */ |
2fe85427 | 651 | #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) |
82b89778 | 652 | #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) |
45ac1403 | 653 | #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) |
607ca46e | 654 | /* |
101592b4 AB |
655 | * These PERF_RECORD_MISC_* flags below are safely reused |
656 | * for the following events: | |
657 | * | |
658 | * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events | |
659 | * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events | |
660 | * | |
661 | * | |
662 | * PERF_RECORD_MISC_EXACT_IP: | |
663 | * Indicates that the content of PERF_SAMPLE_IP points to | |
664 | * the actual instruction that triggered the event. See also | |
665 | * perf_event_attr::precise_ip. | |
666 | * | |
667 | * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: | |
668 | * Indicates that thread was preempted in TASK_RUNNING state. | |
607ca46e DH |
669 | */ |
670 | #define PERF_RECORD_MISC_EXACT_IP (1 << 14) | |
101592b4 | 671 | #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) |
607ca46e DH |
672 | /* |
673 | * Reserve the last bit to indicate some extended misc field | |
674 | */ | |
675 | #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) | |
676 | ||
677 | struct perf_event_header { | |
678 | __u32 type; | |
679 | __u16 misc; | |
680 | __u16 size; | |
681 | }; | |
682 | ||
e4222673 HB |
683 | struct perf_ns_link_info { |
684 | __u64 dev; | |
685 | __u64 ino; | |
686 | }; | |
687 | ||
688 | enum { | |
689 | NET_NS_INDEX = 0, | |
690 | UTS_NS_INDEX = 1, | |
691 | IPC_NS_INDEX = 2, | |
692 | PID_NS_INDEX = 3, | |
693 | USER_NS_INDEX = 4, | |
694 | MNT_NS_INDEX = 5, | |
695 | CGROUP_NS_INDEX = 6, | |
696 | ||
697 | NR_NAMESPACES, /* number of available namespaces */ | |
698 | }; | |
699 | ||
607ca46e DH |
700 | enum perf_event_type { |
701 | ||
702 | /* | |
703 | * If perf_event_attr.sample_id_all is set then all event types will | |
704 | * have the sample_type selected fields related to where/when | |
ff3d527c AH |
705 | * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, |
706 | * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed | |
707 | * just after the perf_event_header and the fields already present for | |
708 | * the existing fields, i.e. at the end of the payload. That way a newer | |
709 | * perf.data file will be supported by older perf tools, with these new | |
710 | * optional fields being ignored. | |
607ca46e | 711 | * |
a5cdd40c PZ |
712 | * struct sample_id { |
713 | * { u32 pid, tid; } && PERF_SAMPLE_TID | |
714 | * { u64 time; } && PERF_SAMPLE_TIME | |
715 | * { u64 id; } && PERF_SAMPLE_ID | |
716 | * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID | |
717 | * { u32 cpu, res; } && PERF_SAMPLE_CPU | |
ff3d527c | 718 | * { u64 id; } && PERF_SAMPLE_IDENTIFIER |
a5cdd40c | 719 | * } && perf_event_attr::sample_id_all |
ff3d527c AH |
720 | * |
721 | * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The | |
722 | * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed | |
723 | * relative to header.size. | |
a5cdd40c PZ |
724 | */ |
725 | ||
726 | /* | |
607ca46e DH |
727 | * The MMAP events record the PROT_EXEC mappings so that we can |
728 | * correlate userspace IPs to code. They have the following structure: | |
729 | * | |
730 | * struct { | |
731 | * struct perf_event_header header; | |
732 | * | |
733 | * u32 pid, tid; | |
734 | * u64 addr; | |
735 | * u64 len; | |
736 | * u64 pgoff; | |
737 | * char filename[]; | |
c5ecceef | 738 | * struct sample_id sample_id; |
607ca46e DH |
739 | * }; |
740 | */ | |
741 | PERF_RECORD_MMAP = 1, | |
742 | ||
743 | /* | |
744 | * struct { | |
745 | * struct perf_event_header header; | |
746 | * u64 id; | |
747 | * u64 lost; | |
a5cdd40c | 748 | * struct sample_id sample_id; |
607ca46e DH |
749 | * }; |
750 | */ | |
751 | PERF_RECORD_LOST = 2, | |
752 | ||
753 | /* | |
754 | * struct { | |
755 | * struct perf_event_header header; | |
756 | * | |
757 | * u32 pid, tid; | |
758 | * char comm[]; | |
a5cdd40c | 759 | * struct sample_id sample_id; |
607ca46e DH |
760 | * }; |
761 | */ | |
762 | PERF_RECORD_COMM = 3, | |
763 | ||
764 | /* | |
765 | * struct { | |
766 | * struct perf_event_header header; | |
767 | * u32 pid, ppid; | |
768 | * u32 tid, ptid; | |
769 | * u64 time; | |
a5cdd40c | 770 | * struct sample_id sample_id; |
607ca46e DH |
771 | * }; |
772 | */ | |
773 | PERF_RECORD_EXIT = 4, | |
774 | ||
775 | /* | |
776 | * struct { | |
777 | * struct perf_event_header header; | |
778 | * u64 time; | |
779 | * u64 id; | |
780 | * u64 stream_id; | |
a5cdd40c | 781 | * struct sample_id sample_id; |
607ca46e DH |
782 | * }; |
783 | */ | |
784 | PERF_RECORD_THROTTLE = 5, | |
785 | PERF_RECORD_UNTHROTTLE = 6, | |
786 | ||
787 | /* | |
788 | * struct { | |
789 | * struct perf_event_header header; | |
790 | * u32 pid, ppid; | |
791 | * u32 tid, ptid; | |
792 | * u64 time; | |
a5cdd40c | 793 | * struct sample_id sample_id; |
607ca46e DH |
794 | * }; |
795 | */ | |
796 | PERF_RECORD_FORK = 7, | |
797 | ||
798 | /* | |
799 | * struct { | |
800 | * struct perf_event_header header; | |
801 | * u32 pid, tid; | |
802 | * | |
803 | * struct read_format values; | |
a5cdd40c | 804 | * struct sample_id sample_id; |
607ca46e DH |
805 | * }; |
806 | */ | |
807 | PERF_RECORD_READ = 8, | |
808 | ||
809 | /* | |
810 | * struct { | |
811 | * struct perf_event_header header; | |
812 | * | |
ff3d527c AH |
813 | * # |
814 | * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. | |
815 | * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position | |
816 | * # is fixed relative to header. | |
817 | * # | |
818 | * | |
819 | * { u64 id; } && PERF_SAMPLE_IDENTIFIER | |
607ca46e DH |
820 | * { u64 ip; } && PERF_SAMPLE_IP |
821 | * { u32 pid, tid; } && PERF_SAMPLE_TID | |
822 | * { u64 time; } && PERF_SAMPLE_TIME | |
823 | * { u64 addr; } && PERF_SAMPLE_ADDR | |
824 | * { u64 id; } && PERF_SAMPLE_ID | |
825 | * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID | |
826 | * { u32 cpu, res; } && PERF_SAMPLE_CPU | |
827 | * { u64 period; } && PERF_SAMPLE_PERIOD | |
828 | * | |
829 | * { struct read_format values; } && PERF_SAMPLE_READ | |
830 | * | |
831 | * { u64 nr, | |
832 | * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN | |
833 | * | |
834 | * # | |
835 | * # The RAW record below is opaque data wrt the ABI | |
836 | * # | |
837 | * # That is, the ABI doesn't make any promises wrt to | |
838 | * # the stability of its content, it may vary depending | |
839 | * # on event, hardware, kernel version and phase of | |
840 | * # the moon. | |
841 | * # | |
842 | * # In other words, PERF_SAMPLE_RAW contents are not an ABI. | |
843 | * # | |
844 | * | |
845 | * { u32 size; | |
846 | * char data[size];}&& PERF_SAMPLE_RAW | |
847 | * | |
b878e7fb VW |
848 | * { u64 nr; |
849 | * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK | |
607ca46e DH |
850 | * |
851 | * { u64 abi; # enum perf_sample_regs_abi | |
852 | * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER | |
853 | * | |
854 | * { u64 size; | |
855 | * char data[size]; | |
856 | * u64 dyn_size; } && PERF_SAMPLE_STACK_USER | |
c3feedf2 AK |
857 | * |
858 | * { u64 weight; } && PERF_SAMPLE_WEIGHT | |
a5cdd40c | 859 | * { u64 data_src; } && PERF_SAMPLE_DATA_SRC |
189b84fb | 860 | * { u64 transaction; } && PERF_SAMPLE_TRANSACTION |
60e2364e SE |
861 | * { u64 abi; # enum perf_sample_regs_abi |
862 | * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR | |
fc7ce9c7 | 863 | * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR |
607ca46e DH |
864 | * }; |
865 | */ | |
866 | PERF_RECORD_SAMPLE = 9, | |
867 | ||
13d7a241 SE |
868 | /* |
869 | * The MMAP2 records are an augmented version of MMAP, they add | |
870 | * maj, min, ino numbers to be used to uniquely identify each mapping | |
871 | * | |
872 | * struct { | |
873 | * struct perf_event_header header; | |
874 | * | |
875 | * u32 pid, tid; | |
876 | * u64 addr; | |
877 | * u64 len; | |
878 | * u64 pgoff; | |
879 | * u32 maj; | |
880 | * u32 min; | |
881 | * u64 ino; | |
882 | * u64 ino_generation; | |
f972eb63 | 883 | * u32 prot, flags; |
13d7a241 SE |
884 | * char filename[]; |
885 | * struct sample_id sample_id; | |
886 | * }; | |
887 | */ | |
888 | PERF_RECORD_MMAP2 = 10, | |
889 | ||
68db7e98 AS |
890 | /* |
891 | * Records that new data landed in the AUX buffer part. | |
892 | * | |
893 | * struct { | |
894 | * struct perf_event_header header; | |
895 | * | |
896 | * u64 aux_offset; | |
897 | * u64 aux_size; | |
898 | * u64 flags; | |
899 | * struct sample_id sample_id; | |
900 | * }; | |
901 | */ | |
902 | PERF_RECORD_AUX = 11, | |
903 | ||
ec0d7729 AS |
904 | /* |
905 | * Indicates that instruction trace has started | |
906 | * | |
907 | * struct { | |
908 | * struct perf_event_header header; | |
909 | * u32 pid; | |
910 | * u32 tid; | |
81df978c | 911 | * struct sample_id sample_id; |
ec0d7729 AS |
912 | * }; |
913 | */ | |
914 | PERF_RECORD_ITRACE_START = 12, | |
915 | ||
f38b0dbb KL |
916 | /* |
917 | * Records the dropped/lost sample number. | |
918 | * | |
919 | * struct { | |
920 | * struct perf_event_header header; | |
921 | * | |
922 | * u64 lost; | |
923 | * struct sample_id sample_id; | |
924 | * }; | |
925 | */ | |
926 | PERF_RECORD_LOST_SAMPLES = 13, | |
927 | ||
45ac1403 AH |
928 | /* |
929 | * Records a context switch in or out (flagged by | |
930 | * PERF_RECORD_MISC_SWITCH_OUT). See also | |
931 | * PERF_RECORD_SWITCH_CPU_WIDE. | |
932 | * | |
933 | * struct { | |
934 | * struct perf_event_header header; | |
935 | * struct sample_id sample_id; | |
936 | * }; | |
937 | */ | |
938 | PERF_RECORD_SWITCH = 14, | |
939 | ||
940 | /* | |
941 | * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and | |
942 | * next_prev_tid that are the next (switching out) or previous | |
943 | * (switching in) pid/tid. | |
944 | * | |
945 | * struct { | |
946 | * struct perf_event_header header; | |
947 | * u32 next_prev_pid; | |
948 | * u32 next_prev_tid; | |
949 | * struct sample_id sample_id; | |
950 | * }; | |
951 | */ | |
952 | PERF_RECORD_SWITCH_CPU_WIDE = 15, | |
953 | ||
e4222673 HB |
954 | /* |
955 | * struct { | |
956 | * struct perf_event_header header; | |
957 | * u32 pid; | |
958 | * u32 tid; | |
959 | * u64 nr_namespaces; | |
960 | * { u64 dev, inode; } [nr_namespaces]; | |
961 | * struct sample_id sample_id; | |
962 | * }; | |
963 | */ | |
964 | PERF_RECORD_NAMESPACES = 16, | |
965 | ||
607ca46e DH |
966 | PERF_RECORD_MAX, /* non-ABI */ |
967 | }; | |
968 | ||
969 | #define PERF_MAX_STACK_DEPTH 127 | |
c85b0334 | 970 | #define PERF_MAX_CONTEXTS_PER_STACK 8 |
607ca46e DH |
971 | |
972 | enum perf_callchain_context { | |
973 | PERF_CONTEXT_HV = (__u64)-32, | |
974 | PERF_CONTEXT_KERNEL = (__u64)-128, | |
975 | PERF_CONTEXT_USER = (__u64)-512, | |
976 | ||
977 | PERF_CONTEXT_GUEST = (__u64)-2048, | |
978 | PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, | |
979 | PERF_CONTEXT_GUEST_USER = (__u64)-2560, | |
980 | ||
981 | PERF_CONTEXT_MAX = (__u64)-4095, | |
982 | }; | |
983 | ||
68db7e98 AS |
984 | /** |
985 | * PERF_RECORD_AUX::flags bits | |
986 | */ | |
987 | #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ | |
2023a0d2 | 988 | #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ |
ae0c2d99 | 989 | #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ |
085b3062 | 990 | #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ |
68db7e98 | 991 | |
643fd0b9 PZ |
992 | #define PERF_FLAG_FD_NO_GROUP (1UL << 0) |
993 | #define PERF_FLAG_FD_OUTPUT (1UL << 1) | |
994 | #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ | |
995 | #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ | |
607ca46e | 996 | |
8c5073db | 997 | #if defined(__LITTLE_ENDIAN_BITFIELD) |
d6be9ad6 SE |
998 | union perf_mem_data_src { |
999 | __u64 val; | |
1000 | struct { | |
1001 | __u64 mem_op:5, /* type of opcode */ | |
1002 | mem_lvl:14, /* memory hierarchy level */ | |
1003 | mem_snoop:5, /* snoop mode */ | |
1004 | mem_lock:2, /* lock instr */ | |
1005 | mem_dtlb:7, /* tlb access */ | |
6ae5fa61 AK |
1006 | mem_lvl_num:4, /* memory hierarchy level number */ |
1007 | mem_remote:1, /* remote */ | |
1008 | mem_snoopx:2, /* snoop mode, ext */ | |
1009 | mem_rsvd:24; | |
d6be9ad6 SE |
1010 | }; |
1011 | }; | |
8c5073db SB |
1012 | #elif defined(__BIG_ENDIAN_BITFIELD) |
1013 | union perf_mem_data_src { | |
1014 | __u64 val; | |
1015 | struct { | |
6ae5fa61 AK |
1016 | __u64 mem_rsvd:24, |
1017 | mem_snoopx:2, /* snoop mode, ext */ | |
1018 | mem_remote:1, /* remote */ | |
1019 | mem_lvl_num:4, /* memory hierarchy level number */ | |
8c5073db SB |
1020 | mem_dtlb:7, /* tlb access */ |
1021 | mem_lock:2, /* lock instr */ | |
1022 | mem_snoop:5, /* snoop mode */ | |
1023 | mem_lvl:14, /* memory hierarchy level */ | |
1024 | mem_op:5; /* type of opcode */ | |
1025 | }; | |
1026 | }; | |
1027 | #else | |
1028 | #error "Unknown endianness" | |
1029 | #endif | |
d6be9ad6 SE |
1030 | |
1031 | /* type of opcode (load/store/prefetch,code) */ | |
1032 | #define PERF_MEM_OP_NA 0x01 /* not available */ | |
1033 | #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ | |
1034 | #define PERF_MEM_OP_STORE 0x04 /* store instruction */ | |
1035 | #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ | |
1036 | #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ | |
1037 | #define PERF_MEM_OP_SHIFT 0 | |
1038 | ||
1039 | /* memory hierarchy (memory level, hit or miss) */ | |
1040 | #define PERF_MEM_LVL_NA 0x01 /* not available */ | |
1041 | #define PERF_MEM_LVL_HIT 0x02 /* hit level */ | |
1042 | #define PERF_MEM_LVL_MISS 0x04 /* miss level */ | |
1043 | #define PERF_MEM_LVL_L1 0x08 /* L1 */ | |
1044 | #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ | |
cc2f5a8a SE |
1045 | #define PERF_MEM_LVL_L2 0x20 /* L2 */ |
1046 | #define PERF_MEM_LVL_L3 0x40 /* L3 */ | |
d6be9ad6 SE |
1047 | #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ |
1048 | #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ | |
1049 | #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ | |
1050 | #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ | |
1051 | #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ | |
1052 | #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ | |
1053 | #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ | |
1054 | #define PERF_MEM_LVL_SHIFT 5 | |
1055 | ||
6ae5fa61 AK |
1056 | #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ |
1057 | #define PERF_MEM_REMOTE_SHIFT 37 | |
1058 | ||
1059 | #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ | |
1060 | #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ | |
1061 | #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ | |
1062 | #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ | |
1063 | /* 5-0xa available */ | |
1064 | #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ | |
1065 | #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ | |
1066 | #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ | |
1067 | #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ | |
1068 | #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ | |
1069 | ||
1070 | #define PERF_MEM_LVLNUM_SHIFT 33 | |
1071 | ||
d6be9ad6 SE |
1072 | /* snoop mode */ |
1073 | #define PERF_MEM_SNOOP_NA 0x01 /* not available */ | |
1074 | #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ | |
1075 | #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ | |
1076 | #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ | |
1077 | #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ | |
1078 | #define PERF_MEM_SNOOP_SHIFT 19 | |
1079 | ||
6ae5fa61 AK |
1080 | #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ |
1081 | /* 1 free */ | |
1082 | #define PERF_MEM_SNOOPX_SHIFT 37 | |
1083 | ||
d6be9ad6 SE |
1084 | /* locked instruction */ |
1085 | #define PERF_MEM_LOCK_NA 0x01 /* not available */ | |
1086 | #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ | |
1087 | #define PERF_MEM_LOCK_SHIFT 24 | |
1088 | ||
1089 | /* TLB access */ | |
1090 | #define PERF_MEM_TLB_NA 0x01 /* not available */ | |
1091 | #define PERF_MEM_TLB_HIT 0x02 /* hit level */ | |
1092 | #define PERF_MEM_TLB_MISS 0x04 /* miss level */ | |
1093 | #define PERF_MEM_TLB_L1 0x08 /* L1 */ | |
1094 | #define PERF_MEM_TLB_L2 0x10 /* L2 */ | |
1095 | #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ | |
1096 | #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ | |
1097 | #define PERF_MEM_TLB_SHIFT 26 | |
1098 | ||
1099 | #define PERF_MEM_S(a, s) \ | |
0d9dfc23 | 1100 | (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) |
d6be9ad6 | 1101 | |
274481de VW |
1102 | /* |
1103 | * single taken branch record layout: | |
1104 | * | |
1105 | * from: source instruction (may not always be a branch insn) | |
1106 | * to: branch target | |
1107 | * mispred: branch target was mispredicted | |
1108 | * predicted: branch target was predicted | |
1109 | * | |
1110 | * support for mispred, predicted is optional. In case it | |
1111 | * is not supported mispred = predicted = 0. | |
1112 | * | |
1113 | * in_tx: running in a hardware transaction | |
1114 | * abort: aborting a hardware transaction | |
71ef3c6b | 1115 | * cycles: cycles from last branch (or 0 if not supported) |
eb0baf8a | 1116 | * type: branch type |
274481de VW |
1117 | */ |
1118 | struct perf_branch_entry { | |
1119 | __u64 from; | |
1120 | __u64 to; | |
1121 | __u64 mispred:1, /* target mispredicted */ | |
1122 | predicted:1,/* target predicted */ | |
1123 | in_tx:1, /* in transaction */ | |
1124 | abort:1, /* transaction abort */ | |
71ef3c6b | 1125 | cycles:16, /* cycle count to last branch */ |
eb0baf8a JY |
1126 | type:4, /* branch type */ |
1127 | reserved:40; | |
274481de VW |
1128 | }; |
1129 | ||
607ca46e | 1130 | #endif /* _UAPI_LINUX_PERF_EVENT_H */ |