[linux-2.6-block.git] / include / uapi / linux / nvme.h

/*
 * Definitions for the NVM Express interface
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _UAPI_LINUX_NVME_H
#define _UAPI_LINUX_NVME_H

#include <linux/types.h>

struct nvme_id_power_state {
	__le16			max_power;	/* centiwatts */
	__u8			rsvd2;
	__u8			flags;
	__le32			entry_lat;	/* microseconds */
	__le32			exit_lat;	/* microseconds */
	__u8			read_tput;
	__u8			read_lat;
	__u8			write_tput;
	__u8			write_lat;
	__le16			idle_power;
	__u8			idle_scale;
	__u8			rsvd19;
	__le16			active_power;
	__u8			active_work_scale;
	__u8			rsvd23[9];
};

enum {
	NVME_PS_FLAGS_MAX_POWER_SCALE	= 1 << 0,
	NVME_PS_FLAGS_NON_OP_STATE	= 1 << 1,
};

struct nvme_id_ctrl {
	__le16			vid;
	__le16			ssvid;
	char			sn[20];
	char			mn[40];
	char			fr[8];
	__u8			rab;
	__u8			ieee[3];
	__u8			mic;
	__u8			mdts;
	__u16			cntlid;
	__u32			ver;
	__u8			rsvd84[172];
	__le16			oacs;
	__u8			acl;
	__u8			aerl;
	__u8			frmw;
	__u8			lpa;
	__u8			elpe;
	__u8			npss;
	__u8			avscc;
	__u8			apsta;
	__le16			wctemp;
	__le16			cctemp;
	__u8			rsvd270[242];
	__u8			sqes;
	__u8			cqes;
	__u8			rsvd514[2];
	__le32			nn;
	__le16			oncs;
	__le16			fuses;
	__u8			fna;
	__u8			vwc;
	__le16			awun;
	__le16			awupf;
	__u8			nvscc;
	__u8			rsvd531;
	__le16			acwu;
	__u8			rsvd534[2];
	__le32			sgls;
	__u8			rsvd540[1508];
	struct nvme_id_power_state	psd[32];
	__u8			vs[1024];
};

enum {
	NVME_CTRL_ONCS_COMPARE			= 1 << 0,
	NVME_CTRL_ONCS_WRITE_UNCORRECTABLE	= 1 << 1,
	NVME_CTRL_ONCS_DSM			= 1 << 2,
	NVME_CTRL_VWC_PRESENT			= 1 << 0,
};

struct nvme_lbaf {
	__le16			ms;
	__u8			ds;
	__u8			rp;
};

struct nvme_id_ns {
	__le64			nsze;
	__le64			ncap;
	__le64			nuse;
	__u8			nsfeat;
	__u8			nlbaf;
	__u8			flbas;
	__u8			mc;
	__u8			dpc;
	__u8			dps;
	__u8			nmic;
	__u8			rescap;
	__u8			fpi;
	__u8			rsvd33;
	__le16			nawun;
	__le16			nawupf;
	__le16			nacwu;
	__u8			rsvd40[80];
	__u8			eui64[8];
	struct nvme_lbaf	lbaf[16];
	__u8			rsvd192[192];
	__u8			vs[3712];
};

enum {
	NVME_NS_FEAT_THIN	= 1 << 0,
	NVME_LBAF_RP_BEST	= 0,
	NVME_LBAF_RP_BETTER	= 1,
	NVME_LBAF_RP_GOOD	= 2,
	NVME_LBAF_RP_DEGRADED	= 3,
};

struct nvme_smart_log {
	__u8			critical_warning;
	__u8			temperature[2];
	__u8			avail_spare;
	__u8			spare_thresh;
	__u8			percent_used;
	__u8			rsvd6[26];
	__u8			data_units_read[16];
	__u8			data_units_written[16];
	__u8			host_reads[16];
	__u8			host_writes[16];
	__u8			ctrl_busy_time[16];
	__u8			power_cycles[16];
	__u8			power_on_hours[16];
	__u8			unsafe_shutdowns[16];
	__u8			media_errors[16];
	__u8			num_err_log_entries[16];
	__le32			warning_temp_time;
	__le32			critical_comp_time;
	__le16			temp_sensor[8];
	__u8			rsvd216[296];
};

enum {
	NVME_SMART_CRIT_SPARE		= 1 << 0,
	NVME_SMART_CRIT_TEMPERATURE	= 1 << 1,
	NVME_SMART_CRIT_RELIABILITY	= 1 << 2,
	NVME_SMART_CRIT_MEDIA		= 1 << 3,
	NVME_SMART_CRIT_VOLATILE_MEMORY	= 1 << 4,
};

struct nvme_lba_range_type {
	__u8			type;
	__u8			attributes;
	__u8			rsvd2[14];
	__u64			slba;
	__u64			nlb;
	__u8			guid[16];
	__u8			rsvd48[16];
};

enum {
	NVME_LBART_TYPE_FS	= 0x01,
	NVME_LBART_TYPE_RAID	= 0x02,
	NVME_LBART_TYPE_CACHE	= 0x03,
	NVME_LBART_TYPE_SWAP	= 0x04,

	NVME_LBART_ATTRIB_TEMP	= 1 << 0,
	NVME_LBART_ATTRIB_HIDE	= 1 << 1,
};

/* I/O commands */

enum nvme_opcode {
	nvme_cmd_flush		= 0x00,
	nvme_cmd_write		= 0x01,
	nvme_cmd_read		= 0x02,
	nvme_cmd_write_uncor	= 0x04,
	nvme_cmd_compare	= 0x05,
	nvme_cmd_dsm		= 0x09,
};

struct nvme_common_command {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__le32			cdw2[2];
	__le64			metadata;
	__le64			prp1;
	__le64			prp2;
	__le32			cdw10[6];
};

struct nvme_rw_command {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2;
	__le64			metadata;
	__le64			prp1;
	__le64			prp2;
	__le64			slba;
	__le16			length;
	__le16			control;
	__le32			dsmgmt;
	__le32			reftag;
	__le16			apptag;
	__le16			appmask;
};

enum {
	NVME_RW_LR			= 1 << 15,
	NVME_RW_FUA			= 1 << 14,
	NVME_RW_DSM_FREQ_UNSPEC		= 0,
	NVME_RW_DSM_FREQ_TYPICAL	= 1,
	NVME_RW_DSM_FREQ_RARE		= 2,
	NVME_RW_DSM_FREQ_READS		= 3,
	NVME_RW_DSM_FREQ_WRITES		= 4,
	NVME_RW_DSM_FREQ_RW		= 5,
	NVME_RW_DSM_FREQ_ONCE		= 6,
	NVME_RW_DSM_FREQ_PREFETCH	= 7,
	NVME_RW_DSM_FREQ_TEMP		= 8,
	NVME_RW_DSM_LATENCY_NONE	= 0 << 4,
	NVME_RW_DSM_LATENCY_IDLE	= 1 << 4,
	NVME_RW_DSM_LATENCY_NORM	= 2 << 4,
	NVME_RW_DSM_LATENCY_LOW		= 3 << 4,
	NVME_RW_DSM_SEQ_REQ		= 1 << 6,
	NVME_RW_DSM_COMPRESSED		= 1 << 7,
};

struct nvme_dsm_cmd {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			nr;
	__le32			attributes;
	__u32			rsvd12[4];
};

enum {
	NVME_DSMGMT_IDR		= 1 << 0,
	NVME_DSMGMT_IDW		= 1 << 1,
	NVME_DSMGMT_AD		= 1 << 2,
};

struct nvme_dsm_range {
	__le32			cattr;
	__le32			nlb;
	__le64			slba;
};

/* Admin commands */

enum nvme_admin_opcode {
	nvme_admin_delete_sq		= 0x00,
	nvme_admin_create_sq		= 0x01,
	nvme_admin_get_log_page		= 0x02,
	nvme_admin_delete_cq		= 0x04,
	nvme_admin_create_cq		= 0x05,
	nvme_admin_identify		= 0x06,
	nvme_admin_abort_cmd		= 0x08,
	nvme_admin_set_features		= 0x09,
	nvme_admin_get_features		= 0x0a,
	nvme_admin_async_event		= 0x0c,
	nvme_admin_activate_fw		= 0x10,
	nvme_admin_download_fw		= 0x11,
	nvme_admin_format_nvm		= 0x80,
	nvme_admin_security_send	= 0x81,
	nvme_admin_security_recv	= 0x82,
};

enum {
	NVME_QUEUE_PHYS_CONTIG	= (1 << 0),
	NVME_CQ_IRQ_ENABLED	= (1 << 1),
	NVME_SQ_PRIO_URGENT	= (0 << 1),
	NVME_SQ_PRIO_HIGH	= (1 << 1),
	NVME_SQ_PRIO_MEDIUM	= (2 << 1),
	NVME_SQ_PRIO_LOW	= (3 << 1),
	NVME_FEAT_ARBITRATION	= 0x01,
	NVME_FEAT_POWER_MGMT	= 0x02,
	NVME_FEAT_LBA_RANGE	= 0x03,
	NVME_FEAT_TEMP_THRESH	= 0x04,
	NVME_FEAT_ERR_RECOVERY	= 0x05,
	NVME_FEAT_VOLATILE_WC	= 0x06,
	NVME_FEAT_NUM_QUEUES	= 0x07,
	NVME_FEAT_IRQ_COALESCE	= 0x08,
	NVME_FEAT_IRQ_CONFIG	= 0x09,
	NVME_FEAT_WRITE_ATOMIC	= 0x0a,
	NVME_FEAT_ASYNC_EVENT	= 0x0b,
	NVME_FEAT_SW_PROGRESS	= 0x0c,
	NVME_LOG_ERROR		= 0x01,
	NVME_LOG_SMART		= 0x02,
	NVME_LOG_FW_SLOT	= 0x03,
	NVME_LOG_RESERVATION	= 0x80,
	NVME_FWACT_REPL		= (0 << 3),
	NVME_FWACT_REPL_ACTV	= (1 << 3),
	NVME_FWACT_ACTV		= (2 << 3),
};

struct nvme_identify {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			cns;
	__u32			rsvd11[5];
};

struct nvme_features {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			fid;
	__le32			dword11;
	__u32			rsvd12[4];
};

struct nvme_create_cq {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__u64			rsvd8;
	__le16			cqid;
	__le16			qsize;
	__le16			cq_flags;
	__le16			irq_vector;
	__u32			rsvd12[4];
};

struct nvme_create_sq {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__u64			rsvd8;
	__le16			sqid;
	__le16			qsize;
	__le16			sq_flags;
	__le16			cqid;
	__u32			rsvd12[4];
};

struct nvme_delete_queue {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[9];
	__le16			qid;
	__u16			rsvd10;
	__u32			rsvd11[5];
};

struct nvme_abort_cmd {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[9];
	__le16			sqid;
	__u16			cid;
	__u32			rsvd11[5];
};

struct nvme_download_firmware {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__le64			prp2;
	__le32			numd;
	__le32			offset;
	__u32			rsvd12[4];
};

struct nvme_format_cmd {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[4];
	__le32			cdw10;
	__u32			rsvd11[5];
};

struct nvme_command {
	union {
		struct nvme_common_command common;
		struct nvme_rw_command rw;
		struct nvme_identify identify;
		struct nvme_features features;
		struct nvme_create_cq create_cq;
		struct nvme_create_sq create_sq;
		struct nvme_delete_queue delete_queue;
		struct nvme_download_firmware dlfw;
		struct nvme_format_cmd format;
		struct nvme_dsm_cmd dsm;
		struct nvme_abort_cmd abort;
	};
};

enum {
	NVME_SC_SUCCESS			= 0x0,
	NVME_SC_INVALID_OPCODE		= 0x1,
	NVME_SC_INVALID_FIELD		= 0x2,
	NVME_SC_CMDID_CONFLICT		= 0x3,
	NVME_SC_DATA_XFER_ERROR		= 0x4,
	NVME_SC_POWER_LOSS		= 0x5,
	NVME_SC_INTERNAL		= 0x6,
	NVME_SC_ABORT_REQ		= 0x7,
	NVME_SC_ABORT_QUEUE		= 0x8,
	NVME_SC_FUSED_FAIL		= 0x9,
	NVME_SC_FUSED_MISSING		= 0xa,
	NVME_SC_INVALID_NS		= 0xb,
	NVME_SC_CMD_SEQ_ERROR		= 0xc,
	NVME_SC_LBA_RANGE		= 0x80,
	NVME_SC_CAP_EXCEEDED		= 0x81,
	NVME_SC_NS_NOT_READY		= 0x82,
	NVME_SC_CQ_INVALID		= 0x100,
	NVME_SC_QID_INVALID		= 0x101,
	NVME_SC_QUEUE_SIZE		= 0x102,
	NVME_SC_ABORT_LIMIT		= 0x103,
	NVME_SC_ABORT_MISSING		= 0x104,
	NVME_SC_ASYNC_LIMIT		= 0x105,
	NVME_SC_FIRMWARE_SLOT		= 0x106,
	NVME_SC_FIRMWARE_IMAGE		= 0x107,
	NVME_SC_INVALID_VECTOR		= 0x108,
	NVME_SC_INVALID_LOG_PAGE	= 0x109,
	NVME_SC_INVALID_FORMAT		= 0x10a,
	NVME_SC_BAD_ATTRIBUTES		= 0x180,
	NVME_SC_WRITE_FAULT		= 0x280,
	NVME_SC_READ_ERROR		= 0x281,
	NVME_SC_GUARD_CHECK		= 0x282,
	NVME_SC_APPTAG_CHECK		= 0x283,
	NVME_SC_REFTAG_CHECK		= 0x284,
	NVME_SC_COMPARE_FAILED		= 0x285,
	NVME_SC_ACCESS_DENIED		= 0x286,
	NVME_SC_DNR			= 0x4000,
};

struct nvme_completion {
	__le32	result;		/* Used by admin commands to return data */
	__u32	rsvd;
	__le16	sq_head;	/* how much of this queue may be reclaimed */
	__le16	sq_id;		/* submission queue that generated this entry */
	__u16	command_id;	/* of the command which completed */
	__le16	status;		/* did the command fail, and if so, why? */
};

struct nvme_user_io {
	__u8	opcode;
	__u8	flags;
	__u16	control;
	__u16	nblocks;
	__u16	rsvd;
	__u64	metadata;
	__u64	addr;
	__u64	slba;
	__u32	dsmgmt;
	__u32	reftag;
	__u16	apptag;
	__u16	appmask;
};

struct nvme_admin_cmd {
	__u8	opcode;
	__u8	flags;
	__u16	rsvd1;
	__u32	nsid;
	__u32	cdw2;
	__u32	cdw3;
	__u64	metadata;
	__u64	addr;
	__u32	metadata_len;
	__u32	data_len;
	__u32	cdw10;
	__u32	cdw11;
	__u32	cdw12;
	__u32	cdw13;
	__u32	cdw14;
	__u32	cdw15;
	__u32	timeout_ms;
	__u32	result;
};

#define NVME_IOCTL_ID		_IO('N', 0x40)
#define NVME_IOCTL_ADMIN_CMD	_IOWR('N', 0x41, struct nvme_admin_cmd)
#define NVME_IOCTL_SUBMIT_IO	_IOW('N', 0x42, struct nvme_user_io)

#endif /* _UAPI_LINUX_NVME_H */
Commit	Line	Data
42c77683 MW	1	/*
42c77683 MW	2	* Definitions for the NVM Express interface
8757ad65	3	* Copyright (c) 2011-2014, Intel Corporation.
42c77683 MW	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
42c77683 MW	13	*/
	14
	15	#ifndef _UAPI_LINUX_NVME_H
	16	#define _UAPI_LINUX_NVME_H
	17
	18	#include <linux/types.h>
	19
	20	struct nvme_id_power_state {
	21	__le16 max_power; /* centiwatts */
685585c2 KB	22	__u8 rsvd2;
685585c2 KB	23	__u8 flags;
42c77683 MW	24	__le32 entry_lat; /* microseconds */
	25	__le32 exit_lat; /* microseconds */
	26	__u8 read_tput;
	27	__u8 read_lat;
	28	__u8 write_tput;
	29	__u8 write_lat;
23372af1 MW	30	__le16 idle_power;
	31	__u8 idle_scale;
	32	__u8 rsvd19;
	33	__le16 active_power;
	34	__u8 active_work_scale;
	35	__u8 rsvd23[9];
42c77683 MW	36	};
42c77683 MW	37
685585c2 KB	38	enum {
	39	NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
	40	NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
	41	};
	42
42c77683 MW	43	struct nvme_id_ctrl {
	44	__le16 vid;
	45	__le16 ssvid;
	46	char sn[20];
	47	char mn[40];
	48	char fr[8];
	49	__u8 rab;
	50	__u8 ieee[3];
	51	__u8 mic;
	52	__u8 mdts;
f2727f7e	53	__u16 cntlid;
23372af1 MW	54	__u32 ver;
23372af1 MW	55	__u8 rsvd84[172];
42c77683 MW	56	__le16 oacs;
	57	__u8 acl;
	58	__u8 aerl;
	59	__u8 frmw;
	60	__u8 lpa;
	61	__u8 elpe;
	62	__u8 npss;
f2727f7e DJL	63	__u8 avscc;
f2727f7e DJL	64	__u8 apsta;
23372af1 MW	65	__le16 wctemp;
	66	__le16 cctemp;
	67	__u8 rsvd270[242];
42c77683 MW	68	__u8 sqes;
	69	__u8 cqes;
	70	__u8 rsvd514[2];
	71	__le32 nn;
	72	__le16 oncs;
	73	__le16 fuses;
	74	__u8 fna;
	75	__u8 vwc;
	76	__le16 awun;
	77	__le16 awupf;
f2727f7e DJL	78	__u8 nvscc;
	79	__u8 rsvd531;
	80	__le16 acwu;
	81	__u8 rsvd534[2];
	82	__le32 sgls;
	83	__u8 rsvd540[1508];
42c77683 MW	84	struct nvme_id_power_state psd[32];
	85	__u8 vs[1024];
	86	};
	87
	88	enum {
	89	NVME_CTRL_ONCS_COMPARE = 1 << 0,
	90	NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
	91	NVME_CTRL_ONCS_DSM = 1 << 2,
a7d2ce28	92	NVME_CTRL_VWC_PRESENT = 1 << 0,
42c77683 MW	93	};
	94
	95	struct nvme_lbaf {
	96	__le16 ms;
	97	__u8 ds;
	98	__u8 rp;
	99	};
	100
	101	struct nvme_id_ns {
	102	__le64 nsze;
	103	__le64 ncap;
	104	__le64 nuse;
	105	__u8 nsfeat;
	106	__u8 nlbaf;
	107	__u8 flbas;
	108	__u8 mc;
	109	__u8 dpc;
	110	__u8 dps;
f2727f7e DJL	111	__u8 nmic;
f2727f7e DJL	112	__u8 rescap;
23372af1 MW	113	__u8 fpi;
	114	__u8 rsvd33;
	115	__le16 nawun;
	116	__le16 nawupf;
	117	__le16 nacwu;
	118	__u8 rsvd40[80];
f2727f7e	119	__u8 eui64[8];
42c77683 MW	120	struct nvme_lbaf lbaf[16];
	121	__u8 rsvd192[192];
	122	__u8 vs[3712];
	123	};
	124
	125	enum {
	126	NVME_NS_FEAT_THIN = 1 << 0,
	127	NVME_LBAF_RP_BEST = 0,
	128	NVME_LBAF_RP_BETTER = 1,
	129	NVME_LBAF_RP_GOOD = 2,
	130	NVME_LBAF_RP_DEGRADED = 3,
	131	};
	132
	133	struct nvme_smart_log {
	134	__u8 critical_warning;
	135	__u8 temperature[2];
	136	__u8 avail_spare;
	137	__u8 spare_thresh;
	138	__u8 percent_used;
	139	__u8 rsvd6[26];
	140	__u8 data_units_read[16];
	141	__u8 data_units_written[16];
	142	__u8 host_reads[16];
	143	__u8 host_writes[16];
	144	__u8 ctrl_busy_time[16];
	145	__u8 power_cycles[16];
	146	__u8 power_on_hours[16];
	147	__u8 unsafe_shutdowns[16];
	148	__u8 media_errors[16];
	149	__u8 num_err_log_entries[16];
23372af1 MW	150	__le32 warning_temp_time;
	151	__le32 critical_comp_time;
	152	__le16 temp_sensor[8];
	153	__u8 rsvd216[296];
42c77683 MW	154	};
	155
	156	enum {
	157	NVME_SMART_CRIT_SPARE = 1 << 0,
	158	NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
	159	NVME_SMART_CRIT_RELIABILITY = 1 << 2,
	160	NVME_SMART_CRIT_MEDIA = 1 << 3,
	161	NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
	162	};
	163
	164	struct nvme_lba_range_type {
	165	__u8 type;
	166	__u8 attributes;
	167	__u8 rsvd2[14];
	168	__u64 slba;
	169	__u64 nlb;
	170	__u8 guid[16];
	171	__u8 rsvd48[16];
	172	};
	173
	174	enum {
	175	NVME_LBART_TYPE_FS = 0x01,
	176	NVME_LBART_TYPE_RAID = 0x02,
	177	NVME_LBART_TYPE_CACHE = 0x03,
	178	NVME_LBART_TYPE_SWAP = 0x04,
	179
	180	NVME_LBART_ATTRIB_TEMP = 1 << 0,
	181	NVME_LBART_ATTRIB_HIDE = 1 << 1,
	182	};
	183
	184	/* I/O commands */
	185
	186	enum nvme_opcode {
	187	nvme_cmd_flush = 0x00,
	188	nvme_cmd_write = 0x01,
	189	nvme_cmd_read = 0x02,
	190	nvme_cmd_write_uncor = 0x04,
	191	nvme_cmd_compare = 0x05,
	192	nvme_cmd_dsm = 0x09,
	193	};
	194
	195	struct nvme_common_command {
	196	__u8 opcode;
	197	__u8 flags;
	198	__u16 command_id;
	199	__le32 nsid;
	200	__le32 cdw2[2];
	201	__le64 metadata;
	202	__le64 prp1;
	203	__le64 prp2;
	204	__le32 cdw10[6];
	205	};
	206
	207	struct nvme_rw_command {
	208	__u8 opcode;
	209	__u8 flags;
	210	__u16 command_id;
	211	__le32 nsid;
	212	__u64 rsvd2;
	213	__le64 metadata;
	214	__le64 prp1;
	215	__le64 prp2;
	216	__le64 slba;
	217	__le16 length;
218	__le16 control;
219	__le32 dsmgmt;
220	__le32 reftag;
221	__le16 apptag;
222	__le16 appmask;
223	};
224
225	enum {
226	NVME_RW_LR = 1 << 15,
227	NVME_RW_FUA = 1 << 14,
228	NVME_RW_DSM_FREQ_UNSPEC = 0,
229	NVME_RW_DSM_FREQ_TYPICAL = 1,
230	NVME_RW_DSM_FREQ_RARE = 2,
231	NVME_RW_DSM_FREQ_READS = 3,
232	NVME_RW_DSM_FREQ_WRITES = 4,
233	NVME_RW_DSM_FREQ_RW = 5,
234	NVME_RW_DSM_FREQ_ONCE = 6,
235	NVME_RW_DSM_FREQ_PREFETCH = 7,
236	NVME_RW_DSM_FREQ_TEMP = 8,
237	NVME_RW_DSM_LATENCY_NONE = 0 << 4,
238	NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
239	NVME_RW_DSM_LATENCY_NORM = 2 << 4,
240	NVME_RW_DSM_LATENCY_LOW = 3 << 4,
241	NVME_RW_DSM_SEQ_REQ = 1 << 6,
242	NVME_RW_DSM_COMPRESSED = 1 << 7,
243	};
244
245	struct nvme_dsm_cmd {
246	__u8 opcode;
247	__u8 flags;
248	__u16 command_id;
249	__le32 nsid;
250	__u64 rsvd2[2];
251	__le64 prp1;
252	__le64 prp2;
253	__le32 nr;
254	__le32 attributes;
255	__u32 rsvd12[4];
256	};
257
258	enum {
259	NVME_DSMGMT_IDR = 1 << 0,
260	NVME_DSMGMT_IDW = 1 << 1,
261	NVME_DSMGMT_AD = 1 << 2,
262	};
263
264	struct nvme_dsm_range {
265	__le32 cattr;
266	__le32 nlb;
267	__le64 slba;
268	};
269
270	/* Admin commands */
271
272	enum nvme_admin_opcode {
273	nvme_admin_delete_sq = 0x00,
274	nvme_admin_create_sq = 0x01,
275	nvme_admin_get_log_page = 0x02,
276	nvme_admin_delete_cq = 0x04,
277	nvme_admin_create_cq = 0x05,
278	nvme_admin_identify = 0x06,
279	nvme_admin_abort_cmd = 0x08,
280	nvme_admin_set_features = 0x09,
281	nvme_admin_get_features = 0x0a,
282	nvme_admin_async_event = 0x0c,
283	nvme_admin_activate_fw = 0x10,
284	nvme_admin_download_fw = 0x11,
285	nvme_admin_format_nvm = 0x80,
286	nvme_admin_security_send = 0x81,
287	nvme_admin_security_recv = 0x82,
288	};
289
290	enum {
291	NVME_QUEUE_PHYS_CONTIG = (1 << 0),
292	NVME_CQ_IRQ_ENABLED = (1 << 1),
293	NVME_SQ_PRIO_URGENT = (0 << 1),
294	NVME_SQ_PRIO_HIGH = (1 << 1),
295	NVME_SQ_PRIO_MEDIUM = (2 << 1),
296	NVME_SQ_PRIO_LOW = (3 << 1),
297	NVME_FEAT_ARBITRATION = 0x01,
298	NVME_FEAT_POWER_MGMT = 0x02,
299	NVME_FEAT_LBA_RANGE = 0x03,
300	NVME_FEAT_TEMP_THRESH = 0x04,
301	NVME_FEAT_ERR_RECOVERY = 0x05,
302	NVME_FEAT_VOLATILE_WC = 0x06,
303	NVME_FEAT_NUM_QUEUES = 0x07,
304	NVME_FEAT_IRQ_COALESCE = 0x08,
305	NVME_FEAT_IRQ_CONFIG = 0x09,
306	NVME_FEAT_WRITE_ATOMIC = 0x0a,
307	NVME_FEAT_ASYNC_EVENT = 0x0b,
308	NVME_FEAT_SW_PROGRESS = 0x0c,
3d69bb6e MW	309	NVME_LOG_ERROR = 0x01,
	310	NVME_LOG_SMART = 0x02,
	311	NVME_LOG_FW_SLOT = 0x03,
	312	NVME_LOG_RESERVATION = 0x80,
42c77683 MW	313	NVME_FWACT_REPL = (0 << 3),
	314	NVME_FWACT_REPL_ACTV = (1 << 3),
	315	NVME_FWACT_ACTV = (2 << 3),
	316	};
	317
	318	struct nvme_identify {
	319	__u8 opcode;
	320	__u8 flags;
	321	__u16 command_id;
	322	__le32 nsid;
	323	__u64 rsvd2[2];
	324	__le64 prp1;
	325	__le64 prp2;
	326	__le32 cns;
	327	__u32 rsvd11[5];
	328	};
	329
	330	struct nvme_features {
	331	__u8 opcode;
	332	__u8 flags;
	333	__u16 command_id;
	334	__le32 nsid;
	335	__u64 rsvd2[2];
	336	__le64 prp1;
	337	__le64 prp2;
	338	__le32 fid;
	339	__le32 dword11;
	340	__u32 rsvd12[4];
	341	};
	342
	343	struct nvme_create_cq {
	344	__u8 opcode;
	345	__u8 flags;
	346	__u16 command_id;
	347	__u32 rsvd1[5];
	348	__le64 prp1;
	349	__u64 rsvd8;
	350	__le16 cqid;
	351	__le16 qsize;
	352	__le16 cq_flags;
	353	__le16 irq_vector;
	354	__u32 rsvd12[4];
	355	};
	356
	357	struct nvme_create_sq {
	358	__u8 opcode;
	359	__u8 flags;
	360	__u16 command_id;
	361	__u32 rsvd1[5];
	362	__le64 prp1;
	363	__u64 rsvd8;
	364	__le16 sqid;
	365	__le16 qsize;
	366	__le16 sq_flags;
	367	__le16 cqid;
	368	__u32 rsvd12[4];
	369	};
	370
	371	struct nvme_delete_queue {
	372	__u8 opcode;
	373	__u8 flags;
	374	__u16 command_id;
	375	__u32 rsvd1[9];
	376	__le16 qid;
377	__u16 rsvd10;
378	__u32 rsvd11[5];
379	};
380
c30341dc KB	381	struct nvme_abort_cmd {
	382	__u8 opcode;
	383	__u8 flags;
	384	__u16 command_id;
	385	__u32 rsvd1[9];
	386	__le16 sqid;
	387	__u16 cid;
	388	__u32 rsvd11[5];
	389	};
	390
42c77683 MW	391	struct nvme_download_firmware {
	392	__u8 opcode;
	393	__u8 flags;
	394	__u16 command_id;
	395	__u32 rsvd1[5];
	396	__le64 prp1;
	397	__le64 prp2;
	398	__le32 numd;
	399	__le32 offset;
	400	__u32 rsvd12[4];
	401	};
	402
	403	struct nvme_format_cmd {
	404	__u8 opcode;
	405	__u8 flags;
	406	__u16 command_id;
	407	__le32 nsid;
	408	__u64 rsvd2[4];
	409	__le32 cdw10;
	410	__u32 rsvd11[5];
	411	};
	412
	413	struct nvme_command {
	414	union {
	415	struct nvme_common_command common;
	416	struct nvme_rw_command rw;
	417	struct nvme_identify identify;
	418	struct nvme_features features;
	419	struct nvme_create_cq create_cq;
	420	struct nvme_create_sq create_sq;
	421	struct nvme_delete_queue delete_queue;
	422	struct nvme_download_firmware dlfw;
	423	struct nvme_format_cmd format;
	424	struct nvme_dsm_cmd dsm;
c30341dc	425	struct nvme_abort_cmd abort;
42c77683 MW	426	};
	427	};
	428
	429	enum {
	430	NVME_SC_SUCCESS = 0x0,
	431	NVME_SC_INVALID_OPCODE = 0x1,
	432	NVME_SC_INVALID_FIELD = 0x2,
	433	NVME_SC_CMDID_CONFLICT = 0x3,
	434	NVME_SC_DATA_XFER_ERROR = 0x4,
	435	NVME_SC_POWER_LOSS = 0x5,
	436	NVME_SC_INTERNAL = 0x6,
	437	NVME_SC_ABORT_REQ = 0x7,
	438	NVME_SC_ABORT_QUEUE = 0x8,
	439	NVME_SC_FUSED_FAIL = 0x9,
	440	NVME_SC_FUSED_MISSING = 0xa,
	441	NVME_SC_INVALID_NS = 0xb,
	442	NVME_SC_CMD_SEQ_ERROR = 0xc,
	443	NVME_SC_LBA_RANGE = 0x80,
	444	NVME_SC_CAP_EXCEEDED = 0x81,
	445	NVME_SC_NS_NOT_READY = 0x82,
	446	NVME_SC_CQ_INVALID = 0x100,
	447	NVME_SC_QID_INVALID = 0x101,
	448	NVME_SC_QUEUE_SIZE = 0x102,
	449	NVME_SC_ABORT_LIMIT = 0x103,
	450	NVME_SC_ABORT_MISSING = 0x104,
	451	NVME_SC_ASYNC_LIMIT = 0x105,
	452	NVME_SC_FIRMWARE_SLOT = 0x106,
	453	NVME_SC_FIRMWARE_IMAGE = 0x107,
	454	NVME_SC_INVALID_VECTOR = 0x108,
	455	NVME_SC_INVALID_LOG_PAGE = 0x109,
	456	NVME_SC_INVALID_FORMAT = 0x10a,
	457	NVME_SC_BAD_ATTRIBUTES = 0x180,
	458	NVME_SC_WRITE_FAULT = 0x280,
	459	NVME_SC_READ_ERROR = 0x281,
	460	NVME_SC_GUARD_CHECK = 0x282,
	461	NVME_SC_APPTAG_CHECK = 0x283,
	462	NVME_SC_REFTAG_CHECK = 0x284,
	463	NVME_SC_COMPARE_FAILED = 0x285,
	464	NVME_SC_ACCESS_DENIED = 0x286,
edd10d33	465	NVME_SC_DNR = 0x4000,
42c77683 MW	466	};
	467
	468	struct nvme_completion {
	469	__le32 result; /* Used by admin commands to return data */
	470	__u32 rsvd;
	471	__le16 sq_head; /* how much of this queue may be reclaimed */
	472	__le16 sq_id; /* submission queue that generated this entry */
	473	__u16 command_id; /* of the command which completed */
	474	__le16 status; /* did the command fail, and if so, why? */
	475	};
	476
	477	struct nvme_user_io {
	478	__u8 opcode;
	479	__u8 flags;
	480	__u16 control;
	481	__u16 nblocks;
	482	__u16 rsvd;
	483	__u64 metadata;
	484	__u64 addr;
	485	__u64 slba;
	486	__u32 dsmgmt;
	487	__u32 reftag;
	488	__u16 apptag;
	489	__u16 appmask;
	490	};
	491
	492	struct nvme_admin_cmd {
	493	__u8 opcode;
	494	__u8 flags;
	495	__u16 rsvd1;
	496	__u32 nsid;
	497	__u32 cdw2;
	498	__u32 cdw3;
	499	__u64 metadata;
	500	__u64 addr;
	501	__u32 metadata_len;
	502	__u32 data_len;
	503	__u32 cdw10;
	504	__u32 cdw11;
	505	__u32 cdw12;
	506	__u32 cdw13;
	507	__u32 cdw14;
	508	__u32 cdw15;
	509	__u32 timeout_ms;
	510	__u32 result;
	511	};
	512
	513	#define NVME_IOCTL_ID _IO('N', 0x40)
	514	#define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
	515	#define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
	516
	517	#endif /* _UAPI_LINUX_NVME_H */