[linux-block.git] / include / uapi / linux / mdio.h

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
 * linux/mdio.h: definitions for MDIO (clause 45) transceivers
 * Copyright 2006-2009 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#ifndef _UAPI__LINUX_MDIO_H__
#define _UAPI__LINUX_MDIO_H__

#include <linux/types.h>
#include <linux/mii.h>

/* MDIO Manageable Devices (MMDs). */
#define MDIO_MMD_PMAPMD		1	/* Physical Medium Attachment/
					 * Physical Medium Dependent */
#define MDIO_MMD_WIS		2	/* WAN Interface Sublayer */
#define MDIO_MMD_PCS		3	/* Physical Coding Sublayer */
#define MDIO_MMD_PHYXS		4	/* PHY Extender Sublayer */
#define MDIO_MMD_DTEXS		5	/* DTE Extender Sublayer */
#define MDIO_MMD_TC		6	/* Transmission Convergence */
#define MDIO_MMD_AN		7	/* Auto-Negotiation */
#define MDIO_MMD_C22EXT		29	/* Clause 22 extension */
#define MDIO_MMD_VEND1		30	/* Vendor specific 1 */
#define MDIO_MMD_VEND2		31	/* Vendor specific 2 */

/* Generic MDIO registers. */
#define MDIO_CTRL1		MII_BMCR
#define MDIO_STAT1		MII_BMSR
#define MDIO_DEVID1		MII_PHYSID1
#define MDIO_DEVID2		MII_PHYSID2
#define MDIO_SPEED		4	/* Speed ability */
#define MDIO_DEVS1		5	/* Devices in package */
#define MDIO_DEVS2		6
#define MDIO_CTRL2		7	/* 10G control 2 */
#define MDIO_STAT2		8	/* 10G status 2 */
#define MDIO_PMA_TXDIS		9	/* 10G PMA/PMD transmit disable */
#define MDIO_PMA_RXDET		10	/* 10G PMA/PMD receive signal detect */
#define MDIO_PMA_EXTABLE	11	/* 10G PMA/PMD extended ability */
#define MDIO_PKGID1		14	/* Package identifier */
#define MDIO_PKGID2		15
#define MDIO_AN_ADVERTISE	16	/* AN advertising (base page) */
#define MDIO_AN_LPA		19	/* AN LP abilities (base page) */
#define MDIO_PCS_EEE_ABLE	20	/* EEE Capability register */
#define MDIO_PCS_EEE_ABLE2	21	/* EEE Capability register 2 */
#define MDIO_PMA_NG_EXTABLE	21	/* 2.5G/5G PMA/PMD extended ability */
#define MDIO_PCS_EEE_WK_ERR	22	/* EEE wake error counter */
#define MDIO_PHYXS_LNSTAT	24	/* PHY XGXS lane state */
#define MDIO_AN_EEE_ADV		60	/* EEE advertisement */
#define MDIO_AN_EEE_LPABLE	61	/* EEE link partner ability */
#define MDIO_AN_EEE_ADV2	62	/* EEE advertisement 2 */
#define MDIO_AN_EEE_LPABLE2	63	/* EEE link partner ability 2 */

/* Media-dependent registers. */
#define MDIO_PMA_10GBT_SWAPPOL	130	/* 10GBASE-T pair swap & polarity */
#define MDIO_PMA_10GBT_TXPWR	131	/* 10GBASE-T TX power control */
#define MDIO_PMA_10GBT_SNR	133	/* 10GBASE-T SNR margin, lane A.
					 * Lanes B-D are numbered 134-136. */
#define MDIO_PMA_10GBR_FECABLE	170	/* 10GBASE-R FEC ability */
#define MDIO_PCS_10GBX_STAT1	24	/* 10GBASE-X PCS status 1 */
#define MDIO_PCS_10GBRT_STAT1	32	/* 10GBASE-R/-T PCS status 1 */
#define MDIO_PCS_10GBRT_STAT2	33	/* 10GBASE-R/-T PCS status 2 */
#define MDIO_AN_10GBT_CTRL	32	/* 10GBASE-T auto-negotiation control */
#define MDIO_AN_10GBT_STAT	33	/* 10GBASE-T auto-negotiation status */

/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
#define MDIO_PMA_LASI_RXCTRL	0x9000	/* RX_ALARM control */
#define MDIO_PMA_LASI_TXCTRL	0x9001	/* TX_ALARM control */
#define MDIO_PMA_LASI_CTRL	0x9002	/* LASI control */
#define MDIO_PMA_LASI_RXSTAT	0x9003	/* RX_ALARM status */
#define MDIO_PMA_LASI_TXSTAT	0x9004	/* TX_ALARM status */
#define MDIO_PMA_LASI_STAT	0x9005	/* LASI status */

/* Control register 1. */
/* Enable extended speed selection */
#define MDIO_CTRL1_SPEEDSELEXT		(BMCR_SPEED1000 | BMCR_SPEED100)
/* All speed selection bits */
#define MDIO_CTRL1_SPEEDSEL		(MDIO_CTRL1_SPEEDSELEXT | 0x003c)
#define MDIO_CTRL1_FULLDPLX		BMCR_FULLDPLX
#define MDIO_CTRL1_LPOWER		BMCR_PDOWN
#define MDIO_CTRL1_RESET		BMCR_RESET
#define MDIO_PMA_CTRL1_LOOPBACK		0x0001
#define MDIO_PMA_CTRL1_SPEED1000	BMCR_SPEED1000
#define MDIO_PMA_CTRL1_SPEED100		BMCR_SPEED100
#define MDIO_PCS_CTRL1_LOOPBACK		BMCR_LOOPBACK
#define MDIO_PHYXS_CTRL1_LOOPBACK	BMCR_LOOPBACK
#define MDIO_AN_CTRL1_RESTART		BMCR_ANRESTART
#define MDIO_AN_CTRL1_ENABLE		BMCR_ANENABLE
#define MDIO_AN_CTRL1_XNP		0x2000	/* Enable extended next page */
#define MDIO_PCS_CTRL1_CLKSTOP_EN	0x400	/* Stop the clock during LPI */

/* 10 Gb/s */
#define MDIO_CTRL1_SPEED10G		(MDIO_CTRL1_SPEEDSELEXT | 0x00)
/* 10PASS-TS/2BASE-TL */
#define MDIO_CTRL1_SPEED10P2B		(MDIO_CTRL1_SPEEDSELEXT | 0x04)
/* 2.5 Gb/s */
#define MDIO_CTRL1_SPEED2_5G		(MDIO_CTRL1_SPEEDSELEXT | 0x18)
/* 5 Gb/s */
#define MDIO_CTRL1_SPEED5G		(MDIO_CTRL1_SPEEDSELEXT | 0x1c)

/* Status register 1. */
#define MDIO_STAT1_LPOWERABLE		0x0002	/* Low-power ability */
#define MDIO_STAT1_LSTATUS		BMSR_LSTATUS
#define MDIO_STAT1_FAULT		0x0080	/* Fault */
#define MDIO_AN_STAT1_LPABLE		0x0001	/* Link partner AN ability */
#define MDIO_AN_STAT1_ABLE		BMSR_ANEGCAPABLE
#define MDIO_AN_STAT1_RFAULT		BMSR_RFAULT
#define MDIO_AN_STAT1_COMPLETE		BMSR_ANEGCOMPLETE
#define MDIO_AN_STAT1_PAGE		0x0040	/* Page received */
#define MDIO_AN_STAT1_XNP		0x0080	/* Extended next page status */

/* Speed register. */
#define MDIO_SPEED_10G			0x0001	/* 10G capable */
#define MDIO_PMA_SPEED_2B		0x0002	/* 2BASE-TL capable */
#define MDIO_PMA_SPEED_10P		0x0004	/* 10PASS-TS capable */
#define MDIO_PMA_SPEED_1000		0x0010	/* 1000M capable */
#define MDIO_PMA_SPEED_100		0x0020	/* 100M capable */
#define MDIO_PMA_SPEED_10		0x0040	/* 10M capable */
#define MDIO_PCS_SPEED_10P2B		0x0002	/* 10PASS-TS/2BASE-TL capable */

/* Device present registers. */
#define MDIO_DEVS_PRESENT(devad)	(1 << (devad))
#define MDIO_DEVS_C22PRESENT		MDIO_DEVS_PRESENT(0)
#define MDIO_DEVS_PMAPMD		MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
#define MDIO_DEVS_WIS			MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
#define MDIO_DEVS_PCS			MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
#define MDIO_DEVS_PHYXS			MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
#define MDIO_DEVS_DTEXS			MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
#define MDIO_DEVS_TC			MDIO_DEVS_PRESENT(MDIO_MMD_TC)
#define MDIO_DEVS_AN			MDIO_DEVS_PRESENT(MDIO_MMD_AN)
#define MDIO_DEVS_C22EXT		MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
#define MDIO_DEVS_VEND1			MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
#define MDIO_DEVS_VEND2			MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)

/* Control register 2. */
#define MDIO_PMA_CTRL2_TYPE		0x000f	/* PMA/PMD type selection */
#define MDIO_PMA_CTRL2_10GBCX4		0x0000	/* 10GBASE-CX4 type */
#define MDIO_PMA_CTRL2_10GBEW		0x0001	/* 10GBASE-EW type */
#define MDIO_PMA_CTRL2_10GBLW		0x0002	/* 10GBASE-LW type */
#define MDIO_PMA_CTRL2_10GBSW		0x0003	/* 10GBASE-SW type */
#define MDIO_PMA_CTRL2_10GBLX4		0x0004	/* 10GBASE-LX4 type */
#define MDIO_PMA_CTRL2_10GBER		0x0005	/* 10GBASE-ER type */
#define MDIO_PMA_CTRL2_10GBLR		0x0006	/* 10GBASE-LR type */
#define MDIO_PMA_CTRL2_10GBSR		0x0007	/* 10GBASE-SR type */
#define MDIO_PMA_CTRL2_10GBLRM		0x0008	/* 10GBASE-LRM type */
#define MDIO_PMA_CTRL2_10GBT		0x0009	/* 10GBASE-T type */
#define MDIO_PMA_CTRL2_10GBKX4		0x000a	/* 10GBASE-KX4 type */
#define MDIO_PMA_CTRL2_10GBKR		0x000b	/* 10GBASE-KR type */
#define MDIO_PMA_CTRL2_1000BT		0x000c	/* 1000BASE-T type */
#define MDIO_PMA_CTRL2_1000BKX		0x000d	/* 1000BASE-KX type */
#define MDIO_PMA_CTRL2_100BTX		0x000e	/* 100BASE-TX type */
#define MDIO_PMA_CTRL2_10BT		0x000f	/* 10BASE-T type */
#define MDIO_PMA_CTRL2_2_5GBT		0x0030  /* 2.5GBaseT type */
#define MDIO_PMA_CTRL2_5GBT		0x0031  /* 5GBaseT type */
#define MDIO_PCS_CTRL2_TYPE		0x0003	/* PCS type selection */
#define MDIO_PCS_CTRL2_10GBR		0x0000	/* 10GBASE-R type */
#define MDIO_PCS_CTRL2_10GBX		0x0001	/* 10GBASE-X type */
#define MDIO_PCS_CTRL2_10GBW		0x0002	/* 10GBASE-W type */
#define MDIO_PCS_CTRL2_10GBT		0x0003	/* 10GBASE-T type */

/* Status register 2. */
#define MDIO_STAT2_RXFAULT		0x0400	/* Receive fault */
#define MDIO_STAT2_TXFAULT		0x0800	/* Transmit fault */
#define MDIO_STAT2_DEVPRST		0xc000	/* Device present */
#define MDIO_STAT2_DEVPRST_VAL		0x8000	/* Device present value */
#define MDIO_PMA_STAT2_LBABLE		0x0001	/* PMA loopback ability */
#define MDIO_PMA_STAT2_10GBEW		0x0002	/* 10GBASE-EW ability */
#define MDIO_PMA_STAT2_10GBLW		0x0004	/* 10GBASE-LW ability */
#define MDIO_PMA_STAT2_10GBSW		0x0008	/* 10GBASE-SW ability */
#define MDIO_PMA_STAT2_10GBLX4		0x0010	/* 10GBASE-LX4 ability */
#define MDIO_PMA_STAT2_10GBER		0x0020	/* 10GBASE-ER ability */
#define MDIO_PMA_STAT2_10GBLR		0x0040	/* 10GBASE-LR ability */
#define MDIO_PMA_STAT2_10GBSR		0x0080	/* 10GBASE-SR ability */
#define MDIO_PMD_STAT2_TXDISAB		0x0100	/* PMD TX disable ability */
#define MDIO_PMA_STAT2_EXTABLE		0x0200	/* Extended abilities */
#define MDIO_PMA_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
#define MDIO_PMA_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */
#define MDIO_PCS_STAT2_10GBR		0x0001	/* 10GBASE-R capable */
#define MDIO_PCS_STAT2_10GBX		0x0002	/* 10GBASE-X capable */
#define MDIO_PCS_STAT2_10GBW		0x0004	/* 10GBASE-W capable */
#define MDIO_PCS_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
#define MDIO_PCS_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */

/* Transmit disable register. */
#define MDIO_PMD_TXDIS_GLOBAL		0x0001	/* Global PMD TX disable */
#define MDIO_PMD_TXDIS_0		0x0002	/* PMD TX disable 0 */
#define MDIO_PMD_TXDIS_1		0x0004	/* PMD TX disable 1 */
#define MDIO_PMD_TXDIS_2		0x0008	/* PMD TX disable 2 */
#define MDIO_PMD_TXDIS_3		0x0010	/* PMD TX disable 3 */

/* Receive signal detect register. */
#define MDIO_PMD_RXDET_GLOBAL		0x0001	/* Global PMD RX signal detect */
#define MDIO_PMD_RXDET_0		0x0002	/* PMD RX signal detect 0 */
#define MDIO_PMD_RXDET_1		0x0004	/* PMD RX signal detect 1 */
#define MDIO_PMD_RXDET_2		0x0008	/* PMD RX signal detect 2 */
#define MDIO_PMD_RXDET_3		0x0010	/* PMD RX signal detect 3 */

/* Extended abilities register. */
#define MDIO_PMA_EXTABLE_10GCX4		0x0001	/* 10GBASE-CX4 ability */
#define MDIO_PMA_EXTABLE_10GBLRM	0x0002	/* 10GBASE-LRM ability */
#define MDIO_PMA_EXTABLE_10GBT		0x0004	/* 10GBASE-T ability */
#define MDIO_PMA_EXTABLE_10GBKX4	0x0008	/* 10GBASE-KX4 ability */
#define MDIO_PMA_EXTABLE_10GBKR		0x0010	/* 10GBASE-KR ability */
#define MDIO_PMA_EXTABLE_1000BT		0x0020	/* 1000BASE-T ability */
#define MDIO_PMA_EXTABLE_1000BKX	0x0040	/* 1000BASE-KX ability */
#define MDIO_PMA_EXTABLE_100BTX		0x0080	/* 100BASE-TX ability */
#define MDIO_PMA_EXTABLE_10BT		0x0100	/* 10BASE-T ability */
#define MDIO_PMA_EXTABLE_NBT		0x4000  /* 2.5/5GBASE-T ability */

/* PHY XGXS lane state register. */
#define MDIO_PHYXS_LNSTAT_SYNC0		0x0001
#define MDIO_PHYXS_LNSTAT_SYNC1		0x0002
#define MDIO_PHYXS_LNSTAT_SYNC2		0x0004
#define MDIO_PHYXS_LNSTAT_SYNC3		0x0008
#define MDIO_PHYXS_LNSTAT_ALIGN		0x1000

/* PMA 10GBASE-T pair swap & polarity */
#define MDIO_PMA_10GBT_SWAPPOL_ABNX	0x0001	/* Pair A/B uncrossed */
#define MDIO_PMA_10GBT_SWAPPOL_CDNX	0x0002	/* Pair C/D uncrossed */
#define MDIO_PMA_10GBT_SWAPPOL_AREV	0x0100	/* Pair A polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_BREV	0x0200	/* Pair B polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_CREV	0x0400	/* Pair C polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_DREV	0x0800	/* Pair D polarity reversed */

/* PMA 10GBASE-T TX power register. */
#define MDIO_PMA_10GBT_TXPWR_SHORT	0x0001	/* Short-reach mode */

/* PMA 10GBASE-T SNR registers. */
/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
#define MDIO_PMA_10GBT_SNR_BIAS		0x8000
#define MDIO_PMA_10GBT_SNR_MAX		127

/* PMA 10GBASE-R FEC ability register. */
#define MDIO_PMA_10GBR_FECABLE_ABLE	0x0001	/* FEC ability */
#define MDIO_PMA_10GBR_FECABLE_ERRABLE	0x0002	/* FEC error indic. ability */

/* PCS 10GBASE-R/-T status register 1. */
#define MDIO_PCS_10GBRT_STAT1_BLKLK	0x0001	/* Block lock attained */

/* PCS 10GBASE-R/-T status register 2. */
#define MDIO_PCS_10GBRT_STAT2_ERR	0x00ff
#define MDIO_PCS_10GBRT_STAT2_BER	0x3f00

/* AN 10GBASE-T control register. */
#define MDIO_AN_10GBT_CTRL_ADV2_5G	0x0080	/* Advertise 2.5GBASE-T */
#define MDIO_AN_10GBT_CTRL_ADV5G	0x0100	/* Advertise 5GBASE-T */
#define MDIO_AN_10GBT_CTRL_ADV10G	0x1000	/* Advertise 10GBASE-T */

/* AN 10GBASE-T status register. */
#define MDIO_AN_10GBT_STAT_LP2_5G	0x0020  /* LP is 2.5GBT capable */
#define MDIO_AN_10GBT_STAT_LP5G		0x0040  /* LP is 5GBT capable */
#define MDIO_AN_10GBT_STAT_LPTRR	0x0200	/* LP training reset req. */
#define MDIO_AN_10GBT_STAT_LPLTABLE	0x0400	/* LP loop timing ability */
#define MDIO_AN_10GBT_STAT_LP10G	0x0800	/* LP is 10GBT capable */
#define MDIO_AN_10GBT_STAT_REMOK	0x1000	/* Remote OK */
#define MDIO_AN_10GBT_STAT_LOCOK	0x2000	/* Local OK */
#define MDIO_AN_10GBT_STAT_MS		0x4000	/* Master/slave config */
#define MDIO_AN_10GBT_STAT_MSFLT	0x8000	/* Master/slave config fault */

/* EEE Supported/Advertisement/LP Advertisement registers.
 *
 * EEE capability Register (3.20), Advertisement (7.60) and
 * Link partner ability (7.61) registers have and can use the same identical
 * bit masks.
 */
#define MDIO_AN_EEE_ADV_100TX	0x0002	/* Advertise 100TX EEE cap */
#define MDIO_AN_EEE_ADV_1000T	0x0004	/* Advertise 1000T EEE cap */
/* Note: the two defines above can be potentially used by the user-land
 * and cannot remove them now.
 * So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros
 * using the previous ones (that can be considered obsolete).
 */
#define MDIO_EEE_100TX		MDIO_AN_EEE_ADV_100TX	/* 100TX EEE cap */
#define MDIO_EEE_1000T		MDIO_AN_EEE_ADV_1000T	/* 1000T EEE cap */
#define MDIO_EEE_10GT		0x0008	/* 10GT EEE cap */
#define MDIO_EEE_1000KX		0x0010	/* 1000KX EEE cap */
#define MDIO_EEE_10GKX4		0x0020	/* 10G KX4 EEE cap */
#define MDIO_EEE_10GKR		0x0040	/* 10G KR EEE cap */
#define MDIO_EEE_40GR_FW	0x0100	/* 40G R fast wake */
#define MDIO_EEE_40GR_DS	0x0200	/* 40G R deep sleep */
#define MDIO_EEE_100GR_FW	0x1000	/* 100G R fast wake */
#define MDIO_EEE_100GR_DS	0x2000	/* 100G R deep sleep */

#define MDIO_EEE_2_5GT		0x0001	/* 2.5GT EEE cap */
#define MDIO_EEE_5GT		0x0002	/* 5GT EEE cap */

/* 2.5G/5G Extended abilities register. */
#define MDIO_PMA_NG_EXTABLE_2_5GBT	0x0001	/* 2.5GBASET ability */
#define MDIO_PMA_NG_EXTABLE_5GBT	0x0002	/* 5GBASET ability */

/* LASI RX_ALARM control/status registers. */
#define MDIO_PMA_LASI_RX_PHYXSLFLT	0x0001	/* PHY XS RX local fault */
#define MDIO_PMA_LASI_RX_PCSLFLT	0x0008	/* PCS RX local fault */
#define MDIO_PMA_LASI_RX_PMALFLT	0x0010	/* PMA/PMD RX local fault */
#define MDIO_PMA_LASI_RX_OPTICPOWERFLT	0x0020	/* RX optical power fault */
#define MDIO_PMA_LASI_RX_WISLFLT	0x0200	/* WIS local fault */

/* LASI TX_ALARM control/status registers. */
#define MDIO_PMA_LASI_TX_PHYXSLFLT	0x0001	/* PHY XS TX local fault */
#define MDIO_PMA_LASI_TX_PCSLFLT	0x0008	/* PCS TX local fault */
#define MDIO_PMA_LASI_TX_PMALFLT	0x0010	/* PMA/PMD TX local fault */
#define MDIO_PMA_LASI_TX_LASERPOWERFLT	0x0080	/* Laser output power fault */
#define MDIO_PMA_LASI_TX_LASERTEMPFLT	0x0100	/* Laser temperature fault */
#define MDIO_PMA_LASI_TX_LASERBICURRFLT	0x0200	/* Laser bias current fault */

/* LASI control/status registers. */
#define MDIO_PMA_LASI_LSALARM		0x0001	/* LS_ALARM enable/status */
#define MDIO_PMA_LASI_TXALARM		0x0002	/* TX_ALARM enable/status */
#define MDIO_PMA_LASI_RXALARM		0x0004	/* RX_ALARM enable/status */

/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */

#define MDIO_PHY_ID_C45			0x8000
#define MDIO_PHY_ID_PRTAD		0x03e0
#define MDIO_PHY_ID_DEVAD		0x001f
#define MDIO_PHY_ID_C45_MASK						\
	(MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)

static inline __u16 mdio_phy_id_c45(int prtad, int devad)
{
	return MDIO_PHY_ID_C45 | (prtad << 5) | devad;
}

/* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/
#define MDIO_USXGMII_EEE_CLK_STP	0x0080	/* EEE clock stop supported */
#define MDIO_USXGMII_EEE		0x0100	/* EEE supported */
#define MDIO_USXGMII_SPD_MASK		0x0e00	/* USXGMII speed mask */
#define MDIO_USXGMII_FULL_DUPLEX	0x1000	/* USXGMII full duplex */
#define MDIO_USXGMII_DPX_SPD_MASK	0x1e00	/* USXGMII duplex and speed bits */
#define MDIO_USXGMII_10			0x0000	/* 10Mbps */
#define MDIO_USXGMII_10HALF		0x0000	/* 10Mbps half-duplex */
#define MDIO_USXGMII_10FULL		0x1000	/* 10Mbps full-duplex */
#define MDIO_USXGMII_100		0x0200	/* 100Mbps */
#define MDIO_USXGMII_100HALF		0x0200	/* 100Mbps half-duplex */
#define MDIO_USXGMII_100FULL		0x1200	/* 100Mbps full-duplex */
#define MDIO_USXGMII_1000		0x0400	/* 1000Mbps */
#define MDIO_USXGMII_1000HALF		0x0400	/* 1000Mbps half-duplex */
#define MDIO_USXGMII_1000FULL		0x1400	/* 1000Mbps full-duplex */
#define MDIO_USXGMII_10G		0x0600	/* 10Gbps */
#define MDIO_USXGMII_10GHALF		0x0600	/* 10Gbps half-duplex */
#define MDIO_USXGMII_10GFULL		0x1600	/* 10Gbps full-duplex */
#define MDIO_USXGMII_2500		0x0800	/* 2500Mbps */
#define MDIO_USXGMII_2500HALF		0x0800	/* 2500Mbps half-duplex */
#define MDIO_USXGMII_2500FULL		0x1800	/* 2500Mbps full-duplex */
#define MDIO_USXGMII_5000		0x0a00	/* 5000Mbps */
#define MDIO_USXGMII_5000HALF		0x0a00	/* 5000Mbps half-duplex */
#define MDIO_USXGMII_5000FULL		0x1a00	/* 5000Mbps full-duplex */
#define MDIO_USXGMII_LINK		0x8000	/* PHY link with copper-side partner */

#endif /* _UAPI__LINUX_MDIO_H__ */
Commit	Line	Data
e2be04c7	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
607ca46e DH	2	/*
	3	* linux/mdio.h: definitions for MDIO (clause 45) transceivers
	4	* Copyright 2006-2009 Solarflare Communications Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation, incorporated herein by reference.
	9	*/
	10
	11	#ifndef _UAPI__LINUX_MDIO_H__
	12	#define _UAPI__LINUX_MDIO_H__
	13
	14	#include <linux/types.h>
	15	#include <linux/mii.h>
	16
	17	/* MDIO Manageable Devices (MMDs). */
	18	#define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/
	19	* Physical Medium Dependent */
	20	#define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */
	21	#define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */
	22	#define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
	23	#define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
	24	#define MDIO_MMD_TC 6 /* Transmission Convergence */
	25	#define MDIO_MMD_AN 7 /* Auto-Negotiation */
	26	#define MDIO_MMD_C22EXT 29 /* Clause 22 extension */
	27	#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */
	28	#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */
	29
	30	/* Generic MDIO registers. */
	31	#define MDIO_CTRL1 MII_BMCR
	32	#define MDIO_STAT1 MII_BMSR
	33	#define MDIO_DEVID1 MII_PHYSID1
	34	#define MDIO_DEVID2 MII_PHYSID2
	35	#define MDIO_SPEED 4 /* Speed ability */
	36	#define MDIO_DEVS1 5 /* Devices in package */
	37	#define MDIO_DEVS2 6
	38	#define MDIO_CTRL2 7 /* 10G control 2 */
	39	#define MDIO_STAT2 8 /* 10G status 2 */
	40	#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
	41	#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
	42	#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
	43	#define MDIO_PKGID1 14 /* Package identifier */
	44	#define MDIO_PKGID2 15
	45	#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
	46	#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
	47	#define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */
99b60d56	48	#define MDIO_PCS_EEE_ABLE2 21 /* EEE Capability register 2 */
7fd8afa8	49	#define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
607ca46e DH	50	#define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */
	51	#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
	52	#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
	53	#define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */
99b60d56 HK	54	#define MDIO_AN_EEE_ADV2 62 /* EEE advertisement 2 */
99b60d56 HK	55	#define MDIO_AN_EEE_LPABLE2 63 /* EEE link partner ability 2 */
607ca46e DH	56
	57	/* Media-dependent registers. */
	58	#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
	59	#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
	60	#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
	61	* Lanes B-D are numbered 134-136. */
	62	#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
	63	#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
	64	#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
	65	#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
	66	#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
	67	#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
	68
	69	/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
	70	#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
	71	#define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
	72	#define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
	73	#define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
	74	#define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
	75	#define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
	76
	77	/* Control register 1. */
	78	/* Enable extended speed selection */
	79	#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 \| BMCR_SPEED100)
	80	/* All speed selection bits */
	81	#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT \| 0x003c)
	82	#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
	83	#define MDIO_CTRL1_LPOWER BMCR_PDOWN
	84	#define MDIO_CTRL1_RESET BMCR_RESET
	85	#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
	86	#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
	87	#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
	88	#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
	89	#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
	90	#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
	91	#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
	92	#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
	93	#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */
	94
	95	/* 10 Gb/s */
	96	#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT \| 0x00)
	97	/* 10PASS-TS/2BASE-TL */
	98	#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT \| 0x04)
7fd8afa8 MC	99	/* 2.5 Gb/s */
	100	#define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT \| 0x18)
	101	/* 5 Gb/s */
	102	#define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT \| 0x1c)
607ca46e DH	103
	104	/* Status register 1. */
	105	#define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */
	106	#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
	107	#define MDIO_STAT1_FAULT 0x0080 /* Fault */
	108	#define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */
	109	#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE
	110	#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT
	111	#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE
	112	#define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */
	113	#define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */
	114
	115	/* Speed register. */
	116	#define MDIO_SPEED_10G 0x0001 /* 10G capable */
	117	#define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
	118	#define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
	119	#define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */
	120	#define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */
	121	#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */
	122	#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
	123
	124	/* Device present registers. */
	125	#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
3b5e74e0	126	#define MDIO_DEVS_C22PRESENT MDIO_DEVS_PRESENT(0)
607ca46e DH	127	#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
	128	#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
	129	#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
	130	#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
	131	#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
	132	#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC)
	133	#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
	134	#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
998a8a83 HK	135	#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
998a8a83 HK	136	#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
607ca46e DH	137
	138	/* Control register 2. */
	139	#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */
	140	#define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
	141	#define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */
	142	#define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */
	143	#define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */
	144	#define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */
	145	#define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */
	146	#define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */
	147	#define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */
	148	#define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */
	149	#define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */
	150	#define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */
	151	#define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */
	152	#define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */
	153	#define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */
	154	#define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */
	155	#define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
7fd8afa8 MC	156	#define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */
7fd8afa8 MC	157	#define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */
607ca46e DH	158	#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */
	159	#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
	160	#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
	161	#define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */
	162	#define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */
	163
	164	/* Status register 2. */
	165	#define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */
	166	#define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */
	167	#define MDIO_STAT2_DEVPRST 0xc000 /* Device present */
	168	#define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */
	169	#define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */
	170	#define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */
	171	#define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */
	172	#define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */
	173	#define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */
	174	#define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */
	175	#define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */
	176	#define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */
	177	#define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */
	178	#define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */
	179	#define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
	180	#define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
	181	#define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */
	182	#define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */
	183	#define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */
	184	#define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
	185	#define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
	186
	187	/* Transmit disable register. */
	188	#define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */
	189	#define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */
	190	#define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */
	191	#define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */
	192	#define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */
	193
	194	/* Receive signal detect register. */
	195	#define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */
	196	#define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */
	197	#define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */
	198	#define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */
	199	#define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */
	200
	201	/* Extended abilities register. */
	202	#define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */
	203	#define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */
	204	#define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */
	205	#define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */
	206	#define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */
	207	#define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */
	208	#define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
	209	#define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
	210	#define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
7fd8afa8	211	#define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */
607ca46e DH	212
	213	/* PHY XGXS lane state register. */
	214	#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
	215	#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002
	216	#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004
	217	#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008
	218	#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000
	219
	220	/* PMA 10GBASE-T pair swap & polarity */
	221	#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */
	222	#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */
	223	#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */
	224	#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */
	225	#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */
	226	#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */
	227
	228	/* PMA 10GBASE-T TX power register. */
	229	#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */
	230
	231	/* PMA 10GBASE-T SNR registers. */
	232	/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
	233	#define MDIO_PMA_10GBT_SNR_BIAS 0x8000
	234	#define MDIO_PMA_10GBT_SNR_MAX 127
	235
	236	/* PMA 10GBASE-R FEC ability register. */
	237	#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */
	238	#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */
	239
	240	/* PCS 10GBASE-R/-T status register 1. */
	241	#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */
	242
	243	/* PCS 10GBASE-R/-T status register 2. */
	244	#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff
	245	#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00
	246
	247	/* AN 10GBASE-T control register. */
7fd8afa8 MC	248	#define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */
7fd8afa8 MC	249	#define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */
607ca46e DH	250	#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */
	251
	252	/* AN 10GBASE-T status register. */
7fd8afa8 MC	253	#define MDIO_AN_10GBT_STAT_LP2_5G 0x0020 /* LP is 2.5GBT capable */
7fd8afa8 MC	254	#define MDIO_AN_10GBT_STAT_LP5G 0x0040 /* LP is 5GBT capable */
607ca46e DH	255	#define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */
	256	#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */
	257	#define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */
	258	#define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */
	259	#define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */
	260	#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
	261	#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
	262
	263	/* EEE Supported/Advertisement/LP Advertisement registers.
	264	*
	265	* EEE capability Register (3.20), Advertisement (7.60) and
	266	* Link partner ability (7.61) registers have and can use the same identical
	267	* bit masks.
	268	*/
	269	#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
	270	#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */
	271	/* Note: the two defines above can be potentially used by the user-land
	272	* and cannot remove them now.
	273	* So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros
	274	* using the previous ones (that can be considered obsolete).
	275	*/
	276	#define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */
	277	#define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T /* 1000T EEE cap */
	278	#define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */
	279	#define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */
	280	#define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */
	281	#define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */
99b60d56 HK	282	#define MDIO_EEE_40GR_FW 0x0100 /* 40G R fast wake */
	283	#define MDIO_EEE_40GR_DS 0x0200 /* 40G R deep sleep */
	284	#define MDIO_EEE_100GR_FW 0x1000 /* 100G R fast wake */
	285	#define MDIO_EEE_100GR_DS 0x2000 /* 100G R deep sleep */
	286
	287	#define MDIO_EEE_2_5GT 0x0001 /* 2.5GT EEE cap */
	288	#define MDIO_EEE_5GT 0x0002 /* 5GT EEE cap */
607ca46e	289
7fd8afa8 MC	290	/* 2.5G/5G Extended abilities register. */
	291	#define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 /* 2.5GBASET ability */
	292	#define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 /* 5GBASET ability */
	293
607ca46e DH	294	/* LASI RX_ALARM control/status registers. */
	295	#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
	296	#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */
	297	#define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */
	298	#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */
	299	#define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */
	300
	301	/* LASI TX_ALARM control/status registers. */
	302	#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */
	303	#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */
	304	#define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */
	305	#define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */
	306	#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */
	307	#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */
	308
	309	/* LASI control/status registers. */
	310	#define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */
	311	#define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */
	312	#define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */
	313
	314	/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
	315
	316	#define MDIO_PHY_ID_C45 0x8000
	317	#define MDIO_PHY_ID_PRTAD 0x03e0
	318	#define MDIO_PHY_ID_DEVAD 0x001f
	319	#define MDIO_PHY_ID_C45_MASK \
	320	(MDIO_PHY_ID_C45 \| MDIO_PHY_ID_PRTAD \| MDIO_PHY_ID_DEVAD)
	321
	322	static inline __u16 mdio_phy_id_c45(int prtad, int devad)
	323	{
	324	return MDIO_PHY_ID_C45 \| (prtad << 5) \| devad;
	325	}
	326
c4471ad9 MW	327	/* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/
	328	#define MDIO_USXGMII_EEE_CLK_STP 0x0080 /* EEE clock stop supported */
	329	#define MDIO_USXGMII_EEE 0x0100 /* EEE supported */
	330	#define MDIO_USXGMII_SPD_MASK 0x0e00 /* USXGMII speed mask */
	331	#define MDIO_USXGMII_FULL_DUPLEX 0x1000 /* USXGMII full duplex */
	332	#define MDIO_USXGMII_DPX_SPD_MASK 0x1e00 /* USXGMII duplex and speed bits */
	333	#define MDIO_USXGMII_10 0x0000 /* 10Mbps */
	334	#define MDIO_USXGMII_10HALF 0x0000 /* 10Mbps half-duplex */
	335	#define MDIO_USXGMII_10FULL 0x1000 /* 10Mbps full-duplex */
	336	#define MDIO_USXGMII_100 0x0200 /* 100Mbps */
	337	#define MDIO_USXGMII_100HALF 0x0200 /* 100Mbps half-duplex */
	338	#define MDIO_USXGMII_100FULL 0x1200 /* 100Mbps full-duplex */
	339	#define MDIO_USXGMII_1000 0x0400 /* 1000Mbps */
	340	#define MDIO_USXGMII_1000HALF 0x0400 /* 1000Mbps half-duplex */
	341	#define MDIO_USXGMII_1000FULL 0x1400 /* 1000Mbps full-duplex */
	342	#define MDIO_USXGMII_10G 0x0600 /* 10Gbps */
	343	#define MDIO_USXGMII_10GHALF 0x0600 /* 10Gbps half-duplex */
	344	#define MDIO_USXGMII_10GFULL 0x1600 /* 10Gbps full-duplex */
	345	#define MDIO_USXGMII_2500 0x0800 /* 2500Mbps */
	346	#define MDIO_USXGMII_2500HALF 0x0800 /* 2500Mbps half-duplex */
	347	#define MDIO_USXGMII_2500FULL 0x1800 /* 2500Mbps full-duplex */
	348	#define MDIO_USXGMII_5000 0x0a00 /* 5000Mbps */
	349	#define MDIO_USXGMII_5000HALF 0x0a00 /* 5000Mbps half-duplex */
	350	#define MDIO_USXGMII_5000FULL 0x1a00 /* 5000Mbps full-duplex */
	351	#define MDIO_USXGMII_LINK 0x8000 /* PHY link with copper-side partner */
	352
607ca46e	353	#endif /* _UAPI__LINUX_MDIO_H__ */