[linux-block.git] / include / uapi / linux / kfd_ioctl.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef KFD_IOCTL_H_INCLUDED
#define KFD_IOCTL_H_INCLUDED

#include <drm/drm.h>
#include <linux/ioctl.h>

#define KFD_IOCTL_MAJOR_VERSION 1
#define KFD_IOCTL_MINOR_VERSION 1

struct kfd_ioctl_get_version_args {
	__u32 major_version;	/* from KFD */
	__u32 minor_version;	/* from KFD */
};

/* For kfd_ioctl_create_queue_args.queue_type. */
#define KFD_IOC_QUEUE_TYPE_COMPUTE		0x0
#define KFD_IOC_QUEUE_TYPE_SDMA			0x1
#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL		0x2
#define KFD_IOC_QUEUE_TYPE_SDMA_XGMI		0x3

#define KFD_MAX_QUEUE_PERCENTAGE	100
#define KFD_MAX_QUEUE_PRIORITY		15

struct kfd_ioctl_create_queue_args {
	__u64 ring_base_address;	/* to KFD */
	__u64 write_pointer_address;	/* from KFD */
	__u64 read_pointer_address;	/* from KFD */
	__u64 doorbell_offset;	/* from KFD */

	__u32 ring_size;		/* to KFD */
	__u32 gpu_id;		/* to KFD */
	__u32 queue_type;		/* to KFD */
	__u32 queue_percentage;	/* to KFD */
	__u32 queue_priority;	/* to KFD */
	__u32 queue_id;		/* from KFD */

	__u64 eop_buffer_address;	/* to KFD */
	__u64 eop_buffer_size;	/* to KFD */
	__u64 ctx_save_restore_address; /* to KFD */
	__u32 ctx_save_restore_size;	/* to KFD */
	__u32 ctl_stack_size;		/* to KFD */
};

struct kfd_ioctl_destroy_queue_args {
	__u32 queue_id;		/* to KFD */
	__u32 pad;
};

struct kfd_ioctl_update_queue_args {
	__u64 ring_base_address;	/* to KFD */

	__u32 queue_id;		/* to KFD */
	__u32 ring_size;		/* to KFD */
	__u32 queue_percentage;	/* to KFD */
	__u32 queue_priority;	/* to KFD */
};

struct kfd_ioctl_set_cu_mask_args {
	__u32 queue_id;		/* to KFD */
	__u32 num_cu_mask;		/* to KFD */
	__u64 cu_mask_ptr;		/* to KFD */
};

struct kfd_ioctl_get_queue_wave_state_args {
	__u64 ctl_stack_address;	/* to KFD */
	__u32 ctl_stack_used_size;	/* from KFD */
	__u32 save_area_used_size;	/* from KFD */
	__u32 queue_id;			/* to KFD */
	__u32 pad;
};

/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
#define KFD_IOC_CACHE_POLICY_COHERENT 0
#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1

struct kfd_ioctl_set_memory_policy_args {
	__u64 alternate_aperture_base;	/* to KFD */
	__u64 alternate_aperture_size;	/* to KFD */

	__u32 gpu_id;			/* to KFD */
	__u32 default_policy;		/* to KFD */
	__u32 alternate_policy;		/* to KFD */
	__u32 pad;
};

/*
 * All counters are monotonic. They are used for profiling of compute jobs.
 * The profiling is done by userspace.
 *
 * In case of GPU reset, the counter should not be affected.
 */

struct kfd_ioctl_get_clock_counters_args {
	__u64 gpu_clock_counter;	/* from KFD */
	__u64 cpu_clock_counter;	/* from KFD */
	__u64 system_clock_counter;	/* from KFD */
	__u64 system_clock_freq;	/* from KFD */

	__u32 gpu_id;		/* to KFD */
	__u32 pad;
};

struct kfd_process_device_apertures {
	__u64 lds_base;		/* from KFD */
	__u64 lds_limit;		/* from KFD */
	__u64 scratch_base;		/* from KFD */
	__u64 scratch_limit;		/* from KFD */
	__u64 gpuvm_base;		/* from KFD */
	__u64 gpuvm_limit;		/* from KFD */
	__u32 gpu_id;		/* from KFD */
	__u32 pad;
};

/*
 * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use
 * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an
 * unlimited number of GPUs.
 */
#define NUM_OF_SUPPORTED_GPUS 7
struct kfd_ioctl_get_process_apertures_args {
	struct kfd_process_device_apertures
			process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */

	/* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
	__u32 num_of_nodes;
	__u32 pad;
};

struct kfd_ioctl_get_process_apertures_new_args {
	/* User allocated. Pointer to struct kfd_process_device_apertures
	 * filled in by Kernel
	 */
	__u64 kfd_process_device_apertures_ptr;
	/* to KFD - indicates amount of memory present in
	 *  kfd_process_device_apertures_ptr
	 * from KFD - Number of entries filled by KFD.
	 */
	__u32 num_of_nodes;
	__u32 pad;
};

#define MAX_ALLOWED_NUM_POINTS    100
#define MAX_ALLOWED_AW_BUFF_SIZE 4096
#define MAX_ALLOWED_WAC_BUFF_SIZE  128

struct kfd_ioctl_dbg_register_args {
	__u32 gpu_id;		/* to KFD */
	__u32 pad;
};

struct kfd_ioctl_dbg_unregister_args {
	__u32 gpu_id;		/* to KFD */
	__u32 pad;
};

struct kfd_ioctl_dbg_address_watch_args {
	__u64 content_ptr;		/* a pointer to the actual content */
	__u32 gpu_id;		/* to KFD */
	__u32 buf_size_in_bytes;	/*including gpu_id and buf_size */
};

struct kfd_ioctl_dbg_wave_control_args {
	__u64 content_ptr;		/* a pointer to the actual content */
	__u32 gpu_id;		/* to KFD */
	__u32 buf_size_in_bytes;	/*including gpu_id and buf_size */
};

/* Matching HSA_EVENTTYPE */
#define KFD_IOC_EVENT_SIGNAL			0
#define KFD_IOC_EVENT_NODECHANGE		1
#define KFD_IOC_EVENT_DEVICESTATECHANGE		2
#define KFD_IOC_EVENT_HW_EXCEPTION		3
#define KFD_IOC_EVENT_SYSTEM_EVENT		4
#define KFD_IOC_EVENT_DEBUG_EVENT		5
#define KFD_IOC_EVENT_PROFILE_EVENT		6
#define KFD_IOC_EVENT_QUEUE_EVENT		7
#define KFD_IOC_EVENT_MEMORY			8

#define KFD_IOC_WAIT_RESULT_COMPLETE		0
#define KFD_IOC_WAIT_RESULT_TIMEOUT		1
#define KFD_IOC_WAIT_RESULT_FAIL		2

#define KFD_SIGNAL_EVENT_LIMIT			4096

/* For kfd_event_data.hw_exception_data.reset_type. */
#define KFD_HW_EXCEPTION_WHOLE_GPU_RESET	0
#define KFD_HW_EXCEPTION_PER_ENGINE_RESET	1

/* For kfd_event_data.hw_exception_data.reset_cause. */
#define KFD_HW_EXCEPTION_GPU_HANG	0
#define KFD_HW_EXCEPTION_ECC		1

/* For kfd_hsa_memory_exception_data.ErrorType */
#define KFD_MEM_ERR_NO_RAS		0
#define KFD_MEM_ERR_SRAM_ECC		1
#define KFD_MEM_ERR_POISON_CONSUMED	2
#define KFD_MEM_ERR_GPU_HANG		3

struct kfd_ioctl_create_event_args {
	__u64 event_page_offset;	/* from KFD */
	__u32 event_trigger_data;	/* from KFD - signal events only */
	__u32 event_type;		/* to KFD */
	__u32 auto_reset;		/* to KFD */
	__u32 node_id;		/* to KFD - only valid for certain
							event types */
	__u32 event_id;		/* from KFD */
	__u32 event_slot_index;	/* from KFD */
};

struct kfd_ioctl_destroy_event_args {
	__u32 event_id;		/* to KFD */
	__u32 pad;
};

struct kfd_ioctl_set_event_args {
	__u32 event_id;		/* to KFD */
	__u32 pad;
};

struct kfd_ioctl_reset_event_args {
	__u32 event_id;		/* to KFD */
	__u32 pad;
};

struct kfd_memory_exception_failure {
	__u32 NotPresent;	/* Page not present or supervisor privilege */
	__u32 ReadOnly;	/* Write access to a read-only page */
	__u32 NoExecute;	/* Execute access to a page marked NX */
	__u32 imprecise;	/* Can't determine the	exact fault address */
};

/* memory exception data*/
struct kfd_hsa_memory_exception_data {
	struct kfd_memory_exception_failure failure;
	__u64 va;
	__u32 gpu_id;
	__u32 ErrorType; /* 0 = no RAS error,
			  * 1 = ECC_SRAM,
			  * 2 = Link_SYNFLOOD (poison),
			  * 3 = GPU hang (not attributable to a specific cause),
			  * other values reserved
			  */
};

/* hw exception data */
struct kfd_hsa_hw_exception_data {
	__u32 reset_type;
	__u32 reset_cause;
	__u32 memory_lost;
	__u32 gpu_id;
};

/* Event data */
struct kfd_event_data {
	union {
		struct kfd_hsa_memory_exception_data memory_exception_data;
		struct kfd_hsa_hw_exception_data hw_exception_data;
	};				/* From KFD */
	__u64 kfd_event_data_ext;	/* pointer to an extension structure
					   for future exception types */
	__u32 event_id;		/* to KFD */
	__u32 pad;
};

struct kfd_ioctl_wait_events_args {
	__u64 events_ptr;		/* pointed to struct
					   kfd_event_data array, to KFD */
	__u32 num_events;		/* to KFD */
	__u32 wait_for_all;		/* to KFD */
	__u32 timeout;		/* to KFD */
	__u32 wait_result;		/* from KFD */
};

struct kfd_ioctl_set_scratch_backing_va_args {
	__u64 va_addr;	/* to KFD */
	__u32 gpu_id;	/* to KFD */
	__u32 pad;
};

struct kfd_ioctl_get_tile_config_args {
	/* to KFD: pointer to tile array */
	__u64 tile_config_ptr;
	/* to KFD: pointer to macro tile array */
	__u64 macro_tile_config_ptr;
	/* to KFD: array size allocated by user mode
	 * from KFD: array size filled by kernel
	 */
	__u32 num_tile_configs;
	/* to KFD: array size allocated by user mode
	 * from KFD: array size filled by kernel
	 */
	__u32 num_macro_tile_configs;

	__u32 gpu_id;		/* to KFD */
	__u32 gb_addr_config;	/* from KFD */
	__u32 num_banks;		/* from KFD */
	__u32 num_ranks;		/* from KFD */
	/* struct size can be extended later if needed
	 * without breaking ABI compatibility
	 */
};

struct kfd_ioctl_set_trap_handler_args {
	__u64 tba_addr;		/* to KFD */
	__u64 tma_addr;		/* to KFD */
	__u32 gpu_id;		/* to KFD */
	__u32 pad;
};

struct kfd_ioctl_acquire_vm_args {
	__u32 drm_fd;	/* to KFD */
	__u32 gpu_id;	/* to KFD */
};

/* Allocation flags: memory types */
#define KFD_IOC_ALLOC_MEM_FLAGS_VRAM		(1 << 0)
#define KFD_IOC_ALLOC_MEM_FLAGS_GTT		(1 << 1)
#define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR		(1 << 2)
#define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL	(1 << 3)
#define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP	(1 << 4)
/* Allocation flags: attributes/access options */
#define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE	(1 << 31)
#define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE	(1 << 30)
#define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC		(1 << 29)
#define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE	(1 << 28)
#define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM	(1 << 27)
#define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT	(1 << 26)

/* Allocate memory for later SVM (shared virtual memory) mapping.
 *
 * @va_addr:     virtual address of the memory to be allocated
 *               all later mappings on all GPUs will use this address
 * @size:        size in bytes
 * @handle:      buffer handle returned to user mode, used to refer to
 *               this allocation for mapping, unmapping and freeing
 * @mmap_offset: for CPU-mapping the allocation by mmapping a render node
 *               for userptrs this is overloaded to specify the CPU address
 * @gpu_id:      device identifier
 * @flags:       memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above
 */
struct kfd_ioctl_alloc_memory_of_gpu_args {
	__u64 va_addr;		/* to KFD */
	__u64 size;		/* to KFD */
	__u64 handle;		/* from KFD */
	__u64 mmap_offset;	/* to KFD (userptr), from KFD (mmap offset) */
	__u32 gpu_id;		/* to KFD */
	__u32 flags;
};

/* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu
 *
 * @handle: memory handle returned by alloc
 */
struct kfd_ioctl_free_memory_of_gpu_args {
	__u64 handle;		/* to KFD */
};

/* Map memory to one or more GPUs
 *
 * @handle:                memory handle returned by alloc
 * @device_ids_array_ptr:  array of gpu_ids (__u32 per device)
 * @n_devices:             number of devices in the array
 * @n_success:             number of devices mapped successfully
 *
 * @n_success returns information to the caller how many devices from
 * the start of the array have mapped the buffer successfully. It can
 * be passed into a subsequent retry call to skip those devices. For
 * the first call the caller should initialize it to 0.
 *
 * If the ioctl completes with return code 0 (success), n_success ==
 * n_devices.
 */
struct kfd_ioctl_map_memory_to_gpu_args {
	__u64 handle;			/* to KFD */
	__u64 device_ids_array_ptr;	/* to KFD */
	__u32 n_devices;		/* to KFD */
	__u32 n_success;		/* to/from KFD */
};

/* Unmap memory from one or more GPUs
 *
 * same arguments as for mapping
 */
struct kfd_ioctl_unmap_memory_from_gpu_args {
	__u64 handle;			/* to KFD */
	__u64 device_ids_array_ptr;	/* to KFD */
	__u32 n_devices;		/* to KFD */
	__u32 n_success;		/* to/from KFD */
};

struct kfd_ioctl_get_dmabuf_info_args {
	__u64 size;		/* from KFD */
	__u64 metadata_ptr;	/* to KFD */
	__u32 metadata_size;	/* to KFD (space allocated by user)
				 * from KFD (actual metadata size)
				 */
	__u32 gpu_id;	/* from KFD */
	__u32 flags;		/* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */
	__u32 dmabuf_fd;	/* to KFD */
};

struct kfd_ioctl_import_dmabuf_args {
	__u64 va_addr;	/* to KFD */
	__u64 handle;	/* from KFD */
	__u32 gpu_id;	/* to KFD */
	__u32 dmabuf_fd;	/* to KFD */
};

/* Register offset inside the remapped mmio page
 */
enum kfd_mmio_remap {
	KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0,
	KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4,
};

#define AMDKFD_IOCTL_BASE 'K'
#define AMDKFD_IO(nr)			_IO(AMDKFD_IOCTL_BASE, nr)
#define AMDKFD_IOR(nr, type)		_IOR(AMDKFD_IOCTL_BASE, nr, type)
#define AMDKFD_IOW(nr, type)		_IOW(AMDKFD_IOCTL_BASE, nr, type)
#define AMDKFD_IOWR(nr, type)		_IOWR(AMDKFD_IOCTL_BASE, nr, type)

#define AMDKFD_IOC_GET_VERSION			\
		AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)

#define AMDKFD_IOC_CREATE_QUEUE			\
		AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)

#define AMDKFD_IOC_DESTROY_QUEUE		\
		AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)

#define AMDKFD_IOC_SET_MEMORY_POLICY		\
		AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)

#define AMDKFD_IOC_GET_CLOCK_COUNTERS		\
		AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)

#define AMDKFD_IOC_GET_PROCESS_APERTURES	\
		AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)

#define AMDKFD_IOC_UPDATE_QUEUE			\
		AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)

#define AMDKFD_IOC_CREATE_EVENT			\
		AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)

#define AMDKFD_IOC_DESTROY_EVENT		\
		AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)

#define AMDKFD_IOC_SET_EVENT			\
		AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)

#define AMDKFD_IOC_RESET_EVENT			\
		AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)

#define AMDKFD_IOC_WAIT_EVENTS			\
		AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)

#define AMDKFD_IOC_DBG_REGISTER			\
		AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)

#define AMDKFD_IOC_DBG_UNREGISTER		\
		AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)

#define AMDKFD_IOC_DBG_ADDRESS_WATCH		\
		AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)

#define AMDKFD_IOC_DBG_WAVE_CONTROL		\
		AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)

#define AMDKFD_IOC_SET_SCRATCH_BACKING_VA	\
		AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args)

#define AMDKFD_IOC_GET_TILE_CONFIG                                      \
		AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args)

#define AMDKFD_IOC_SET_TRAP_HANDLER		\
		AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args)

#define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW	\
		AMDKFD_IOWR(0x14,		\
			struct kfd_ioctl_get_process_apertures_new_args)

#define AMDKFD_IOC_ACQUIRE_VM			\
		AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args)

#define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU		\
		AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args)

#define AMDKFD_IOC_FREE_MEMORY_OF_GPU		\
		AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args)

#define AMDKFD_IOC_MAP_MEMORY_TO_GPU		\
		AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args)

#define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU	\
		AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args)

#define AMDKFD_IOC_SET_CU_MASK		\
		AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args)

#define AMDKFD_IOC_GET_QUEUE_WAVE_STATE		\
		AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)

#define AMDKFD_IOC_GET_DMABUF_INFO		\
		AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args)

#define AMDKFD_IOC_IMPORT_DMABUF		\
		AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)

#define AMDKFD_COMMAND_START		0x01
#define AMDKFD_COMMAND_END		0x1E

#endif
Commit	Line	Data
b7facbae OG	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22
	23	#ifndef KFD_IOCTL_H_INCLUDED
	24	#define KFD_IOCTL_H_INCLUDED
	25
472b46c3	26	#include <drm/drm.h>
b7facbae OG	27	#include <linux/ioctl.h>
	28
	29	#define KFD_IOCTL_MAJOR_VERSION 1
29a5d3eb	30	#define KFD_IOCTL_MINOR_VERSION 1
b7facbae OG	31
b7facbae OG	32	struct kfd_ioctl_get_version_args {
472b46c3 MR	33	__u32 major_version; /* from KFD */
472b46c3 MR	34	__u32 minor_version; /* from KFD */
b7facbae OG	35	};
	36
	37	/* For kfd_ioctl_create_queue_args.queue_type. */
1b4670f6 OZ	38	#define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0
	39	#define KFD_IOC_QUEUE_TYPE_SDMA 0x1
	40	#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2
	41	#define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3
b7facbae OG	42
	43	#define KFD_MAX_QUEUE_PERCENTAGE 100
	44	#define KFD_MAX_QUEUE_PRIORITY 15
	45
	46	struct kfd_ioctl_create_queue_args {
472b46c3 MR	47	__u64 ring_base_address; /* to KFD */
	48	__u64 write_pointer_address; /* from KFD */
	49	__u64 read_pointer_address; /* from KFD */
	50	__u64 doorbell_offset; /* from KFD */
	51
	52	__u32 ring_size; /* to KFD */
	53	__u32 gpu_id; /* to KFD */
	54	__u32 queue_type; /* to KFD */
	55	__u32 queue_percentage; /* to KFD */
	56	__u32 queue_priority; /* to KFD */
	57	__u32 queue_id; /* from KFD */
	58
	59	__u64 eop_buffer_address; /* to KFD */
	60	__u64 eop_buffer_size; /* to KFD */
	61	__u64 ctx_save_restore_address; /* to KFD */
373d7080 FK	62	__u32 ctx_save_restore_size; /* to KFD */
373d7080 FK	63	__u32 ctl_stack_size; /* to KFD */
b7facbae OG	64	};
	65
	66	struct kfd_ioctl_destroy_queue_args {
472b46c3 MR	67	__u32 queue_id; /* to KFD */
472b46c3 MR	68	__u32 pad;
b7facbae OG	69	};
	70
	71	struct kfd_ioctl_update_queue_args {
472b46c3	72	__u64 ring_base_address; /* to KFD */
b7facbae	73
472b46c3 MR	74	__u32 queue_id; /* to KFD */
	75	__u32 ring_size; /* to KFD */
	76	__u32 queue_percentage; /* to KFD */
	77	__u32 queue_priority; /* to KFD */
b7facbae OG	78	};
b7facbae OG	79
a7fe68a1 FK	80	struct kfd_ioctl_set_cu_mask_args {
	81	__u32 queue_id; /* to KFD */
	82	__u32 num_cu_mask; /* to KFD */
	83	__u64 cu_mask_ptr; /* to KFD */
	84	};
	85
5df099e8	86	struct kfd_ioctl_get_queue_wave_state_args {
8e7f9171 DL	87	__u64 ctl_stack_address; /* to KFD */
	88	__u32 ctl_stack_used_size; /* from KFD */
	89	__u32 save_area_used_size; /* from KFD */
	90	__u32 queue_id; /* to KFD */
	91	__u32 pad;
5df099e8 JC	92	};
5df099e8 JC	93
b7facbae OG	94	/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
	95	#define KFD_IOC_CACHE_POLICY_COHERENT 0
	96	#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
	97
	98	struct kfd_ioctl_set_memory_policy_args {
472b46c3 MR	99	__u64 alternate_aperture_base; /* to KFD */
472b46c3 MR	100	__u64 alternate_aperture_size; /* to KFD */
b7facbae	101
472b46c3 MR	102	__u32 gpu_id; /* to KFD */
	103	__u32 default_policy; /* to KFD */
	104	__u32 alternate_policy; /* to KFD */
	105	__u32 pad;
b7facbae OG	106	};
	107
	108	/*
	109	* All counters are monotonic. They are used for profiling of compute jobs.
	110	* The profiling is done by userspace.
	111	*
	112	* In case of GPU reset, the counter should not be affected.
	113	*/
	114
	115	struct kfd_ioctl_get_clock_counters_args {
472b46c3 MR	116	__u64 gpu_clock_counter; /* from KFD */
	117	__u64 cpu_clock_counter; /* from KFD */
	118	__u64 system_clock_counter; /* from KFD */
	119	__u64 system_clock_freq; /* from KFD */
b7facbae	120
472b46c3 MR	121	__u32 gpu_id; /* to KFD */
472b46c3 MR	122	__u32 pad;
b7facbae OG	123	};
b7facbae OG	124
b7facbae	125	struct kfd_process_device_apertures {
472b46c3 MR	126	__u64 lds_base; /* from KFD */
	127	__u64 lds_limit; /* from KFD */
	128	__u64 scratch_base; /* from KFD */
	129	__u64 scratch_limit; /* from KFD */
	130	__u64 gpuvm_base; /* from KFD */
	131	__u64 gpuvm_limit; /* from KFD */
	132	__u32 gpu_id; /* from KFD */
	133	__u32 pad;
b7facbae OG	134	};
b7facbae OG	135
c7bcbfa4 FK	136	/*
	137	* AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use
	138	* AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an
	139	* unlimited number of GPUs.
	140	*/
	141	#define NUM_OF_SUPPORTED_GPUS 7
b7facbae OG	142	struct kfd_ioctl_get_process_apertures_args {
	143	struct kfd_process_device_apertures
	144	process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */
	145
	146	/* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
472b46c3 MR	147	__u32 num_of_nodes;
472b46c3 MR	148	__u32 pad;
b7facbae OG	149	};
b7facbae OG	150
c7bcbfa4 FK	151	struct kfd_ioctl_get_process_apertures_new_args {
	152	/* User allocated. Pointer to struct kfd_process_device_apertures
	153	* filled in by Kernel
	154	*/
	155	__u64 kfd_process_device_apertures_ptr;
	156	/* to KFD - indicates amount of memory present in
	157	* kfd_process_device_apertures_ptr
	158	* from KFD - Number of entries filled by KFD.
	159	*/
	160	__u32 num_of_nodes;
	161	__u32 pad;
	162	};
	163
aef11009 YS	164	#define MAX_ALLOWED_NUM_POINTS 100
	165	#define MAX_ALLOWED_AW_BUFF_SIZE 4096
	166	#define MAX_ALLOWED_WAC_BUFF_SIZE 128
	167
	168	struct kfd_ioctl_dbg_register_args {
472b46c3 MR	169	__u32 gpu_id; /* to KFD */
472b46c3 MR	170	__u32 pad;
aef11009 YS	171	};
	172
	173	struct kfd_ioctl_dbg_unregister_args {
472b46c3 MR	174	__u32 gpu_id; /* to KFD */
472b46c3 MR	175	__u32 pad;
aef11009 YS	176	};
	177
	178	struct kfd_ioctl_dbg_address_watch_args {
472b46c3 MR	179	__u64 content_ptr; /* a pointer to the actual content */
	180	__u32 gpu_id; /* to KFD */
	181	__u32 buf_size_in_bytes; /including gpu_id and buf_size /
aef11009 YS	182	};
	183
	184	struct kfd_ioctl_dbg_wave_control_args {
472b46c3 MR	185	__u64 content_ptr; /* a pointer to the actual content */
	186	__u32 gpu_id; /* to KFD */
	187	__u32 buf_size_in_bytes; /including gpu_id and buf_size /
aef11009 YS	188	};
aef11009 YS	189
29a5d3eb AL	190	/* Matching HSA_EVENTTYPE */
	191	#define KFD_IOC_EVENT_SIGNAL 0
	192	#define KFD_IOC_EVENT_NODECHANGE 1
	193	#define KFD_IOC_EVENT_DEVICESTATECHANGE 2
	194	#define KFD_IOC_EVENT_HW_EXCEPTION 3
	195	#define KFD_IOC_EVENT_SYSTEM_EVENT 4
	196	#define KFD_IOC_EVENT_DEBUG_EVENT 5
	197	#define KFD_IOC_EVENT_PROFILE_EVENT 6
	198	#define KFD_IOC_EVENT_QUEUE_EVENT 7
	199	#define KFD_IOC_EVENT_MEMORY 8
	200
	201	#define KFD_IOC_WAIT_RESULT_COMPLETE 0
	202	#define KFD_IOC_WAIT_RESULT_TIMEOUT 1
	203	#define KFD_IOC_WAIT_RESULT_FAIL 2
	204
7e86a365	205	#define KFD_SIGNAL_EVENT_LIMIT 4096
29a5d3eb	206
0c119aba SL	207	/* For kfd_event_data.hw_exception_data.reset_type. */
	208	#define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0
	209	#define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1
	210
	211	/* For kfd_event_data.hw_exception_data.reset_cause. */
	212	#define KFD_HW_EXCEPTION_GPU_HANG 0
	213	#define KFD_HW_EXCEPTION_ECC 1
	214
9b54d201 EH	215	/* For kfd_hsa_memory_exception_data.ErrorType */
	216	#define KFD_MEM_ERR_NO_RAS 0
	217	#define KFD_MEM_ERR_SRAM_ECC 1
	218	#define KFD_MEM_ERR_POISON_CONSUMED 2
	219	#define KFD_MEM_ERR_GPU_HANG 3
0c119aba	220
29a5d3eb	221	struct kfd_ioctl_create_event_args {
472b46c3 MR	222	__u64 event_page_offset; /* from KFD */
	223	__u32 event_trigger_data; /* from KFD - signal events only */
	224	__u32 event_type; /* to KFD */
	225	__u32 auto_reset; /* to KFD */
	226	__u32 node_id; /* to KFD - only valid for certain
29a5d3eb	227	event types */
472b46c3 MR	228	__u32 event_id; /* from KFD */
472b46c3 MR	229	__u32 event_slot_index; /* from KFD */
29a5d3eb AL	230	};
	231
	232	struct kfd_ioctl_destroy_event_args {
472b46c3 MR	233	__u32 event_id; /* to KFD */
472b46c3 MR	234	__u32 pad;
29a5d3eb AL	235	};
	236
	237	struct kfd_ioctl_set_event_args {
472b46c3 MR	238	__u32 event_id; /* to KFD */
472b46c3 MR	239	__u32 pad;
29a5d3eb AL	240	};
	241
	242	struct kfd_ioctl_reset_event_args {
472b46c3 MR	243	__u32 event_id; /* to KFD */
472b46c3 MR	244	__u32 pad;
29a5d3eb AL	245	};
	246
	247	struct kfd_memory_exception_failure {
472b46c3 MR	248	__u32 NotPresent; /* Page not present or supervisor privilege */
	249	__u32 ReadOnly; /* Write access to a read-only page */
	250	__u32 NoExecute; /* Execute access to a page marked NX */
2640c3fa	251	__u32 imprecise; /* Can't determine the exact fault address */
29a5d3eb AL	252	};
	253
	254	/* memory exception data*/
	255	struct kfd_hsa_memory_exception_data {
	256	struct kfd_memory_exception_failure failure;
472b46c3 MR	257	__u64 va;
472b46c3 MR	258	__u32 gpu_id;
9b54d201 EH	259	__u32 ErrorType; /* 0 = no RAS error,
	260	* 1 = ECC_SRAM,
	261	* 2 = Link_SYNFLOOD (poison),
	262	* 3 = GPU hang (not attributable to a specific cause),
	263	* other values reserved
	264	*/
29a5d3eb AL	265	};
29a5d3eb AL	266
0c119aba SL	267	/* hw exception data */
0c119aba SL	268	struct kfd_hsa_hw_exception_data {
aba11838 DL	269	__u32 reset_type;
	270	__u32 reset_cause;
	271	__u32 memory_lost;
	272	__u32 gpu_id;
0c119aba SL	273	};
	274
	275	/* Event data */
29a5d3eb AL	276	struct kfd_event_data {
	277	union {
	278	struct kfd_hsa_memory_exception_data memory_exception_data;
0c119aba	279	struct kfd_hsa_hw_exception_data hw_exception_data;
29a5d3eb	280	}; /* From KFD */
472b46c3	281	__u64 kfd_event_data_ext; /* pointer to an extension structure
29a5d3eb	282	for future exception types */
472b46c3 MR	283	__u32 event_id; /* to KFD */
472b46c3 MR	284	__u32 pad;
29a5d3eb AL	285	};
	286
	287	struct kfd_ioctl_wait_events_args {
472b46c3	288	__u64 events_ptr; /* pointed to struct
aef11009	289	kfd_event_data array, to KFD */
472b46c3 MR	290	__u32 num_events; /* to KFD */
	291	__u32 wait_for_all; /* to KFD */
	292	__u32 timeout; /* to KFD */
	293	__u32 wait_result; /* from KFD */
29a5d3eb AL	294	};
29a5d3eb AL	295
6a1c9510	296	struct kfd_ioctl_set_scratch_backing_va_args {
b4d08520 DL	297	__u64 va_addr; /* to KFD */
	298	__u32 gpu_id; /* to KFD */
	299	__u32 pad;
6a1c9510 MR	300	};
6a1c9510 MR	301
5d71dbc3 YZ	302	struct kfd_ioctl_get_tile_config_args {
5d71dbc3 YZ	303	/* to KFD: pointer to tile array */
b4d08520	304	__u64 tile_config_ptr;
5d71dbc3	305	/* to KFD: pointer to macro tile array */
b4d08520	306	__u64 macro_tile_config_ptr;
5d71dbc3 YZ	307	/* to KFD: array size allocated by user mode
	308	* from KFD: array size filled by kernel
	309	*/
b4d08520	310	__u32 num_tile_configs;
5d71dbc3 YZ	311	/* to KFD: array size allocated by user mode
	312	* from KFD: array size filled by kernel
	313	*/
b4d08520	314	__u32 num_macro_tile_configs;
5d71dbc3	315
b4d08520 DL	316	__u32 gpu_id; /* to KFD */
	317	__u32 gb_addr_config; /* from KFD */
	318	__u32 num_banks; /* from KFD */
	319	__u32 num_ranks; /* from KFD */
5d71dbc3 YZ	320	/* struct size can be extended later if needed
	321	* without breaking ABI compatibility
	322	*/
	323	};
	324
d7b9bd22	325	struct kfd_ioctl_set_trap_handler_args {
a1102445 FK	326	__u64 tba_addr; /* to KFD */
	327	__u64 tma_addr; /* to KFD */
	328	__u32 gpu_id; /* to KFD */
	329	__u32 pad;
d7b9bd22 FK	330	};
d7b9bd22 FK	331
5ec7e028 FK	332	struct kfd_ioctl_acquire_vm_args {
	333	__u32 drm_fd; /* to KFD */
	334	__u32 gpu_id; /* to KFD */
	335	};
	336
	337	/* Allocation flags: memory types */
	338	#define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0)
	339	#define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1)
	340	#define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2)
	341	#define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3)
d8e408a8	342	#define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4)
5ec7e028 FK	343	/* Allocation flags: attributes/access options */
	344	#define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31)
	345	#define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30)
	346	#define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29)
	347	#define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28)
	348	#define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27)
	349	#define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26)
	350
	351	/* Allocate memory for later SVM (shared virtual memory) mapping.
	352	*
	353	* @va_addr: virtual address of the memory to be allocated
	354	* all later mappings on all GPUs will use this address
	355	* @size: size in bytes
	356	* @handle: buffer handle returned to user mode, used to refer to
	357	* this allocation for mapping, unmapping and freeing
	358	* @mmap_offset: for CPU-mapping the allocation by mmapping a render node
	359	* for userptrs this is overloaded to specify the CPU address
	360	* @gpu_id: device identifier
	361	* @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above
	362	*/
	363	struct kfd_ioctl_alloc_memory_of_gpu_args {
	364	__u64 va_addr; /* to KFD */
	365	__u64 size; /* to KFD */
	366	__u64 handle; /* from KFD */
	367	__u64 mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */
	368	__u32 gpu_id; /* to KFD */
	369	__u32 flags;
	370	};
	371
	372	/* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu
	373	*
	374	* @handle: memory handle returned by alloc
	375	*/
	376	struct kfd_ioctl_free_memory_of_gpu_args {
	377	__u64 handle; /* to KFD */
	378	};
	379
	380	/* Map memory to one or more GPUs
	381	*
	382	* @handle: memory handle returned by alloc
	383	* @device_ids_array_ptr: array of gpu_ids (__u32 per device)
	384	* @n_devices: number of devices in the array
	385	* @n_success: number of devices mapped successfully
	386	*
	387	* @n_success returns information to the caller how many devices from
	388	* the start of the array have mapped the buffer successfully. It can
	389	* be passed into a subsequent retry call to skip those devices. For
	390	* the first call the caller should initialize it to 0.
	391	*
	392	* If the ioctl completes with return code 0 (success), n_success ==
	393	* n_devices.
	394	*/
	395	struct kfd_ioctl_map_memory_to_gpu_args {
	396	__u64 handle; /* to KFD */
	397	__u64 device_ids_array_ptr; /* to KFD */
	398	__u32 n_devices; /* to KFD */
	399	__u32 n_success; /* to/from KFD */
	400	};
	401
	402	/* Unmap memory from one or more GPUs
	403	*
	404	* same arguments as for mapping
	405	*/
	406	struct kfd_ioctl_unmap_memory_from_gpu_args {
407	__u64 handle; /* to KFD */
408	__u64 device_ids_array_ptr; /* to KFD */
409	__u32 n_devices; /* to KFD */
410	__u32 n_success; /* to/from KFD */
411	};
412
1dde0ea9 FK	413	struct kfd_ioctl_get_dmabuf_info_args {
	414	__u64 size; /* from KFD */
	415	__u64 metadata_ptr; /* to KFD */
	416	__u32 metadata_size; /* to KFD (space allocated by user)
	417	* from KFD (actual metadata size)
	418	*/
	419	__u32 gpu_id; /* from KFD */
	420	__u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */
	421	__u32 dmabuf_fd; /* to KFD */
	422	};
	423
	424	struct kfd_ioctl_import_dmabuf_args {
	425	__u64 va_addr; /* to KFD */
	426	__u64 handle; /* from KFD */
	427	__u32 gpu_id; /* to KFD */
	428	__u32 dmabuf_fd; /* to KFD */
	429	};
	430
88807dc8 OZ	431	/* Register offset inside the remapped mmio page
	432	*/
	433	enum kfd_mmio_remap {
	434	KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0,
	435	KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4,
	436	};
	437
b81c55db OG	438	#define AMDKFD_IOCTL_BASE 'K'
	439	#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
	440	#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
	441	#define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type)
	442	#define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type)
b7facbae	443
b81c55db OG	444	#define AMDKFD_IOC_GET_VERSION \
b81c55db OG	445	AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)
b7facbae	446
b81c55db OG	447	#define AMDKFD_IOC_CREATE_QUEUE \
b81c55db OG	448	AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)
b7facbae	449
b81c55db OG	450	#define AMDKFD_IOC_DESTROY_QUEUE \
b81c55db OG	451	AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)
b7facbae	452
b81c55db OG	453	#define AMDKFD_IOC_SET_MEMORY_POLICY \
b81c55db OG	454	AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)
b7facbae	455
b81c55db OG	456	#define AMDKFD_IOC_GET_CLOCK_COUNTERS \
b81c55db OG	457	AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)
b7facbae	458
b81c55db OG	459	#define AMDKFD_IOC_GET_PROCESS_APERTURES \
b81c55db OG	460	AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)
b7facbae	461
b81c55db OG	462	#define AMDKFD_IOC_UPDATE_QUEUE \
	463	AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
	464
29a5d3eb AL	465	#define AMDKFD_IOC_CREATE_EVENT \
	466	AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)
	467
	468	#define AMDKFD_IOC_DESTROY_EVENT \
	469	AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)
	470
	471	#define AMDKFD_IOC_SET_EVENT \
	472	AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)
	473
	474	#define AMDKFD_IOC_RESET_EVENT \
	475	AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)
	476
	477	#define AMDKFD_IOC_WAIT_EVENTS \
	478	AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
	479
aef11009 YS	480	#define AMDKFD_IOC_DBG_REGISTER \
	481	AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
	482
	483	#define AMDKFD_IOC_DBG_UNREGISTER \
	484	AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
	485
	486	#define AMDKFD_IOC_DBG_ADDRESS_WATCH \
	487	AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
	488
	489	#define AMDKFD_IOC_DBG_WAVE_CONTROL \
	490	AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
	491
6a1c9510 MR	492	#define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \
	493	AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args)
	494
5d71dbc3 YZ	495	#define AMDKFD_IOC_GET_TILE_CONFIG \
	496	AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args)
	497
d7b9bd22 FK	498	#define AMDKFD_IOC_SET_TRAP_HANDLER \
	499	AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args)
	500
c7bcbfa4 FK	501	#define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \
	502	AMDKFD_IOWR(0x14, \
	503	struct kfd_ioctl_get_process_apertures_new_args)
	504
5ec7e028 FK	505	#define AMDKFD_IOC_ACQUIRE_VM \
	506	AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args)
	507
	508	#define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \
	509	AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args)
	510
	511	#define AMDKFD_IOC_FREE_MEMORY_OF_GPU \
	512	AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args)
	513
	514	#define AMDKFD_IOC_MAP_MEMORY_TO_GPU \
	515	AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args)
	516
	517	#define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \
	518	AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args)
	519
a7fe68a1 FK	520	#define AMDKFD_IOC_SET_CU_MASK \
	521	AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args)
	522
5df099e8 JC	523	#define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \
	524	AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)
	525
1dde0ea9 FK	526	#define AMDKFD_IOC_GET_DMABUF_INFO \
	527	AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args)
	528
	529	#define AMDKFD_IOC_IMPORT_DMABUF \
	530	AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
	531
b81c55db	532	#define AMDKFD_COMMAND_START 0x01
4b3e30ed	533	#define AMDKFD_COMMAND_END 0x1E
b7facbae OG	534
b7facbae OG	535	#endif